Driving backboard, manufacturing method thereof, display panel and display device

Abstract

The present disclosure provides a kind of drive backboard and its manufacturing method, display panel, display device, it is related to display technical field.The drive backboard includes: substrate, active layer, first gate insulating layer, first gate metal layer, dielectric layer, source-drain metal layer, active layer includes the drive channel region of drive transistor, first gate metal layer includes first conductive part, and first conductive part and drive channel region exist overlapping area;Dielectric layer has first via, and the spacing between the orthographic projection of first via and the orthographic projection of drive channel region is less than or equal to 0.5 microns;Source-drain metal layer includes first connecting piece, and first connecting piece is connected with first conductive part by first via.In the embodiment of the present disclosure, by adjusting the planar spacing between the first via connected with first conductive part and the drive channel region of drive transistor, the subthreshold swing of drive transistor can be increased, so as to improve the gray scale control ability of pixel circuit.

Description

[0001] This disclosure is a divisional application. The original application has the application number 202310200220.8, the application date is February 28, 2023, and the invention title is "Drive Backplate and its Manufacturing Method, Display Panel, Display Device". Technical Field

[0002] This disclosure relates to the field of display technology, and more specifically, to a driving backplane and its manufacturing method, a display panel, and a display device. Background Technology

[0003] With the rapid development of display technology, users have increasingly higher requirements for the resolution of display devices. However, as the resolution of display devices increases and the luminous efficiency of their light-emitting devices improves, the pixel current in the pixel circuits that drive these devices decreases. This results in insufficient grayscale control of the transistors in the pixel circuits, leading to poor display quality.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this disclosure is to provide a driving backplane and its manufacturing method, a display panel, and a display device that can improve grayscale control capabilities and thus improve display effects.

[0006] According to one aspect of this disclosure, a driving backplane is provided, the driving backplane including a plurality of pixel circuits, each pixel circuit including a driving transistor, the driving backplane comprising: Substrate; An active layer is located on one side of the substrate and includes a driving active portion of the driving transistor, the driving active portion having a driving channel region. A first gate insulating layer is located on the side of the active layer away from the substrate and at least covers the driving active portion; A first gate metal layer is located on the side of the first gate insulating layer away from the substrate, and includes a first conductive portion, wherein the first conductive portion and the driving channel region have an overlapping area. A dielectric layer is located on the side of the first gate metal layer opposite to the substrate and has a first via extending through the first conductive portion. The distance between the orthographic projection of the first via on the substrate and the orthographic projection of the driving channel region on the substrate is less than or equal to 0.5 micrometers. The source / drain metal layer is located on the side of the dielectric layer opposite to the substrate and includes a first connecting piece, which is connected to the first conductive part through the first via.

[0007] According to any of the drive backplanes described in this disclosure, the orthographic projection of the first via on the substrate overlaps with the orthographic projection of the drive channel region on the substrate.

[0008] According to any of the drive backplanes described in this disclosure, a portion of the orthographic projection edge of the first via on the substrate coincides with a portion of the orthographic projection edge of the drive channel region on the substrate.

[0009] According to any of the drive backplanes described in this disclosure, the center point of the orthographic projection of the first via on the substrate coincides with the midpoint of the orthographic projection of the drive channel region on the substrate in the width direction.

[0010] According to any of the drive backplanes described in this disclosure, the orthographic projection of the first via on the substrate is circular, and the diameter of the orthographic projection of the first via on the substrate is greater than or equal to 1.5 micrometers and less than or equal to 5 micrometers.

[0011] According to any of the drive backplanes described in this disclosure, the orthographic projection of the first via on the substrate is elliptical or rectangular.

[0012] According to any of the drive backplanes described in this disclosure, the dielectric layer has a plurality of first vias, and the first connecting piece is connected to the first conductive portion through the plurality of first vias.

[0013] According to any of the drive backplanes described in this disclosure, the distance between the orthographic projection of the plurality of first vias on the substrate and the orthographic projection of the drive channel region on the substrate is less than or equal to 0.5 micrometers.

[0014] According to any of the driving backplanes described in this disclosure, the center points of the orthographic projections of the plurality of first vias on the substrate coincide with the midpoint of the orthographic projection of the driving channel region on the substrate in the width direction.

[0015] According to one aspect of this disclosure, a method for manufacturing a driving backplane is provided, the driving backplane including a plurality of pixel circuits, each pixel circuit including a driving transistor, the method comprising: Provide a substrate; A buffer layer is formed on one side of the substrate. An active layer is formed on the side of the buffer layer away from the substrate, the active layer including a driving active portion of the driving transistor, the driving active portion having a driving channel region; A first gate insulating layer is formed on the side of the active layer away from the substrate, and the first gate insulating layer at least covers the driving active portion; A first gate metal layer is formed on the side of the first gate insulating layer away from the substrate. The gate metal layer includes a first conductive portion, and there is an overlapping region between the first conductive portion and the driving channel region. A dielectric layer is formed on the side of the first gate metal layer away from the substrate. The dielectric layer has a first via extending through the first conductive portion. The distance between the orthographic projection of the first via on the substrate and the orthographic projection of the driving channel region on the substrate is less than or equal to 0.5 micrometers. A source / drain metal layer is formed on the side of the dielectric layer opposite to the substrate. The source / drain metal layer includes a first connecting piece, which passes through the first via and is connected to the first conductive portion.

[0016] According to one aspect of this disclosure, a display panel is provided, comprising: The drive backplane described in the above aspect; The light-emitting device is located on the side of the source / drain metal layer away from the substrate and is connected to the driving transistor.

[0017] According to one aspect of this disclosure, a display device is provided, including the display panel described in the above aspect.

[0018] The embodiments disclosed herein include at least the following technical effects: In this embodiment of the disclosure, by adjusting the planar spacing between the first via connecting the first conductive part and the driving channel region of the driving transistor (i.e., the spacing between the orthographic projection of the first via and the orthographic projection of the driving channel region), it is easier to increase the subthreshold swing of the driving transistor, thereby improving the grayscale control capability of the pixel circuit, and thus improving the display effect when the display panel displays the image.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0021] Figure 1This is a cross-sectional structural diagram of the driving transistor region of a display panel provided in an embodiment of the present disclosure.

[0022] Figure 2 This is a cross-sectional structural diagram of the driving transistor region of another display panel provided in an embodiment of this disclosure.

[0023] Figure 3 This is a schematic diagram of a pixel circuit provided for an embodiment of the present disclosure.

[0024] Figure 4 for Figure 1 or Figure 2 The diagram shows a top view of a driving transistor.

[0025] Figure 5 This is a top view of a switching transistor provided for an embodiment of the present disclosure.

[0026] Figure 6 The output characteristic curves of a driving transistor and a switching transistor are provided for embodiments of this disclosure.

[0027] Figure 7 for Figure 1 or Figure 2 A top view of another driving transistor structure is shown.

[0028] Figure 8 for Figure 1 or Figure 2 The diagram shows a top view of another type of driving transistor.

[0029] Figure 9 for Figure 1 or Figure 2 The diagram shows a top view of another type of driving transistor.

[0030] Figure 10 Provided for the embodiments of this disclosure Figure 4 , Figure 9 The output characteristic curve of the driving transistor is shown.

[0031] Figure 11 for Figure 1 or Figure 2 The diagram shows a top view of another type of driving transistor.

[0032] Figure 12 for Figure 1 or Figure 2 The diagram shows a top view of another type of driving transistor.

[0033] Figure label: 100. Display panel; 10. Drive backplate; 20. Light-emitting layer; 101. Substrate; 102. Buffer layer; 103. Active layer; 104. First gate insulating layer; 105. First gate metal layer; 106. Second gate insulating layer; 107. Second gate metal layer; 108. Dielectric layer; 109. Source / drain metal layer; 110. Planarization layer; 1031, Driving active section; 1032, Driving channel region; 1033, Switching active section; 1034, Switching channel region; 1035a, First doped section; 1035b, Second doped section; 1051, First conductive part; 1052, Second conductive part; 1081, First via; 1082, Second via; 1091, First connecting piece; 1092, Second connecting piece; 1093a, Third connecting piece; 1093b, Fourth connecting piece. Detailed Implementation

[0034] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0035] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0036] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0037] Furthermore, the thickness and area of ​​each layer are exaggerated in the accompanying drawings for clarity. It should be understood that when a layer, area, or component is mentioned as being "on" another part, it means that it is located directly on that other part, or that there may be other components in between.

[0038] The transistors involved in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Taking a transistor as an example, a transistor is a device that includes at least three terminals: a control terminal, a first terminal, and a second terminal. A transistor has a channel region between the first terminal and the second terminal, and current can flow through the first terminal, the channel region, and the second terminal. The channel region refers to the area where the current mainly flows. The first terminal is the source, and the second terminal is the drain, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the "first terminal" and the "second terminal" can be interchanged.

[0039] Figure 1 A partial cross-sectional structural diagram of a display panel 100 provided in this disclosure is illustrated. Figure 2 A partial cross-sectional structural diagram of another display panel 100 provided in this disclosure embodiment is illustrated. For example... Figure 1 or Figure 2 As shown, the display panel 100 includes a driving backplate 10 and a light-emitting layer 20.

[0040] The driving backplane 10 includes multiple pixel circuits spaced apart, and the light-emitting layer 20 includes multiple light-emitting devices spaced apart. Each pixel circuit is connected to at least one corresponding light-emitting device (e.g., one pixel circuit is connected to one corresponding light-emitting device). In this way, the corresponding light-emitting device can be driven to emit light through the pixel circuit, thereby realizing the display of the image.

[0041] Among them, such as Figure 1 or Figure 2 As shown, the driving backplane 10 includes a substrate 101 and a driving layer (not shown in the figure), and the driving layer is located between the substrate 101 and the light-emitting layer 20. The driving layer includes multiple pixel circuits.

[0042] In this embodiment, the substrate 101 can be made of either inorganic or organic materials. For example, in some embodiments, the substrate 101 can be made of glass materials such as so-lime glass, quartz glass, or sapphire glass, or metal materials such as stainless steel, aluminum, or nickel. In other embodiments, the substrate 101 can be made of polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyethersulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or combinations thereof.

[0043] The substrate 101 can be a single-layer structure or a multi-layer composite structure. Taking the multi-layer composite structure of the substrate 101 as an example, the substrate 101 includes a first polyimide layer, a protective film layer and a second polyimide layer sequentially stacked in the direction close to the driving layer.

[0044] In this embodiment, the pixel circuit included in the driving layer can be a 4T2C, 6T1C, 7T1C, or other circuits, as long as it can drive the light-emitting device to emit light. This embodiment does not impose any special limitations on this. nTmC indicates that a pixel circuit includes n transistors (represented by the letter "T") and m capacitors Cst (represented by the letter "C").

[0045] The pixel circuit includes transistors that can be thin-film transistors (TFTs), which can be selected from top-gate TFTs, bottom-gate TFTs, or dual-gate TFTs; the capacitors can be bipolar capacitors or tripolar capacitors. The channel region of the TFT can be made of amorphous silicon semiconductor material, low-temperature polycrystalline silicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, or other types of semiconductor material; the TFT can be an N-type TFT or a P-type TFT.

[0046] In this pixel circuit, at least one driving transistor is included among the multiple transistors. For example, if the pixel circuit is a 4T2C circuit, the pixel circuit includes one driving transistor, three switching transistors and two capacitors; if the pixel circuit is a 7T1C circuit, the pixel circuit includes one driving transistor, six switching transistors and one capacitor.

[0047] For the 7T1C circuit, such as Figure 3 As shown, the pixel circuit includes a driving transistor DT, a first switching transistor ST1, a second switching transistor ST2, a third switching transistor ST3, a fourth switching transistor ST4, a fifth switching transistor ST5, a sixth switching transistor ST6, and a capacitor Cst.

[0048] The first terminal of the driving transistor DT is electrically connected to the first terminal of the first switching transistor ST1 and the first terminal of the sixth switching transistor ST6, respectively. The second terminal of the driving transistor DT is electrically connected to the second terminal of the third switching transistor ST3 and the first terminal of the fourth switching transistor ST4, respectively. The control terminal of the driving transistor DT is electrically connected to the first terminal of the second switching transistor ST2, the first terminal of the third switching transistor ST3, and the first plate of the capacitor Cst, respectively.

[0049] In this configuration, the second terminal of the first switching transistor ST1 is used to input a data signal, and the control terminal of the first switching transistor ST1 is used to input a scan signal; the second terminal of the second switching transistor ST2 is used to input a first initial voltage signal, and the control terminal of the second switching transistor ST2 is used to input a reset signal; the control terminal of the third switching transistor ST3 is used to input a scan signal; the second terminal of the fourth switching transistor ST4 is electrically connected to the first terminal of the fifth switching transistor ST5 and is used to electrically connect to the light-emitting device, and the control terminal of the fourth switching transistor ST4 is used to input a light-emitting control signal; the second terminal of the fifth switching transistor ST5 is used to input a second initial voltage signal, and the control terminal of the fifth switching transistor ST5 is used to input a reset signal; the second terminal of the sixth switching transistor ST6 is electrically connected to the second plate of the capacitor Cst and is used to input a power supply signal, and the control terminal of the sixth switching transistor ST6 is used to input a light-emitting control signal.

[0050] In some implementations, such as Figure 1 or Figure 2 The driving layer includes the following layers stacked sequentially in the direction away from the substrate 101: a buffer layer 102, an active layer 103, a gate insulating layer (a first gate insulating layer 104 and / or a second gate insulating layer 106), a gate metal layer (a first gate metal layer 105 and / or a second gate metal layer 107), a dielectric layer 108, a source / drain metal layer 109, and a planarization layer 110.

[0051] The active layer 103 can be a polysilicon layer, an oxide thin film layer, or other structural layers, as long as it can form the channel region of each transistor and the doped portions (with conductive properties) located on both sides of the channel region. This disclosure does not limit this.

[0052] The gate metal layer and source / drain metal layer 109 can be single-layer or multi-layer structures. For example, the gate metal layer may include a first gate metal layer 105 and a second gate metal layer 107, and / or the source / drain metal layer 109 may include a first source / drain metal layer and a second source / drain metal layer. When the gate metal layer and the source / drain metal layer 109 are multi-layer structures, the number of layers of the gate insulating layer and the planarization layer 110 will be adjusted accordingly, and this disclosure does not limit this.

[0053] The gate metal layer includes conductive portions of each transistor, and the conductive portions of each transistor overlap with the channel region of the corresponding transistor, so that the overlapping region between the conductive portions and the channel region of each transistor forms the control electrode of each transistor. The planarization layer 110 is provided with vias, and a pixel circuit is connected to at least one light-emitting device through the vias on the planarization layer 110.

[0054] In this embodiment of the disclosure, the multiple light-emitting devices of the light-emitting layer 20 can be divided into multiple light-emitting units, and the multiple light-emitting units are arranged in an array. Each light-emitting unit includes multiple light-emitting devices with different emitting colors. For example, a light-emitting unit may include a red light-emitting device that emits red light, a green light-emitting device that emits green light, and a blue light-emitting device that emits blue light; or a light-emitting unit may include a red light-emitting device that emits red light, a green light-emitting device that emits green light, a blue light-emitting device that emits blue light, and a white light-emitting device that emits white light.

[0055] In some embodiments, the light-emitting device is an organic light-emitting diode (OLED), which includes a first electrode, a light-emitting functional layer, and a second electrode sequentially stacked along a direction away from the substrate 101.

[0056] The first electrode can be disposed on the side of the driving layer away from the substrate 101 and connected to the corresponding pixel circuit. The first electrode can be a single-layer structure or a composite of multiple layers. For example, when the first electrode is a single-layer structure, it may include a transparent ITO layer; when the first electrode is a composite of multiple layers, it includes a first transparent ITO layer, a reflective Ag layer, and a second transparent ITO layer stacked sequentially away from the driving layer. The second electrode covers the light-emitting functional layer, and the second electrodes of multiple light-emitting devices can share a single electrode layer. The second electrode can be a single-layer structure or a composite of multiple layers. For example, when the second electrode is a single-layer structure, it may be a MgAg composite material layer.

[0057] The light-emitting functional layer includes at least a composite light-emitting layer (EML). Taking the first electrode as the anode and the second electrode as the cathode as an example, holes can be transported to the composite light-emitting layer (EML) through the first electrode, and electrons can be transported to the composite light-emitting layer (EML) through the second electrode. Light emission is then achieved in the composite light-emitting layer (EML) through the recombination of holes and electrons, and the color of the emitted light depends on the material of the composite light-emitting layer (EML). To improve the hole and electron transport efficiency and enhance the light emission effect of the composite light-emitting layer (EML), the side of the composite light-emitting layer (EML) near the first electrode has at least one of a hole injection layer (HIL), a hole transport layer (HTL), and an electron blocking layer (EBL), and the side of the composite light-emitting layer (EML) near the second electrode has at least one of a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0058] In this embodiment of the disclosure, the light-emitting layer 20 includes a pixel definition layer. The pixel definition layer is located on the side of the first electrode away from the substrate 101 and has pixel openings corresponding to a plurality of light-emitting devices. The first electrode includes an exposed area exposed at the corresponding pixel opening and a covered area covered by the pixel definition layer. The exposed area of ​​the first electrode forms the light-emitting area of ​​the corresponding light-emitting device.

[0059] In some embodiments, the display panel 100 also includes functional layers, such as a thin-film encapsulation layer, a touch function layer, etc.

[0060] Taking the display panel 100 including a thin film encapsulation layer as an example, the thin film encapsulation layer is located on the side of the light-emitting layer 20 away from the substrate 101, so as to cover the light-emitting device included in the light-emitting layer 20, thereby protecting the light-emitting device from external water and oxygen corrosion.

[0061] The thin-film encapsulation layer may include alternating layers of inorganic and organic encapsulation layers. The inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the organic light-emitting functional layer and causing material degradation; the organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers.

[0062] The display panel 100 has a display area and a peripheral area located around the display area. The edge of the inorganic encapsulation layer may be located in the peripheral area, and the edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer. For example, the thin film encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on the side of the light-emitting layer 20 facing away from the substrate 101.

[0063] Taking the display panel 100 including a touch function layer as an example, the touch function layer is located on the side of the thin film encapsulation layer away from the substrate 101, so as to realize the touch operation of the display panel 100.

[0064] like Figure 1 and Figure 4 As shown, the driving backplane 10 includes: a substrate 101, an active layer 103, a first gate insulating layer 104, a first gate metal layer 105, a dielectric layer 108, and a source / drain metal layer 109. The active layer 103 is located on one side of the substrate 101 and includes a driving active portion 1031 for driving transistors. The driving active portion 1031 has a driving channel region 1032. The first gate insulating layer 104 is located on the side of the active layer 103 away from the substrate 101 and at least covers the driving active portion 1031. The first gate metal layer 105 is located on the side of the first gate insulating layer 104 away from the substrate 101 and includes a first conductive portion 1051. The first conductive portion 1051 and the driving channel region 1032 have an overlapping area; the dielectric layer 108 is located on the side of the first gate metal layer 105 away from the substrate 101, and has a first via 1081 that extends through to the first conductive portion 1051. The distance between the orthographic projection of the first via 1081 on the substrate 101 and the orthographic projection of the driving channel region 1032 on the substrate 101 is less than or equal to 0.5 micrometers; the source / drain metal layer 109 is located on the side of the dielectric layer 108 away from the substrate 101, and includes a first connecting piece 1091. The first connecting piece 1091 is connected to the first conductive portion 1051 through the first via 1081.

[0065] In this embodiment of the disclosure, by adjusting the planar spacing between the first via 1081 connecting the first conductive part 1051 and the driving channel region 1032 of the driving transistor (i.e., the spacing between the orthographic projection of the first via 1081 and the orthographic projection of the driving channel region 1032), the subthreshold swing of the driving transistor can be increased, which facilitates the improvement of the grayscale control capability of the pixel circuit, and thus improves the display effect of the display panel 100 when displaying images, including the driving backplate 10.

[0066] In this disclosure, all orthographic projections refer to orthographic projections on the substrate 101. The relationship between the subthreshold swing and trap capacitance of the transistor in this disclosure is shown in the following formula:

[0067] In the above formula, S refers to the subthreshold swing, k refers to the Boltzmann constant, T refers to the thermodynamic temperature of the transistor, and q refers to the electron charge. This refers to the trap capacitance of a transistor. This refers to the gate-source capacitance of a transistor.

[0068] As can be seen from the above formula, the subthreshold swing of the transistor increases with the increase of the trap capacitance. After careful study, this disclosure found that the influence of the trap capacitance of the driving transistor on the subthreshold swing of the driving transistor can be improved by narrowing the distance between the orthographic projection of the first via 1081 and the orthographic projection of the driving channel region 1032. Thus, the subthreshold swing of the driving transistor can be increased without increasing the trap capacitance, thereby improving the grayscale control capability.

[0069] In the embodiments of this disclosure, such as Figure 4 As shown, the driving active portion 1031 of the active layer 103 also includes a first doped portion 1035a and a second doped portion 1035b located on both sides of the driving channel region 1032. At this time, the source / drain metal layer 109 also includes a third connecting piece 1093a and a fourth connecting piece 1093b. The third connecting piece 1093a is connected to the first doped portion 1035a through a via, and the fourth connecting piece 1093b is connected to the second doped portion 1035b through a via.

[0070] The first doped portion 1035a and the second doped portion 1035b serve as the source and drain of the driving transistor, respectively, thereby facilitating the connection between the third connecting piece 1093a and the fourth connecting piece 1093b and other switching transistors of the pixel circuit.

[0071] In the embodiments of this disclosure, such as Figure 5 As shown, the active layer 103 further includes a switching active portion 1033 of a switching transistor, the switching active portion 1033 having a switching channel region 1034, and the first gate insulating layer 104 also covers the switching active portion 1033; the first gate metal layer 105 includes a second conductive portion 1052, and the second conductive portion 1052 and the switching channel region 1034 have an overlapping region; the dielectric layer 108 has a second via 1082 extending to the second conductive portion 1052; the source / drain metal layer 109 includes a second connecting piece 1092, the second connecting piece 1092 being connected to the second conductive portion 1052 through the second via 1082.

[0072] The number of active switch portions 1033, the number of second conductive portions 1052, and the number of second vias 1082 can all be referenced to the number of switching transistors included in the pixel circuit, and the active switch portions 1033, the second conductive portions 1052, and the second vias 1082 correspond one-to-one.

[0073] Optionally, the distance between the orthographic projection of the second via 1082 on the substrate 101 and the orthographic projection of the switching channel region 1034 on the substrate 101 is less than or equal to 0.5 micrometers. Of course, since the subthreshold swing of the switching transistor has little impact on the light-emitting effect of the light-emitting device when the pixel circuit controls the corresponding light-emitting device, the distance between the orthographic projection of the second via 1082 on the substrate 101 and the orthographic projection of the switching channel region 1034 on the substrate 101 can also be greater than or equal to 0.5 micrometers. That is, the distance between the orthographic projection of the first via 1081 on the substrate 101 and the orthographic projection of the driving channel region 1032 on the substrate 101 is less than the distance between the orthographic projection of the second via 1082 on the substrate 101 and the orthographic projection of the switching channel region 1034 on the substrate 101. This makes the subthreshold swing of the driving transistor greater than the subthreshold swing of the switching transistor, thereby improving the grayscale control capability of the display panel 100. For example, the distance between the orthographic projection of the second via 1082 on the substrate 101 and the orthographic projection of the switch channel region 1034 on the substrate 101 is greater than or equal to 0.5 micrometers and less than or equal to 1.5 micrometers.

[0074] Where the distance between the orthographic projection of the first via 1081 on the substrate 101 and the orthographic projection of the driving channel region 1032 on the substrate 101 is less than or equal to 0.5 micrometers, and the distance between the orthographic projection of the second via 1082 on the substrate 101 and the orthographic projection of the switching channel region 1034 on the substrate 101 is greater than 0.5 micrometers, the output characteristic curve S1 of the driving transistor and the output characteristic curve S2 of the switching transistor are as follows: Figure 6 As shown in the figure, the subthreshold swing of the driving transistor is significantly greater than that of the switching transistor.

[0075] In some implementations, such as Figure 2 As shown, the driving backplane 10 also includes a second gate insulating layer 106 and a second gate metal layer 107. The second gate insulating layer 106 and the second gate metal layer 107 are located between the first gate metal layer 105 and the dielectric layer 108, and the second gate insulating layer 106 is located on the side close to the substrate 101.

[0076] The second gate metal layer 107 includes a third conductive portion. The orthographic projection of the first conductive portion 1051 on the substrate 101 overlaps with the orthographic projection of the third conductive portion on the substrate 101, so that the first conductive portion 1051 and the third conductive portion respectively form the two plates of the capacitor included in the pixel circuit.

[0077] The first via 1081 penetrates not only the dielectric layer 108 but also the second gate insulating layer 106 to ensure the connection between the first connecting piece 1091 and the first conductive portion 1051. The second gate metal layer 107 has a through hole, and the edge of the orthographic projection of the through hole on the substrate 101 is located outside the orthographic projection of the first via 1081 on the substrate 101 to avoid the first connecting piece 1091 from being connected to the second gate metal layer 107 when it is connected to the first conductive portion 1051.

[0078] In this embodiment of the disclosure, the orthographic projection of the first via 1081 on the substrate 101 can be circular, elliptical, rectangular (e.g., square), etc., as long as it can form an interface defect on the dielectric layer 108.

[0079] As can be seen from the above formula, the subthreshold swing of the transistor increases with the increase of the trap capacitance. The larger the area of ​​the orthogonal projection of the first via 1081 on the substrate 101, the larger the interface defect on the dielectric layer 108, which in turn makes the trap capacitance of the driving transistor larger, and thus the subthreshold swing of the driving transistor larger.

[0080] Therefore, in this embodiment of the present disclosure, in addition to narrowing the distance between the orthographic projection of the first via 1081 on the substrate 101 and the orthographic projection of the driving channel region 1032 on the substrate 101 to increase the subthreshold swing of the driving transistor, the area of ​​the orthographic projection of the first via 1081 on the substrate 101 can also be increased compared with the conventional design of the first via 1081 to increase the subthreshold swing of the driving transistor.

[0081] In conjunction with the above, the dielectric layer 108 has a second via 1082, and the area of ​​the orthographic projection of the second via 1082 is set in accordance with conventional design. At this time, the area of ​​the orthographic projection of the first via 1081 on the substrate 101 is set by an enlarged design, so that the area of ​​the orthographic projection of the first via 1081 on the substrate 101 is greater than the area of ​​the orthographic projection of the second via 1082 on the substrate 101. This makes the subthreshold swing of the driving transistor greater than the subthreshold swing of the switching transistor, thereby improving the grayscale control capability of the display panel 100.

[0082] For example, such as Figure 7 As shown, the orthographic projection of the first via 1081 on the substrate 101 is adjusted to be elliptical, thereby increasing the area of ​​the orthographic projection of the first via 1081 on the substrate 101 compared to the conventional design of the first via 1081, and thus increasing the subthreshold swing of the driving transistor; or, as... Figure 8As shown, the orthographic projection of the first via 1081 on the substrate 101 is adjusted to be rectangular, thereby increasing the area of ​​the orthographic projection of the first via 1081 on the substrate 101 compared to the conventional design of the first via 1081, and thus increasing the subthreshold swing of the driving transistor; or, as... Figure 4 As shown, the orthogonal projection of the first via 1081 on the substrate 101 is adjusted to be circular, thereby increasing the area of ​​the orthogonal projection of the first via 1081 on the substrate 101 compared to the conventional design of the first via 1081, thereby increasing the subthreshold swing of the driving transistor.

[0083] In the case where the orthogonal projection of the first via 1081 on the substrate 101 is circular, the diameter of the orthogonal projection of the first via 1081 on the substrate 101 is greater than or equal to 1.5 micrometers and less than or equal to 5 micrometers.

[0084] In some embodiments, the orthographic projection of the first via 1081 on the substrate 101 overlaps with the orthographic projection of the drive channel region 1032 on the substrate 101 (i.e., the distance between the orthographic projection of the first via 1081 on the substrate 101 and the orthographic projection of the drive channel region 1032 on the substrate 101 is zero). This further reduces the distance between the orthographic projection of the first via 1081 on the substrate 101 and the orthographic projection of the drive channel region 1032 on the substrate 101, thereby increasing the influence of the trap capacitance at the interface defect of the dielectric layer 108 on the subthreshold swing of the drive transistor, and further increasing the subthreshold swing of the drive transistor.

[0085] Optionally, such as Figure 9 As shown, a portion of the edge of the orthographic projection of the first via 1081 onto the substrate 101 coincides with a portion of the edge of the orthographic projection of the drive channel region 1032 onto the substrate 101. Alternatively, as... Figure 4 As shown, the center point of the orthographic projection of the first via 1081 on the substrate 101 coincides with the midpoint of the orthographic projection of the drive channel region 1032 on the substrate 101 in the width direction W.

[0086] Wherein, when the center point of the orthographic projection of the first via 1081 on the substrate 101 coincides with the midpoint of the orthographic projection of the driving channel region 1032 in the width direction, the orthographic projection of the first via 1081 on the substrate 101 can extend beyond the orthographic projection of the driving channel region 1032 on the substrate 101 in the width direction; of course, it is also possible that the orthographic projection of the driving channel region 1032 on the substrate 101 extends beyond the orthographic projection of the first via 1081 on the substrate 101 in the width direction of the driving channel region 1032, and the embodiments disclosed herein do not limit this.

[0087] Regarding the above, Figure 9 The structure of the driving transistor is shown, and the output characteristic curve of the driving transistor is as follows: Figure 10 Curves S11, S12, and S13 are shown; for the above... Figure 4 The structure of the driving transistor is shown, and the output characteristic curve of the driving transistor is as follows: Figure 10 The curves S14, S15, and S16 are shown. Figure 10 As can be seen from curves S11, S12, and S13 shown above, the above... Figure 9 The structure of the driving transistor shown has a subthreshold swing greater than or equal to 0.4 and less than or equal to 0.7; while the structure of the driving transistor is... Figure 10 As can be seen from curves S14, S15, and S16, the above... Figure 4 The structure of the driving transistor shown has a subthreshold swing greater than or equal to 0.5 and less than or equal to 0.8.

[0088] In some implementations, such as Figure 11 or Figure 12 As shown, the dielectric layer 108 has a plurality of first vias 1081, and the first connecting piece 1091 is connected to the first conductive portion 1051 through the plurality of first vias 1081. In this way, multiple interface defects are formed in the dielectric layer 108 through the plurality of first vias 1081, thereby forming multiple trap capacitors that affect the subthreshold swing of the driving transistor, thereby increasing the subthreshold swing of the driving transistor and further improving the grayscale control capability of the pixel circuit.

[0089] Specifically, for the plurality of first vias 1081 in the dielectric layer 108, the distance between the orthographic projection of a portion of the first vias 1081 onto the substrate 101 and the orthographic projection of the driving channel region 1032 may be less than or equal to 0.5 micrometers. In this case, the trap capacitance corresponding to this portion of the first vias 1081 has a significant impact on the subthreshold swing of the driving transistor. Alternatively, the distance between the orthographic projection of the plurality of first vias 1081 onto the substrate 101 and the orthographic projection of the driving channel region 1032 onto the substrate 101 may all be less than or equal to 0.5 micrometers. In this case, the trap capacitance corresponding to the plurality of first vias 1081 has a significant impact on the subthreshold swing of the driving transistor. For example, such as Figure 11 As shown, the dielectric layer 108 has three first vias 1081, and the partial edges of the orthogonal projection of the three first vias 1081 on the substrate 101 coincide with the partial edges of the drive channel region 1032.

[0090] Specifically, for the plurality of first vias 1081 in the dielectric layer 108, the center points of the orthographic projections of some of the first vias 1081 on the substrate 101 may coincide with the midpoint of the orthographic projection of the driving channel region 1032 in the width direction. In this case, the trap capacitors corresponding to these first vias 1081 have a significant impact on the subthreshold swing of the driving transistor. Alternatively, the center points of the orthographic projections of the plurality of first vias 1081 on the substrate 101 may coincide with the midpoint of the orthographic projection of the driving channel region 1032 on the substrate 101 in the width direction. In this case, the trap capacitors corresponding to the plurality of first vias 1081 all have a significant impact on the subthreshold swing of the driving transistor. For example, such as Figure 12 As shown, the dielectric layer 108 has three first vias 1081, and the center point of the orthographic projection of the three first vias 1081 on the substrate 101 coincides with the midpoint of the orthographic projection of the drive channel region 1032 on the substrate 101 in the width direction.

[0091] This disclosure also provides a method for manufacturing a driving backplane, which includes multiple pixel circuits, each pixel circuit including a driving transistor. The method includes the following steps S101 to S107.

[0092] Step S101: Provide a substrate. Step S102: Fabricate a buffer layer on one side of the substrate. Step S103: An active layer is formed on the side of the buffer layer away from the substrate. The active layer includes a first active portion, which has a driving channel region. Step S104: A first gate insulating layer is formed on the side of the active layer away from the substrate, and the first gate insulating layer at least covers the first active portion. Step S105: A first gate metal layer is formed on the side of the first gate insulating layer away from the substrate. The gate metal layer includes a first conductive portion. The first conductive portion and the driving channel region have an overlapping region. The region on the first conductive portion that overlaps with the driving channel region forms the control electrode of the driving transistor. Step S106: A dielectric layer is formed on the side of the first gate metal layer away from the substrate. The dielectric layer has a first via that extends through to the first conductive portion. The distance between the orthographic projection of the first via on the substrate and the orthographic projection of the driving channel region on the substrate is less than or equal to 0.5 micrometers. Step S107: A source / drain metal layer is formed on the side of the dielectric layer away from the substrate. The source / drain metal layer includes a first connecting piece, which passes through a first via and is connected to a first conductive part.

[0093] In this embodiment of the disclosure, the driving backplate manufactured by the above steps brings the distance between the orthographic projection of the first via and the orthographic projection of the driving channel region closer, thereby increasing the subthreshold swing of the driving transistor. This facilitates the improvement of the grayscale control capability of the pixel circuit, and thus improves the display effect of the display panel when displaying images, including the driving backplate.

[0094] The driving backplane fabricated in the above steps is only the most basic structure. For driving backplanes with other structures, the fabrication method may optionally include: before step S106, fabricating a second gate insulating layer on the side of the first gate metal layer facing away from the substrate, then fabricating a second gate metal layer on the side of the second gate insulating layer facing away from the substrate, and finally fabricating the dielectric layer from step S106 on the side of the second gate metal layer facing away from the substrate. In this case, the first via penetrates not only the dielectric layer but also the second gate insulating layer.

[0095] The materials and specific structures of each film layer in the above steps can be referred to the embodiments described above, and will not be repeated in this disclosure. In addition, in step S103 above, taking a polycrystalline silicon film layer as the active layer as an example, an amorphous silicon film layer can be first formed on the side of the buffer layer away from the substrate, and then the amorphous silicon film layer can be laser crystallized to obtain a polycrystalline silicon film layer; after step S105 above, it is further included that, based on the first conductive portion included in the first gate metal layer, the positions on both sides of the driving active portion located on both sides of the driving channel region are doped to obtain two doped portions, which serve as the first electrode and the second electrode of the driving transistor.

[0096] It should be noted that although the steps of the method for manufacturing the drive backplane in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0097] This disclosure also provides a display device that includes the display panel described in the above embodiments. Thus, for a display device including the aforementioned display panel, when displaying an image, the image display effect can be improved based on a higher grayscale control capability.

[0098] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes: a driving backplane and light-emitting devices, wherein the driving backplane includes a plurality of pixel circuits and the pixel circuits include driving transistors; The drive backplate includes: Substrate; An active layer is located on one side of the substrate and includes a driving active portion of the driving transistor, the driving active portion having a driving channel region. A first gate insulating layer is located on the side of the active layer away from the substrate and at least covers the driving active portion; A first gate metal layer is located on the side of the first gate insulating layer away from the substrate and includes a first conductive portion. The first conductive portion and the driving channel region have an overlapping area. The first conductive portion is used to form the control electrode of the driving transistor. The second gate insulating layer is located on the side of the first gate metal layer away from the substrate and at least covers the first conductive portion; The second gate metal layer is located on the side of the second gate insulating layer that is away from the substrate. A dielectric layer is located on the side of the second gate metal layer that faces away from the substrate. The first via penetrates the second gate insulating layer and the dielectric layer to the first conductive portion, and the distance between the orthographic projection of the first via on the substrate and the orthographic projection of the driving channel region on the substrate is less than or equal to 0.5 micrometers; A source / drain metal layer is located on the side of the dielectric layer opposite to the substrate, and includes a first connecting piece, which is connected to the first conductive part through the first via. The light-emitting device is located on the side of the source / drain metal layer away from the substrate and is connected to the driving transistor. The light-emitting device is an organic light-emitting diode and includes a first electrode, a light-emitting functional layer, and a second electrode stacked sequentially along the direction away from the substrate.

2. The display panel as described in claim 1, characterized in that, The orthographic projection of the first via on the substrate overlaps with the orthographic projection of the driving channel region on the substrate.

3. The display panel as described in claim 2, characterized in that, The partial edge of the orthographic projection of the first via on the substrate coincides with the partial edge of the orthographic projection of the drive channel region on the substrate.

4. The display panel as described in claim 2, characterized in that, The center point of the orthographic projection of the first via on the substrate coincides with the midpoint of the orthographic projection of the drive channel region on the substrate in the width direction.

5. The display panel as described in claim 1, characterized in that, The second gate metal layer has through holes; The projection of the first via on the substrate is located within the orthographic projection of the through hole on the substrate, or the edge of the orthographic projection of the through hole on the substrate is located outside the orthographic projection of the first via on the substrate.

6. The display panel as described in claim 1, characterized in that, The pixel circuit includes a capacitor, and the second gate metal layer includes a third conductive portion; The orthographic projection of the third conductive part on the substrate overlaps with the orthographic projection of the first conductive part on the substrate, and the first conductive part and the third conductive part respectively form the two plates of the capacitor.

7. The display panel as described in any one of claims 1-6, characterized in that, The orthographic projection of the first via on the substrate is circular, and the diameter of the orthographic projection of the first via on the substrate is greater than or equal to 1.5 micrometers and less than or equal to 5 micrometers.

8. The display panel as described in any one of claims 1-6, characterized in that, The drive backplate includes a plurality of first vias, and the first connecting piece is connected to the first conductive part through the plurality of first vias.

9. The display panel as described in claim 8, characterized in that, The distance between the orthographic projection of the plurality of first vias on the substrate and the orthographic projection of the drive channel region on the substrate is less than or equal to 0.5 micrometers.

10. The display panel as claimed in claim 9, characterized in that, The orthographic projections of the plurality of first vias on the substrate overlap with the orthographic projections of the drive channel region on the substrate.

11. The display panel as claimed in claim 10, characterized in that, The partial edges of the orthographic projection of the plurality of first vias on the substrate coincide with the partial edges of the orthographic projection of the drive channel region on the substrate.

12. The display panel as claimed in claim 10, characterized in that, The center point of the orthographic projection of the plurality of first vias on the substrate coincides with the midpoint of the orthographic projection of the drive channel region on the substrate in the width direction.

13. The display panel as claimed in claim 8, characterized in that, The pixel circuit also includes a switching transistor; The active layer further includes a switching active portion of the switching transistor, the switching active portion having a switching channel region, the first gate insulating layer further covering the switching active portion, the first gate metal layer further includes a second conductive portion, the second conductive portion and the switching channel region having an overlapping region, the second conductive portion being used to form the control electrode of the switching transistor; The driving backplane also includes a second via, which penetrates the second gate insulating layer and the dielectric layer to the second conductive portion. The source / drain metal layer also includes a second connecting piece, which is connected to the second conductive portion through the second via.

14. The display panel as claimed in claim 13, characterized in that, The distance between the orthographic projection of the second via on the substrate and the orthographic projection of the switching channel region on the substrate is greater than 0.5 micrometers.

15. The display panel as claimed in claim 13, characterized in that, The sum of the projected areas of the first vias on the substrate is greater than the projected area of ​​the second vias on the substrate.

16. The display panel as described in any one of claims 1-6, characterized in that, The pixel circuit includes a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, and a capacitor; The first terminal of the driving transistor is electrically connected to the first terminal of the first switching transistor and the first terminal of the sixth switching transistor, respectively. The second terminal of the driving transistor is electrically connected to the second terminal of the third switching transistor and the first terminal of the fourth switching transistor, respectively. The control terminal of the driving transistor is electrically connected to the first terminal of the second switching transistor, the first terminal of the third switching transistor, and the first plate of the capacitor, respectively. The second terminal of the first switching transistor is used to input a data signal, and the control terminal of the first switching transistor is used to input a scan signal; the second terminal of the second switching transistor is used to input a first initial voltage signal, and the control terminal of the second switching transistor is used to input a reset signal; the control terminal of the third switching transistor is used to input a scan signal; the second terminal of the fourth switching transistor is electrically connected to the first terminal of the fifth switching transistor and is used to electrically connect to the light-emitting device, and the control terminal of the fourth switching transistor is used to input a light-emitting control signal; the second terminal of the fifth switching transistor is used to input a second initial voltage signal, and the control terminal of the fifth switching transistor is used to input a reset signal; the second terminal of the sixth switching transistor is electrically connected to the second plate of the capacitor and is used to input a power supply signal, and the control terminal of the sixth switching transistor is used to input a light-emitting control signal.

17. A method for manufacturing a display panel, characterized in that, The display panel includes a driving backplane and light-emitting devices. The driving backplane includes multiple pixel circuits, each pixel circuit including a driving transistor. The method includes: Provide a substrate; A buffer layer is formed on one side of the substrate. An active layer is formed on the side of the buffer layer away from the substrate, the active layer including a driving active portion of the driving transistor, the driving active portion having a driving channel region; A first gate insulating layer is formed on the side of the active layer away from the substrate, and the first gate insulating layer at least covers the driving active portion; A first gate metal layer is formed on the side of the first gate insulating layer away from the substrate. The gate metal layer includes a first conductive portion, and there is an overlapping region between the first conductive portion and the driving channel region. A dielectric layer is formed on the side of the first gate metal layer away from the substrate. The dielectric layer has a first via extending through the first conductive portion. The distance between the orthographic projection of the first via on the substrate and the orthographic projection of the driving channel region on the substrate is less than or equal to 0.5 micrometers. A source / drain metal layer is formed on the side of the dielectric layer opposite to the substrate. The source / drain metal layer includes a first connecting piece, which passes through the first via and is connected to the first conductive portion. The light-emitting device is fabricated on the side of the source / drain metal layer away from the substrate. The light-emitting device is connected to the driving transistor. The light-emitting device is an organic light-emitting diode and includes a first electrode, a light-emitting functional layer, and a second electrode stacked sequentially along the direction away from the substrate.

18. A display device, characterized in that, Includes the display panel described in any one of claims 1-16.

Images