Dual-gate transistor subthreshold swing regulation method and pixel circuit

Abstract

The application discloses a double-gate transistor sub-threshold swing regulation method and a pixel circuit. The method comprises the following steps: providing a first voltage as a regulation input signal to a first gate of a double-gate transistor; obtaining a second voltage based on a preset linear function relationship and the regulation input signal; and inputting the second voltage into a second gate of the double-gate transistor. The preset linear function relationship comprises a gain coefficient, and the gain coefficient is configured to regulate the sub-threshold swing of the double-gate transistor. According to the method, the input preset linear function relationship corresponding to the double-gate transistor is designed, and the double-gate modulation and circuit compensation are cooperated, so that the high-precision uniformity control of the current under the low gray scale condition and the improvement of the high-resolution electroluminescent display quality are realized.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a method for controlling the subthreshold swing of a dual-gate transistor and a pixel circuit. Background Technology

[0002] Amorphous oxide thin-film transistors (ICPs), such as indium gallium zinc oxide (IGNI) thin-film transistors (LTBs), with their low off-state current and high uniformity, together with low-temperature polycrystalline silicon (LTSi) thin-film transistors (LTSi), form the technological cornerstone of modern high-resolution electroluminescent display backplanes. Among them, IGBTs have become key components in high-end televisions and other fields due to their advantages in manufacturing large-size, high-uniformity panels. For example, in the pixel driving circuit module architecture of active-matrix OLED displays, IGBTs perform a dual function: acting as switching transistors for pixel addressing and as driving transistors to convert data voltage into the driving current required by the OLED. Their performance directly affects the accuracy and uniformity of the displayed image. As display pixel density continues to increase, the operating current of a single pixel continues to decrease, and low grayscale control increasingly relies on the current stability of the driving TFT subthreshold region. However, the low subthreshold swing of existing IGBTs makes the driving thin-film transistors extremely sensitive to data voltage fluctuations at low grayscale levels. Even with compensation circuits, it is difficult to overcome the current mismatch and grayscale inhomogeneity problems caused by the excessively low subthreshold swing.

[0003] Currently, to improve current control consistency at low grayscale levels, the industry has proposed increasing the subthreshold swing of indium gallium zinc oxide thin-film transistors (IGNTs) to suppress subthreshold current deviation. However, a low subthreshold swing is still required to ensure data voltage writing speed and accuracy. On the other hand, existing pixel driver circuit module designs are also dedicated to solving the low grayscale uniformity problem, but still face the dual challenges of structural complexity and control precision.

[0004] Therefore, existing solutions have failed to provide a complete solution that simultaneously achieves accuracy, robustness, and structural simplicity for high pixel density displays in low grayscale scenarios. Summary of the Invention

[0005] This application aims to at least solve the technical problems existing in the prior art. To this end, the first aspect of this application proposes a subthreshold swing control method and pixel circuit for a dual-gate transistor, wherein the channel of the dual-gate transistor is at least partially sandwiched between the first gate and the second gate of the dual-gate transistor, and the method includes: A first voltage is provided to the first gate of the dual-gate transistor as a control input signal; Based on a preset linear function relationship and the controlled input signal, a second voltage is obtained, and the second voltage is input to the second gate of the dual-gate transistor; The preset linear function relationship includes a gain coefficient, which is configured to control the subthreshold swing of the dual-gate transistor.

[0006] In one possible implementation, the first gate is a back gate terminal, the second gate is a top gate terminal, the first voltage is the back gate voltage, and the second voltage is the top gate voltage; the back gate terminal is used to receive the back gate voltage, and the top gate terminal is used to receive the top gate voltage.

[0007] In one possible implementation, the first gate is a top gate terminal, the second gate is a back gate terminal, the first voltage is the top gate voltage, and the second voltage is the back gate voltage; the back gate terminal is used to receive the back gate voltage, and the top gate terminal is used to receive the top gate voltage.

[0008] In one possible implementation, the preset linear function relationship is: ,in, Indicates the first voltage. Indicates the second voltage. Indicates the gain coefficient. The offset voltage is represented; the sign of the gain coefficient is used to control the trend change of the subthreshold swing of the dual-gate transistor.

[0009] In one possible implementation, the preset linear function relationship is achieved through an operational amplifier feedback network, which includes an operational amplifier, a first resistor, and a second resistor. The gain coefficient is determined by the ratio of the first resistor to the second resistor.

[0010] A second aspect of this application provides a pixel circuit integrating a dual-gate transistor as described in any one of the first aspects. The pixel circuit includes a subthreshold swing modulation circuit module and a pixel driving circuit module. The pixel driving circuit module integrates a dual-gate transistor for generating a driving current, wherein: The subthreshold swing control circuit module is configured to receive a first voltage and output a second voltage that has a linear relationship with the first voltage; wherein the first voltage is the back gate voltage and the second voltage is the top gate voltage, or the first voltage is the top gate voltage and the second voltage is the back gate voltage. A dual-gate transistor includes a first gate and a second gate. A first voltage is provided to the first gate of the dual-gate transistor as a control input signal. A second voltage is obtained based on a preset linear function relationship and the control input signal. The second voltage is input to the second gate of the dual-gate transistor so that the dual-gate driving transistor drives the light-emitting device based on the first voltage and the second voltage. The first gate is a back gate terminal and the second gate is a top gate terminal, or the first gate is a top gate terminal and the second gate is a back gate terminal. The preset linear function relationship includes a gain coefficient, which is configured to control the subthreshold swing of the dual-gate transistor.

[0011] In one possible implementation, the pixel driving circuit module further includes a compensation circuit unit for offsetting the threshold voltage drift of the dual-gate transistor. The compensation circuit unit employs a common-drain architecture or a common-source architecture, wherein: When the compensation circuit unit adopts a common-drain architecture, the anode of the light-emitting device is connected to the source of the dual-gate transistor, and the cathode of the light-emitting device is connected to a low level. When the compensation circuit unit adopts a common-source architecture, the cathode of the light-emitting device is connected to the drain of the dual-gate transistor, and the anode of the light-emitting device is connected to a high level.

[0012] In one possible implementation, when the compensation circuit unit adopts a common-drain architecture or a common-source architecture, the pixel driving circuit module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a light-emitting device, and a storage capacitor; wherein the second transistor, the third transistor, the fourth transistor, and the fifth transistor are all switching transistors, and the first transistor is a dual-gate transistor for generating driving current. The second transistor is used to provide the signal from the initial voltage signal terminal to the first gate of the first transistor under the control of the first scan control signal. The third transistor is used to turn on the first node and the second node under the control of the first scan control signal; wherein the first node and the second node are located at the source and drain terminals of the third transistor, respectively. The fourth transistor is used to provide the data signal terminal to the second node under the control of the second scan control signal; The fifth transistor is used to provide the driving current of the first transistor to the light-emitting device under the control of the third scan control signal, so as to drive the light-emitting device to emit light; A storage capacitor is used to couple the voltage of the second node to the first gate of the first transistor when the first gate of the first transistor is floating.

[0013] In one possible implementation, when the compensation circuit unit adopts a common-source architecture, the pixel driving circuit module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a light-emitting device, and a storage capacitor; wherein the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are all switching transistors, the first transistor is a dual-gate transistor for generating driving current, and the cathode of the light-emitting device is connected to the drain of the dual-gate transistor through the sixth transistor, wherein: The second transistor is used to provide the signal from the initial voltage signal terminal to the first gate of the first transistor under the control of the first scan control signal. The third transistor is used to turn on the first node and the second node under the control of the first scan control signal; wherein the first node and the second node are located at the source and drain terminals of the third transistor, respectively. The fourth transistor is used to provide the data signal terminal to the second node under the control of the second scan control signal; The fifth transistor is used to provide the driving current of the first transistor to the light-emitting device under the control of the third scan control signal, so as to drive the light-emitting device to emit light; The sixth transistor is used to turn off during non-light-emitting phases to control unintended light emission from the light-emitting device; A storage capacitor is used to couple the voltage of the second node to the first gate of the first transistor when the first gate of the first transistor is floating.

[0014] A third aspect of this application provides a pixel array, characterized in that the pixel array is composed of pixel driving circuit modules in a plurality of pixel circuits described in the second aspect.

[0015] The fourth aspect of this application discloses an active matrix electroluminescent display panel, characterized in that it includes a timing controller, a source driver, and a pixel array as described in the third aspect; wherein the timing controller is configured to generate timing control signals required for the operation of the pixel circuit; and the source driver is configured to generate voltage data.

[0016] The embodiments of this application have the following beneficial effects: This application provides a method for controlling the subthreshold swing of a dual-gate transistor and a pixel circuit. The method includes providing a first voltage to the first gate of the dual-gate transistor as a control input signal; obtaining a second voltage based on a preset linear function relationship and the control input signal; and inputting the second voltage to the second gate of the dual-gate transistor. The preset linear function relationship includes a gain coefficient, and the subthreshold swing of the dual-gate transistor is controlled by configuring the gain coefficient. This solution achieves high-precision current uniformity control and improved high-resolution electroluminescent display quality under low grayscale conditions by designing the preset linear function relationship corresponding to the dual-gate transistor and through the synergistic effect of dual-gate modulation and circuit compensation. Furthermore, by designing the preset linear function relationship, dynamic modulation of the second voltage of the output signal can be efficiently achieved, thereby improving the efficiency and accuracy of adjusting the subthreshold swing of the dual-gate transistor. Attached Figure Description

[0017] Figure 1 A flowchart illustrating the steps of the dual-gate transistor subthreshold swing control method provided in this application embodiment; Figure 2 A schematic diagram of a control circuit provided in an embodiment of this application; Figure 3A relationship curve diagram showing the linear control of the top gate voltage by the back gate voltage is provided in an embodiment of this application; Figure 4 A transfer characteristic curve of a dual-gate transistor under different gain coefficients is provided for an embodiment of this application; Figure 5 A schematic diagram of another control circuit provided in an embodiment of this application; Figure 6 A circuit diagram of a pixel driving circuit module provided in an embodiment of this application; Figure 7 A schematic diagram of a pixel array provided in an embodiment of this application; Figure 8 A schematic diagram of a pixel driving circuit module with a common-drain architecture is provided for an embodiment of this application; Figure 9 A timing diagram of a pixel circuit provided in an embodiment of this application; Figure 10 A schematic diagram of a pixel driving circuit module with a common source architecture is provided for an embodiment of this application; Figure 11 A schematic diagram of another common-source architecture pixel driving circuit module provided in this application embodiment; Figure 12 A timing diagram of another pixel circuit provided in an embodiment of this application; Figure 13 This is a schematic diagram of another pixel array provided in an embodiment of this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0019] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, the use of "based on" or "according to" implies openness and inclusiveness, because processes, steps, calculations, or other actions "based on" or "according to" one or more of the stated conditions or values ​​may in practice be based on additional conditions or beyond the stated values.

[0020] This application provides a method for controlling the subthreshold swing of a dual-gate transistor, such as... Figure 1 As shown, Figure 1 A flowchart illustrating the steps of a dual-gate transistor subthreshold swing modulation method provided in this application embodiment, the method comprising: Step 102: Provide a first voltage to the first gate of the dual-gate transistor as a control input signal.

[0021] Step 104: Based on the preset linear function relationship and the controlled input signal, the second voltage is obtained.

[0022] Step 106: Input the second voltage into the second gate of the dual-gate transistor.

[0023] In this dual-gate transistor, the channel is at least partially sandwiched between the first gate and the second gate of the dual-gate transistor. A first voltage can be provided to the first gate of the dual-gate transistor as a control input signal. Then, based on a preset linear function relationship and the control input signal, the obtained second voltage can be input to the second gate of the dual-gate transistor, so that the dual-gate transistor drives the light-emitting device based on the first voltage and the second voltage.

[0024] In some optional embodiments, the first gate is a back gate terminal, the second gate is a top gate terminal, the first voltage is the back gate voltage, and the second voltage is the top gate voltage. Thus, the back gate terminal is used to receive the back gate voltage, and the top gate terminal is used to receive the top gate voltage. In this case, the back gate terminal serves as a control signal input terminal, and the top gate terminal serves as the controlled terminal.

[0025] In some alternative embodiments, the first gate is a top gate terminal, the second gate is a back gate terminal, the first voltage is the top gate voltage, and the second voltage is the back gate voltage. Thus, the back gate terminal is used to receive the back gate voltage, and the top gate terminal is used to receive the top gate voltage. In this case, the top gate terminal serves as a control signal input terminal, and the back gate terminal serves as the controlled terminal.

[0026] Next, a second voltage can be obtained based on a preset linear function relationship and by adjusting the input signal. The preset linear function relationship includes a gain coefficient, which is configured to regulate the subthreshold swing of the dual-gate transistor. Optionally, the preset linear function relationship may also include an offset voltage, which is used to regulate the threshold voltage of the dual-gate transistor.

[0027] Optionally, the realization of the preset linear function relationship does not depend on a specific gate role assignment, that is, either of the two gates of the dual-gate transistor can be used as the control signal input terminal, and the other as the controlled terminal.

[0028] Furthermore, there are various ways to achieve this preset linear function relationship, and the embodiments of this application do not specifically limit it.

[0029] In some optional embodiments, the preset linear function relationship is: ,in, Indicates the first voltage. Indicates the second voltage. Indicates the gain coefficient. The offset voltage is represented; the sign of the gain coefficient is used to control the trend change of the subthreshold swing of the dual-gate transistor.

[0030] For example, the preset linear function relationship can be: ,in, Indicates the first voltage. Indicates the second voltage. Indicates the gain coefficient. This indicates the turn-on voltage of the other gate when a reference voltage is set for one gate of a dual-gate transistor. This represents the reference voltage; the sign of the gain coefficient is used to control the trend of the subthreshold swing of the dual-gate transistor. Equivalent to the offset voltage in the above formula When the gain coefficient is positive, it can control the subthreshold swing of the dual-gate transistor to decrease; when the gain coefficient is negative, it can control the subthreshold swing of the dual-gate transistor to increase.

[0031] The aforementioned preset linear function relationship is achieved through an operational amplifier feedback network, which includes an operational amplifier, a first resistor, and a second resistor. The gain coefficient is determined by the ratio of the first resistor to the second resistor, and the offset voltage or reference voltage is determined by the V0 input of the operational amplifier. Bias Sure.

[0032] In some alternative embodiments, such as Figure 2 As shown, Figure 2 This is a schematic diagram of a control circuit provided in an embodiment of this application, wherein the non-inverting input terminal of the operational amplifier is connected to V. Bias The inverting input terminal of the operational amplifier is connected to the control input signal. DATA[j] and with the first resistor R BG Electrical connection, second resistor R FB respectively with the first resistor R BG And electrically connect to the output terminal of the operational amplifier. T Drive It is a dual-gate transistor. DATA[j] Indicates the control of the input signal, DATA_TG[j] This represents the second voltage output by the operational amplifier. Figure 2 In the case where the gain coefficient is negative, the absolute value of the negative gain coefficient is determined by the ratio of the first resistor to the second resistor. It should be noted that the subthreshold swing control circuit module is... Figure 2The components other than the pixel driving circuit module.

[0033] In some alternative embodiments, when the gain factor is positive, the specific circuit diagram is similar to... Figure 2 Similarly, in this case, the non-inverting input of the operational amplifier is connected to the control input signal. DATA[j] The inverting input of the operational amplifier is connected to V. Bias and with the first resistor R BG Electrical connection, second resistor R FB respectively with the first resistor R BG And the output terminal of the operational amplifier is electrically connected.

[0034] Specifically, based on the above Figure 2 This circuit uses the back-gate voltage as the control input signal and dynamically modulates the top-gate voltage through an operational amplifier feedback network. ,in, Indicates the top gate voltage. Indicates the back gate voltage. , Corresponding offset voltage The final adjusted top gate voltage is written to the top gate terminal of the dual-gate transistor via the data line, thereby achieving active and precise adjustment of the subthreshold swing of the dual-gate transistor.

[0035] In the above Figure 2 Based on the control circuit shown, Figure 3 This application provides an embodiment of a curve showing the relationship between the back gate voltage and the top gate voltage, where different gain coefficients are used. The family of curves under the given values ​​indicates that by configuring It can be precisely set This allows for proportional control of the subthreshold swing. Parameters As the core of control, it can be flexibly configured through circuit design. Different gain coefficients... The values ​​include -0.67, -0.71, -0.73, -0.75, and -0.8.

[0036] Based on the above-mentioned control circuit, Figure 4 This application provides a transfer characteristic curve of a dual-gate transistor under different gain coefficients. The vertical axis represents the logarithm of the drain current of the dual-gate transistor. The different gain coefficients... The values ​​include 0, -0.39, -0.55, -0.59, and -0.7. It can be seen that, in different... Under certain conditions, the same dual-gate transistor can exhibit a set of transfer characteristic curves with different subthreshold swings. This characteristic indicates that the dual-gate transistor still possesses excellent grayscale control capability and good electrical adjustability under extremely low current conditions, making it particularly suitable for high-precision low grayscale display applications. This behavior stems from its wide data voltage regulation range after the subthreshold swing is increased, enabling precise current control in the low current range, thereby ensuring the accuracy and continuity of grayscale representation.

[0037] In other alternative embodiments, such as Figure 5 As shown, Figure 5 A schematic diagram of another control circuit provided in an embodiment of this application, wherein the circuit includes an input loop resistor R. in Output circuit resistance R out , V Bias The load transistor in the subthreshold swing control circuit module T 1. Dual-gate transistor in the subthreshold swing control circuit module T 2. Pixel driving circuit module, control input signal DATA[j] The output second voltage serves as the drive control signal. DATA_TG[j] Scan control signal SCAN[i], reference voltage V REF VDD represents a high level, and VSS represents a low level. When this circuit achieves the aforementioned preset linear function relationship, Gain coefficient in It can be represented as It should be noted that the subthreshold swing control circuit module is... Figure 5 The components other than the pixel driving circuit module.

[0038] This embodiment provides a method for subthreshold swing control of a dual-gate transistor and a pixel circuit. The method includes providing a first voltage to the first gate of the dual-gate transistor as a control input signal; obtaining a second voltage based on a preset linear function relationship and the control input signal; and inputting the second voltage to the second gate of the dual-gate transistor. The preset linear function relationship includes a gain coefficient, and the subthreshold swing of the dual-gate transistor is controlled by configuring the gain coefficient. This solution achieves high-precision current uniformity control and improved high-resolution electroluminescent display quality under low grayscale conditions by designing the preset linear function relationship corresponding to the dual-gate transistor and through the synergistic effect of dual-gate modulation and circuit compensation. Furthermore, by designing the preset linear function relationship, dynamic modulation of the second voltage of the output signal can be efficiently achieved, thereby improving the efficiency and accuracy of adjusting the subthreshold swing of the dual-gate transistor.

[0039] This application embodiment also provides a pixel circuit, which includes: a subthreshold swing control circuit module and a pixel driving circuit module. The pixel driving circuit module integrates a dual-gate transistor for generating a driving current, wherein: The subthreshold swing control circuit module is configured to receive a first voltage and output a second voltage that is linearly related to the first voltage. The first voltage is either the back gate voltage or the second voltage is either the top gate voltage or the top gate voltage.

[0040] A dual-gate transistor includes a first gate and a second gate. A first voltage is provided to the first gate of the dual-gate transistor as a control input signal. A second voltage is obtained based on a preset linear function relationship and the control input signal. The second voltage is input to the second gate of the dual-gate transistor. The first gate is the back gate terminal and the second gate is the top gate terminal, or the first gate is the top gate terminal and the second gate is the back gate terminal. The preset linear function relationship includes a gain coefficient, and the subthreshold swing of the dual-gate transistor is controlled by configuring the gain coefficient.

[0041] Optionally, such as Figure 6 As shown, Figure 6 This application provides a schematic diagram of a pixel driving circuit module, which includes a switching transistor. M 1. Dual-gate transistor used for output drive current M 2. Capacitor C 1. Adjust the input signal DATA[j] The output second voltage serves as the drive control signal. DATA_TG[j] Scan control signal SCAN[i] ELVDD Indicates a high level. ELVSS This indicates a low level.

[0042] Based on the above Figure 6 For example, this application also provides a pixel array, which is based on multiple Figure 6 The given pixel driving circuit module is used to construct it. Among them, such as... Figure 7 As shown, Figure 7 This is a schematic diagram of a pixel array provided in an embodiment of this application. Each pixel unit in the pixel array includes a switching transistor M1, a dual-gate transistor M2, and a capacitor C1, and their back gates share an independent back gate control line. In this case, the subthreshold swing control circuit module can be monolithically integrated with the pixel array to form the peripheral driving circuit of the display panel; or the subthreshold swing control circuit module can be integrated into a separate silicon-based driver chip and connected to the pixel array through an external interface. The control input signal includes... DATA[1] ...DATA[j] The output drive control signals include DATA_TG[1]...DATA_TG[j]The scan control signals include SCAN[1]...SCAN[i].

[0043] To address the issue of how to compensate for the threshold voltage drift of dual-gate transistors in a pixel array, this application further designs a compensation module. Optionally, the pixel driving circuit module also includes a compensation circuit unit, which is used to compensate for the threshold voltage drift of the dual-gate transistors. The compensation circuit unit adopts a common-drain architecture or a common-source architecture, wherein: When the compensation circuit unit adopts a common-drain architecture, the anode of the light-emitting device is connected to the source of the dual-gate transistor, and the cathode of the light-emitting device is connected to a low level. When the compensation circuit unit adopts a common-source architecture, the cathode of the light-emitting device is connected to the drain of the dual-gate transistor, and the anode of the light-emitting device is connected to a high level.

[0044] In some optional embodiments, when the compensation circuit unit adopts a common-drain architecture or a common-source architecture, the pixel driving circuit module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a light-emitting device, and a storage capacitor; wherein the second transistor, the third transistor, the fourth transistor, and the fifth transistor are all switching transistors, and the first transistor is a dual-gate transistor for generating driving current. The second transistor is used to provide the signal from the initial voltage signal terminal to the first gate of the first transistor under the control of the first scan control signal. The third transistor is used to turn on the first node and the second node under the control of the first scan control signal; wherein the first node and the second node are located at the source and drain terminals of the third transistor, respectively. The fourth transistor is used to provide the data signal terminal to the second node under the control of the second scan control signal; The fifth transistor is used to provide the driving current of the first transistor to the light-emitting device under the control of the third scan control signal, so as to drive the light-emitting device to emit light; A storage capacitor is used to couple the voltage of the second node to the first gate of the first transistor when the first gate of the first transistor is floating.

[0045] like Figure 8 As shown, Figure 8 This application provides a schematic diagram of a pixel driving circuit module with a common-drain architecture, which simultaneously features subthreshold swing control and threshold voltage V. TH The circuit employs a 5T1C structure, including: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a light-emitting device, and a storage capacitor C1. By introducing a dual-gate transistor and a compensation circuit unit, this circuit scheme achieves compensation for the threshold voltage V of the driving transistor. THCoordinated regulation of variation and subthreshold swing amplitude. In addition, VDD in the figure represents the positive power supply, which provides the circuit with a high operating level, VSS represents the negative power supply (or ground), which provides the circuit with a low operating level, SC1[i] is the first scan control signal, SC2[i] is the second scan control signal, and SC3[i] is the third scan control signal. These are all timing control signals of the pixel circuit, which can control the conduction or cutoff of T2, T3, T4, and T5, respectively.

[0046] Figure 8 The light-emitting device in the circuit is a diode. The anode of the light-emitting device is connected to the source of T5, and the cathode of the light-emitting device is connected to the low level VSS.

[0047] The above Figure 8 The circuit connections are as follows: the drain of dual-gate transistor T1 is connected to the high-level power supply VDD, the source is connected to the drain of switching transistors T3 and T5, the first gate is connected to the source of switching transistor T2, and the second gate is connected to the data signal terminal. DATA_TG [j] Here, the first gate can be the top gate and the second gate can be the back gate. The drain of the switching transistor T2 is connected to the initial voltage signal terminal, the source is connected to the first gate of the dual-gate transistor T1 and the upper plate of the storage capacitor C1, and the gate is connected to the first scan control signal terminal. The drain of switching transistor T3 is connected to the source of dual-gate transistor T1, the source of which is connected to the source of switching transistor T4 and the lower plate of storage capacitor C1, and the gate is connected to the first scan control signal terminal. The drain of switching transistor T4 is connected to the data signal terminal. DATA[j] The source is connected to the source of the switching transistor T3, and the gate is connected to the second scan control signal terminal; The drain of the switching transistor T5 is connected to the source of the dual-gate transistor T1, the source is connected to the anode of the light-emitting device, and the gate is connected to the third scan control signal terminal. The anode of the light-emitting device is connected to the source of the switching transistor T5, and the cathode is connected to the low-level power supply VSS. The intersection of the source of the dual-gate transistor T1 and the drain of the switching transistor T3 can be called the first node; The intersection of the source of switching transistor T3 and the source of switching transistor T4 can be called the second node; The intersection of the first gate of the dual-gate transistor T1 and the source of the switching transistor T2 can be called the third node.

[0048] Based on the above Figure 8 , Figure 9 A timing diagram of a pixel circuit provided in an embodiment of this application, wherein: (1) During the initialization phase, specifically, SC1[i] and SC2[i] go high to enable T2, T3, and T4, which are higher than the threshold voltage of T1. The voltage level at point A is stored via T2, while the voltage levels at points B and C are pulled low to VSS; where... This represents the initial voltage.

[0049] (2) This is the threshold compensation stage. Specifically, SC2[i] goes low, and at this time T1 is due to When activated, the voltage level at point B will be pulled up until it becomes... This is accompanied by the turn-off of T1. During this process, the voltage at point C remains consistent with that at point B. Specifically, V... th1 V represents the threshold voltage of the first transistor T1. GS This represents the gate-source voltage of the transistor.

[0050] (3) For the data input and subthreshold swing amplitude control stage, specifically, SC1[i] becomes low level, SC2[i] becomes high level, and T4 is turned on. DATA[j] The voltage at point A will always differ from the voltage at point C by V due to the bootstrap effect of the storage capacitor C1, as input is sent to point C via T4. th1 , become .at the same time, DATA_TG[[j] through DATA[j] The feedback modulation is written to the top gate of the dual-gate transistor, thereby changing the subthreshold swing value of T1. Wherein, V DATA The data voltage is an analog voltage signal generated by the source driver based on the input digital image data. Its voltage amplitude corresponds to the grayscale brightness of the target pixel. (4) is the light-emitting stage T4. Specifically, after SC3[i] becomes high, T5 is turned on, and the light-emitting device starts to emit light.

[0051] The timing diagram above clearly illustrates the voltage changes at key nodes during initialization, compensation, data writing, and emission stages, demonstrating how the circuit achieves the threshold voltage V at different stages. TH Sampling, subthreshold swing adjustment and current drive functions.

[0052] The above Figure 8 The same collaborative mechanism applies to the common-source architecture, which offers advantages in driving efficiency and compensation for threshold voltage drift. In some alternative embodiments, such as Figure 10 As shown, Figure 10 This application provides a schematic diagram of a pixel driving circuit module with a common-source architecture, which is related to... Figure 8 Similarly, both adopt a 5T1C structure, and Figure 8The only difference in the circuit connection is that the cathode of the light-emitting device is connected to the drain of T1, and the anode of the light-emitting device is connected to the high level VDD.

[0053] The above Figure 10 The circuit connections are as follows: the drain of the dual-gate transistor T1 is connected to the cathode of the light-emitting device, the source is connected to the drain of the switching transistors T3 and T5, the first gate is connected to the source of the switching transistor T2, and the second gate is connected to the data signal terminal. DATA_ TG[j] Here, the first gate can be the top gate and the second gate can be the back gate. The drain of the switching transistor T2 is connected to the initial voltage signal terminal, the source is connected to the first gate of the dual-gate transistor T1 and the upper plate of the storage capacitor C1, and the gate is connected to the first scan control signal terminal. The drain of switching transistor T3 is connected to the source of dual-gate transistor T1, the source of which is connected to the source of switching transistor T4 and the lower plate of storage capacitor C1, and the gate is connected to the first scan control signal terminal. The drain of switching transistor T4 is connected to the data signal terminal. DATA[j] The source is connected to the source of the switching transistor T3, and the gate is connected to the second scan control signal terminal; The drain of switching transistor T5 is connected to the source of dual-gate transistor T1, the source is connected to the low-level power supply VSS, and the gate is connected to the third scan control signal terminal. The anode of the light-emitting device is connected to the high-level power supply VDD, and the cathode is connected to the drain of the dual-gate transistor T1; The intersection of the source of the dual-gate transistor T1 and the drain of the switching transistor T3 can be called the first node; The intersection of the source of switching transistor T3 and the source of switching transistor T4 can be called the second node; The intersection of the first gate of the dual-gate transistor T1 and the source of the switching transistor T2 can be called the third node.

[0054] In this configuration, although there may be a very short period of unintended emission during the non-emission phase, its duration can be controlled to within 100 microseconds. This time is much shorter than the visual persistence time of the human eye, and the resulting equivalent flicker frequency is much higher than the flicker fusion critical frequency. Therefore, no obvious flicker or image quality degradation will be produced in visual perception, achieving an optimized balance between circuit complexity and display quality.

[0055] Based on the above Figure 10 The corresponding timing diagram under this architecture is the same as above. Figure 9 The timings are the same, and the timings for each operation can be referenced from the timings corresponding to the common-drain architecture described above, so they will not be repeated here.

[0056] In some alternative embodiments, when the compensation circuit unit adopts a common-source architecture, the pixel driving circuit module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a light-emitting device, and a storage capacitor; wherein the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are all switching transistors, the first transistor is a dual-gate transistor for generating driving current, and the cathode of the light-emitting device is connected to the drain of the dual-gate transistor through the sixth transistor, wherein: The second transistor is used to provide the signal from the initial voltage signal terminal to the first gate of the first transistor under the control of the first scan control signal. The third transistor is used to turn on the first node and the second node under the control of the first scan control signal; wherein the first node and the second node are located at the source and drain terminals of the third transistor, respectively. The fourth transistor is used to provide the data signal terminal to the second node under the control of the second scan control signal; The fifth transistor is used to provide the driving current of the first transistor to the light-emitting device under the control of the third scan control signal, so as to drive the light-emitting device to emit light; The sixth transistor is used to turn off during non-light-emitting phases to control unintended light emission from the light-emitting device; A storage capacitor is used to couple the voltage of the second node to the first gate of the first transistor when the first gate of the first transistor is floating.

[0057] Among them, such as Figure 11 As shown, Figure 11 This is a schematic diagram of another common-source pixel driving circuit module provided in an embodiment of this application. The circuit adopts a 6T1C structure, including: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a light-emitting device, and a storage capacitor C1. The light-emitting device is a diode as shown in the figure. The cathode of the light-emitting device is connected to the drain of T6, and the anode of the light-emitting device is connected to a high-level VDD. SC1[i] is the first scan control signal, SC2[i] is the second scan control signal, SC3[i] is the third scan control signal, and SC4[i] is the fourth scan control signal. These are all timing control signals for the pixel circuit, which can control the conduction or cutoff of T2, T3, T4, T5, and T6, respectively. With the addition of the sixth transistor T6, T6 is configured to conduct during the compensation phase to establish a compensation charging path; conduct during the light-emitting phase to establish a path for the driving current to the light-emitting device; and be turned off during the initialization and non-light-emitting phases, thereby ensuring that the light-emitting device is completely cut off and avoiding unexpected light emission.

[0058] The above Figure 11The circuit connections are as follows: the drain of dual-gate transistor T1 is connected to the source of switching transistor T6, and the source is connected to the drain of switching transistors T3 and T5. The first gate is connected to the source of switching transistor T2, and the second gate is connected to the data signal terminal. DATA_TG[j] Here, the first gate can be the top gate and the second gate can be the back gate. The drain of the switching transistor T2 is connected to the initial voltage signal terminal, the source is connected to the first gate of the dual-gate transistor T1 and the upper plate of the storage capacitor C1, and the gate is connected to the first scan control signal terminal. The drain of switching transistor T3 is connected to the source of dual-gate transistor T1, the source of which is connected to the source of switching transistor T4 and the lower plate of storage capacitor C1, and the gate is connected to the first scan control signal terminal. The drain of switching transistor T4 is connected to the data signal terminal. DATA[j] The source is connected to the source of the switching transistor T3, and the gate is connected to the second scan control signal terminal; The drain of switching transistor T5 is connected to the source of dual-gate transistor T1, the source is connected to the low-level power supply VSS, and the gate is connected to the fourth scan control signal terminal. The drain of the switching transistor T6 is connected to the cathode of the light-emitting device, the source is connected to the drain of the dual-gate transistor T1, and the gate is connected to the third scan control signal terminal. The anode of the light-emitting device is connected to the high-level power supply VDD, and the cathode is connected to the drain of the switching transistor T6; The intersection of the source of the dual-gate transistor T1 and the drain of the switching transistor T3 can be called the first node; The intersection of the source of switching transistor T3 and the source of switching transistor T4 can be called the second node; The intersection of the first gate of the dual-gate transistor T1 and the source of the switching transistor T2 can be called the third node.

[0059] It should be noted that the first node mentioned above is point B, the second node mentioned above is point C, and the third node mentioned above is point A.

[0060] Based on the above Figure 11 , Figure 12 Another timing diagram of a pixel circuit provided in this application embodiment, wherein: (1) During the initialization phase, specifically, SC1[i] and SC2[i] go high to enable T2, T3, and T4, which are higher than the threshold voltage of T1. Point A is stored via T2, and the levels at points B and C are pulled low to VSS.

[0061] (2) This is the threshold compensation stage. Specifically, SC2[i] goes low, SC3[i] goes high, and T6 is turned on. At this time, T1 is due to This will activate the circuit, thus the voltage level at point B will be pulled up until the voltage at point B becomes... This is accompanied by the T1 transistor being turned off. During this process, the voltage at point C remains consistent with that at point B.

[0062] (3) During the data input and subthreshold swing amplitude control stage, specifically, SC1[i] and SC3[i] go low, SC2[i] goes high, and T4 is turned on. Data voltage DATA[j] The voltage at point A will always differ from the voltage at point C by V due to the bootstrap effect of the storage capacitor C1, as input is sent to point C via T4. th1 , become .at the same time, DATA_TG[j] through DATA[j] The feedback modulation is written to the top gate of the dual-gate transistor, thereby changing the subthreshold swing value of T1.

[0063] (4) is the light-emitting stage. Specifically, after SC3[i] goes high, T5 turns on and the light-emitting device starts to emit light.

[0064] In addition, this application also provides an active matrix electroluminescent display panel, including a pixel array, a timing controller, and a source driver. The pixel array is constructed from the aforementioned plurality of pixel circuits; the timing controller is configured to generate timing control signals required for the operation of the pixel driving circuit module; and the source driver is configured to generate voltage data.

[0065] Among them, such as Figure 13 As shown, Figure 13 This is a schematic diagram of another pixel array provided in an embodiment of this application. This pixel array is implemented based on a 5T1C architecture or a 6T1C architecture, and integrates complete threshold voltage compensation and subthreshold swing control functions. It should be noted that the 5T1C architecture or 6T1C architecture here can respectively adopt the above... Figure 8 , Figure 10 , Figure 11 The specific architecture that corresponds to it.

[0066] The specific implementation process and beneficial effects of the above-mentioned pixel circuit and active matrix electroluminescent display panel can be referred to the various embodiments of the above-mentioned dual-gate transistor subthreshold swing control method, and will not be repeated here.

[0067] It is readily understood that, based on the several embodiments provided in this application, those skilled in the art can combine, split, or reorganize the embodiments of this application to obtain other embodiments, none of which exceed the protection scope of this application.

[0068] The above detailed embodiments further illustrate the purpose, technical solution, and beneficial effects of the embodiments of this application. It should be understood that the above are merely specific embodiments of the embodiments of this application and are not intended to limit the protection scope of the embodiments of this application. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solutions of the embodiments of this application should be included within the protection scope of the embodiments of this application.

Claims

1. A method for controlling the subthreshold swing of a dual-gate transistor, characterized in that, The channel of the dual-gate transistor is at least partially sandwiched between the first gate and the second gate of the dual-gate transistor, and the method includes: A first voltage is provided to the first gate of the dual-gate transistor as a control input signal; Based on the preset linear function relationship and the control input signal, a second voltage is obtained, and the second voltage is input to the second gate of the dual-gate transistor; The preset linear function relationship includes a gain coefficient, which is configured to control the subthreshold swing of the dual-gate transistor.

2. The method according to claim 1, characterized in that, The first gate is a back gate terminal, the second gate is a top gate terminal, the first voltage is a back gate voltage, and the second voltage is a top gate voltage; the back gate terminal is used to receive the back gate voltage, and the top gate terminal is used to receive the top gate voltage.

3. The method according to claim 1, characterized in that, The first gate is the top gate terminal, the second gate is the back gate terminal, the first voltage is the top gate voltage, and the second voltage is the back gate voltage; the back gate terminal is used to receive the back gate voltage, and the top gate terminal is used to receive the top gate voltage.

4. The method according to any one of claims 1-3, characterized in that, The preset linear function relationship is as follows: ,in, Indicates the first voltage. Indicates the second voltage. Indicates the gain coefficient. The value represents the offset voltage; the sign of the gain coefficient is used to control the trend change of the subthreshold swing of the dual-gate transistor.

5. The method according to any one of claims 1-3, characterized in that, The preset linear function relationship is realized through an operational amplifier feedback network, which includes an operational amplifier, a first resistor, and a second resistor. The gain coefficient is determined by the ratio of the first resistor to the second resistor.

6. A pixel circuit, characterized in that, The pixel circuit integrates the dual-gate transistor according to any one of claims 1-5, and the pixel circuit includes: a subthreshold swing control circuit module and a pixel driving circuit module, wherein the pixel driving circuit module integrates a dual-gate transistor for generating driving current, wherein: The subthreshold swing control circuit module is configured to receive a first voltage and output a second voltage that has a linear functional relationship with the first voltage; wherein the first voltage is a back gate voltage and the second voltage is a top gate voltage, or the first voltage is a top gate voltage and the second voltage is a back gate voltage. The dual-gate transistor includes a first gate and a second gate. A first voltage is provided to the first gate of the dual-gate transistor as a control input signal. A second voltage is obtained based on a preset linear function relationship and the control input signal. The second voltage is input to the second gate of the dual-gate transistor so that the dual-gate transistor drives a light-emitting device based on the first voltage and the second voltage. Wherein, the first gate is a back gate terminal and the second gate is a top gate terminal, or the first gate is a top gate terminal and the second gate is a back gate terminal. The preset linear function relationship includes a gain coefficient, and the subthreshold swing of the dual-gate transistor is controlled by configuring the gain coefficient.

7. The pixel circuit according to claim 6, characterized in that, The pixel driving circuit module further includes a compensation circuit unit, which is used to offset the threshold voltage drift of the dual-gate transistor. The compensation circuit unit adopts a common-drain architecture or a common-source architecture, wherein: When the compensation circuit unit adopts a common-drain architecture, the anode of the light-emitting device is connected to the source of the dual-gate transistor, and the cathode of the light-emitting device is connected to a low level. When the compensation circuit unit adopts a common-source architecture, the cathode of the light-emitting device is connected to the drain of the dual-gate transistor, and the anode of the light-emitting device is connected to a high level.

8. The pixel circuit according to claim 7, characterized in that, When the compensation circuit unit adopts a common-drain architecture or a common-source architecture, the pixel driving circuit module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a light-emitting device, and a storage capacitor; wherein, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are all switching transistors, and the first transistor is a dual-gate transistor for generating driving current. The second transistor is used to provide the signal from the initial voltage signal terminal to the first gate of the first transistor under the control of the first scan control signal; The third transistor is used to turn on the first node and the second node under the control of the first scan control signal; wherein the first node and the second node are respectively located at the source and drain of the third transistor. The fourth transistor is used to provide the signal from the data signal terminal to the second node under the control of the second scan control signal; The fifth transistor is used to provide the driving current of the first transistor to the light-emitting device under the control of the third scan control signal, so as to drive the light-emitting device to emit light; A storage capacitor is used to couple the voltage of the second node to the first gate of the first transistor when the first gate of the first transistor is floating.

9. The pixel circuit according to claim 7, characterized in that, When the compensation circuit unit adopts a common-source architecture, the pixel driving circuit module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a light-emitting device, and a storage capacitor; wherein, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are all switching transistors, the first transistor is a dual-gate transistor for generating driving current, and the cathode of the light-emitting device is connected to the drain of the dual-gate transistor through the sixth transistor, wherein: The second transistor is used to provide the signal from the initial voltage signal terminal to the first gate of the first transistor under the control of the first scan control signal; The third transistor is used to turn on the first node and the second node under the control of the first scan control signal; wherein the first node and the second node are respectively located at the source and drain of the third transistor. The fourth transistor is used to provide the signal from the data signal terminal to the second node under the control of the second scan control signal; The fifth transistor is used to provide the driving current of the first transistor to the light-emitting device under the control of the third scan control signal, so as to drive the light-emitting device to emit light; The sixth transistor is used to turn off during the non-light-emitting phase to control the unintended light emission of the light-emitting device; A storage capacitor is used to couple the voltage of the second node to the first gate of the first transistor when the first gate of the first transistor is floating.

10. A pixel array, characterized in that, The pixel array is composed of a pixel driving circuit module in the pixel circuit according to any one of claims 6-9.

11. An active matrix electroluminescent display panel, characterized in that, The device includes a timing controller, a source driver, and the pixel array of claim 10; wherein the timing controller is configured to generate timing control signals required for the operation of the pixel circuit; and the source driver is configured to generate voltage data.

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