Display backplane and method of making the same
By setting a hydrogen blocking unit above the active layer of a low-temperature polycrystalline silicon thin-film transistor, the problems of uniformity and accuracy in the hydrogen replenishment process are solved, the subthreshold swing is increased, and the color brightness uniformity at low gray levels is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO LTD
- Filing Date
- 2022-06-15
- Publication Date
- 2026-06-23
AI Technical Summary
In the hydrogen replenishment process, the uniformity and precision of existing low-temperature polycrystalline silicon thin-film transistors are difficult to control, resulting in a reduction in the subthreshold swing of electrical properties and uneven color brightness at low gray levels.
Hydrogen blocking units are set in the gate layer above the active layer of the low-temperature polycrystalline silicon thin-film transistor to block hydrogen diffusion, improve the uniformity of hydrogen replenishment, and increase the subthreshold swing.
It improves the uniformity of color brightness in low grayscale displays and enhances the display effect.
Smart Images
Figure CN115064556B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of displays, and more specifically to a display backplate and its manufacturing method. Background Technology
[0002] In recent years, the new LTPO (Low Temperature Polycrystalline Oxide) technology, which combines low temperature polycrystalline silicon thin film transistors and metal oxide transistors in the same pixel circuit, has emerged. In the existing process, hydrogen replenishment is performed on the low temperature polycrystalline silicon thin film transistor. Since the uniformity and accuracy of hydrogen replenishment are difficult to control, it has a significant impact on the channel of the low temperature polycrystalline silicon active layer, resulting in a reduction in the subthreshold swing of the electrical properties of the low temperature polycrystalline silicon thin film transistor. This leads to uneven color brightness at low gray levels during lamp testing.
[0003] Therefore, there is an urgent need for a display backplate and its manufacturing method to solve the above-mentioned technical problems. Summary of the Invention
[0004] This invention provides a display backplane and its manufacturing method, which can alleviate the technical problem of small subthreshold swing of electrical properties in current low-temperature polycrystalline silicon thin-film transistors.
[0005] This invention provides a display back panel, comprising:
[0006] A plurality of first thin-film transistors, each first thin-film transistor comprising a first active layer and a first gate layer, wherein the first active layer comprises low-temperature polycrystalline silicon;
[0007] A plurality of second thin-film transistors, the second thin-film transistors including a second active layer, the second active layer including a metal oxide;
[0008] Wherein, at least one of the first gate layers includes a first gate unit and a first hydrogen barrier unit, wherein the first hydrogen barrier unit is located between the first gate unit and the first active layer.
[0009] Preferably, the first thin-film transistor further includes a second gate layer, the second gate layer being located on the side of the first gate layer away from the first active layer; wherein, at least one of the second gate layers includes a second gate unit and a second hydrogen barrier unit, the second hydrogen barrier unit being located between the second gate unit and the first active layer.
[0010] Preferably, the first gate unit and the second gate unit are made of the same material; the first hydrogen barrier unit and the second hydrogen barrier unit are made of the same material, and the first hydrogen barrier unit is made of a different material than the first gate unit; wherein, the material of the first hydrogen barrier unit includes titanium.
[0011] Preferably, the first gate unit and the first hydrogen barrier unit are integrally disposed, and the second gate unit and the second hydrogen barrier unit are integrally disposed; wherein, the first gate unit and the first hydrogen barrier unit are titanium alloys, and the second gate unit and the second hydrogen barrier unit are titanium alloys.
[0012] Preferably, the second thin-film transistor further includes a third gate layer and a fourth gate layer, wherein the third gate layer is disposed on the same layer as the second gate layer, and the fourth gate layer is located on the side of the second active layer away from the third gate layer; wherein at least one of the third gate layers includes a third gate unit and a third hydrogen barrier unit, the third hydrogen barrier unit being located on the side of the third gate unit away from the second active layer, and at least one of the fourth gate layers includes a fourth gate unit and a fourth hydrogen barrier unit, the third hydrogen barrier unit being located on the side of the third gate unit away from the second active layer.
[0013] Preferably, the third gate unit and the third hydrogen barrier unit are integrally disposed, and the fourth gate unit and the fourth hydrogen barrier unit are integrally disposed; wherein, the third gate unit and the third hydrogen barrier unit are titanium alloys, and the fourth gate unit and the fourth hydrogen barrier unit are titanium alloys.
[0014] Preferably, the first thin-film transistor further includes a first source-drain layer, and the second active layer is located on the side of the first source-drain layer away from the first active layer.
[0015] Preferably, the first thin-film transistor further includes a first source-drain layer, which is disposed in the same layer as the second active layer.
[0016] The present invention also provides a method for manufacturing a display back panel, comprising:
[0017] Provide a substrate;
[0018] A first active layer comprising low-temperature polycrystalline silicon is formed on the substrate;
[0019] A first gate layer comprising a first hydrogen barrier unit and a first gate unit is formed on the side of the first active layer away from the substrate;
[0020] A second active layer comprising a metal oxide is formed on the side of the first gate layer away from the substrate;
[0021] The first hydrogen barrier unit is located between the first gate unit and the first active layer.
[0022] Preferably, the step of forming a second active layer comprising a metal oxide on the side of the first gate layer away from the substrate includes: forming a first interlayer insulating layer comprising a plurality of first vias on the side of the first gate layer away from the substrate, the first vias exposing the first active layer; performing high-temperature annealing on the film layer between the first interlayer insulating layer and the substrate; and forming a second active layer comprising a metal oxide on the side of the first interlayer insulating layer away from the substrate.
[0023] The beneficial effects of this invention are as follows: By setting a hydrogen blocking unit in the gate layer above the active layer of the low-temperature polycrystalline silicon thin-film transistor, the hydrogen blocking unit can block hydrogen diffusion in the active layer of the low-temperature polycrystalline silicon thin-film transistor during the hydrogen replenishment process. This improves the uniformity of hydrogen replenishment in the overall display backplane, reduces the impact of hydrogen replenishment on the first active layer, increases the subthreshold swing of the low-temperature polycrystalline silicon thin-film transistor, improves the color brightness uniformity of the display at low gray levels, and improves the display effect. Attached Figure Description
[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 This is a schematic diagram of the first structure of the display back panel provided in an embodiment of the present invention;
[0026] Figure 2 This is a schematic diagram of the second structure of the display backplate provided in an embodiment of the present invention;
[0027] Figure 3 This is a schematic diagram of the third structure of the display back panel provided in an embodiment of the present invention;
[0028] Figure 4 This is a schematic diagram of the fourth structure of the display back panel provided in the embodiments of the present invention;
[0029] Figure 5 This is a flowchart of the steps in the manufacturing method of the display back panel provided in an embodiment of the present invention;
[0030] Figure 6A , Figure 6B This is a schematic diagram of the first process of manufacturing a display back panel according to an embodiment of the present invention;
[0031] Figure 7A , Figure 7B This is a schematic diagram of the second process of manufacturing a display back panel according to an embodiment of the present invention;
[0032] Figure 8 This is a schematic diagram of the structure of the display module provided in an embodiment of the present invention;
[0033] Figure 9 This is a schematic diagram of the structure of the display device provided in an embodiment of the present invention. Detailed Implementation
[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of the present invention and are not intended to limit the present invention. In the present invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.
[0035] In recent years, the new LTPO (Low Temperature Polycrystalline Oxide) technology, which combines low temperature polycrystalline silicon thin film transistors and metal oxide transistors in the same pixel circuit, has emerged. In the existing process, hydrogen replenishment is performed on the low temperature polycrystalline silicon thin film transistor. Since the uniformity and accuracy of hydrogen replenishment are difficult to control, it has a significant impact on the channel of the low temperature polycrystalline silicon active layer, resulting in a reduction in the subthreshold swing of the electrical properties of the low temperature polycrystalline silicon thin film transistor. This leads to uneven color brightness at low gray levels during lamp testing.
[0036] Please see Figures 1 to 4 This invention provides a display back panel 100, comprising:
[0037] A plurality of first thin-film transistors 200, each first thin-film transistor 200 including a first active layer 210 and a first gate layer 220, wherein the first active layer 210 includes low-temperature polycrystalline silicon;
[0038] A plurality of second thin-film transistors 300, each second thin-film transistor 300 including a second active layer 310, the second active layer 310 including a metal oxide;
[0039] Wherein, at least one of the first gate layers 220 includes a first gate unit 222 and a first hydrogen barrier unit 221, wherein the first hydrogen barrier unit 221 is located between the first gate unit 222 and the first active layer 210.
[0040] This invention provides a hydrogen blocking unit in the gate layer above the active layer of a low-temperature polycrystalline silicon thin-film transistor (LTSP). During the hydrogen replenishment process, the hydrogen blocking unit blocks hydrogen diffusion in the active layer of the LTSP, thereby improving the uniformity of hydrogen replenishment in the overall display backplane, reducing the impact of hydrogen replenishment on the first active layer, increasing the subthreshold swing of the LTSP, improving the color brightness uniformity of the display at low gray levels, and improving the display effect.
[0041] The technical solution of the present invention will now be described in conjunction with specific embodiments.
[0042] In this embodiment, please refer to Figure 1 The display backplane 100 includes a plurality of first thin-film transistors 200 and a plurality of second thin-film transistors 300. The first thin-film transistors 200 include a first active layer 210 and a first gate layer 220. The first active layer 210 includes low-temperature polycrystalline silicon. The second thin-film transistors 300 include a second active layer 310. The second active layer 310 includes a metal oxide. At least one of the first gate layers 220 includes a first gate unit 222 and a first hydrogen barrier unit 221. The first hydrogen barrier unit 221 is located between the first gate unit 222 and the first active layer 210.
[0043] During the fabrication of the display backplane 100, a hydrogen replenishment process is performed. Hydrogen diffuses through the inorganic film layer above the first active layer 210 to the first active layer 210, affecting the performance of the first active layer 210 and thus reducing the subthreshold swing of the low-temperature polycrystalline silicon thin-film transistor. This application addresses this by providing a hydrogen blocking unit 221 in the first gate layer 220 above the first active layer 210. The first hydrogen blocking unit 221 can block hydrogen diffusion, thereby avoiding the impact of the hydrogen replenishment process on the first active layer 210 and reducing the hydrogen content of the first active layer 210. At the same time, the precision of the hydrogen replenishment process is difficult to control. The provision of the first hydrogen blocking unit 221 can increase the amount of hydrogen replenished in the overall display backplane 100, thereby improving the uniformity of hydrogen replenishment in the overall display backplane 100, ultimately increasing the subthreshold swing of the low-temperature polycrystalline silicon thin-film transistor, improving the color brightness uniformity of the display at low gray levels, and improving the display effect.
[0044] In some embodiments, the second active layer 310 includes a metal oxide, which can be any one of IGZO, IGZTO, IGTO, Pr-IZO and InO. This paper takes IGZO as an example for experimental characterization.
[0045] In some embodiments, please refer to Figure 1The first thin-film transistor 200 further includes a second gate layer 230, which is located on the side of the first gate layer 220 away from the first active layer 210; wherein at least one of the second gate layers 230 includes a second gate unit 232 and a second hydrogen barrier unit 231, and the second hydrogen barrier unit 231 is located between the second gate unit 232 and the first active layer 210.
[0046] The first thin-film transistor 200 has a dual-gate structure. The dual-gate structure and dual hydrogen-blocking units protect the first active layer 210 from hydrogen, further avoiding the impact of the hydrogen replenishment process on the first active layer 210, reducing the hydrogen content of the first active layer 210, thereby improving the uniformity of hydrogen replenishment in the overall display backplane 100, and ultimately increasing the subthreshold swing of the low-temperature polycrystalline silicon thin-film transistor, improving the color brightness uniformity of the display at low gray levels, and improving the display effect.
[0047] In some embodiments, please refer to Figure 1 The first gate unit 222 and the second gate unit 232 are made of the same material; the first hydrogen barrier unit 221 and the second hydrogen barrier unit 231 are made of the same material, and the first hydrogen barrier unit 221 is made of a different material than the first gate unit 222; wherein, the material of the first hydrogen barrier unit 221 includes titanium.
[0048] The first gate unit 222 and the second gate unit 232 can be conventional gate materials, such as molybdenum. The materials of the first hydrogen barrier unit 221 and the second hydrogen barrier unit 231 include titanium, which can be pure metallic titanium, titanium alloys, such as TiN and TiMo, or titanium stacks, such as Ti / Fe and Ti / Ni. Taking the first gate layer 220 as an example, the first gate unit 222 and the first hydrogen barrier unit 221 of the first gate layer 220 can be deposited using physical deposition technology in one process, at two time points. First, the material of the first hydrogen barrier unit 221 is deposited, then the material of the first gate unit 222 is deposited, and then the first hydrogen barrier unit 221 and the first gate unit 222 are uniformly patterned to form the first hydrogen barrier unit 221 and the first gate unit 222. The process route is relatively simple and easy to implement.
[0049] In some embodiments, please refer to Figure 2 The first gate unit 222 and the first hydrogen barrier unit 221 are integrally disposed, and the second gate unit 232 and the second hydrogen barrier unit 231 are integrally disposed; wherein, the first gate unit 222 and the first hydrogen barrier unit 221 are titanium alloys, and the second gate unit 232 and the second hydrogen barrier unit 231 are titanium alloys.
[0050] The first hydrogen barrier unit 221 and the first gate unit 222 can be integrally formed, as can the second hydrogen barrier unit 231 and the second gate unit 232. Taking the first gate layer 220 as an example, the material of the first gate layer 220 is a titanium alloy, such as TiN or TiMo, or it can be a titanium stack, such as Ti / Fe or Ti / Ni. The material of the first gate layer 220 is formed directly in one process, and the first hydrogen barrier unit 221 and the first gate unit 222 are patterned in one step, saving time, improving the integrity, ensuring more uniform titanium dispersion, providing sufficient dispersion thickness, and enhancing the hydrogen barrier effect.
[0051] In some embodiments, please refer to Figure 1 The second thin-film transistor 300 further includes a third gate layer 320 and a fourth gate layer 330. The third gate layer 320 is disposed on the same layer as the second gate layer 230, and the fourth gate layer 330 is located on the side of the second active layer 310 away from the third gate layer 320. At least one of the third gate layers 320 includes a third gate unit 322 and a third hydrogen barrier unit 321. The third hydrogen barrier unit 321 is located on the side of the third gate unit 322 away from the second active layer 310. At least one of the fourth gate layers 330 includes a fourth gate unit 332 and a fourth hydrogen barrier unit 331. The third hydrogen barrier unit 321 is located on the side of the third gate unit 322 away from the second active layer 310.
[0052] Optimization of metal oxide thin-film transistors can improve the overall performance stability of LTPO, increase the subthreshold swing of low-temperature polycrystalline silicon thin-film transistors, improve the color brightness uniformity of displays at low gray levels, and improve the display effect.
[0053] In some embodiments, please refer to Figure 2 The third gate unit 322 and the third hydrogen barrier unit 321 are integrally disposed, and the fourth gate unit 332 and the fourth hydrogen barrier unit 331 are integrally disposed; wherein, the third gate unit 322 and the third hydrogen barrier unit 321 are titanium alloys, and the fourth gate unit 332 and the fourth hydrogen barrier unit 331 are titanium alloys.
[0054] The third gate unit 322 is integrally disposed with the third hydrogen barrier unit 321, and the fourth gate unit 332 is integrally disposed with the fourth hydrogen barrier unit 331. The principle and mechanism are the same as those of the first gate unit 222 being integrally disposed with the first hydrogen barrier unit 221, and will not be repeated here.
[0055] In some embodiments, please refer to Figure 1The display backplane 100 includes a first insulating layer 510 located between the first active layer 210 and the first gate layer 220, a second insulating layer 520 located between the first gate layer 220 and the second gate layer 230, a first interlayer insulating layer 410 located on the side of the second gate layer 230 away from the substrate 110, a third insulating layer 530 located between the second active layer 310 and the fourth gate layer 330, and a second interlayer insulating layer 420 located on the side of the fourth gate layer 330 away from the substrate 110.
[0056] The first thin-film transistor 200 further includes a first source-drain layer 240, and the second thin-film transistor 300 further includes a second source-drain layer 340. The first source-drain layer 240 and the second source-drain layer 340 can be disposed in the same layer. The second source-drain layer 340 is disposed on the side of the second interlayer insulating layer 420 away from the first active layer 210.
[0057] The second interlayer insulating layer 420 includes a plurality of second vias, the second vias exposing the second active layer 310, and the second source-drain layer 340 is electrically connected to the second active layer 310 through the second vias.
[0058] In some embodiments, the second interlayer insulating layer 420 further includes a plurality of third vias, the third vias exposing the first active layer 210, or the third vias exposing the first source-drain layer 240, the second source-drain layer 340 being electrically connected to the first active layer 210 through the third vias, or the second source-drain layer 340 being electrically connected to the first source-drain layer 240 through the third vias.
[0059] The second interlayer insulating layer 420 includes a plurality of fourth vias, which expose the first active layer 210, and the first source-drain layer 240 is electrically connected to the first active layer 210 through the fourth vias.
[0060] The display backplane 100 also includes a planarization layer 540 located on the side of the second source / drain layer 340 away from the substrate 110.
[0061] In some embodiments, please refer to Figure 3 The first thin-film transistor 200 further includes a first source-drain layer 240, and the second active layer 310 is located on the side of the first source-drain layer 240 away from the substrate 110.
[0062] The second active layer 310 is above the first source-drain layer 240. The display backplane 100 further includes a fourth insulating layer 550 located between the first source-drain layer 240 and the second active layer 310. The first thin-film transistor 200 further includes a first interlayer insulating layer 410 located on the side of the first gate layer 220 away from the second active layer 310, and a first source-drain layer 240 located on the side of the first interlayer insulating layer 410 away from the second active layer 310. The first interlayer insulating layer 410 includes a plurality of first vias 610, the first vias 610 allowing the first active layer 210 to pass through. The second active layer 310 is exposed and located above the first source-drain layer 240. The fabrication process of the second active layer 310 is after the fabrication process of the first source-drain layer 240. The hydrogen replenishment process and the annealing process are generally performed when the first interlayer insulating layer 410 is formed. Therefore, the hydrogen replenishment process and the annealing process will not affect the second active layer 310. The performance tuning of the first thin film transistor 200 can be performed before the formation of the second active layer 310, thereby increasing the adjustment threshold, increasing the subthreshold swing of the first thin film transistor 200, improving the color brightness uniformity of the display at low gray levels, and improving the display effect.
[0063] In some embodiments, please refer to Figure 4 The first thin-film transistor 200 further includes a first source-drain layer 240, which is disposed on the same layer as the second active layer 310.
[0064] The co-location of the second active layer 310 and the first source / drain layer 240 saves an insulating layer. Simultaneously, the fabrication process of the second active layer 310 can be completed after the fabrication process of the first source / drain layer 240. While hydrogen replenishment and annealing processes inevitably affect the second active layer 310, the performance tuning of the first thin-film transistor 200 can be performed during the formation of the second active layer 310. This increases the adjustment threshold, expands the subthreshold swing of the first thin-film transistor 200, improves the color uniformity of the display at low grayscale levels, and enhances the display effect.
[0065] In some embodiments, Figure 3 , Figure 4 Any one of the first gate layer 220, the second gate layer 230, the third gate layer 320, and the fourth gate layer 330 can be a conventional gate layer material.
[0066] In some embodiments, please refer to Figure 3The second thin-film transistor 300 further includes a second interlayer insulating layer 420 located on the side of the fourth gate layer 330 away from the second active layer 310, and a second source-drain layer 340 located on the side of the second interlayer insulating layer 420 away from the second active layer 310.
[0067] In some embodiments, please refer to Figure 3 , Figure 4 The second interlayer insulating layer 420 includes a plurality of second vias, the second vias exposing the second active layer 310, and the second source-drain layer 340 is electrically connected to the second active layer 310 through the second vias.
[0068] In some embodiments, please refer to Figure 3 , Figure 4 The second interlayer insulating layer 420 further includes a plurality of third vias, wherein the third vias expose the first active layer 210, or the third vias expose the first source-drain layer 240, and the second source-drain layer 340 is electrically connected to the first active layer 210 through the third vias, or the second source-drain layer 340 is electrically connected to the first source-drain layer 240 through the third vias.
[0069] In some embodiments, please refer to Figure 1 The display back panel 100 further includes a substrate 110 and a light-shielding layer 120 located in the substrate 110. The light-shielding layer 120 corresponds to the first active layer 210 and the light-shielding layer 120 blocks the light from the first active layer 210.
[0070] This invention provides a hydrogen blocking unit in the gate layer above the active layer of a low-temperature polycrystalline silicon thin-film transistor (LTSP). During the hydrogen replenishment process, the hydrogen blocking unit blocks hydrogen diffusion in the active layer of the LTSP, thereby improving the uniformity of hydrogen replenishment in the overall display backplane, reducing the impact of hydrogen replenishment on the first active layer, increasing the subthreshold swing of the LTSP, improving the color brightness uniformity of the display at low gray levels, and improving the display effect.
[0071] Please see Figure 5 This invention also provides a method for manufacturing a display back panel 100, comprising:
[0072] S100, providing a substrate 110;
[0073] S200, A first active layer 210 comprising low-temperature polycrystalline silicon is formed on the substrate 110;
[0074] S300, A first gate layer 220 including a first hydrogen barrier unit 221 and a first gate unit 222 is formed on the side of the first active layer 210 away from the substrate 110;
[0075] S400, A second active layer 310 comprising metal oxide is formed on the side of the first gate layer 220 away from the substrate 110.
[0076] The first hydrogen barrier unit 221 is located between the first gate unit 222 and the first active layer 210.
[0077] This invention provides a hydrogen blocking unit in the gate layer above the active layer of a low-temperature polycrystalline silicon thin-film transistor (LTSP). During the hydrogen replenishment process, the hydrogen blocking unit blocks hydrogen diffusion in the active layer of the LTSP, thereby improving the uniformity of hydrogen replenishment in the overall display backplane, reducing the impact of hydrogen replenishment on the first active layer, increasing the subthreshold swing of the LTSP, improving the color brightness uniformity of the display at low gray levels, and improving the display effect.
[0078] The technical solution of the present invention will now be described in conjunction with specific embodiments.
[0079] In this embodiment, the method for manufacturing the display back panel 100 includes:
[0080] S100, a substrate 110 is provided, please refer to Figure 6A .
[0081] In some embodiments, the material of the substrate 110 may be a rigid material, such as glass, or a flexible material, such as polyimide, without specific limitation.
[0082] S200, A first active layer 210 comprising low-temperature polycrystalline silicon is formed on the substrate 110. (See below) Figure 6A .
[0083] In some embodiments, the first active layer 210 comprises a low-temperature polycrystalline silicon material.
[0084] S300, A first gate layer 220, including a first hydrogen barrier unit 221 and a first gate unit 222, is formed on the side of the first active layer 210 away from the substrate 110. Please refer to [link to previous section]. Figure 6B .
[0085] In some embodiments, since the first hydrogen barrier unit 221 and the first gate unit 222 are not integrally disposed, step S300 includes:
[0086] S310a, A first hydrogen barrier material layer is formed on the side of the first active layer 210 away from the substrate 110.
[0087] S320a, A first gate material layer is formed on the side of the first hydrogen barrier material layer away from the substrate 110.
[0088] S330a, The first hydrogen barrier material layer and the first gate material layer are patterned to form the first hydrogen barrier unit 221 and the first gate unit 222, thereby forming the first gate layer 220.
[0089] The first thin-film transistor 200 has a dual-gate structure. The dual-gate structure and dual hydrogen-blocking units protect the first active layer 210 from hydrogen, further avoiding the impact of the hydrogen replenishment process on the first active layer 210, reducing the hydrogen content of the first active layer 210, thereby improving the uniformity of hydrogen replenishment in the overall display backplane 100, and ultimately increasing the subthreshold swing of the low-temperature polycrystalline silicon thin-film transistor, improving the color brightness uniformity of the display at low gray levels, and improving the display effect.
[0090] In some embodiments, since the first hydrogen barrier unit 221 and the first gate unit 222 are integrally configured, step S300 includes:
[0091] S310b, A first gate material layer is formed on the side of the first active layer 210 away from the substrate 110.
[0092] S320b: Pattern the first gate material layer to form the first hydrogen barrier unit 221 and the first gate unit 222, thereby forming the first gate layer 220.
[0093] The first gate unit 222 and the second gate unit 232 can be conventional gate materials, such as molybdenum. The materials of the first hydrogen barrier unit 221 and the second hydrogen barrier unit 231 include titanium, which can be pure metallic titanium, titanium alloys, such as TiN and TiMo, or titanium stacks, such as Ti / Fe and Ti / Ni. Taking the first gate layer 220 as an example, the first gate unit 222 and the first hydrogen barrier unit 221 of the first gate layer 220 can be deposited using physical deposition technology in one process, at two time points. First, the material of the first hydrogen barrier unit 221 is deposited, then the material of the first gate unit 222 is deposited, and then the first hydrogen barrier unit 221 and the first gate unit 222 are uniformly patterned to form the first hydrogen barrier unit 221 and the first gate unit 222. The process route is relatively simple and easy to implement.
[0094] S400, A second active layer 310 comprising a metal oxide is formed on the side of the first gate layer 220 away from the substrate 110. (See also...) Figure 1 .
[0095] In some embodiments, step S400 includes:
[0096] S410, A first interlayer insulating layer 410 including a plurality of first vias 610 is formed on the side of the first gate layer 220 away from the substrate 110. The first vias 610 expose the first active layer 210. Please refer to [link to previous section]. Figure 7A ;
[0097] S420, the film layer between the first interlayer insulating layer 410 and the substrate 110 is subjected to high-temperature annealing.
[0098] In some embodiments, step S420 includes:
[0099] S421. The film layer between the first interlayer insulating layer 410 and the substrate 110 is subjected to high-temperature annealing.
[0100] In some embodiments, hydrogen replenishment can be performed uniformly after the second interlayer insulating layer 420 is formed.
[0101] S422. The performance of the film layer between the first interlayer insulating layer 410 and the substrate 110 is adjusted.
[0102] The hydrogen replenishment process and annealing process are generally performed when the first interlayer insulating layer 410 is formed. Therefore, the hydrogen replenishment process and annealing process will not affect the second active layer 310. The performance adjustment of the first thin film transistor 200 can be performed before the second active layer 310 is formed, thereby increasing the adjustment threshold, increasing the subthreshold swing of the first thin film transistor 200, improving the color brightness uniformity of the display under low grayscale, and improving the display effect.
[0103] S430, A second active layer 310 comprising a metal oxide is formed on the side of the first interlayer insulating layer 410 away from the substrate 110. (See also...) Figure 7B .
[0104] In some embodiments, step S430 includes:
[0105] S431. A first source / drain layer 240 is formed on the side of the first interlayer insulating layer 410 away from the substrate 110.
[0106] S432. A second active layer 310 is formed on the side of the first source / drain layer 240 away from the substrate 110.
[0107] In some embodiments, the first thin-film transistor 200 further includes a first source-drain layer 240, which is disposed on the same layer as the second active layer 310.
[0108] The co-location of the second active layer 310 and the first source / drain layer 240 saves an insulating layer. Simultaneously, the fabrication process of the second active layer 310 can be completed after the fabrication process of the first source / drain layer 240. While hydrogen replenishment and annealing processes inevitably affect the second active layer 310, the performance tuning of the first thin-film transistor 200 can be performed during the formation of the second active layer 310. This increases the adjustment threshold, expands the subthreshold swing of the first thin-film transistor 200, improves the color uniformity of the display at low grayscale levels, and enhances the display effect.
[0109] In some embodiments, the second thin-film transistor 300 further includes a second interlayer insulating layer 420 located on the side of the fourth gate layer 330 away from the second active layer 310, and a second source-drain layer 340 located on the side of the second interlayer insulating layer 420 away from the second active layer 310.
[0110] In some embodiments, the fabrication processes for the second gate layer 230, the third gate layer 320, and the fourth gate layer 330 are similar to those for the first gate layer 220, and will not be described in detail here.
[0111] In some embodiments, the first thin-film transistor 200 further includes a second gate layer 230, which is located on the side of the first gate layer 220 away from the first active layer 210; wherein at least one of the second gate layers 230 includes a second gate unit 232 and a second hydrogen barrier unit 231, and the second hydrogen barrier unit 231 is located between the second gate unit 232 and the first active layer 210.
[0112] In some embodiments, the first gate unit 222 and the second gate unit 232 are made of the same material; the first hydrogen barrier unit 221 and the second hydrogen barrier unit 231 are made of the same material, and the first hydrogen barrier unit 221 is made of a different material than the first gate unit 222; wherein, the material of the first hydrogen barrier unit 221 includes titanium.
[0113] In some embodiments, the first gate unit 222 and the first hydrogen barrier unit 221 are integrally disposed, and the second gate unit 232 and the second hydrogen barrier unit 231 are integrally disposed; wherein, the first gate unit 222 and the first hydrogen barrier unit 221 are titanium alloys, and the second gate unit 232 and the second hydrogen barrier unit 231 are titanium alloys.
[0114] In some embodiments, the second thin-film transistor 300 further includes a third gate layer 320 and a fourth gate layer 330, wherein the third gate layer 320 is disposed on the same layer as the second gate layer 230, and the fourth gate layer 330 is located on the side of the second active layer 310 away from the third gate layer 320; wherein at least one of the third gate layers 320 includes a third gate unit 322 and a third hydrogen barrier unit 321, wherein the third hydrogen barrier unit 321 is located on the side of the third gate unit 322 away from the second active layer 310, and at least one of the fourth gate layers 330 includes a fourth gate unit 332 and a fourth hydrogen barrier unit 331, wherein the third hydrogen barrier unit 321 is located on the side of the third gate unit 322 away from the second active layer 310.
[0115] In some embodiments, the third gate unit 322 and the third hydrogen barrier unit 321 are integrally disposed, and the fourth gate unit 332 and the fourth hydrogen barrier unit 331 are integrally disposed; wherein, the third gate unit 322 and the third hydrogen barrier unit 321 are titanium alloys, and the fourth gate unit 332 and the fourth hydrogen barrier unit 331 are titanium alloys.
[0116] In some embodiments, experiments were conducted on subthreshold swings of different structures, wherein, with Figure 1 The first gate layer 220, the second gate layer 230, the third gate layer 320, and the fourth gate layer 330 in the experiment are conventional gate layer materials and are used as a blank experiment, named Experimental Group A; Figure 3 The first gate layer 220, the second gate layer 230, the third gate layer 320, and the fourth gate layer 330 in the experiment are conventional gate layer materials. For comparison, this group is named Experimental Group B. Figure 4 The first gate layer 220, the second gate layer 230, the third gate layer 320, and the fourth gate layer 330 in the experiment are made of conventional gate layer materials. For comparison, this group is named Experimental Group C. Figure 1 The structure in the diagram is used for a comparative experiment and is named experimental group D; Figure 2 The structure shown is for comparative experiments and is named Experimental Group E; DTFT represents the first thin-film transistor 200, IGZO represents the second thin-film transistor 300, Vth represents the threshold voltage (in V), DR represents the operating voltage range (in V), and SS represents the subthreshold swing (in mV / dec), characterized as shown in the table below:
[0117]
[0118] The characterization data shows that experiments B / C / D / E all have higher SS values than experiment A, which effectively improves the problem of uneven color brightness at low gray levels, while also increasing production capacity and making it more conducive to mass production.
[0119] This invention provides a hydrogen blocking unit in the gate layer above the active layer of a low-temperature polycrystalline silicon thin-film transistor (LTSP). During the hydrogen replenishment process, the hydrogen blocking unit blocks hydrogen diffusion in the active layer of the LTSP, thereby improving the uniformity of hydrogen replenishment in the overall display backplane, reducing the impact of hydrogen replenishment on the first active layer, increasing the subthreshold swing of the LTSP, improving the color brightness uniformity of the display at low gray levels, and improving the display effect.
[0120] Please see Figure 8 The present invention also provides a display module 10, including a display back panel 100 as described above.
[0121] In this embodiment, the display module 10 can be a liquid crystal display module 10 or a self-emissive display module 10. That is, the display backplate 100 can serve as a backlight module for the liquid crystal display module 10 or as a display device for the self-emissive display module 10.
[0122] In some embodiments, the display module 10 may be a liquid crystal display module 10, and the display module 10 may further include a liquid crystal layer, a color filter layer, and upper and lower polarizing layers.
[0123] Please see Figure 9 The present invention also provides a display device 1, including a display module 10 as described above and a device body 2, wherein the device body 2 and the display module 10 are integrated into one unit.
[0124] For the specific structure of the display module 10 and the display back panel 100, please refer to any of the above-mentioned embodiments and drawings of the display module 10 and the display back panel 100, which will not be repeated here.
[0125] In this embodiment, the main body 2 of the device may include a middle frame, frame adhesive, etc., and the display device 1 may be a display terminal such as a mobile phone, tablet, or television, which is not limited here.
[0126] This invention discloses a display backplane and its fabrication method. The display backplane includes multiple first thin-film transistors (TFTs) and multiple second thin-film transistors (TFTs). The first TFTs include a first active layer and a first gate layer. The first active layer includes low-temperature polycrystalline silicon (LTPS). The second TFTs include a second active layer, which includes a metal oxide layer. At least one first gate layer includes a first gate unit and a first hydrogen barrier unit, with the first hydrogen barrier unit located between the first gate unit and the first active layer. By setting a hydrogen barrier unit in the gate layer above the active layer of the LTPS, this invention allows the hydrogen barrier unit to block hydrogen diffusion in the active layer of the LTPS during the hydrogen replenishment process. This improves the uniformity of hydrogen replenishment in the overall display backplane, reduces the impact of hydrogen replenishment on the active layer, increases the subthreshold swing of the LTPS, improves the color brightness uniformity at low grayscale levels, and enhances the display effect.
[0127] The above provides a detailed description of a display backplate and its manufacturing method according to embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.
Claims
1. A display back panel, characterized in that, Includes a substrate and a plurality of first thin-film transistors and a plurality of second thin-film transistors disposed on the substrate: The first thin-film transistor includes a first active layer, a first gate layer, and a first source / drain layer located on the side of the first gate layer away from the first active layer. The first active layer includes low-temperature polycrystalline silicon. The second thin-film transistor includes a second active layer, which includes a metal oxide. Wherein, at least one of the first gate layers includes a first gate unit and a first hydrogen barrier unit, the first hydrogen barrier unit is located between the first gate unit and the first active layer, the first gate unit and the first hydrogen barrier unit have the same pattern, and the material of the first hydrogen barrier unit includes titanium. The second active layer is located on the side of the first source / drain layer away from the first active layer, or the first source / drain layer and the second active layer are disposed on the same layer, and the manufacturing process of the second active layer is after the manufacturing process of the first source / drain layer. The display backplane further includes a first interlayer insulating layer disposed between the first gate layer and the first source / drain layer. The film layer between the first interlayer insulating layer and the substrate has a hydrogen replenishment process and an annealing process, and the hydrogen replenishment process and the annealing process are performed before the process of the first source / drain layer.
2. The display back panel according to claim 1, characterized in that, The first thin-film transistor further includes a second gate layer, which is located on the side of the first gate layer away from the first active layer; Wherein, at least one of the second gate layers includes a second gate unit and a second hydrogen barrier unit, wherein the second hydrogen barrier unit is located between the second gate unit and the first active layer.
3. The display back panel according to claim 2, characterized in that, The first gate unit and the second gate unit are made of the same material; The first hydrogen barrier unit and the second hydrogen barrier unit are made of the same material, while the first hydrogen barrier unit is made of a different material than the first gate unit.
4. The display back panel according to claim 2, characterized in that, The first gate unit and the first hydrogen barrier unit are integrally disposed together, and the second gate unit and the second hydrogen barrier unit are integrally disposed together; Wherein, the first gate unit and the first hydrogen barrier unit are titanium alloys, and the second gate unit and the second hydrogen barrier unit are titanium alloys.
5. The display back panel according to claim 2, characterized in that, The second thin-film transistor further includes a third gate layer and a fourth gate layer, wherein the third gate layer is disposed on the same layer as the second gate layer, and the fourth gate layer is located on the side of the second active layer away from the third gate layer; Wherein, at least one of the third gate layers includes a third gate unit and a third hydrogen barrier unit, the third hydrogen barrier unit being located on the side of the third gate unit away from the second active layer, and at least one of the fourth gate layers includes a fourth gate unit and a fourth hydrogen barrier unit.
6. The display back panel according to claim 5, characterized in that, The third gate unit is integrally disposed with the third hydrogen barrier unit, and the fourth gate unit is integrally disposed with the fourth hydrogen barrier unit; The third gate unit and the third hydrogen barrier unit are both made of titanium alloy, as are the fourth gate unit and the fourth hydrogen barrier unit.
7. A method for manufacturing a display back panel, characterized in that, include: Provide a substrate; A first active layer comprising low-temperature polycrystalline silicon is formed on the substrate; A first gate layer comprising a first hydrogen barrier unit and a first gate unit is formed on the side of the first active layer away from the substrate. The first gate unit and the first hydrogen barrier unit have the same pattern, and the material of the first hydrogen barrier unit includes titanium. A first interlayer insulating layer is formed on the side of the first gate layer away from the substrate; A first source / drain layer is formed on the side of the first interlayer insulating layer away from the substrate; A second active layer comprising a metal oxide is formed on the side of the first gate layer away from the substrate. The second active layer is located on the side of the first source / drain layer away from the first active layer, or the first source / drain layer and the second active layer are disposed on the same layer. The first hydrogen barrier unit is located between the first gate unit and the first active layer; The film layer between the first interlayer insulating layer and the substrate has a hydrogen replenishment process and an annealing process, and the hydrogen replenishment process and the annealing process are performed before the process of the first source and drain layer.
8. The method for manufacturing a display back panel according to claim 7, characterized in that, The step of forming a second active layer comprising a metal oxide on the side of the first gate layer away from the substrate includes: A first interlayer insulating layer comprising a plurality of first vias is formed on the side of the first gate layer away from the substrate, the first vias exposing the first active layer; The film layer between the first interlayer insulating layer and the substrate is subjected to high-temperature annealing; A second active layer comprising metal oxide is formed on the side of the first interlayer insulating layer away from the substrate.