Hybrid conduction mechanism gate-all-around transistor and its fabrication method, equipment and fabrication method

Abstract

This invention provides a hybrid conduction mechanism gate-all-around transistor, comprising: a gate-all-around MOSFET device, including a substrate, a first source region, a first drain region, a first gate dielectric layer, and a gate-all-around channel control gate; wherein the first source region and the first drain region are doped with first ions; a second source region is formed between the substrate and the first source region, and a second drain region is formed between the substrate and the first drain region, and the height of the second source region and the second drain region is not less than the height of the substrate between the first source region and the first drain region; wherein the second drain region is doped with first ions, and the second source region is doped with second ions; a bottom control gate; the bottom control gate covers the surface of the gate dielectric layer on the substrate; the gate-all-around channel control gate covers the surface of the bottom control gate, and the difference in work function between the bottom control gate and the gate-all-around channel control gate is greater than 0.5 eV. This technical solution solves the problem that the ultra-steep subthreshold swing characteristic of less than 60 mV / dec in the bottom subthreshold region cannot be highlighted.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and more particularly to a hybrid conduction mechanism gate-around transistor and its fabrication method, apparatus and fabrication method. Background Technology

[0002] As device dimensions continue to shrink, power consumption has become a major challenge in advancing Moore's Law. A primary method for reducing device power consumption is to enhance gate control capabilities. Due to their superior electrostatic control of the channel and higher layout efficiency at extremely small sizes, gate-all-around (GAA) nanowire (NW) / nanofash (NS) transistors are strong candidates for next-generation CMOS device structures, surpassing fin field-effect transistors. Another effective method for reducing device power consumption is to decrease the supply voltage VDD. Traditional MOSFET devices have a theoretical limit of 60mV / dec at room temperature due to the thermodynamic distribution of kT / q, which prevents ULSI chips based on traditional MOSFET devices from continuously reducing the supply voltage.

[0003] Tunneling field-effect transistors (TFETs) are among the most promising devices for future ultra-low power integrated circuit applications due to their excellent subthreshold characteristics, low off-state leakage current, and low switching power consumption. Because their conduction mechanism is quantum mechanical band-to-band tunneling, which is not limited by thermodynamic temperature, the subthreshold swing of TFETs can exceed the 60mV / dec limit at room temperature.

[0004] The novel hybrid conduction mechanism of gate-all-around field-effect transistors, which combines tunneling transistors with gate-all-around nanowire / nanosheet field-effect transistors, can effectively suppress bottom leakage current and significantly improve the subthreshold characteristics of the device.

[0005] However, due to the low current of the bottom tunneling transistor, the current of the bottom tunneling transistor is masked by the current of the upper nanosheet under the same gate metal, and the ultra-steep subthreshold swing characteristic of the bottom tunneling transistor in the subthreshold region of less than 60mV / dec cannot be highlighted.

[0006] Therefore, developing a gate-around field-effect transistor that can highlight the ultra-steep subthreshold swing characteristics of the device (less than 60 mV / dec) has become a key technical issue that needs to be addressed by those skilled in the art. Summary of the Invention

[0007] This invention provides a hybrid conduction mechanism gate-all-around transistor and its fabrication method, apparatus, and fabrication method to solve the problem that the bottom tunneling transistor in a conventional hybrid conduction mechanism gate-all-around transistor cannot highlight the ultra-steep subthreshold swing characteristic of less than 60mV / dec in the subthreshold region.

[0008] According to a first aspect of the present invention, a hybrid conduction mechanism gate-around transistor is provided, comprising:

[0009] A gate-all-around MOSFET device includes a substrate, a first source region, a first drain region, a first gate dielectric layer, and a gate-all-around channel control gate; the first source region and the first drain region are arranged along a first direction; wherein the first source region and the first drain region are doped with first ions; wherein the first direction is characterized as a direction parallel to the substrate;

[0010] A second source region and a second drain region are formed between the substrate and the first source region, and the second drain region is formed between the substrate and the first drain region. The heights of both the second source region and the second drain region are not lower than the height of the substrate between the first source region and the first drain region. The second drain region is doped with a first ion, and the second source region is doped with a second ion, and the types of the first ion and the second ion are different. The first gate dielectric layer represents a gate dielectric layer directly formed on the substrate between the first source region and the first drain region.

[0011] Bottom control gate; the bottom control gate covers the surface of the first gate dielectric layer; the surrounding trench control gate, near the substrate, covers the surface of the bottom control gate;

[0012] The difference in work function between the bottom control gate and the surrounding gate channel control gate is greater than 0.5 eV.

[0013] Optionally, the difference between the work function of the bottom control gate and the work function of the surrounding gate channel control gate is 0.5eV-0.9eV.

[0014] Optionally, a first protective layer may be further included between the surrounding gate channel control gate and the bottom control gate near the substrate.

[0015] Optionally, the bottom control fence is a P-type control fence; the surrounding trench control fence is an N-type control fence.

[0016] Optionally, the bottom control fence is an N-type control fence; the surrounding trench control fence is a P-type control fence.

[0017] Optionally, the bottom control gate is made of doped polycrystalline silicon, cobalt, nickel, other metals, or metal silicides.

[0018] Optionally, the bottom control gate is made of TiN.

[0019] Optionally, the thickness of the bottom control gate along the second direction is 20 to 200 nm.

[0020] Optionally, the material of the enclosure trench control grid is TiAl.

[0021] Optionally, the thickness of the surrounding trench control grid along the second direction is 20-200 nm; the second direction is perpendicular to the first direction.

[0022] Optionally, the gate-around MOSFET device further includes:

[0023] A channel layer is formed between a first source region and a first drain region, and is spaced apart in a direction away from the substrate; the gate dielectric layer includes the first gate dielectric layer; the gate dielectric also covers a portion of the surface of the channel layer; the surrounding gate control gate also covers the surface of the gate dielectric layer; wherein the surrounding gate control gate closest to the substrate also covers the bottom control gate;

[0024] Inner walls are formed on the surface of the channel layer between the first source region and the gate dielectric layer, and between the first drain region and the gate dielectric layer;

[0025] A source metal layer, a gate metal layer, and a drain metal layer; the source metal layer and the drain metal layer are respectively formed on the surfaces of the first source region and the first drain region, and respectively completely enclose the first source region and the second source region, as well as the first drain region and the second drain region; the gate metal layer is formed at the top of the gate surrounding channel control gate;

[0026] An interlayer dielectric layer covers the surfaces of the source metal layer, the gate metal layer, the drain metal layer, and the inner sidewall;

[0027] Several metal contact layers penetrate the interlayer dielectric layer and are respectively connected to the source metal layer, the gate metal layer and the drain metal layer.

[0028] According to a second aspect of the present invention, a method for fabricating a hybrid conduction mechanism gate-around transistor is provided, for fabricating the hybrid conduction mechanism gate-around transistor as described in any one of the first aspects of the present invention, comprising:

[0029] A gate-all-around MOSFET device is formed, comprising a second source region, a second drain region, and a bottom control gate; wherein the gate-all-around MOSFET device includes a substrate, a first source region, a first drain region, a first gate dielectric layer, and a gate-all-around channel control gate; wherein the first source region and the first drain region are doped with the first ion; the second source region and the second drain region are respectively formed between the substrate and the first source region, and between the substrate and the first drain region, and the height of the second source region and the second drain region is not less than the height of the substrate between the first source region and the first drain region; wherein the second drain region is doped with the first ion, and the second source region is doped with the second ion; the first gate dielectric layer characterizes the gate dielectric layer formed on the substrate between the first source region and the first drain region; the bottom control gate covers the surface of the first gate dielectric layer; the gate-all-around channel control gate covers the surface of the bottom control gate;

[0030] The difference in work function between the bottom control gate and the surrounding gate channel control gate is greater than 0.5 eV.

[0031] Optionally, the method for fabricating the hybrid conduction mechanism gate-around transistor, forming the gate-around MOSFET device and the second source region, the second drain region, and the bottom control gate, specifically includes:

[0032] Provide one of the aforementioned substrates;

[0033] The sacrificial layer and the channel layer are formed; the sacrificial layer and the channel layer are stacked on the substrate at intervals;

[0034] The sacrificial layer and the channel layer are etched to form a fin structure, and the substrate on both sides of the fin structure along the first direction is over-etched to form a first cavity and a second cavity; wherein the first cavity and the second cavity are arranged sequentially along the first direction;

[0035] A false gate structure is formed, and the two ends of the sacrificial layer along the first direction are etched to form an inner sidewall cavity;

[0036] The inner wall is formed; the inner wall is formed in the cavity of the inner wall;

[0037] The second source region and the second drain region are formed; the second source region is formed in the first cavity, and the second drain region is formed in the second cavity;

[0038] The first source region and the first drain region are formed; the first source region and the first drain region are respectively formed at the top of the second source region and the second drain region;

[0039] Remove the dummy gate structure and release the channel layer to form a channel cavity;

[0040] The gate dielectric layer, the surrounding gate trench control gate, and the bottom control gate are formed;

[0041] The source metal layer, the gate metal layer, the drain metal layer, the interlayer dielectric layer, and the metal contact layer are formed.

[0042] Optionally, forming the gate dielectric layer, the surrounding gate channel control gate, and the bottom control gate specifically includes:

[0043] The gate dielectric layer is formed; the gate dielectric layer encloses the channel layer and covers the surface of the substrate between the second drain region and the second source region;

[0044] Deposit bottom control grid material in the channel cavity;

[0045] The bottom control gate material is etched, and a portion of the bottom control gate material on the surface of the first gate dielectric layer is retained to form the bottom control gate on the surface of the first gate dielectric layer;

[0046] The surrounding gate channel control gate is formed; the surrounding gate channel control gate encloses the gate dielectric layer; wherein, when the surrounding gate channel control gate is formed, the surrounding gate channel control gate closest to the substrate simultaneously covers the bottom control gate.

[0047] Optionally, after depositing the bottom control gate material in the channel cavity, the method further includes: forming the first protective layer; the first protective layer is formed on the surface of the bottom control gate.

[0048] According to a third aspect of the present invention, an electronic device is provided, comprising a hybrid conduction mechanism gate-around transistor as described in any of the first aspects of the present invention.

[0049] According to a fourth aspect of the present invention, a method for manufacturing an electronic device is provided, comprising the method for manufacturing a hybrid conduction mechanism gate-around transistor as described in any of the second aspects of the present invention.

[0050] This application provides a hybrid conduction mechanism gate-all-around transistor (GABOT), which creatively proposes the following: by setting a bottom control gate in a conventional hybrid conduction mechanism GABOT transistor, wherein the bottom control gate covers the surface of the first gate dielectric layer, and the gate-all-around channel control gate covers the surface of the bottom control gate; the first gate dielectric layer characterizes the gate dielectric layer formed on the substrate between the first source region and the first drain region; more importantly, the difference in work function between the bottom control gate and the gate-all-around channel control gate is greater than 0.5 eV, which increases the bottom tunneling transistor current compared to the conventional hybrid conduction mechanism GABOT transistor, avoids the bottom tunneling transistor current being masked by the current of the upper channel layer, and solves the problem that the ultra-steep subthreshold swing characteristic of less than 60 mV / dec in the subthreshold region of the bottom tunneling transistor in the conventional hybrid conduction mechanism GABOT transistor cannot be highlighted. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a schematic diagram of a device structure fabricated according to a method for fabricating a gate-around transistor with a hybrid conduction mechanism, provided in an embodiment of the present invention. Figure 1 ;

[0053] Figure 2 This is a schematic flowchart of a method for fabricating a hybrid conduction mechanism gate-around transistor according to an embodiment of the present invention;

[0054] Figure 3 This is a schematic diagram of the device structure at different process stages fabricated according to the method for fabricating a gate-around transistor with a hybrid conduction mechanism, provided in an embodiment of the present invention. Figure 1 ;

[0055] Figure 4 This is a schematic diagram of the device structure at different process stages fabricated according to the method for fabricating a gate-around transistor with a hybrid conduction mechanism, provided in an embodiment of the present invention. Figure 2 ;

[0056] Figure 5 This is a schematic diagram of the device structure at different process stages fabricated according to the method for fabricating a gate-around transistor with a hybrid conduction mechanism, provided in an embodiment of the present invention. Figure 3 ;

[0057] Figure 6 This is a schematic diagram of the device structure at different process stages fabricated according to the method for fabricating a gate-around transistor with a hybrid conduction mechanism, provided in an embodiment of the present invention. Figure 4 ;

[0058] Figure 7 This is a schematic diagram of the device structure at different process stages fabricated according to the method for fabricating a gate-around transistor with a hybrid conduction mechanism, provided in an embodiment of the present invention. Figure 5 ;

[0059] Figure 8 This is a schematic diagram of a device structure fabricated according to a method for fabricating a gate-around transistor with a hybrid conduction mechanism, provided in an embodiment of the present invention. Figure 2 ;

[0060] Explanation of reference numerals in the attached figures:

[0061] 101-Substrate;

[0062] 102 - Second source region;

[0063] 103 - First Source Region;

[0064] 104 - Inner wall;

[0065] 105-channel layer;

[0066] 106 - Gate dielectric layer;

[0067] 107 - Bottom control grid material;

[0068] 108 - Bottom control gate;

[0069] 109 - Fence control fence for trenches;

[0070] 110 - Interlayer dielectric layer;

[0071] 111 - Drain metal layer;

[0072] 112 - Source metal layer;

[0073] 113 - Gate metal layer;

[0074] 114 - Metal contact layer;

[0075] 115 - First leak zone;

[0076] 116 - Second leak zone;

[0077] 117 - First protective layer. Detailed Implementation

[0078] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0079] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0080] Since the hybrid conduction mechanism gate-around field-effect transistor can effectively suppress bottom leakage current and significantly improve the subthreshold characteristics of the device, the bottom tunneling transistor current is low. Therefore, under the same gate metal, the bottom tunneling transistor current is masked by the nanosheet current of the upper layer, and the ultra-steep subthreshold swing characteristic of the bottom tunneling transistor in the subthreshold region of less than 60mV / dec cannot be highlighted.

[0081] In view of this, the inventors of this application, through repeated experiments and demonstrations, discovered that by introducing a dual work function metal deposition process, the bottom tunneling transistor can be turned on before the upper nanosheet, thereby achieving an ultra-steep subthreshold swing of less than 60 mV / dec. Specifically, compared to conventional hybrid conduction mechanism gate-all-around transistors, the dual work function metal deposition process involves setting a bottom control gate; enabling the hybrid conduction mechanism gate-all-around transistor to simultaneously possess a bottom control gate and a gate-all-around channel control gate; and establishing a sufficiently large work function difference between the bottom control gate and the gate-all-around channel control gate to ensure that the bottom tunneling transistor turns on before the upper nanosheet, thus achieving an ultra-steep subthreshold swing of less than 60 mV / dec.

[0082] It is evident that the technical solution provided in this application, by setting a bottom control gate and a gate surrounding channel control gate with a sufficiently large work function difference, solves the problem that the ultra-steep subthreshold swing characteristic of the bottom tunneling transistor in the subthreshold region of conventional hybrid conduction mechanism gate surrounding transistors cannot be highlighted (less than 60mV / dec).

[0083] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0084] Please refer to Figures 1-6 According to an embodiment of the present invention, a hybrid conduction mechanism gate-around transistor is provided, comprising:

[0085] A gate-all-around MOSFET device includes a substrate 101, a first source region 103, a first drain region 115, a first gate dielectric layer, and a gate-all-around channel control gate 109; the first source region 103 and the first drain region 115 are arranged along a first direction; wherein the first source region 103 and the first drain region 115 are doped with first ions; wherein the first direction is characterized as a direction parallel to the substrate 101.

[0086] A second source region 102 and a second drain region 116 are formed, wherein the second source region 102 is formed between the substrate 101 and the first source region 103, and the second drain region 116 is formed between the substrate 101 and the first drain region 115, and the heights of the second source region 102 and the second drain region 116 are not lower than the height of the substrate 101 between the first source region 103 and the first drain region 115; wherein the second drain region 116 is doped with a first ion, and the second source region 102 is doped with a second ion, and the type of the first ion is different from the type of the second ion; wherein the first gate dielectric layer represents the gate dielectric layer 106 directly formed on the substrate 101 between the first source region 103 and the first drain region 115.

[0087] Bottom control gate 108; the bottom control gate 108 covers the surface of the first gate dielectric layer; the surrounding gate channel control gate 109 near the substrate 101 covers the surface of the bottom control gate 108;

[0088] Wherein, the difference in work function between the bottom control gate 108 and the gate surrounding channel control gate 109 is greater than 0.5 eV, and the hybrid conduction mechanism gate surrounding transistor is as follows: Figure 1 As shown.

[0089] The second source region 102 and the second drain region 116 can both be a single structural layer or multiple structural layers; the present invention is not limited to these configurations. The first direction refers to the horizontal direction on the paper, and the second direction refers to the vertical direction on the paper.

[0090] This application provides a hybrid conduction mechanism gate-all-around transistor, which creatively proposes: by setting a bottom control gate 108 in a conventional hybrid conduction mechanism gate-all-around transistor, wherein the bottom control gate 108 covers the surface of the first gate dielectric layer, and the gate-all-around channel control gate 109 covers the surface of the bottom control gate 108; the first gate dielectric layer is characterized by the gate dielectric layer 106 formed on the substrate 101 between the first source region 103 and the first drain region 115; more importantly, the difference in work function between the bottom control gate 108 and the gate-all-around channel control gate 109 is greater than 0.5eV, which increases the bottom tunneling transistor current compared to a conventional hybrid conduction mechanism gate-all-around transistor, avoids the bottom tunneling transistor current being masked by the current of the upper channel layer 105, and causes the bottom tunneling transistor to turn on before the upper channel layer 105, thereby achieving an ultra-steep subthreshold swing of less than 60mV / dec.

[0091] As can be seen, the technical solution provided by this invention solves the problem that the bottom tunneling transistor in a conventional hybrid conduction mechanism gate-around transistor cannot highlight the ultra-steep subthreshold swing characteristic of less than 60mV / dec in the subthreshold region.

[0092] If the difference between the work function of the bottom control gate 108 and the work function of the gate-around-the-channel control gate 109 is too small, the bottom TFET current will still be masked by the current of the upper gate-around-the-channel in the subthreshold region, preventing the device from achieving a subthreshold swing below 60mV / dec. If the difference between the work function of the bottom control gate 108 and the work function of the gate-around-the-channel control gate 109 is too large, the peak phenomenon in the device characteristics will be very obvious.

[0093] Therefore, in a preferred embodiment, the difference between the work function of the bottom control gate 108 and the work function of the surrounding gate channel control gate 109 is 0.5eV-0.9eV.

[0094] In one embodiment, for an N-type device, the work function of the bottom control gate is 0.5 eV-0.9 eV smaller than that of the surrounding gate channel control gate;

[0095] In another implementation, for P-type devices, the work function of the bottom control gate is 0.5 eV-0.9 eV greater than that of the surrounding gate channel control gate;

[0096] In one embodiment, the bottom control gate 108 is a P-type control gate or an N-type control gate; the surrounding gate channel control gate 109 is an N-type control gate or a P-type control gate; the bottom control gate and the surrounding gate channel control gate have different doping types.

[0097] Specifically, the P-type control gate can be formed from metallic materials such as: TiN, Ti, TiAlN, TaC, TaCN, TaSiN, TaSi2, NiSi2, Mn, Zr, ZrSi2, TaN, Ru, Al, Mo, MoSi2, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal nitrides, metal aluminates, zirconium silicate, zirconium aluminate, and combinations thereof.

[0098] Specifically, the N-type control gate can be made of materials such as TiAlN, Ti, Ag, Al, TaAl, TaAlC, TaC, TaCN, TaSiN, Mn, Zr, other suitable N-type work function materials, or combinations thereof.

[0099] In one specific embodiment, for an N-type device, the bottom control gate 108 is a P-type control gate; the gate surrounding channel control gate 109 is an N-type control gate. In another specific embodiment, the material of the bottom control gate 108 is doped polycrystalline silicon, cobalt, nickel, other metals, or metal silicides. In a specific example, the material of the bottom control gate 108 is TiN;

[0100] In one embodiment, the material of the enclosure trench control fence 109 is TiAl.

[0101] In another specific embodiment, for a P-type device, the bottom control gate is an N-type control gate; the surrounding gate channel control gate is a P-type control gate. In one specific example, the bottom control gate 108 is made of TiAl; the surrounding gate channel control gate 109 is made of TiN.

[0102] In one embodiment, the thickness of the bottom control gate 108 along the second direction is 20-200 nm; the second direction is perpendicular to the first direction.

[0103] In one embodiment, a first protective layer is further included between the gate-around-the-channel control gate 109 and the bottom control gate 108 near the substrate. The first protective layer is used to protect the bottom control gate 108 from damage during fabrication. In one embodiment, the thickness of the gate-around-the-channel control gate 109 along the second direction is 20–200 nm.

[0104] In one embodiment, the first ion is a P-type ion or an N-type ion.

[0105] In one embodiment, the second ion is a P-type ion or an N-type ion.

[0106] Specifically, the P-type ions are: hydrides, fluorides, or chlorides of boron, specifically one or a combination of the following materials: B2H6, B4H10, B6H10, B10H14, B18H22, BF3, or BCl3; the N-type ions are: hydrides and fluorides of phosphorus and arsenic, specifically one or a combination of the following materials: phosphine, arsine, phosphorus pentafluoride, phosphorus trifluoride, arsenic pentafluoride, or arsenic trifluoride.

[0107] The channel region and the bottom Fin region (i.e., the substrate 101 between the second source region 102 and the second drain region 116) are undoped or lightly doped i-regions;

[0108] For the N-type device, the first source region 103 is N-type doped with a doping concentration of approximately 1E18cm⁻³-1E22cm⁻³, and the first drain region 115 is N-type doped with a doping concentration of approximately [missing information].

[0109] The second source region 102 is P-type doped with a doping concentration of approximately 1E18cm-3-1E22cm-3, and the second drain region 116 is N-type doped with a doping concentration of approximately 1E16cm-3-1E21cm-3.

[0110] For the P-type device, the first source region 103 is P-type doped with a doping concentration of approximately 1E18cm⁻³-1E22cm⁻³, the first drain region 115 is P-type doped with a doping concentration of approximately 1E18cm⁻³-1E20cm⁻³, the second source region 102 is N-type doped with a doping concentration of approximately 1E18cm⁻³-1E22cm⁻³, and the second drain region 116 is P-type doped with a doping concentration of approximately 1E16cm⁻³-1E21cm⁻³.

[0111] In the hybrid conduction mechanism gate-all-around transistor, the thickness and doping concentration of the second source region 102 and the second drain region 116 are important parameters for device design. If the thickness of the second source region 102 or the second drain region 116 is too thin, the bottom tunneling field-effect transistor will have a small impact on the total current, and the improvement on the subthreshold swing characteristics of the device will be limited; if the thickness of the second source region 102 or the second drain region 116 is too thick, it will increase the difficulty of the process and lead to a decrease in device consistency and reliability. The doping concentration of the second source region 102 cannot be too low. If the doping concentration is too low, the resistance of the second source region 102 will increase, and the lower doping will reduce the tunneling probability of the bottom tunneling transistor, making band-to-band tunneling more difficult and the current will decrease. The doping concentration of the second drain region 116 also needs to be controlled within a certain range. If the doping concentration is too low, the resistance of the bottom drain region will increase and the current will decrease; if the doping concentration is too high, the channel bipolar effect of the TFET device will be more significant. Therefore, in a preferred embodiment, the thickness of the second source region 102 and / or the second drain region 116 is 5nm-50nm. In a preferred embodiment, the doped ion concentration in the second source region 102 and / or the second drain region 116 is 1E16cm⁻³-1E22cm⁻³.

[0112] In one embodiment, the material of the second source region 102 and the material of the second drain region 116 are binary or ternary compounds of group II-VI, III-V or IV-IV.

[0113] In one embodiment, the material of the second source region 102 and the material of the second drain region 116 are Si, SiGe, or Ge.

[0114] In one embodiment, the gate-around MOSFET device further includes:

[0115] A channel layer 105 is formed between a first source region 103 and a first drain region 115, and is spaced apart in a direction away from the substrate 101; the gate dielectric layer 106 includes the first gate dielectric layer; the gate dielectric also covers a portion of the surface of the channel layer 105; the surrounding gate control gate 109 also covers the surface of the gate dielectric layer 106; wherein the surrounding gate control gate 109 closest to the substrate 101 also covers the bottom control gate 108.

[0116] Inner wall 104 is formed on the surface of the channel layer 105 between the first source region 103 and the gate dielectric layer 106, and between the first drain region 115 and the gate dielectric layer 106.

[0117] A source metal layer 112, a gate metal layer 113, and a drain metal layer 111 are formed on the surfaces of the first source region 103 and the first drain region 115, respectively, and completely enclose the first source region 103 and the second source region 102, as well as the first drain region 115 and the second drain region 116, respectively; the gate metal layer 113 is formed at the top of the gate surrounding channel control gate 109.

[0118] Interlayer dielectric layer 110 covers the surface of the source metal layer 112, the gate metal layer 113, the drain metal layer 111, and the inner sidewall 104;

[0119] A plurality of metal contact layers 114 penetrate the interlayer dielectric layer 110 and are respectively connected to the source metal layer 112, the gate metal layer 113 and the drain metal layer 111.

[0120] According to an embodiment of the present invention, a method for fabricating a hybrid conduction mechanism gate-all-around transistor is also provided, for fabricating the hybrid conduction mechanism gate-all-around transistor described in any of the foregoing embodiments of the present invention, wherein a schematic flowchart of the fabrication method is shown below. Figure 2 As shown, the method includes:

[0121] S11: Form the gate-all-around MOSFET device, the second source region 102, the second drain region 116, and the bottom control gate 108; wherein, the gate-all-around MOSFET device includes the substrate 101, the first source region 103, the first drain region 115, the first gate dielectric layer, and the gate-all-around channel control gate 109; wherein, the first source region 103 and the first drain region 115 are doped with the first ions; the second source region 102 and the second drain region 116 are respectively formed between the substrate 101 and the first source region 103, and between the substrate 101 and the first drain region 115. The heights of the second source region 102 and the second drain region 116 are not lower than the height of the substrate 101 between the first source region 103 and the first drain region 115; wherein the second drain region 116 is doped with the first ion, and the second source region 102 is doped with the second ion; the first gate dielectric layer characterizes the gate dielectric layer 106 formed on the substrate 101 between the first source region 103 and the first drain region 115; the bottom control gate 108 covers the surface of the first gate dielectric layer; the surrounding gate channel control gate 109 near the substrate 101 covers the surface of the bottom control gate 108;

[0122] The difference in work function between the bottom control gate 108 and the surrounding gate channel control gate 109 is greater than 0.5 eV.

[0123] In one embodiment, step S11, forming the gate-all-around MOSFET device, the second source region 102, the second drain region 116, and the bottom control gate 108, specifically includes:

[0124] S111: Provide one of the substrates 101;

[0125] S112: Forming the sacrificial layer and the channel layer 105; the sacrificial layer and the channel layer 105 are stacked on the substrate 101 with a gap; specifically, the material of the sacrificial layer is SiGe, and the material of the channel layer 105 is Si; in a specific embodiment, the sacrificial layer and the channel layer 105 106 have the following crystal orientation: <100> The Si / SiGe stack has a thickness of approximately 10-20 nm per layer.

[0126] In step S112, the length of the control device channel is approximately 50nm-100nm.

[0127] S113: Etch the sacrificial layer and the channel layer 105 to form a fin structure, and over-etch the substrate 101 on both sides of the fin structure along the first direction to form a first cavity and a second cavity; wherein the first cavity and the second cavity are arranged sequentially along the first direction;

[0128] S114: Form a dummy gate structure and etch the two ends of the sacrificial layer along the first direction to form an inner sidewall 104 cavity; in a specific example, the thickness of the dummy gate structure is about 50 nm.

[0129] S115: Form the inner sidewall 104; the inner sidewall 104 is formed in the cavity of the inner sidewall 104; in a specific example, the inner sidewall 104 is formed by LPCVD deposition of Si3N4.

[0130] S116: Form the second source region 102 and the second drain region 116; the second source region 102 is formed in the first cavity, and the second drain region 116 is formed in the second cavity;

[0131] In one embodiment, step S116, forming the second source region 102 and the second drain region 116, specifically includes:

[0132] S1161: Form a patterned first mask layer; the patterned first mask layer covers the second cavity, the dummy gate structure, and the surface of the inner wall 104;

[0133] S1162: The material filling the first cavity forms the second source region 102, and the patterned first mask layer is removed; in a specific example, the second source region 102 is doped with boron at a concentration of approximately 1E21cm⁻¹. -3 .

[0134] S1163: Form a patterned second mask layer; the patterned second mask layer covers the surface of the second source region 102, the dummy grid structure, and the inner wall 104;

[0135] S1164: The material filling the second drain region 116 in the second cavity forms the second drain region 116, and the patterned second mask layer is removed. In one specific example, the second drain region 116 is doped with As at a concentration of approximately 1E18cm⁻¹. -3 S117: Forming the first source region 103 and the first drain region 115; the first source region 103 and the first drain region 115 are respectively formed at the top of the second source region 102 and the second drain region 116; in a specific example, As is doped in the first source region 103 and the first drain region 115 at a concentration of approximately 1E21cm. -3 Step S117 is followed by: injecting impurities for activation (1050°C, 10s);

[0136] S118: Remove the dummy gate structure and release the channel layer 105 to form a channel cavity;

[0137] S119: Form the gate dielectric layer 106, the surrounding gate channel control gate 109, and the bottom control gate 108;

[0138] In one embodiment, step S119, forming the gate dielectric layer 106, the surrounding gate channel control gate 109, and the bottom control gate 108, specifically includes:

[0139] S1191: Form the gate dielectric layer 106; the gate dielectric layer 106 encloses the channel layer 105, wherein the first gate dielectric layer covers the surface of the substrate 101 between the second drain region 116 and the second source region 102; the device structure after step S1191 is as follows. Figure 3 As shown; specifically, the material of the gate dielectric layer 106 is selected from SiO2, Si3N4, or a high-k gate dielectric material. The method for growing the gate dielectric is selected from one of the following methods: conventional thermal oxidation, nitrogen-doped thermal oxidation, atomic layer deposition, or chemical vapor deposition. In a specific example, the material of the gate dielectric layer 106 is HfO2, and the thickness is 1–5 nm;

[0140] S1192: Deposit bottom control gate material 107 in the channel cavity; the channel cavity refers to the cavity formed between the channel layers 105 after the channel layers 105 are released; the device structure after step S1192 is as follows Figure 4 As shown;

[0141] In one implementation, such as Figure 4As shown, the method of first filling the channel cavity and then performing etching step S1193 is adopted, as follows: Figure 5 As shown, a bottom control gate 108 can be formed on the surface of the first gate dielectric, while the bottom control gate material 107 formed at other locations is removed.

[0142] In another embodiment, unlike the method of first filling the channel cavity and then performing etching step S1193, in step S1192, when depositing the bottom control gate material 107 in the channel cavity, only a certain thickness of bottom control gate material (the same thickness as the bottom control gate 108) is deposited. This is because, in addition to the bottom control gate material of a certain thickness growing on the surface of the first gate dielectric, the same thickness of bottom control gate material also grows on the surface of the channel layer.

[0143] Therefore, in order to protect the bottom control gate material on the surface of the first gate dielectric and remove the bottom control gate material at other locations: in one embodiment, step S1192, after depositing the bottom control gate material 107 in the channel cavity, further includes: forming the first protective layer; the first protective layer is formed on the surface of the bottom control gate 108.

[0144] The formation of the first protective layer specifically includes:

[0145] The material of the first protective layer is filled on the surface of the bottom control gate 108 and in the channel cavity;

[0146] Etching the first protective layer material while retaining a portion of the first protective layer material on the surface of the bottom control gate 108 forms the first protective layer. In one specific example, the material of the first protective layer is the same as the material of the gate metal layer; after the device is fabricated, the first protective layer can be used for conductivity. S1193: Etching the bottom control gate material 107 while retaining a portion of the bottom control gate material 107 on the surface of the first gate dielectric layer, forming the bottom control gate 108 on the surface of the first gate dielectric layer, and a control gate cavity; wherein, the control gate cavity is used for subsequent deposition of the surrounding gate trench control gate 109; the device structure after step S1193 is as follows. Figure 5 As shown;

[0147] In the first embodiment described above, after step S1193, the bottom control gate 108 is directly formed on the surface of the first gate dielectric.

[0148] In the second embodiment described above, after step S1193, a bottom control gate 108 is formed on the surface of the first protective layer, such as... Figure 7As shown. S1194: Form the gate-around-the-channel control gate 109; the gate-around-the-channel control gate 109 surrounds the gate dielectric layer 106; wherein, when forming the gate-around-the-channel control gate 109, the gate-around-the-channel control gate 109 closest to the substrate 101 simultaneously covers the bottom control gate 108. The device structure after step S1194 is as follows. Figure 6 As shown; in one specific example, the material of the surrounding trench control gate 109 is TiAl, or other control gate material; the thickness is 20-200 nm;

[0149] In the first embodiment described above, the bottom perimeter gate channel control gate 109 is formed directly on the surface of the bottom control gate 108;

[0150] In the second embodiment described above, the bottom perimeter trench control grid 109 is formed on the surface of the first protective layer.

[0151] S120: Forming the source metal layer 112, the gate metal layer 113, the drain metal layer 111, the interlayer dielectric layer 110, and the metal contact layer 114, as follows: Figure 1 As shown or Figure 8 As shown (where, Figure 8 (This refers to the device structure fabricated using the second process). The gate metal layer 113 is made of W and has a thickness of 50–200 nm. Furthermore, according to an embodiment of the present invention, an electronic device is also provided, comprising a hybrid conduction mechanism gate-around transistor as described in any of the preceding embodiments of the present invention.

[0152] In addition, according to an embodiment of the present invention, a method for manufacturing an electronic device is also provided, including the method for manufacturing a hybrid conduction mechanism gate-around transistor as described in any of the foregoing embodiments of the present invention.

[0153] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A gate-around transistor with a hybrid conduction mechanism, characterized in that, include: A gate-all-around MOSFET device includes a substrate, a first source region, a first drain region, a first gate dielectric layer, and a gate-all-around channel control gate; the first source region and the first drain region are arranged along a first direction; wherein the first source region and the first drain region are doped with first ions; wherein the first direction is characterized as a direction parallel to the substrate; A second source region and a second drain region are formed between the substrate and the first source region, and the second drain region is formed between the substrate and the first drain region. The heights of both the second source region and the second drain region are not lower than the height of the substrate between the first source region and the first drain region. The second drain region is doped with a first ion, and the second source region is doped with a second ion, and the types of the first ion and the second ion are different. The first gate dielectric layer represents a gate dielectric layer directly formed on the substrate between the first source region and the first drain region. A bottom control gate, the bottom control gate covering the surface of the first gate dielectric layer, and the surrounding gate channel control gate near the substrate, covering the bottom control gate, wherein the difference in work function between the bottom control gate and the surrounding gate channel control gate is greater than 0.5 eV; The bottom control gate is a P-type control gate, and the surrounding gate channel control gate is an N-type control gate. The work function of the bottom control gate is smaller than that of the surrounding gate channel control gate; or the bottom control gate is an N-type control gate, and the surrounding gate channel control gate is a P-type control gate. The work function of the bottom control gate is larger than that of the surrounding gate channel control gate.

2. The hybrid conduction mechanism gate-around transistor according to claim 1, characterized in that, The difference between the work function of the bottom control gate and the work function of the surrounding gate channel control gate is 0.5eV-0.9eV.

3. The hybrid conduction mechanism gate-around transistor according to claim 2, characterized in that, A first protective layer is also included between the surrounding gate channel control gate and the bottom control gate near the substrate.

4. The gate-around transistor with hybrid conduction mechanism according to claim 3, characterized in that, The bottom control gate is made of doped polycrystalline silicon, cobalt, nickel, other metals, or metal silicides.

5. The hybrid conduction mechanism gate-around transistor according to claim 4, characterized in that, The bottom control gate is made of TiN.

6. The gate-around transistor with hybrid conduction mechanism according to claim 5, characterized in that, The thickness of the bottom control gate along the second direction is 20~200nm.

7. The hybrid conduction mechanism gate-around transistor according to claim 6, characterized in that, The material of the control fence for the surrounding trench is TiAl.

8. The hybrid conduction mechanism gate-around transistor according to claim 7, characterized in that, The thickness of the control gate along the second direction is 20~200nm; the second direction is perpendicular to the first direction.

9. The hybrid conduction mechanism gate-around transistor according to any one of claims 1 or 8, characterized in that, The gate-around MOSFET device further includes: A channel layer is formed between a first source region and a first drain region, and is spaced apart in a direction away from the substrate; the gate dielectric layer includes the first gate dielectric layer; the gate dielectric also covers a portion of the surface of the channel layer; the surrounding gate control gate also covers the surface of the gate dielectric layer; wherein the surrounding gate control gate closest to the substrate also covers the bottom control gate; Inner walls are formed on the surface of the channel layer between the first source region and the gate dielectric layer, and between the first drain region and the gate dielectric layer; A source metal layer, a gate metal layer, and a drain metal layer; the source metal layer and the drain metal layer are respectively formed on the surfaces of the first source region and the first drain region, and respectively completely enclose the first source region and the second source region, as well as the first drain region and the second drain region; the gate metal layer is formed at the top of the gate surrounding channel control gate; An interlayer dielectric layer covers the surfaces of the source metal layer, the gate metal layer, the drain metal layer, and the inner sidewall; Several metal contact layers penetrate the interlayer dielectric layer and are respectively connected to the source metal layer, the gate metal layer and the drain metal layer.

10. A method for fabricating a hybrid conduction mechanism gate-all-around transistor, used to fabricate the hybrid conduction mechanism gate-all-around transistor according to any one of claims 1-9, characterized in that, include: A gate-all-around MOSFET device is formed, comprising a second source region, a second drain region, and a bottom control gate; wherein the gate-all-around MOSFET device includes a substrate, a first source region, a first drain region, a first gate dielectric layer, and a gate-all-around channel control gate; wherein the first source region and the first drain region are doped with the first ion; the second source region and the second drain region are respectively formed between the substrate and the first source region, and between the substrate and the first drain region, and the height of the second source region and the second drain region is not less than the height of the substrate between the first source region and the first drain region; wherein the second drain region is doped with the first ion, and the second source region is doped with the second ion; the first gate dielectric layer characterizes the gate dielectric layer formed on the substrate between the first source region and the first drain region; the bottom control gate covers the surface of the first gate dielectric layer; the gate-all-around channel control gate covers the surface of the bottom control gate; wherein the difference in work function between the bottom control gate and the gate-all-around channel control gate is greater than 0.5 eV; The bottom control gate is a P-type control gate, and the surrounding gate channel control gate is an N-type control gate. The work function of the bottom control gate is smaller than that of the surrounding gate channel control gate; or the bottom control gate is an N-type control gate, and the surrounding gate channel control gate is a P-type control gate. The work function of the bottom control gate is larger than that of the surrounding gate channel control gate.

11. The method for fabricating a hybrid conduction mechanism gate-around transistor according to claim 10, characterized in that, The formation of the gate-around MOSFET device, the second source region, the second drain region, and the bottom control gate specifically includes: Provide one of the aforementioned substrates; A sacrificial layer and a channel layer are formed; the sacrificial layer and the channel layer are stacked on the substrate at intervals; The sacrificial layer and the channel layer are etched to form a fin structure, and the substrate on both sides of the fin structure along the first direction is over-etched to form a first cavity and a second cavity; wherein the first cavity and the second cavity are arranged sequentially along the first direction; A false gate structure is formed, and the two ends of the sacrificial layer along the first direction are etched to form an inner sidewall cavity; The inner wall is formed; the inner wall is formed in the cavity of the inner wall; The second source region and the second drain region are formed; the second source region is formed in the first cavity, and the second drain region is formed in the second cavity; The first source region and the first drain region are formed; the first source region and the first drain region are respectively formed at the top of the second source region and the second drain region; Remove the dummy gate structure and release the channel layer to form a channel cavity; The gate dielectric layer, the surrounding gate trench control gate, and the bottom control gate are formed; The source metal layer, the gate metal layer, the drain metal layer, the interlayer dielectric layer, and the metal contact layer are formed.

12. The method for fabricating a hybrid conduction mechanism gate-around transistor according to claim 11, characterized in that, The formation of the gate dielectric layer, the surrounding gate channel control gate, and the bottom control gate specifically includes: The gate dielectric layer is formed; the gate dielectric layer encloses the channel layer and covers the surface of the substrate between the second drain region and the second source region; Deposit bottom control grid material in the channel cavity; The bottom control gate material is etched, and a portion of the bottom control gate material on the surface of the first gate dielectric layer is retained to form the bottom control gate on the surface of the first gate dielectric layer; The surrounding gate channel control gate is formed; the surrounding gate channel control gate encloses the gate dielectric layer; wherein, when the surrounding gate channel control gate is formed, the surrounding gate channel control gate closest to the substrate simultaneously covers the bottom control gate.

13. The method for fabricating a hybrid conduction mechanism gate-around transistor according to claim 12, characterized in that, After depositing the bottom control gate material in the channel cavity, the method further includes: A first protective layer is formed on the surface of the bottom control gate.

14. An electronic device, characterized in that, Includes the hybrid conduction mechanism gate-around transistor as described in any one of claims 1-9.

15. A method for manufacturing an electronic device, characterized in that, The method for fabricating a hybrid conduction mechanism gate-around transistor as described in any one of claims 10-13.

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