Transistor, transistor manufacturing method, pixel circuit, and display panel

Abstract

The application discloses a transistor, a transistor preparation method, a pixel circuit and a display panel. The transistor comprises a substrate, a first gate arranged on one side of the substrate, an active layer arranged on the side, away from the substrate, of the first gate, and partially overlapping the first gate in the thickness direction of the transistor, and a second gate arranged on the side, away from the substrate, of the active layer, partially overlapping the active layer in the thickness direction of the transistor, and not overlapping the projection of the first gate on the active layer, and the second gate and the first gate are electrically connected. By arranging the first gate and the second gate in the transistor and electrically connecting the second gate and the first gate, the requirements of high current output capability and large subthreshold swing can be met simultaneously on the same transistor, thereby solving the problem of uneven brightness display and improving the use performance of the transistor.

Description

Technical Field

[0001] This invention belongs to the field of display technology, and particularly relates to a transistor, a transistor fabrication method, a pixel circuit, and a display panel. Background Technology

[0002] With the advancement of technology, digital display panels such as those used in smartphones and tablets have become widely used. As display technology develops, people have increasingly higher requirements for the display quality of display panels.

[0003] Display panels typically include pixel circuits and light-emitting devices. The pixel circuits drive the light-emitting devices to emit light, thereby enabling the display of images. The pixel circuits include thin-film transistors.

[0004] However, due to the structural limitations of existing transistors, their performance cannot meet the requirements.

[0005] Therefore, there is an urgent need for a new transistor, a transistor fabrication method, a pixel circuit, and a display panel. Summary of the Invention

[0006] This invention provides a transistor, a transistor fabrication method, a pixel circuit, and a display panel. By simultaneously setting a first gate and a second gate in the transistor and electrically connecting the second gate and the first gate, the requirements for high current output capability and large subthreshold swing can be met on the same transistor, thereby solving the problem of uneven brightness display and improving the performance of the transistor.

[0007] In a first aspect, embodiments of the present invention provide a transistor, comprising: a substrate; a first gate disposed on one side of the substrate; an active layer disposed on the side of the first gate away from the substrate, wherein the active layer and the first gate partially overlap along the thickness direction of the transistor; and a second gate disposed on the side of the active layer away from the substrate, wherein the active layer and the second gate partially overlap along the thickness direction of the transistor, wherein the orthographic projection of the second gate on the active layer and the orthographic projection of the first gate on the active layer do not overlap, and the second gate and the first gate are electrically connected.

[0008] Secondly, embodiments of the present invention provide a pixel circuit, including a driving transistor and a switching transistor, wherein the driving transistor is the transistor in any of the above embodiments.

[0009] Thirdly, embodiments of the present invention provide a display panel including the pixel circuits in any of the above embodiments.

[0010] Compared with related technologies, the transistor provided in this embodiment of the invention includes a substrate, a first gate, an active layer, and a second gate. That is, the transistor includes two gates, a first gate and a second gate, which are respectively located on both sides of the active layer along the thickness direction of the transistor. The orthographic projection of the second gate on the active layer and the orthographic projection of the first gate on the active layer do not overlap and do not interfere with each other. The second gate and the first gate are electrically connected to each other. By utilizing the difference in subthreshold swing corresponding to the top gate and bottom gate configurations, the subthreshold swing of the transistor can be increased, while retaining high current output capability. This improves the problem of uneven brightness display that easily occurs when the transistor is applied to a display panel, and improves the performance of the transistor. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of a transistor structure provided according to an embodiment of the present invention; Figure 2 This is a top view of a transistor provided according to an embodiment of the present invention; Figure 3 This is provided by one embodiment of the present invention. Figure 2 Schematic diagram of the cross section at point AA; Figure 4 This is a top view of a transistor provided according to another embodiment of the present invention; Figure 5 This is provided by one embodiment of the present invention. Figure 4 Schematic diagram of the cross section at point BB; Figure 6 This is a flowchart of a transistor fabrication method according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure obtained during the fabrication process of a transistor fabrication method according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure obtained during the fabrication process of a transistor fabrication method according to another embodiment of the present invention; Figure 9 This is a schematic diagram of the structure obtained during the fabrication process of a transistor fabrication method according to another embodiment of the present invention; Figure 10 This is a schematic diagram of the structure obtained during the fabrication process of a transistor fabrication method according to another embodiment of the present invention; Figure 11This is a schematic diagram of the structure obtained during the fabrication process of a transistor fabrication method according to another embodiment of the present invention; Figure 12 This is a schematic diagram of the structure obtained during the fabrication process of a transistor fabrication method according to another embodiment of the present invention; Figure 13 This is a schematic diagram of the structure obtained during the fabrication process of a transistor fabrication method according to another embodiment of the present invention; Figure 14 This is a schematic diagram of the structure obtained during the fabrication process of a transistor fabrication method according to another embodiment of the present invention; Figure 15 This is a schematic diagram of the structure obtained during the fabrication process of a transistor fabrication method according to another embodiment of the present invention; Figure 16 This is a schematic diagram of the structure obtained during the fabrication process of a transistor fabrication method according to another embodiment of the present invention; Figure 17 This is a schematic diagram of the structure obtained during the fabrication process of a transistor fabrication method according to another embodiment of the present invention; Figure 18 This is a schematic diagram of the structure obtained during the fabrication process of a transistor fabrication method according to another embodiment of the present invention; Figure 19 This is a schematic diagram of the structure obtained during the fabrication process of a transistor fabrication method according to another embodiment of the present invention; Figure 20 This is a schematic diagram of the structure obtained during the fabrication process of a transistor fabrication method according to another embodiment of the present invention; Figure 21 This is a schematic diagram of the structure obtained during the fabrication process of a transistor fabrication method according to another embodiment of the present invention; Figure 22 This is a schematic diagram of the structure obtained during the fabrication process of a transistor fabrication method according to another embodiment of the present invention; Figure 23 This is a schematic diagram of a pixel circuit according to an embodiment of the present invention; Figure 24 This is a schematic diagram of a display panel provided according to an embodiment of the present invention. Detailed Implementation

[0013] The features and exemplary embodiments of various aspects of the present invention will now be described in detail. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of the invention by illustrating examples of the invention.

[0014] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0015] In existing technologies, subthreshold swing (SS) is a crucial parameter for thin-film transistors (TFTs) when operating in the subthreshold state and used as logic switches. Also known as the S-factor, it measures the rate of transition between the on and off states of a TFT. When SS is small, the gate-source voltage variation of the TFT is large, which is detrimental to low grayscale expansion and can easily lead to uneven brightness at low grayscale levels. Conversely, when SS is large, the output current of the TFT is small, which is unfavorable for achieving high grayscale brightness. Currently, top-gate oxide transistors (BTOs) have small SS and strong current output capability. Bottom-gate oxide transistors (BTOs) have large SS and weak current output capability, making it impossible to simultaneously meet the requirements of high current output capability and large SS.

[0016] To solve the above problems, the transistor provided in this embodiment of the invention simultaneously provides a first gate 200 and a second gate 400 in the transistor, and makes the second gate 400 and the first gate 200 electrically connected. This allows the transistor to simultaneously meet the requirements of high current output capability and large SS, thereby solving the problem of uneven brightness display.

[0017] To better understand this invention, the following is combined with... Figures 1 to 24 The transistor, transistor fabrication method, pixel circuit, and display panel according to embodiments of the present invention will be described in detail.

[0018] Please refer to the following: Figures 1 to 2 , Figure 1 This is a schematic diagram of a transistor structure provided according to an embodiment of the present invention; Figure 2 This is a top view of a transistor provided according to an embodiment of the present invention.

[0019] This invention provides a transistor, comprising: a substrate 100; a first gate 200 disposed on one side of the substrate 100; an active layer 300 disposed on the side of the first gate 200 away from the substrate 100, with the active layer 300 and the first gate 200 partially overlapping along the thickness direction Z of the transistor; and a second gate 400 disposed on the side of the active layer 300 away from the substrate 100, with the active layer 300 and the second gate 400 partially overlapping along the thickness direction Z of the transistor. The orthographic projection of the second gate 400 on the active layer 300 and the orthographic projection of the first gate 200 on the active layer 300 do not overlap, and the second gate 400 and the first gate 200 are electrically connected.

[0020] The transistor provided in this embodiment of the invention includes a substrate 100, a first gate 200, an active layer 300, and a second gate 400. Specifically, the transistor includes two gates, the first gate 200 and the second gate 400, located on opposite sides of the active layer 300 along the thickness direction Z of the transistor. The orthographic projection of the second gate 400 onto the active layer 300 and the orthographic projection of the first gate 200 onto the active layer 300 do not overlap and do not interfere with each other. The second gate 400 and the first gate 200 are electrically connected to each other. This utilizes the difference in subthreshold swing (SS) corresponding to the top-gate and bottom-gate configurations to increase the transistor's subthreshold swing while retaining high current output capability. This improves the performance of the transistor, addressing the problem of uneven brightness display that often occurs when the transistor is applied to a display panel.

[0021] Optionally, along the thickness direction Z of the transistor, the active layer 300 and the first gate 200 partially overlap, and the second gate 400 is electrically connected to the first gate 200. Considering that the orthographic projection of the second gate 400 on the active layer 300 and the orthographic projection of the first gate 200 on the active layer 300 do not overlap, the first gate 200 and the second gate 400 need to overlap with different regions of the active layer 300 to avoid mutual interference.

[0022] In this embodiment, the second gate 400 and the first gate 200 are electrically connected, meaning that the second gate 400 and the first gate 200 transmit the same signal, but the relative positions of the second gate 400, the first gate 200 and the active layer 300 are different.

[0023] Optionally, the active layer 300 may include a metal oxide.

[0024] Optionally, the transistor can be applied to all-oxide OLED display panels. The active layer 300 of the transistor can be made of In2O3-based semiconductor materials, including but not limited to IGZO (Indium Gallium Zinc Oxide), IGO (Indium Gallium Oxide), IZO (Indium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), and IZTO (Indium Zinc Tin Oxide). Among these, In2O3-based semiconductor materials refer to materials whose main component is In2O3, with other elements (such as Ga, Zn, Sn, etc.) doped or compounded onto it.

[0025] Optionally, the first gate 200 may be made of the same material as the second gate 400 to reduce manufacturing costs.

[0026] Optionally, the first gate 200 may be made of any one of molybdenum (Mo), aluminum (Al), silver (Ag), titanium (Ti) or an alloy thereof.

[0027] Optionally, the substrate 100 can be a rigid substrate, such as a glass substrate 100; or it can be a flexible substrate 100, made of materials such as polyimide, polystyrene, polyethylene terephthalate, parylene, polyethersulfone, or polyethylene naphthalate. The substrate 100 is mainly used to support the devices disposed thereon.

[0028] Optionally, the active layer 300 is the core functional layer of the transistor. It is essentially a thin layer of semiconductor material and is the core area for carrier (electron or hole) transport, signal amplification, and switching control.

[0029] Please see Figure 1 In some optional embodiments, along the thickness direction Z of the transistor, the distance a between the orthographic projection of the first gate on the substrate and the orthographic projection of the second gate on the substrate along the first direction is greater than or equal to 1 micrometer and less than or equal to 5 micrometers. The first direction X is parallel to the extension direction of the active layer 300 and parallel to the plane where the substrate 100 is located.

[0030] In this embodiment, to ensure that the orthographic projections of the second gate 400 and the first gate 200 on the active layer 300 do not overlap, the orthographic projections of the first gate 200 and the second gate 400 on the substrate 100 can be spaced apart along the thickness direction Z of the transistor. The size of the gap is the distance along the first direction X mentioned above. The larger the distance, the less mutual interference may occur between the first gate 200 and the second gate 400. However, this requires a larger extension length of the active layer 300, which affects the overall size of the transistor.

[0031] Therefore, along the thickness direction Z of the transistor, the distance 'a' between the orthogonal projections of the first gate and the second gate on the substrate along the first direction should not be too large. Conversely, the distance 'a' between the orthogonal projections of the first gate and the second gate on the substrate along the first direction should not be too small either. If it is too small, it may cause the first gate 200 and the second gate 400 to interfere with each other, affecting the performance of the transistor.

[0032] Optionally, along the thickness direction Z of the transistor, the distance a between the orthographic projection of the first gate on the substrate and the orthographic projection of the second gate on the substrate along the first direction can be equal to any one of 1 micrometer, 2 micrometer, 3 micrometer, 4 micrometer, and 5 micrometer.

[0033] Please see Figures 2 to 3 , Figure 3 This is provided by one embodiment of the present invention. Figure 2 A cross-sectional view at point AA; In some optional embodiments, the transistor further includes a connection portion 500 disposed on the same layer as the first gate 200, the connection portion 500 and the first gate 200 being electrically connected, and the connection portion 500 and the active layer 300 not overlapping along the thickness direction Z of the transistor. At least one insulating layer is provided between the first gate 200 and the second gate 400, and the connection portion 500 is electrically connected to the second gate 400 through a via K provided in the insulating layer.

[0034] The connection portion 500 is provided to connect the first gate 200 and the second gate 400. At the same time, considering that if the connection portion 500 overlaps with the active layer 300, it may affect the device performance of the transistor. Therefore, it is necessary to restrict the connection portion 500 and the active layer 300 from overlapping along the thickness direction Z of the transistor. In this embodiment, the connection portion 500 can be disposed on the same layer as the first gate 200. Along the direction parallel to the plane where the substrate 100 is located, the connection portion 500 is disposed away from the active layer 300 relative to the first gate 200 to avoid the active layer 300. Then, it is electrically connected to the second gate 400 through the via K provided in the insulating layer.

[0035] In this embodiment, along the thickness direction Z of the transistor, the via K of the insulating layer also needs to not overlap with the active layer 300 and should be set away from the active layer 300.

[0036] Optionally, the connection portion 500 can be formed together with the first gate 200 through the same process, that is, the connection portion 500 and the first gate 200 are made of the same material to reduce production costs.

[0037] Optionally, two insulating layers are provided between the first gate 200 and the second gate 400. One insulating layer is provided between the first gate 200 and the active layer 300, and the other insulating layer is provided between the second gate 400 and the active layer 300. Vias K are provided in both insulating layers, and the vias K on the two insulating layers are connected.

[0038] Please see Figures 4 to 5 , Figure 4 This is a top view of a transistor provided according to another embodiment of the present invention; Figure 5 This is provided by one embodiment of the present invention. Figure 4 A cross-sectional view at point BB; In some other optional embodiments, the transistor further includes a connection portion 500 disposed on the same layer as the second gate 400, the connection portion 500 and the second gate 400 being electrically connected, and the connection portion 500 and the active layer 300 not overlapping along the thickness direction Z of the transistor; at least one insulating layer is provided between the first gate 200 and the second gate 400, and the connection portion 500 is electrically connected to the first gate 200 through a via K provided in the insulating layer.

[0039] In addition to being disposed on the same layer as the first gate 200, the connection portion 500 can also be disposed on the same layer as the second gate 400. That is, two connection portions 500 can be disposed simultaneously, with the two connection portions 500 disposed on the same layer as the first gate 200 and the second gate 400, respectively. Alternatively, only one connection portion 500 can be disposed. For example, in this embodiment, one connection portion 500 disposed on the same layer as the second gate 400 can be disposed along a direction parallel to the plane of the substrate 100, so that the connection portion 500 is disposed away from the active layer 300 relative to the second gate 400 to avoid the active layer 300, and then electrically connected to the first gate 200 through a via K disposed in the insulating layer.

[0040] Optionally, the connection portion 500 and the second gate 400 can be formed together in the same process, that is, the connection portion 500 and the second gate 400 are made of the same material to reduce production costs.

[0041] Please see Figure 4In some optional embodiments, along the thickness direction Z of the transistor, the distance b between the orthographic projection of the connection portion on the substrate and the orthographic projection of the active layer on the substrate along the second direction is greater than or equal to 2 micrometers and less than or equal to 8 micrometers. The second direction Y intersects with the first direction X and is parallel to the plane where the substrate 100 is located.

[0042] Along the thickness direction Z of the transistor, the distance between the orthographic projection of the connection portion 500 on the substrate 100 along the second direction Y and the orthographic projection of the active layer 300 on the substrate 100 should not be too close. If they are too close, it may cause interaction between the connection portion 500 and the active layer 300, affecting the device performance of the transistor. It should also not be too far apart, as this will increase the size of the transistor device and make it difficult to arrange.

[0043] Optionally, along the thickness direction Z of the transistor, the distance b between the orthographic projection of the connection portion on the substrate and the orthographic projection of the active layer on the substrate along the second direction can be equal to any one of 2 micrometers, 3 micrometers, 4 micrometers, 5 micrometers, 6 micrometers, 7 micrometers, and 8 micrometers.

[0044] Please see Figure 1 In some optional embodiments, the active layer 300 includes a first channel region L1 and a second channel region L2, which are spaced apart along the extension direction of the active layer 300; along the thickness direction Z of the transistor, the orthographic projection of the first gate 200 on the substrate 100 covers the orthographic projection of the first channel region L1 on the substrate 100, and the orthographic projection of the second gate 400 on the substrate 100 covers the orthographic projection of the second channel region L2 on the substrate 100.

[0045] It should be noted that, in this embodiment, the transistor has two gates, a first gate 200 and a second gate 400. Along the thickness direction Z of the transistor, the orthographic projection of the second gate 400 onto the active layer 300 does not overlap with the orthographic projection of the first gate 200 onto the active layer 300. Correspondingly, the active layer 300 also includes a first channel region L1 and a second channel region L2 spaced apart. When a large Vds (the voltage applied between the transistor drain 700 and source 600) is applied, a large transverse electric field is formed at the source 600. Electrons are accelerated near the source 600, becoming hot carriers, leading to device degradation. In this structure, since the channel is divided into two parts connected in series, the intermediate conductive region N reduces the channel cross-voltage, decreasing the voltage difference across the channel and thus improving the High Vds effect, preventing uneven brightness display when the transistor is applied to a display panel.

[0046] In this embodiment, along the thickness direction Z of the transistor, the orthogonal projection of the first gate 200 on the substrate 100 covers the orthogonal projection of the first channel region L1 on the substrate 100. That is, the size of the first gate 200 is greater than or equal to the size of the first channel region L1, so as to ensure that the first gate 200 regulates the current of the first channel region L1.

[0047] Similarly, the orthographic projection of the second gate 400 on the substrate 100 covers the orthographic projection of the second channel region L2 on the substrate 100, which can limit the size of the second gate 400 to be greater than or equal to the size of the second channel region L2, so as to ensure the regulation of the current of the second channel region L2 by the second gate 400.

[0048] Please see Figure 1 In some optional embodiments, the transistor further includes a source 600 and a drain 700, both of which are disposed on the side of the second gate 400 away from the substrate 100, or the source 600, drain 700 and the second gate 400 are disposed on the same layer, and the source 600 and drain 700 are electrically connected to the active layer 300 respectively. Along the thickness direction Z of the transistor, the source 600 does not overlap with the first gate 200 and the second gate 400, and the drain 700 does not overlap with the first gate 200 and the second gate 400, respectively.

[0049] Since the source 600 and drain 700 need to be connected to the active layer 300 respectively, when the source 600 and drain 700 are both located on the side of the second gate 400 away from the substrate 100, the connection portion between the source 600 and the active layer 300 and the connection portion between the drain 700 and the active layer 300 should be arranged to avoid the second gate 400. Alternatively, when the source 600, drain 700 and second gate 400 are arranged on the same layer, the source 600, drain 700 and second gate 400 should be insulated from each other.

[0050] Along the thickness direction Z of the transistor, the source 600 does not overlap with the first gate 200 and the second gate 400, respectively. That is, the orthographic projection of the source 600 on the substrate 100 does not coincide with the orthographic projections of the first gate 200 and the second gate 400 on the substrate 100, in order to avoid mutual interference. Similarly, the drain 700 does not overlap with the first gate 200 and the second gate 400, respectively. That is, the orthographic projection of the drain 700 on the substrate 100 does not coincide with the orthographic projections of the first gate 200 and the second gate 400 on the substrate 100, in order to avoid mutual interference.

[0051] Please see Figure 1In some optional embodiments, along the thickness direction Z of the transistor, the distance c1 between the orthographic projection of the source and drain closest to the first gate on the substrate and the orthographic projection of the adjacent first gate on the substrate along the first direction is greater than or equal to 2 micrometers and less than or equal to 9 micrometers.

[0052] It should be noted that, in this embodiment, the one of the source 600 and drain 700 that is closer to the first gate 200 specifically refers to the one with a smaller distance between the orthographic projection of the source 600 and drain 700 on the substrate 100 and the orthographic projection of the first gate 200 on the substrate 100, that is, the one that is disposed adjacent to the first gate 200.

[0053] Since the source 600 and drain 700 are usually connected to the two opposite edge regions of the active layer 300 respectively, and the first gate 200 and the second gate 400 are overlapped in the middle region of the active layer 300, one of the source 600 and drain 700 is located close to the first gate 200 and the other is located close to the second gate 400.

[0054] Along the thickness direction Z of the transistor, the distance c1 between the orthographic projection of the source and drain closest to the first gate on the substrate and the orthographic projection of the adjacent first gate on the substrate along the first direction should not be too large. If it is too large, it will increase the size of the transistor, which is not conducive to the application of the transistor in a high pixel density display panel. It should also not be too small, as it may cause interference between the source 600 and drain 700 closest to the first gate 200 and the first gate 200.

[0055] Optionally, along the thickness direction Z of the transistor, the distance c1 between the orthographic projection of the source and drain closest to the first gate on the substrate and the orthographic projection of the adjacent first gate on the substrate along the first direction can be any one of 2 micrometers, 3 micrometers, 4 micrometers, 5 micrometers, 6 micrometers, 7 micrometers, 8 micrometers, and 9 micrometers.

[0056] Please see Figure 2 Optionally, along the thickness direction Z of the transistor, the distance c2 between the orthographic projection of the source and drain closest to the second gate on the substrate and the orthographic projection of the adjacent second gate on the substrate along the first direction is greater than or equal to 2 micrometers and less than or equal to 9 micrometers. The first direction X is parallel to the extension direction of the active layer 300 and parallel to the plane where the substrate 100 is located.

[0057] Similarly, the source 600 and drain 700 that is closer to the second gate 400 should not be too close to the second gate 400. Optionally, the distance c2 between the orthographic projection of the source and drain that is closer to the second gate on the substrate and the orthographic projection of the adjacent second gate on the substrate along the first direction can be any one of 2 micrometers, 3 micrometers, 4 micrometers, 5 micrometers, 6 micrometers, 7 micrometers, 8 micrometers, and 9 micrometers.

[0058] Please see Figure 6 The present invention also provides a method for fabricating a transistor, comprising the following steps: S110: Provides substrate 100, such as Figure 7 As shown; S120: A first gate 200 is formed on one side of the substrate 100, such as Figure 8 As shown; S130: An active layer 300 is formed on the side of the first gate 200 facing away from the substrate 100. Along the thickness direction Z of the transistor, the active layer 300 and the first gate 200 at least partially overlap, such as... Figure 9 As shown; S140: A second gate 400 is formed on the side of the active layer 300 facing away from the substrate 100. Along the thickness direction Z of the transistor, the active layer 300 and the second gate 400 at least partially overlap. The orthographic projection of the second gate 400 on the active layer 300 and the orthographic projection of the first gate 200 on the active layer 300 do not overlap. The second gate 400 and the first gate 200 are electrically connected. Figure 19 As shown.

[0059] In the transistor fabrication method provided in this embodiment of the invention, the transistor needs to form a first gate 200 and a second gate 400 respectively. The first gate 200 and the second gate 400 are located on both sides of the active layer 300 along the thickness direction Z of the transistor. The orthographic projection of the second gate 400 on the active layer 300 and the orthographic projection of the first gate 200 on the active layer 300 do not overlap and do not interfere with each other. The second gate 400 and the first gate 200 are electrically connected to each other. By utilizing the difference between the first gate 200 and the second gate 400SS, the subthreshold swing (SS) can be increased while retaining the high current output capability. This improves the problem of uneven brightness display in the display panel when the transistor is applied to the display panel, and improves the performance of the transistor.

[0060] In step S110, the substrate 100 can be a rigid substrate, such as a glass substrate; or it can be a flexible substrate, and its material can be polyimide, polystyrene, polyethylene terephthalate, poly(p-xylene), polyethersulfone, or polyethylene naphthalate.

[0061] In step S120, the first gate 200 with the desired pattern can be formed by photolithography. The material of the first gate 200 can be any one of molybdenum (Mo), aluminum (Al), silver (Ag), titanium (Ti) or an alloy material.

[0062] In step S130, an active material layer 301 can be formed first. After forming the active material layer 301, it can be subjected to a conductor-enhancing treatment to change its conductivity type or increase its carrier concentration, transforming the originally non-conductive or weakly conductive active material layer 301 into an active layer 300 with the required conductivity, thereby constituting the channel region or active functional region of the transistor. Specifically, doping treatment can be performed during or after the formation of the active material layer 301 to make the active material layer 301 conductive, thus forming the active layer 300.

[0063] Along the thickness direction Z of the transistor, the active layer 300 and the first gate 200 overlap at least partially, which is the basis for the transistor to realize the electric field control function: the first gate 200 generates an electric field by applying a voltage. This electric field needs to penetrate the gate insulating layer and act on the active layer 300 (channel region). The at least partial overlap of the two in the thickness direction can ensure that the electric field can effectively cover the key area of ​​the active layer 300, thereby realizing precise control of the conduction and cutoff of the carriers in the active layer 300, ensuring the normal operation of the transistor, and meeting the pixel driving requirements of the display panel.

[0064] In step S140, the orthographic projection of the second gate 400 on the active layer 300 does not overlap with the orthographic projection of the first gate 200 on the active layer 300. At the same time, the second gate 400 and the first gate 200 are electrically connected to achieve precise control of the channel of the active layer 300 in a coordinated manner.

[0065] In some optional embodiments, the step of forming the active layer 300 on the side of the first gate 200 facing away from the substrate 100 includes: An active material layer 301 is formed on the side of the first gate 200 facing away from the substrate 100, such as Figure 10 As shown; A second gate material layer 401 is formed on the side of the active material layer 301 facing away from the substrate 100, such as Figure 11 As shown; The second gate material layer 401 is patterned to form a first shielding portion Z1 and a second shielding portion Z2. Along the thickness direction Z of the transistor, the first shielding portion Z1 at least partially overlaps with the first gate 200 and the active material layer 301, while the second shielding portion Z2 does not overlap with the first gate 200, and the second shielding portion Z2 at least partially overlaps with the active material layer 301. Figure 12 As shown; The active material layer 301 is conductively processed using the first shielding portion Z1 and the second shielding portion Z2 as shielding portions to form an active layer 300. The active layer 300 includes a first channel region L1 corresponding to the first gate 200 and a second channel region L2 corresponding to the second gate 400, such as... Figure 13 As shown.

[0066] It should be noted that the active material layer 301 is formed on the side of the first gate 200 away from the substrate 100, and an insulating layer needs to be formed between the active material layer 301 and the first gate 200 to avoid direct connection between the two.

[0067] Next, a second gate material layer 401 is formed and patterned to form a first shielding portion Z1 and a second shielding portion Z2. The first shielding portion Z1 is used to form a first channel region L1 that overlaps with the first gate 200. That is, the first shielding portion Z1 needs to shield the part of the active material layer 301 that needs to form the first channel region L1, and the second shielding portion Z2 needs to shield the part of the active material layer 301 that needs to form the second channel region L2. Then, the active material layer 301 is made conductive, which can be an ion implantation (IMP) process, using the first shielding portion Z1 and the second shielding portion Z2 as masks to selectively implant ions into the active material layer 301.

[0068] Optionally, the active material layer 301 region covered by the first shielding portion Z1 and the second shielding portion Z2 is shielded and protected, and does not accept ion implantation or only accepts light doping treatment, maintaining an intrinsic or weakly conductive state, forming the first channel region L1 and the second channel region L2, which are used to realize conduction and turn-off control under the electric field control of the first gate 200 and the second gate 400; the active material layer 301 region not covered by the shielding portion accepts ion implantation and realizes heavy doping and conductor formation, forming a highly conductive region outside the channel region, which is used as the source 600 region, drain 700 region or electrode lead-out region of the transistor.

[0069] In this embodiment, the first shielding portion Z1 and the second shielding portion Z2 formed by the second gate material layer 401 can be used as a mask to perform targeted conductor treatment on the active material layer 301, eliminating the need to provide an additional mask, effectively reducing the manufacturing cost, simplifying the manufacturing process, and improving the manufacturing efficiency.

[0070] In some optional embodiments, the step of patterning the second gate material layer 401 includes: A photoresist layer 800 is formed on the side of the second gate material layer 401 facing away from the substrate 100, such as Figure 14 As shown; Using a semi-transparent photomask as a shield, the photoresist layer 800 is patterned to form a first photolithographic portion 801 and a second photolithographic portion 802. The thickness of the first photolithographic portion 801 is less than the thickness of the second photolithographic portion 802. Figure 15 As shown; The second gate material layer 401 is etched using the first photolithography section 801 and the second photolithography section 802 as shields to form the first shielding section Z1 and the second shielding section Z2, as follows. Figure 16 As shown; Then, the unshielded portion of the active material layer 301 can be conductively processed using the first shielding portion Z1 and the second shielding portion Z2 as shielding parts to form the active layer 300, such as... Figure 17 As shown.

[0071] Optionally, between the steps of performing a conductor-forming process on the unshielded portion of the active material layer 301 using the first shielding portion Z1 and the second shielding portion Z2 as shielding to form an active layer 300, the active layer 300 including a first channel region L1 corresponding to the first gate 200 and a second channel region L2 corresponding to the second gate 400, and the step of forming the second gate 400 on the side of the active layer 300 away from the substrate 100, the following steps are included: Remove the first photolithography section 801 and part of the second photolithography section 802, such as... Figure 18 As shown.

[0072] It should be noted that, in this embodiment, a semi-transparent light mask can be used as a shield. By adjusting and controlling the light transmittance of different areas of the semi-transparent light mask, the thickness of the first photolithographic part 801 formed is less than the thickness of the second photolithographic part 802.

[0073] The reason for limiting the thickness of the first photolithographic portion 801 to be less than the thickness of the second photolithographic portion 802 is that the first shielding portion Z1 needs to be removed later, while the second shielding portion Z2 needs to be retained to form the second gate 400. Therefore, when removing the first photolithographic portion 801 and part of the second photolithographic portion 802, since the second photolithographic portion 802 is thicker, after completely removing the first photolithographic portion 801, a part of the second photolithographic portion 802 can still be retained on the side of the second shielding portion Z2 away from the substrate 100, so as to protect the second shielding portion Z2 from being etched when the first shielding portion Z1 is removed later.

[0074] By adjusting factors such as etching time and etching solution concentration, it can be ensured that while removing the first photolithography part 801, a portion of the second photolithography part 802 is retained.

[0075] Optionally, the step of forming the second gate 400 on the side of the active layer 300 facing away from the substrate 100 includes: Remove the first blocking portion Z1 and the second photolithography portion 802, retaining the second blocking portion Z2 to form the second gate 400, as follows. Figure 19 As shown.

[0076] Since the first photolithography portion 801 covering the first shielding portion Z1 has been removed in the previous steps, while a portion of the second photolithography portion 802 covering the second shielding portion Z2 is still retained, the second photolithography portion 802 can also protect the second shielding portion Z2. While etching the first shielding portion Z1, the second photolithography portion 802 can be removed at the same time, and the second shielding portion Z2 can be left unetched and retained as the second gate 400.

[0077] In some optional embodiments, between the step of forming the first gate 200 on one side of the substrate 100 and the step of forming the active layer 300 on the side of the first gate 200 away from the substrate 100, the method further includes: forming a first insulating layer J1 on the side of the first gate 200 away from the substrate 100. Between the step of forming an active layer 300 on the side of the first gate 200 away from the substrate 100 and the step of forming a second gate 400 on the side of the active layer 300 away from the substrate 100, the method further includes: forming a second insulating layer J2 on the side of the active layer 300 away from the substrate 100.

[0078] To ensure mutual insulation between the first gate 200 and the active layer 300, and between the second gate 400 and the active layer 300, a first insulating layer J1 and a second insulating layer J2 can be correspondingly provided to achieve insulation isolation. Optionally, the first insulating layer J1 and the second insulating layer J2 can be prepared using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or thermal oxidation. Optionally, the materials of the first insulating layer J1 and the second insulating layer J2 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0079] Please see Figure 20 and Figure 21 In some optional embodiments, between the step of forming the second insulating layer J2 on the side of the active layer 300 facing away from the substrate 100 and the step of forming the second gate material layer 401 on the side of the active material layer 301 facing away from the substrate 100, the method further includes: The first insulating layer J1 and the second insulating layer J2 are etched to form a via K.

[0080] The via K is formed so that the subsequently formed second gate 400 can be connected to the connection portion 500 (which is on the same layer as the first gate 200) through the via K, such as... Figure 20 As shown, or, the connection portion 500 disposed on the same layer as the second gate 400 can be connected to the first gate 200 through a via K, as shown. Figure 5 and Figure 21As shown.

[0081] Please see Figure 22 Optionally, the step of forming the first gate 200 on one side of the substrate 100 may further include: forming a connection portion 500 disposed on the same layer as the first gate 200 and electrically connected to the first gate 200.

[0082] The connection portion 500 can be formed together with the first gate 200 through the same process, that is, the connection portion 500 and the first gate 200 are made of the same material to reduce production costs.

[0083] Please see Figure 5 Optionally, the step of forming the second gate 400 on the side of the active layer 300 away from the substrate 100 further includes: forming a connection portion 500 disposed on the same layer as the second gate 400 and electrically connected to the second gate 400, the connection portion 500 extending into the via K to be electrically connected to the first gate 200.

[0084] Optionally, the connection portion 500 and the second gate 400 can be formed together in the same process, that is, the connection portion 500 and the second gate 400 are made of the same material to reduce production costs.

[0085] In this embodiment, a connection portion 500 disposed on the same layer as the second gate 400 can be provided. The connection portion 500 is disposed away from the active layer 300 relative to the second gate 400 in a direction parallel to the plane of the substrate 100, so as to avoid the active layer 300. It is then electrically connected to the first gate 200 through a via K disposed in the insulating layer.

[0086] Please see Figure 23 , Figure 23 This is a schematic diagram of a pixel circuit provided according to an embodiment of the present invention; the present invention also provides a pixel circuit including a driving transistor and a switching transistor, wherein the driving transistor is the transistor in any of the above embodiments.

[0087] Optionally, depending on actual needs, the pixel circuit can adopt a 7T1C circuit or a 6T1C circuit, etc., where "T" represents a transistor and "C" represents a capacitor.

[0088] Optionally, the pixel circuit typically includes a driving module, a storage module, a data writing module, a light emission control module, and an initialization module.

[0089] The driving module can be used to provide driving current to the light-emitting elements of the display panel. The driving module includes the driving transistors mentioned above. Specifically, the driving current can be controlled to flow to the light-emitting elements by controlling the on and off states of the driving module.

[0090] The storage module is connected to the drive module and functions to store electrical energy. Optionally, the storage module includes the aforementioned storage capacitor C. The storage module can be used to maintain the potential of the control terminal of the drive module. Specifically, during the charging phase of the pixel unit driving process by the pixel drive circuit, the storage module can be charged. During the read / write light emission phase of the drive process, the storage module can use the voltage charged during the charging phase to maintain the potential of the control terminal of the drive module.

[0091] The data writing module is connected to the driver module and the storage module, and is used to write data signals to the control terminal of the driver module. Specifically, the data writing module is connected to the data signal line VDATA and the first scan signal terminal S1. The data signal line VDATA is used to provide data signals. The first scan signal terminal S1 is used to provide a first scan signal. During the charging phase of the driving process, the data writing module, under the control of the first scan signal, uses the data signal to charge the storage module through the driver module. During the read / write phase of the driving process, the storage module uses the voltage charged during the charging phase to maintain the potential of the control terminal of the driver module, which is equivalent to writing data signals to the control terminal of the driver module.

[0092] The light-emitting control module is connected to the light-emitting element, the driving module, and the power supply voltage input terminal, and is used to control the light-emitting element to emit light. Specifically, the light-emitting control module is connected to the light-emitting control signal terminal EM and the first power supply voltage input terminal VDD. The light-emitting control signal terminal EM is used to provide the light-emitting control signal. The first power supply voltage input terminal VDD is used to provide a high-level signal. During the read / write light-emitting phase of the driving process, the light-emitting control module is turned on under the control of the light-emitting control signal, and can transmit the driving current generated by the high-level signal to the light-emitting element, causing the light-emitting element to emit light.

[0093] The initialization module is connected to the driving module and the light-emitting element, and is used to initialize the control terminal of the driving module and the anode of the light-emitting element, respectively. Specifically, the initialization module is connected to the reference voltage signal terminal VREF and the second scan signal terminal S2. The reference voltage signal terminal VREF is used to provide a reference voltage signal, which is used as the initialization signal. In some examples, the voltage of the reference voltage signal is negative. The second scan signal terminal S2 is used to provide the second scan signal. During the initialization phase of the driving process, the initialization module is turned on under the control of the second scan signal. On the one hand, it uses the reference voltage signal to initialize the control terminal of the driving module, and on the other hand, it charges the voltage of the reference voltage signal into the storage module and the anode of the light-emitting element to initialize the anode of the light-emitting element.

[0094] Please see Figure 23Optionally, the pixel circuit can adopt a 7T1C circuit, where "T" refers to TFT (thin-film transistor) and "C" refers to capacitor. Optionally, the driving module includes a first transistor T1, which is the driving transistor in the pixel driving circuit; the storage module includes a storage capacitor C; the data writing module includes a second transistor T2 and a third transistor T3; the light emission control module includes a fifth transistor T5 and a sixth transistor T6; and the initialization module includes a fourth transistor T4 and a seventh transistor T7.

[0095] The control terminal of the first transistor T1 is connected to the second terminal of the storage capacitor C, the second terminal of the third transistor T3, and the second terminal of the fourth transistor T4. The first terminal of the first transistor T1 is connected to the second terminal of the second transistor T2. The second terminal of the first transistor T1 is connected to the first terminal of the third transistor T3 and the first terminal of the sixth transistor T6. The first terminal of the first transistor T1 is the input terminal of the driving module, and the second terminal of the first transistor T1 is the output terminal of the driving module. The first terminal of the first transistor T1 is the source of the aforementioned driving transistor, and the second terminal of the first transistor T1 is the drain of the aforementioned driving transistor. The control terminal of the first transistor T1 is the gate of the aforementioned driving transistor.

[0096] The control terminal of the second transistor T2 is connected to the second scan signal terminal S2. The first terminal of the second transistor T2 is connected to the data signal line VDATA. The second terminal of the second transistor T2 is connected to the first terminal of the first transistor T1.

[0097] The control terminal of the third transistor T3 is connected to the second scan signal terminal S2. The first terminal of the third transistor T3 is connected to the first terminal of the sixth transistor T6. The second terminal of the third transistor T3 is connected to the second terminal of the storage capacitor C and the second terminal of the fourth transistor T4.

[0098] The control terminal of the fourth transistor T4 is connected to the first scan signal terminal S1. The first terminal of the fourth transistor T4 is connected to the reference voltage signal terminal VREF. The second terminal of the fourth transistor T4 is connected to the second terminal of the storage capacitor C.

[0099] The control terminal of the fifth transistor T5 is connected to the light-emitting control signal terminal EM. The first terminal of the fifth transistor T5 is connected to the first terminal of the storage capacitor C, and the second terminal of the fifth transistor T5 is connected to the first terminal of the first transistor T1.

[0100] The control terminal of the sixth transistor T6 is connected to the light-emitting control signal terminal EM. The first terminal of the sixth transistor T6 is connected to the second terminal of the first transistor T1. The second terminal of the sixth transistor T6 is connected to the anode of the light-emitting element.

[0101] The control terminal of the seventh transistor T7 is connected to the third scan signal terminal S3. The first terminal of the seventh transistor T7 is connected to the reference voltage signal terminal VREF. The second terminal of the seventh transistor T7 is connected to the anode of the light-emitting element D1. The second terminal of the seventh transistor T7 is the first output terminal of the initialization module.

[0102] The first terminal of the storage capacitor C is connected to the first power supply voltage input terminal VDD.

[0103] Please see Figure 24 , Figure 24 This is a schematic diagram of a display panel according to an embodiment of the present invention. The present invention also provides a display panel including the pixel circuitry of any of the above embodiments.

[0104] The display panel provided in the embodiments of the present invention can be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, etc.

[0105] The display panel provided in this embodiment of the invention has the technical effects of the pixel circuit in any of the above embodiments. The explanations of the same or corresponding structures and terms in the above embodiments will not be repeated here.

[0106] The display panel provided in this embodiment of the invention can be applied to mobile phones or any electronic product with display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc. This embodiment of the invention does not impose any special limitations on these.

[0107] The above are merely specific embodiments of the present invention. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the protection scope of the present invention.

[0108] It should also be noted that the exemplary embodiments mentioned in this invention describe methods or systems based on a series of steps or apparatus. However, this invention is not limited to the order of the steps described above; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

Claims

1. A transistor, characterized in that, include; substrate; A first gate is disposed on one side of the substrate; An active layer is disposed on the side of the first gate away from the substrate, and the active layer and the first gate partially overlap along the thickness direction of the transistor; The second gate is disposed on the side of the active layer away from the substrate. Along the thickness direction of the transistor, the active layer and the second gate partially overlap. The orthographic projection of the second gate on the active layer and the orthographic projection of the first gate on the active layer do not overlap. The second gate and the first gate are electrically connected.

2. The transistor according to claim 1, characterized in that, Along the thickness direction of the transistor, the distance between the orthographic projection of the first gate on the substrate and the orthographic projection of the second gate on the substrate along the first direction is greater than or equal to 1 micrometer and less than or equal to 5 micrometers. The first direction is parallel to the extension direction of the active layer and parallel to the plane of the substrate.

3. The transistor according to claim 1, characterized in that, It also includes a connection portion disposed on the same layer as the first gate, the connection portion being electrically connected to the first gate, and the connection portion and the active layer not overlapping along the thickness direction of the transistor; At least one insulating layer is provided between the first gate and the second gate, and the connection portion is electrically connected to the second gate through a via provided in the insulating layer.

4. The transistor according to claim 1, characterized in that, It also includes a connection portion disposed on the same layer as the second gate, the connection portion being electrically connected to the second gate, and the connection portion and the active layer not overlapping along the thickness direction of the transistor; At least one insulating layer is provided between the first gate and the second gate, and the connection portion is electrically connected to the first gate through a via provided in the insulating layer.

5. The transistor according to claim 3 or 4, characterized in that, Along the thickness direction of the transistor, the distance between the orthographic projection of the connection portion on the substrate and the orthographic projection of the active layer on the substrate along the second direction is greater than or equal to 2 micrometers and less than or equal to 8 micrometers. The second direction intersects the first direction, the first direction is parallel to the extension direction of the active layer, and both the first direction and the second direction are parallel to the plane of the substrate.

6. The transistor according to claim 1, characterized in that, The active layer includes a first channel region and a second channel region, which are spaced apart along the extension direction of the active layer. Along the thickness direction of the transistor, the orthographic projection of the first gate on the substrate covers the orthographic projection of the first channel region on the substrate, and the orthographic projection of the second gate on the substrate covers the orthographic projection of the second channel region on the substrate.

7. The transistor according to claim 1, characterized in that, It also includes a source and a drain, both of which are disposed on the side of the second gate away from the substrate, or the source, drain and the second gate are disposed on the same layer, and the source and drain are electrically connected to the active layer respectively; Along the thickness direction of the transistor, the source electrode does not overlap with the first gate electrode and the second gate electrode, and the drain electrode does not overlap with the first gate electrode and the second gate electrode, respectively.

8. The transistor according to claim 7, characterized in that, Along the thickness direction of the transistor, the distance between the orthographic projection of the source and the drain closest to the first gate on the substrate and the orthographic projection of the adjacent first gate on the substrate along the first direction is greater than or equal to 2 micrometers and less than or equal to 9 micrometers. And / or, Along the thickness direction of the transistor, the distance between the orthographic projection of the source and the drain closest to the second gate on the substrate and the orthographic projection of the adjacent second gate on the substrate along a first direction is greater than or equal to 2 micrometers and less than or equal to 9 micrometers, the first direction being parallel to the extension direction of the active layer and parallel to the plane of the substrate.

9. The transistor according to claim 1, characterized in that, The active layer comprises a metal oxide.

10. The transistor according to claim 1, characterized in that, The material of the first gate is the same as the material of the second gate.

11. A method for fabricating a transistor, characterized in that, Includes the following steps: Provide substrate; A first gate is formed on one side of the substrate; An active layer is formed on the side of the first gate away from the substrate, and the active layer and the first gate at least partially overlap along the thickness direction of the transistor; A second gate is formed on the side of the active layer away from the substrate. Along the thickness direction of the transistor, the active layer and the second gate at least partially overlap. The orthographic projection of the second gate on the active layer and the orthographic projection of the first gate on the active layer do not overlap. The second gate and the first gate are electrically connected.

12. The transistor fabrication method according to claim 11, characterized in that, The step of forming an active layer on the side of the first gate away from the substrate includes: An active material layer is formed on the side of the first gate away from the substrate; A second gate material layer is formed on the side of the active material layer opposite to the substrate; The second gate material layer is patterned to form a first shielding portion and a second shielding portion. Along the thickness direction of the transistor, the first shielding portion, the first gate, and the active material layer at least partially overlap, while the second shielding portion and the first gate do not overlap, and the second shielding portion and the active material layer at least partially overlap. The active material layer is conductively processed by using the first shielding portion and the second shielding portion as shielding portions to form the active layer. The active layer includes a first channel region corresponding to the first gate and a second channel region corresponding to the second gate.

13. The transistor fabrication method according to claim 12, characterized in that, The step of patterning the second gate material layer includes: A photoresist layer is formed on the side of the second gate material layer away from the substrate; Using a semi-transparent light mask as a shield, the photoresist layer is patterned to form a first photolithography part and a second photolithography part, wherein the thickness of the first photolithography part is smaller than the thickness of the second photolithography part; The second gate material layer is etched using the first photolithography portion and the second photolithography portion as shields to form the first shielding portion and the second shielding portion; Between the steps of performing a conductor-enhancing process on the active material layer using the first and second shielding portions as shields to form the active layer, wherein the active layer includes a first channel region corresponding to the first gate and a second channel region corresponding to the second gate, and the step of forming the second gate on the side of the active layer away from the substrate, the process includes: Remove the first photolithography portion and part of the second photolithography portion.

14. The transistor fabrication method according to claim 13, characterized in that, The step of forming the second gate on the side of the active layer away from the substrate includes: Remove the first blocking portion and the second photolithography portion, and retain the second blocking portion to form the second gate.

15. The transistor fabrication method according to claim 12, characterized in that, Between the step of forming a first gate on one side of the substrate and the step of forming an active layer on the side of the first gate away from the substrate, the method further includes: forming a first insulating layer on the side of the first gate away from the substrate; Between the step of forming an active layer on the side of the first gate away from the substrate and the step of forming a second gate on the side of the active layer away from the substrate, the method further includes: forming a second insulating layer on the side of the active layer away from the substrate.

16. The transistor fabrication method according to claim 15, characterized in that, Between the step of forming a second insulating layer on the side of the active layer away from the substrate and the step of forming a second gate material layer on the side of the active material layer away from the substrate, the method further includes: Etching is performed on the first insulating layer and the second insulating layer to form vias.

17. The transistor fabrication method according to claim 16, characterized in that, The step of forming the first gate on one side of the substrate further includes: A connection portion is formed that is disposed on the same layer as the first gate and is electrically connected to the first gate.

18. The transistor fabrication method according to claim 16, characterized in that, The step of forming the second gate on the side of the active layer away from the substrate further includes: A connection portion is formed that is disposed on the same layer as the second gate and electrically connected to the second gate, the connection portion extending into the via to be electrically connected to the first gate.

19. A pixel circuit, characterized in that, It includes a driving transistor and a switching transistor, wherein the driving transistor is the transistor according to any one of claims 1 to 10.

20. A display panel, characterized in that, Includes the pixel circuit described in claim 19.

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