A cryogenic CMOS transistor, a method for driving such, an integrated circuit, a memory and a bolometer comprising such, a quantum processing unit comprising the integrated circuit

Abstract

There is provided a complementary metal-oxide semiconductor, CMOS, transistor for cryogenic applications, comprising a substrate (101) comprising silicon; a buried oxide layer (102); a silicon on insulator, SOI, layer (103) comprising at least one of: silicon, Si, or isotope 28 of silicon, Si-28; a top gate oxide layer (104) comprising silicon oxide, SiO2, at least one top gate layer (105) comprising at least one of: poly-silicon or metal; and a back gate. The CMOS transistor has conduction and valence band edges essentially free of parasitic states. The CMOS transistor comprises subthreshold swing of 3.9 mV / dec or less, at a temperature of 4 K or below.

Description

TITLE A cryogenic CMOS transistor, a method for driving such, an integrated circuit, a memory and a bolometer comprising such, a quantum processing unit comprising the integrated circuit TECHNICAL FIELD

[0001] The present invention relates to a complementary metal-oxide semiconductor, CMOS, transistor for cryogenic applications; an integrated circuit, IC, comprising one or more CMOS transistors; a method for driving the one or more IC; a quantum processing unit comprising the IC circuit; and uses of a CMOS transistor for cryogenic applications. BACKGROUND

[0002] Complementary metal-oxide semiconductors, CMOSs, are widely used components. Applications in number of areas utilize CMOS technology. For quantum computing, cooling to cryogenic temperatures is often required. Widely used CMOS is expected to be used for cryogenic CMOS applications as well. Cryogenic CMOS could show high performance and low power, while maintaining existing manufacturing. However, cooling may pose challenges; for example, variation is seen to increase at low temperatures. In addition, high power dissipation is a problem in cryogenic CMOS circuits. SUMMARY

[0003] Aim is to enable a cryogenic CMOS transistor operated at temperatures of 4 K, or below with efficiency.

[0004] The invention is defined by the features of the independent claims. Some embodiments are defined in the dependent claims.

[0005] According to a first aspect of the present application, there is provided a complementary metal-oxide semiconductor, CMOS, transistor for cryogenic applications, comprising a substrate comprising silicon; a buried oxide layer; a silicon on insulator, SOI, layer comprising at least one of: silicon, Si, or isotope 28 of silicon, Si-28; a top gate oxidelayer comprising silicon oxide, SiO2, a top gate layer comprising at least one of: poly-silicon or metal; and a back gate. The CMOS transistor has conduction and valence band edges essentially free of parasitic states. The CMOS transistor comprises subthreshold swing of 3.9 mV / dec or less, at a temperature of 4 K or below.

[0006] The cryogenic applications comprise operation temperature of at or below 4 K.

[0007] A CMOS transistor according to the first aspect, may comprise the SOI layer consisting of at least one or both of Si, and Si-28. The CMOS may comprise the top gate oxide layer consisting of SiO2. The CMOS transistor may comprise the top gate layer consisting of at least one or both of: poly-silicon and metal. The CMOS transistor may comprise at least one or more top gate layers. In addition, the CMOS transistor may comprise from none to multiple routing layers. A routing layer may comprise metal. A routing layer is configured to transfer signals. A top gate layer may form a routing layer.

[0008] The one or more top gate layers may comprise a superconductor. The one or more top gate layers may comprise a superconductor comprising inductance per µm2of at least 100 pH, or at least 1 nH, or at least 10 nH. A routing layer, or multiple routing layers, may comprise a superconductor. A routing layer, or multiple routing layers, may comprise a superconductor comprising inductance per µm2of at least 100 pH, or at least 1 nH, or at least 10 nH.

[0009] The CMOS transistor may have subthreshold swing of 2.0 mV / dec or less at a temperature of 2 K or below. The CMOS transistor may have subthreshold swing of 1.0 mV / dec or less at a temperature of 1 K or below. The CMOS transistor may have subthreshold swing of 1.0 mV / dec or less at a temperature of 0.4 K or below.

[0010] The CMOS transistor may comprise regions of n-type or p-type with active dopant concentration of 1019cm-3or more. The back gate may be patterned or doped. The back gate may be a global or a semiglobal back gate. The back gate may be configured to form a static back gate, such that at a temperature of 4 K or below the back gate may be configured to lose its electrical conductivity and to turn into an insulator. The static back gate maybe configured to form a non-volatile memory.

[0011] A source-drain voltage may be of no more than 90 mV at temperatures of 1 K or below without significant single electron oscillations; and less than 50 % conductanceoscillations in a subthreshold regime. The CMOS transistor may comprise a gap between n- type and p-type carriers operable such that the threshold voltages for the n-type and p-type carriers are tuned 0-80 mV above and below a zero voltage, respectively.

[0012] According to a second aspect of the present application, the CMOS transistor of the first aspect may be used as a memory, or a non-volatile memory. There is provided a memory, or a non-volatile memory comprising the CMOS transistor of the first aspect. According to a third aspect of the present application, the CMOS transistor may be used for a digital circuit or for an analogic circuit. According to a fourth aspect of the present application, the CMOS transistor maybe used as a bolometer. There is provided a bolometer comprising the CMOS transistor.

[0013] According to a fifth aspect of the present invention, there is provided an integrated circuit, IC, comprising one or more CMOS transistors according to the first aspect. The IC may be configured to be operated with a drive voltage of 90 mV or less; or 50 mV or less; or 25 mV or less, at a temperature of 4 K or below; or optionally at a temperature of 1 K or below. The IC may comprise a transconductance configured to change at least three orders of magnitude between on- and off-states of at least one or more CMOS transistors in response to operation of the IC with a drive voltage of 90 mV or less. The IC may comprise a static gate. The IC may comprise a superconducting kinetic inductor or a Josephson junction kinetic inductor.

[0014] According to a sixth aspect of the present application, there is provided a quantum processing unit comprising the IC according to the fifth aspect of the present application.

[0015] According to a seventh aspect of the present application, there is provided a method for driving an integrated circuit, IC, comprising one or more CMOS transistors according to the first aspect, comprising operating the IC with a drive voltage of 90 mV or less; or 50 mV or less; or 25 mV, or less, at a temperature of 4 K or below; or optionally at a temperature of 1 K or below. The drive voltage may be 80 mV, for example. In the method the drive voltage may comprise a dynamic drive voltage configured to vary in function of time. The method may comprise applying static voltage to the back gate during cooling to a cryogenic temperature, wherein the back gate is configured to form a static back gate such that at a temperature of 4 K or below the back gate is configured to lose its electrical conductivity and to turn into an insulator. Optionally the back gate is configured to form anon-volatile memory. The method may further comprise refreshing the static back gate by providing light or locally increasing the temperature in order to excite free charge carriers such that the charge carriers are configured to affect the potential of the back gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In the following embodiments are discussed in more detail with reference to the attached drawings, of which:

[0017] Figure 1 illustrates, by way of an example, a transistor.

[0018] Figure 2a illustrates, by way of an example, a side view of a transistor.

[0019] Figure 2b illustrates, by way of an example, a top view of a transistor.

[0020] Figure 3a and 3b illustrate, by way of an example, integrated circuits comprising a transistor.

[0021] Figure 4a illustrates, by way of an example, a diagram of transfer characteristics for n-MOS.

[0022] Figure 4b illustrates, by way of an example, a diagram of transfer characteristics for p-MOS.

[0023] Figures 5a and 5b illustrate, by way of an example, diagrams of transfer characteristics for p-MOS.

[0024] Figures 6a and 6b illustrate, by way of an example, a CMOS transistor used as a bolometer.

[0025] Figure 7 illustrates, by way of an example, a method for driving an integrated circuit, IC, comprising one or more CMOS transistors.

[0026] Figures are presented as illustrative examples and embodiments may not be limited solely to the illustrated parts, but modifications may be made under the scope as defined in the claims. Figures that may not fully present the claimed invention, aim to provide better understanding on the context and relating technical field.DESCRIPTION OF EMBODIMENTS

[0027] There is provided a cryogenic silicon on insulator, SOI, complementary metal- oxide semiconductor, CMOS, transistor for low, cryogenic, temperature and low power dissipation during operation. For cryo-CMOS transistor applications values for the subthreshold swing have surpassed 1 mV / dec, millivolt per decade. CMOS transistor subthreshold swing and performance do not saturate at higher temperatures, like approximately 15-35 K, kelvin. This is due to material choices, clear interfaces and fabrication processes. The provided CMOS transistor enables operation at cryogenic temperatures, at or below 4 K, with high efficiency. This enables prospects for cryogenic semiconductor electronics, since power dissipation in these devices is so low that they are usable at sub-kelvin temperatures, thus suitable for cryogenic applications. Circuits utilizing CMOS transistors as provided are operable with reduced drive voltage while still having good performance.

[0028] Subthreshold swing, SS, or subthreshold slope is used to measure performance of a transistor. Subthreshold swing describes an exponential behaviour of (drain) current as a function of (gate) voltage. It is characterised as a voltage difference that is required for a decade of change in current. Subthreshold swing is inverse of a subthreshold slope. Subthreshold swing is normally minimized when allowed by the application. Smaller subthreshold swing enables better performing CMOS transistor and circuits in terms of drive voltage, leakage current and energy consumption, and overall better performance.

[0029] A subthreshold regime corresponds to a subthreshold or weak inversion region, which occurs when the gate to source voltage, VGS, of a transistor is below its threshold voltage, Vth, resulting in a small amount of current between drain and source, IDS.

[0030] Available cooling power, P, for cryogenic cooling systems decreases significantly towards cryogenic temperatures (T), for example for dilution coolers P ∝ T2. Yet the power dissipation of metal-oxide semiconductor field-effect transistors, MOSFETs, may be reduced by a similar factor. This is mainly due to an improved switching efficiency at cryogenic temperatures, which results from the narrower extend of electronic thermal excitations. This is illustrated by subthreshold swing, SS, which is a figure of merit for switching efficiency. The expression for SS can be obtained by taking the derivative of a gate voltage Vg with respect to logarithm of a drain current Id

[0032] where Idis the drain current, and Vgis the gate voltage.

[0033] Subthreshold swing scales with a temperature T as follows:

[0034] ^^^^^^^^(^^^^) = log (^^^^^^^^^^^^ / ^^^^)

[0035] where kbis the Boltzmann constant and e is the elementary charge. As explained in previous, typically the subthreshold swing follows this temperature difference down to 15 K to 35 K temperature, but the subthreshold swing does not anymore improve, i.e. get smaller, when the transistor is further cooled.

[0036] In addition, use of cryogenic temperatures enables use of superconductors as routing elements as well as having metallic structures better conducting due to reduced electron-phonon interaction leading to further improvements in the energy efficiency.

[0037] Previously, use of devices for CMOS-based cryogenic control has been limited by their large power consumption, which is not compatible with cryogenic operation. While control of a few qubit system has required power in the range of hundreds of milliwatts, mW, scaling up to control of hundreds and more qubits, has not been possible. With transistors having a very small subthreshold swing, this obstacle can be overcome allowing cryogenic control of large-scale quantum processors, or quantum processing units, QPUs.

[0038] Figure 1 illustrates, by way of an example, a transistor. The transistor comprises a substrate 101, which may be called a handle. A buried oxide layer 102 is arranged on top of the substrate 101. A device layer 103 may be called a silicon on insulator, SOI, layer. The device layer 103 is arranged on the buried oxide layer 102. A back gate 106 is arranged on the opposing side of the buried oxide layer 102. A top gate oxide layer 104 is arranged on the device layer 103, between the device layer 103 and a top gate layer 105. The top gate 105 may be called a front gate layer or a gate layer.

[0039] The substrate 101 may comprise a multilayer. Multiple device layers 103 may be arranged on the substrate 101 and one of the device layers 103 may be used for gating, another of the device layers 103 for a transistor channel.

[0040] A back gate 106 may be patterned or doped. The back gate 106 may be a global or a semiglobal back gate. A local back gate is configured for a single transistor, while asemi-global back gate is common for set(s) of transistors, and a global back gate is common for all transistors. The back gate 106 may lose conduction during cooldown when the dopant concentration is low, for example below 1018·1 / cm3. By applying a static voltage during cooling the back gate 106 to a cryogenic temperature enables the back gate 106 to be used as a static gate with very long retention time. The static gate may form, or be used as, a non- volatile memory element. The back gate 106 may be configured to form a static back gate such that at a temperature of 4 K or less the back gate 106 is configured to lose its electrical conductivity and to turn into an insulator. In such case, the back gate 106 is configured to form a non-volatile memory. The back gate 106 may be refreshed by supplying energy to the system, for example, by applying light suitable for exciting charge carriers.

[0041] Memory elements realized by the very low subthreshold swing transistor enable achieving minimal power dissipation. Low or very low subthreshold swing refers throughout this application to 3.9 mV / dec, or less, at a temperature of 4 K, or below. The low subthreshold swing enables charge transfer with minimal memory circuit drive voltage, which is typically from 25 to 50 mV, but no greater than 90 mV, while still leaving off-state gap with very low leakage. The leakage current is at maximum 1 pA, but typically well below that. The cryogenic operation increases retention time, as typically the thermal leakages are exponentially suppressed at low temperatures.

[0042] Superconducting routing and one or more gate layers may be used to lower the power dissipation. They may increase maximum operation rate by reducing resistance. In addition, joule heating may be reduced. Superconducting gate layer(s) or routing layers may be used as highly compact kinetic inductors. The kinetic inductors may be used to make LC- oscillators, which operate as a part of CMOS circuit, where an inductor is represented by L and a capacitor by C, and other circuit elements that require large inductance. The components may be made more compact than geometric inductors, and have negligible dissipative component because of superconductivity. Quality factors exceeding 1 million may be achieved. Combined with CMOS those may form completely new logic circuit family, with possibility to realize all resistor R, inductor L and capacitor C with compact elements. Inductance per µm2may be at least 100 pH, but even 1 nH or 10 nH, or larger. The inductance (per µm2) depends on selected superconducting material and the cross- sectional area of the superconducting nanowire. The smaller the wire is, the higher is the kinetic inductance per length of the wire. The kinetic inductor may be done using Josephson junction or junctions. Those may be made in superconducting quantum interference deviceconfiguration, which allow tuning the inductance with magnetic field. These areal inductance densities enable inductors with negligible parasitic capacitance. Due to small area and low parasitic capacitance, these inductive elements are suitable to be used for high frequencies. The kinetic inductance may be tuned by applying current smaller than critical current or by increasing / lowering temperature of the component, or in extreme cases by driving the kinetic inductor to normal state, which essentially removes the inductive part completely and makes the kinetic inductor to behave as a resistor.

[0043] Doped contact regions, or areas, of Fig.1, illustrated as n++ / p++, are part of a source and a drain, 107, 108, terminals of the transistor. Doped contact regions, n++ / p++, are provided by introducing impurities to an undoped semiconductor. Doping enables modulating properties, like electrical and structural properties, of the doped semiconductor. Alternatively doped source and drain, 107, 108, areas may be created electrostatically. For electrostatic creation of doped areas an electrode, for example similar to the gate electrode, is applied on top of source and drain, 107, 108, areas. Alternatively or in addition, a combination of doped contact regions, n++ / p++, and electrostatically created source and drain, 107, 108, areas may be used. Doped regions, which may be of n-type or p-type, may have active dopant concentration of 1019·1 / cm3or more.

[0044] Semiconductors and insulators have the valence band and the conduction band separated by a band gap. For a semiconductor to function as a conductor it needs to have excited electrons on the conduction band or holes on the valence band. This may be achieved by electrostatically increasing the chemical potential above or below the conduction of the valence band edge, which makes the semiconductor to conduct, assuming it is connected to some reservoir of electrons or holes; or by supplying impurities, dopants, to the channel that can donate an electron that has energy close to the conduction band edge or accept an electron so that resulting hole will be close to the valence band. Once the charge carriers are formed to conduction or valence band those can move and carry current, i.e., conduct electricity. N-type semiconductor has an excess of free electrons in the conduction band compared to p-type semiconductor. P-type of semiconductor has an excess of holes in the valence band compared to n-type. Source current, IS, enters to the channel from the source terminal, and drain current, ID, exits the channel through the drain terminal.

[0045] CMOS circuits typically comprise of both n-type and p-type transistors. Fully depleted silicon on insulator, FD-SOI, technology enables back gating of the n-type and p-type transistors. Typically, the threshold voltage is set by a back gate so that upon applying a front gate voltage the channel potential goes above or below conduction and valence band, respectively, with already as low as possible front gate voltage, while still the transistor being close at zero-potential. Typical target is that even a small top gate voltage starts to increase the observed current in the channel. Yet a very low subthreshold swing enables to leave a (band) gap between gated effective n and p (conduction and valence) band edges around the zero potential with still having minimal drive voltage. If the subthreshold swing is sufficiently low, e.g. at or below 3.9 mV / dec at 4 K, it is no longer dominant contribution factor to the transistor on-state switching, but other effects such as single electron effects and process defects may demand higher drive voltage. At this point leaving a gap between gated effective n and p (conduction and valence) band edges around the zero potential for switching n-type and p-type transistors helps in suppressing parasitic leakages and allowing process variations and defects that could locally affect some of the transistors and have reduced effect on overall performance. For 80 mV drive voltage the gap may be as high as 60 – 70 mV; or below 30 mV; or for 25 mV voltage as high as 10 to 20 mV.

[0046] Figure 2a illustrates, by way of an example, a side view of a transistor. A buried oxide layer 202 is onto a substrate layer 201, and doped regions p++ / n++ are arranged between the buried oxide layer 202 and the substrate layer 201. A top gate layer 205 is on a top gate oxide layer 204.

[0047] Figure 2b illustrates, by way of an example, a top view of a transistor. Doped regions p++ / n++ are arranged on a buried oxide layer 202 and below a top gate layer 205.

[0048] A transistor may be a fin field-effect transistor, FinFET, where the source / drain region forms fins on the silicon surface. In FinFET a transistor is built on a substrate, where the gate is placed on two or more sides of the channel, or even around of the channel, thereby forming a double or even multi gate structure. In alternative, a transistor may be, for example, a CMOS transistor, a SOI transistor, a FET transistor.

[0049] Figures 3a, 3b illustrate, by way of an example, integrated circuits comprising a transistor. A transistor, like a CMOS, may be used for an analogic or a digital circuit. Fig. 3a illustrates an integrated circuit, IC, comprising ground, output pins VOUT, input pins VIN, and power supply pins VDDand VSS. Fig.3b illustrates an IC comprising a processor µP, a micro-controller µC, a signal source SS, an amplifier AMP, an analog-to-digital converter ADC, a digital-to-analog converter DAC, an oscillator OSC, a digital signal processor DSP,and a memory MEM. The IC comprises electronic components, for example, one or more of the components of Fig.3b. The IC may comprise a CMOS integrated circuit with a kinetic inductor. The kinetic inductor may be a superconducting kinetic inductor. In other applications, a kinetic inductor may be replaced by a geometric inductor. The IC utilizing a kinetic may comprise, for example, one or more of the following: CMOS LC-oscillator, low- pass filter, band-pass filter, isolator, bias-tee, signal-mixer or impedance matching network.

[0050] The integrated circuit may be configured to be operated with a drive voltage of 90 mV or less, at a temperature of 4 K or below; or at a temperature of 1 K or below. The drive voltage may be 50 mV or less; or 25 mV or less, at a temperature of 4 K or below; or at a temperature of 1 K or below. The IC may comprise kinetic inductance components. The circuit may comprise a static gate. A very low subthreshold swing enables using only n- or p-type transistors for logic circuits, while maintaining minimal power dissipation.

[0051] The circuit may comprise a transconductance configured to change at least three orders of magnitude between strong inversion and off-state in response to operation of the circuit with a drive voltage of 90 mV or less. Off-state is characterized by having the gate voltage such that the transistor channel potential is within the band gap of silicon, and strong inversion is characterized by having the channel potential above the conduction band edge, or below the valence band edge, so that the channel potential only weakly depends on the gate voltage. This is due to free charge carriers in the channel screen the gate potential. For a single transistor in the circuit inversion and off-state may correspond to on- and off- states of the transistor.

[0052] Having both the top gate 105 and the back gate 106 enables independent tuning of the transistor channel potential. The back gate 106 is configured to provide static potential for n- and p-type devices, like n-MOS and p-MOS transistors, in order to have either the conduction or valence band edge, respectively, close to zero top gate 105 potential. Voltages of the top gate 105 are configured to accumulate charge carriers, which are extended to form doped contact regions 107, 108, into the undoped channel. Tuning the transistor channel potential may be implemented using the top gate 105, while keeping the back gate 106 at ground potential. Source-drain voltage of 90 mV or less, at a temperature of 4 K or less; or at a temperature of 1 K or less, may be used without significant single electron oscillations and less than 50 % conductance oscillations in the subthreshold swing. CMOS transistor comprises a gap between n-type and p-type carriers, which are operated as electronic circuitssuch that a threshold voltage for the n-type and p-type carriers are tuned to 0-80 mV and below a zero voltage, respectively.

[0053] A SOI CMOS transistor for cryogenic applications comprises, on a substrate 101 in the following order: a back gate 106, a buried oxide layer 102, a device layer 103, a top gate oxide layer 104, and a top gate layer 105. The SOI CMOS may comprise one or more pairs of the buried oxide layer 102 and the device layer 102. The device layer 103, being SOI, comprises at least one of: silicon, Si, or isotope 28 of silicon, Si-28. The top gate oxide layer 104 comprises silicon oxide, SiO2. The SOI CMOS comprises at least one or more top gate layers 105. The top gate layer 105 comprises at least one of: poly-silicon, or metal. The SOI CMOS transistor has conduction and valence band edges substantially or essentially free of parasitic states and comprises subthreshold swing of 3.9 mV / dec, or less, at a temperature of 4 K, or below.

[0054] The SOI CMOS transistor according to at least some or all embodiments has subthreshold swing of 2.0 mV / dec or less at a temperature of 2 K or below. The SOI CMOS transistor according to at least some or all embodiments has subthreshold swing of 1.0 mV / dec or less, at a temperature of 1 K or below. The SOI CMOS transistor according to at least some or all embodiments has subthreshold swing of 1.0 mV / dec or less, at a temperature of 0.4 K or below.

[0055] In at least some or all embodiments the buried oxide layer 102 comprises a thickness of 10-500 nm.

[0056] In at least some or all embodiments the device layer 103 comprises a thickness of 5-100 nm. According to at least some or all embodiments the device layer 103 consists of at least one or both of Si, and Si-28.

[0057] In at least some or all embodiments the top gate oxide layer 104 comprises a thickness of 2-100 nm. According to at least some or all embodiments the top gate oxide layer 104 consists of SiO2.

[0058] According to at least some or all embodiments the top gate layer 105 consists of at least one or both of: poly-silicon and metal. According to at least some or all embodiments the top gate layer 105 comprises a superconductor, optionally comprising inductance per µm2of at least 100 pH, or at least 1 nH, or at least 10 nH. The top gate layer refers to at least one top gate layer 105, since there may be one or more top gate layersthroughout this application. The CMOS transistor may further comprise one or more routing layers. The one or more routing layers may be placed anywhere on a microchip.

[0059] A Fully Depleted Silicon on Insulator, or FD-SOI, is a planar process technology that achieves benefits of reduced silicon geometries while actually simplifying the manufacturing process. The buried oxide 102 is configured to form an ultra-thin layer of insulator and positioned on top of the substrate layer 101. Then, device layer 103, formed of a thin silicon film, which implements the transistor channel. Due to thinness, for example 5- 100 nm, of the device layer 103, it is efficient to close the channel. Thus, the channel may be fully depleted. The buried oxide layer 102 lowers the parasitic capacitance between the source and the drain, 107, 108, terminals. The buried oxide layer 102 efficiently confines the electrons flowing from the source, 107 / 108, terminal to the drain, 108 / 107, terminal, thereby reducing performance-degrading leakage currents.

[0060] Experimental evaluation of mass-fabricated pilot-line FD-SOI cryo-CMOS transistors, or MOSFETs, has shown high switching performance. In a cryogen free system,3He evaporation cooling may be utilized with 420 mK base temperature. Source potential and gate potential may be controlled using isolated voltage sources. Drain current, Id,may be measured with a transimpedance amplifier. In order to determine the switching performance of electrons the gate voltage Vghas been swept around a pre-determined threshold region at a constant temperature, and the drain current Id has been measured. In this temperature regime, subthreshold swing SS(T) has been extracted as dlog(Id) / dVgin the linear region. The extracted subthreshold swing SS follows a linear temperature dependence with SS = mlog(10)kBT / e, resulting in a slope factor of m = 1.05 for electrons and m = 1.12 for holes. The slope factor m = (Cg+ Ci) / Cgtakes into account an effect of the interface trap capacitance Ciand the gate capacitance Cg. This significantly surpasses values, which have been measured for comparable devices in the long-channel limit. Further, when cooling the devices to the sub-Kelvin regime, curves free of oscillatory features are seen for both n-type and p-type devices. In addition, no hysteresis appeared down to the base temperature of 420 mK.

[0061] Figures 4a and 4b illustrate, by way of an example, diagrams of electrical transfer (or electrical transport) characteristics for n-MOS and p-MOS, respectively. Electrical transfer characteristics at 420 mK for the same device, for example as illustrated in Fig. 1, are shown for n-MOS in Fig. 4a and for p-MOS in Fig. 4b. The diagram showsdrain current, Id(in amperes, A), in y-axle and gate voltage, Vg(in volts, V). in x-axle. Drain current, Id, versus gate voltage, Vg, transfer characteristics between 100 K and room temperature have been measured at 25 mV source-drain voltage for an n-type device in Fig. 4a and for p-type device in Fig.4b. The temperatures illustrated at lower right corners of the Figs.4a and 4b are shown in the same order in the graphs: the uppermost temperature in the right corner corresponds to the rightmost graph, and the lowest temperature in the right corner corresponds to the leftmost graph, and the other temperatures are seen in the graphs between those in the same order as in the right corner. At upper left corners of Figs.4a and 4b, subthreshold swing versus temperature has been illustrated as fitted according to SS = mlog(10)kBT / e for both electrons and holes, and the thermionic limit has been plotted for reference.

[0062] As Figs. 4a and 4b illustrate an example, where both n-type and p-type transistors achieve record low subthreshold swings at 420 mK with 1.80 mV / dec for electrons and 620 µV / dec for holes.

[0063] Figs. 5a and 5b illustrate, by way of an example, diagrams of switching performance for n-MOS and p-MOS, respectively. The diagram shows drain current, Id(in amperes A), in y-axle and gate voltage, Vg(in volts V) in x-axle. Drain current, Id, versus gate voltage, Vg, transfer characteristics at 420 mK, has been measured at 25 mV source- drain voltage and fitted to charge carrier concentration for electrons or holes, n(Vg), for an n-type device in Fig.5a and for p-type device in Fig.5b.

[0064] A significant enhancement is shown for the switching performance upon cooling to the sub-Kelvin regime. Fig.5a illustrates the switching performance improvement by more than a factor of 2 for electrons when cooling form 4.7 K to 420 mK. Fig. 5b illustrates the switching performance improvement by more than a factor of 5 for holes when cooling form 3.2 K to 420 mK. The illustrated switching performance stands out from other previously reported, as usually SS(T) is found to saturate at temperatures at or above 1 K, and the lowest reported value for SS(T) so far is 7.4 mV / dec overall.

[0065] In the following switching metrics for a SOI CMOS transistor, as described for example in Fig. 1, is modelled with respect to expectations. A fully depleted silicon on insulator, FD-SOI subthreshold region electrical transfer has been modelled and compared to the measured transfer characteristics (for example of Figs.4a and 4b). Diffusion currentis assumed to be solely proportional to the charge carrier density in the channel ^^^^(Ψ), given as Fermi-Dirac distribution, N2Diis the two- dimensional density of states with Ni2D= 0 for E < Eiand Ni2D= gimi / πħ for E ≥ Ei, where E is energy, miis effective charge carrier mass, ħ is reduced Planck’s constant, g is valley degeneracy factor, and index i is c for electrons and v for holes.

[0068] At a given channel potential Ψ, Ei= Ei0± eΨ is the band edge for electrons with Ec = Ec0– eΨ and for holes with Ev = Ev0+ eΨ, respectively. The drop of the gate voltage VGover the gate dielectric in the presence of a finite carrier density is expressed as

[0070] For modelling a threshold swing freeze-out, a broadened band edge with Ni(E) = Ni2De(E ± Ei) / E0,ifor E < Eiand Ni(E) = Ni2Dfor E ≥ Et.

[0071] Due to the convolution with f(E) (paragraph 0066), the subthreshold swing is locked to a temperature independent value for T << Tc(case temperature). Using the above formulas (paragraphs 0066 and 0069) ni(Vg,l) is calculated and the slope of dlog(ni) / dVgis fitted to it in the subthreshold regime. It is assumed that the mobility is density independent. Deviations towards higher voltages are expected and can be explained by the density dependence of charge carrier mobility. For both n- and p-type devices good match of curvature up to the threshold-voltage has been achieved. Thus, the curves are suitable to predict the switching characteristics of the n- and p-type devices, sufficiently well. Assuming exponential band broadening the results are achieved by E0,c= 0.70 meV and E0,v= 0.17 meV.

[0072] The power dissipation of CMOS circuits mainly originates from the charging and discharging of MOSFETs. This applies for cryogenic cryo-CMOS circuits and MHz operation frequencies, in which case the parasitic leakage paths are negligible. In this case the power dissipation Pdynof a single transistor is Pdyn∝ VDD2f, where f is the operation frequency, and VDDis the transistor drive voltage. By lowering VDDfrom state-of-the-art room temperature operation voltage range of 0.5 to 1 V values down to 10 mV that stillenables more than 5 orders of magnitude current difference between on- and off-states with realistic few mV threshold voltage variation, may already lower the dissipation by a factor between 2500 to 10000.

[0073] Lowering the operation voltage causes reduced transistor transition frequency. This may be mitigated by making the gate length shorter. However, also shorter gate length increases probability of undesired single charge effects. To roughly estimate the potential operation speed, single transistor transition frequencies for the n-MOS and p-MOS transistors with 10 mV operation voltage are ^^^ 1 ^^^^^^^^^^^^^= 2^^^^^^^^^^^^^^^^^^^^^^^^ ≈ 1.8 ^^^^^^^^^^^^ for n-MOS and0.6 GHz for p-MOS, where Ronis the transistor resistance with VDS= 10 mV and Vg= 10 mV. These are not fundamental limits, but can be improved by about factor 5 to 10 with thinner dielectric solutions. Here it has been assumed that the band edge is aligned with back gate to near Vg= 0.

[0074] As an example, in a potential operation scenario, giving maximum power dissipation limit, all the transistors are constantly switched on and off, wherein each clock cycle and each transistor is used to provide bias for three consecutive transistor gates. In such operation scenario, the average dissipation of a single transistor is

[0076] which for relatively large transistor, for example having a channel length of 1.2 µm and ISD> 50 nA at 10 mV operation voltage, gives the power dissipation estimate per n-MOS transistor is about 17 pW, and the power dissipation per p-MOS transistor is about 52 pW. In case of a shorter channel, for example 150 nm, which is still relatively long to prevent single charge effects causing problems, the power dissipation per n-MOS transistor drops to 0.4 pW, and the power dissipation per p-MOS transistor drops to 1.2 pW. Typically, available cooling power at 20 µK dilution refrigerators is of the order 10 µW, which enables circuits with about half million 1.2 µm gate length transistors or about twenty million 150 nm gate length transistors. For spin qubit systems, suitable operation temperatures may be hundreds of mK. For example, 0.42 K cooling power of tens of mWs is easily attainable and thus monolithically integrated silicon quantum and classical circuits with circuit complexity form tens of millions to even billions of transistors may be reasonable from dissipation perspective.

[0077] CMOS transistor for cryogenic applications has conduction and valence band edges essentially free of parasitic states. The conduction and valence band edges are chemical potential values at the channel from which the charge carriers can be excited without thermal energy to have observable charge carrier density, for example 109·1 / cm3electrons or holes. If the channel potential is below conduction or above valence band by roughly the amount of thermal broadening, so that thermal excitations of electrons or holes have vanishingly small probability, the charge carriers can be excited only due to parasitic states. Parasitic states refer to undesired states, which may include and / or be due to rogue dopants, interface traps or other defects. The conduction and valance band being essentially or substantially free of parasitic states means that band broadening at the edge of the band is no more than E0,i= 1 meV (paragraph 0069) assuming exponential band broadening.

[0078] Figures 6a and 6b illustrate, by way of an example, a CMOS transistor used as a bolometer. The CMOS transistor comprises a substrate layer or a handle 601. In Fig.6a a handle 601 has been etched away from the region below the transistor. This has effect on how much there is absorption of photons already at the handle 601. The handle 601 comprises silicon, which is quite transparent for large range of infrared and THz radiation. However, some frequencies are absorbed, and for those cases removal of a part of the handle 601 may be beneficial. A buried oxide layer 602 is arranged on top of the handle 601. A SOI layer 603 is arranged on the buried oxide layer 602. A back gate is arranged on the opposing side of the buried oxide layer 602. A top gate oxide layer 604, or a top gate electrode, is arranged on the device layer 603, between the device layer 603 and a top gate layer 605. The top gate 605 may be called a front gate. Figs.6a and 6b further illustrate a source 607 contact area, a drain 608 contact area and doped areas n++ / p++. Arrival direction of an incoming photon 60 is illustrated by an arrow having dashed line. The incoming photon 60 arrives via a back side of the transistor (disc). The CMOS transistor channel is configured to act as an electromagnetic radiation absorbing and temperature sensing element of a bolometer. Bolometers, which comprise semiconductor or superconductor absorptive elements instead of metals, are operated at cryogenic temperatures and enable enhanced sensitivity compared to those with metallic absorptive elements.

[0079] Figure 7 illustrates, by way of an example, a method for driving an integrated circuit, IC, comprising one or more CMOS transistors. The method comprises, at phase 701, driving an integrated circuit, IC, comprising one or more CMOS transistors. The method comprises, at phase 702, operating the IC with a drive voltage of 90 mV or less; or 50 mVor less; or 25 mV or less, at a temperature of 4 K or below; or optionally at a temperature of 1 K or below.

[0080] The method may comprise the drive voltage comprising a dynamic drive voltage configured to vary in function of time. The method may comprise applying static voltage to the back gate during cooling to a cryogenic temperature, optionally for forming a static back gate. The method may comprise refreshing the static back gate by providing light or locally increasing the temperature in order to excite free charge carriers such that the charge carriers are configured to affect the potential of the back gate. The method may comprise operating the IC with a drive voltage of 80 mV.

[0081] In the previous description and figures a SOI CMOS transistor, an IC comprising such and a method for driving the IC are illustrated. Semiconductor cryogenic electronics holds significant potential for emerging fields, such as quantum computing, cloud computing and space technologies. Silicon based technology enables utilize of the same processing technology and capability that is used for room temperature CMOS circuits. For example, devices for CMOS-based cryogenic control of silicon quantum circuits enable qubit control and read-out, both superconducting or semiconductor qubit modalities. Such can be implemented using cryogenic CMOS. This enables efficient realization of a fully integrated quantum processor. Use of devices for CMOS-based cryogenic control. The CMOS transistor may be used as part of an integrated circuit. The CMOS transistor may be used as a non-volatile memory element due to its capability to remain at a static state at cryogenic temperatures.

[0082] Cryogenic CMOS transistor with subthreshold swing 3.9 mV / dec or less, preferably 1.0 mV / dec or less, is directly compatible with single flux quantum, SFQ, superconducting circuit elements without amplification or current to voltage conversion. The voltage level on the single flux quantum circuits is typically about 1–2 mV. The low, or ultra low, subthreshold swing CMOS components combined with the SFQ provides a way to reduce static dissipation. Cryo-CMOS transistors can have almost no static dissipation unlike SFQ. The CMOS transistor with low subthreshold swing enables to provide compact memory element for SFQ. The CMOS transistor with low subthreshold swing enables to provide large scale, compact logic circuits while SFQ has potential to provide blocks that are highly energy efficient while being very fast. SFQ circuits could be, for example,included for microwave signal generation or fast modulation purposes as well as to provide additional logic blocks or transmission lines.

[0083] It is to be understood that the aspects and embodiments disclosed are not necessarily limited to the particular structures, process steps, or materials disclosed herein, but are extended to equivalents thereof as would be recognized by those ordinarily skilled in the relevant arts. It should also be understood that terminology employed herein is used for the purpose of describing particular embodiments only and is not intended to be limiting.

[0084] The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the previous description, numerous specific details are provided, such as examples of structures, lengths, widths, shapes, etc., to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well- known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.

[0085] While the forgoing examples are illustrative of the principles of the present invention in one or more particular applications, it will be apparent to those of ordinary skill in the art that numerous modifications in form, usage and details of implementation can be made without the exercise of inventive faculty, and without departing from the principles and concepts of the attached claims. Accordingly, it is not intended that the invention be limited, except as by the claims set forth below.

[0086] The verbs “to comprise” and “to include” are used in this document as open limitations that neither exclude nor require the existence of also un-recited features. The features recited in depending claims are mutually freely combinable unless otherwise explicitly stated. Furthermore, it is to be understood that the use of “a” or “an”, i.e. a singular form, throughout this document does not exclude a plurality.

Claims

CLAIMS:

1. A quantum processing unit comprising an integrated circuit, IC, operating at drive voltage of 90 mV or less and comprising one or more complementary metal-oxide semiconductor, CMOS, transistors for cryogenic applications, the one or more CMOS transistors comprising in the following order: - a substrate (101) comprising silicon, - a back gate (106), - a buried oxide layer (102), - a silicon on insulator, SOI, layer (103) comprising at least one of: silicon, Si, or isotope 28 of silicon, Si-28, - a top gate oxide layer (104) comprising silicon oxide, SiO2, and - at least one top gate layer (105) comprising at least one of: poly-silicon, or metal, - wherein the CMOS transistor has conduction and valence band edges essentially free of parasitic states; and - wherein the CMOS transistor comprises subthreshold swing of 3.9 mV / dec, or less, at a temperature of 4 kelvins, K, or below.

2. A quantum processing unit according to any of the previous claims, wherein the CMOS transistor comprising at least one of the following: - the buried oxide layer (102) comprises a thickness of 10-500 nm, - the SOI layer (103) comprises a thickness of 5-100 nm, and - the top gate oxide layer (104) comprises a thickness of 2-100 nm.

3. The quantum processing unit according to any of the previous claims, further comprising a routing layer, wherein one or both of the following: at least one of said at least one top gate layer (105) and the routing layer comprises a superconductor, optionally comprising inductance per µm2of at least 100 pH, or at least 1 nH, or at least 10 nH.

4. The quantum processing unit according to any of the previous claims, wherein the CMOS transistor has subthreshold swing of one of the following: - 2.0 mV / dec or less, at a temperature of 2 K or below;- 1.0 mV / dec or less, at a temperature of 1 K or below; or - 1.0 mV / dec or less, at a temperature of 0.4 K or below.

5. The quantum processing unit according to any of the previous claims, comprising regions of n-type or p-type with active dopant concentration of 1019cm-3or more.

6. The quantum processing unit according to any of the previous claims, wherein the back gate (106) is patterned or doped; and / or wherein the back gate (106) is a global or a semiglobal back gate.

7. The quantum processing unit according to any of the previous claims, wherein the back gate (106) is configured to form a static back gate, such that at a temperature of 4 K or below the back gate (106) is configured to lose its electrical conductivity and to turn into an insulator, wherein optionally the static back gate is configured to form a non-volatile memory.

8. The quantum processing unit according to any of the previous claims, comprising a source-drain voltage of no more than 90 mV at temperatures of 4 K or below, or at temperatures of 1 K or below, without significant single electron oscillations and less than 50 % conductance oscillations in a subthreshold regime.

9. The quantum processing unit according to any of the previous claims, comprising a gap between n-type and p-type carriers operable such that threshold voltages for the n-type and p-type carriers are tuned 0-80 mV above and below a zero voltage, respectively.

10. The quantum processing unit according to any of previous claims, including a memory element, or a non-volatile memory element comprising the CMOS transistor according to any of the previous claims 1-9.

11. The quantum processing unit according to any of previous claims, including a bolometer comprising the CMOS transistor according to any of the previous claims 1-9.

12. The quantum processing unit according to any of claims 1-11, wherein the IC is configured to be operated with a drive voltage of 90 mV or less; or 50 mV or less; or 25 mV or less, at a temperature of 4 K or below; or optionally at a temperature of 1 K or below.

13. The quantum processing unit according to any of claims 1-12, comprising a transconductance configured to change at least three orders of magnitude between on- and off-states of at least one or more CMOS transistors in response to operation of the IC with a drive voltage of 90 mV or less.

14. The quantum processing unit according to any of claims 1-13, wherein the back gate (106) comprises a static back gate.

15. The quantum processing unit according to any of claims 1-14, comprising at least one of: a superconducting kinetic inductor, or Josephson junction kinetic inductor.

16. A method for driving an integrated circuit, IC, comprised in a quantum processing unit, the IC comprising one or more CMOS transistors according to any of the claims 1-14, comprising - operating the IC with a drive voltage of 90 mV or less; or 50 mV or less; or 25 mV or less, at a temperature of 4 K or below; or - optionally at a temperature of 1 K or below.

17. The method according to claim 16, wherein the drive voltage comprises a dynamic drive voltage configured to vary in function of time.

18. The method according to any of claims 16-17, comprising applying static voltage to the back gate during cooling to a cryogenic temperature, wherein the back gate is configured to form a static back gate such that at a temperature of 4 K or below the back gate is configured to lose its electrical conductivity and to turn into an insulator, and optionally the back gate is configured to form a non-volatile memory.

19. The method according to claim 18, comprising refreshing the static back gate by providing light or locally increasing the temperature in order to excite free charge carriers such that the charge carriers are configured to affect the potential of the back gate.

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