Reconfigurable dual-gate transistor based on nano ferroelectric material and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor devices, and provides a reconfigurable dual-gate transistor based on a nano ferroelectric material, which is provided with a bottom gate programming gate and a top gate control gate, and uses a form of two discrete gates, thereby greatly reducing crosstalk between transistor programming and transistor control operation, and improving the reliability of the transistor. The non-volatile characteristic and practicability of the transistor are improved, the technical problems of a traditional transistor in the aspects of non-volatile storage and rapid regulation and control are solved, the electrical performance of a transistor device is optimized, and a good P / N transfer characteristic curve and low subthreshold swing are shown.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and specifically to a reconfigurable dual-gate transistor based on nano-ferroelectric materials and its fabrication method. Background Technology

[0002] With the development of integrated circuits, the integration level continues to increase, and the requirements for transistor size continue to decrease. As the process enters the sub-10nm era, silicon-based devices are affected by the short-channel effect, making it difficult to continue shrinking the size. At the same time, the performance improvement of traditional von Neumann architecture computers is limited by the memory wall due to their memory-computation separation architecture. Further growth in integrated circuit performance has put forward new demands for new semiconductor materials and new computing architectures.

[0003] In recent years, dual-gate transistors have attracted widespread attention due to their potential in polarity control and reconfigurability. However, with the continuous shrinking of transistor size and the increasing integration density, traditional metal-oxide-semiconductor (MOS) and silicon-based semiconductor field-effect transistors (SFETs) face problems such as short-channel effects, increased power consumption, and limited subthreshold swing. In particular, at room temperature, the subthreshold swing (SS) of transistors is limited due to the Boltzmann distribution characteristics of electrons, mainly caused by their drift-diffusion working mechanism. Therefore, finding a novel transistor structure and fabrication method to overcome the subthreshold swing limitations of traditional semiconductor devices and reduce threshold voltage and power consumption has become an important direction for the development of the current integrated circuit industry. Summary of the Invention

[0004] This invention provides a reconfigurable dual-gate transistor based on nano-ferroelectric materials and its fabrication method, which solves the technical problems of non-volatile storage and fast control of traditional transistors, optimizes the electrical performance of transistor devices, and exhibits good P / N transfer characteristic curves and low subthreshold swing.

[0005] To achieve the above-mentioned objectives, the present invention provides the following technical solution:

[0006] A reconfigurable dual-gate transistor based on nano-ferroelectric materials, including

[0007] Substrate,

[0008] An insulating layer is disposed on the substrate.

[0009] A bottom-gate programming gate is disposed on the insulating layer.

[0010] A ferroelectric dielectric layer is disposed on the bottom-gate programming gate.

[0011] A channel layer is disposed on the ferroelectric dielectric layer, and the channel layer is a bipolar semiconductor thin film.

[0012] Source and drain electrodes are disposed on the left and right sides above the channel layer.

[0013] A silicon oxide seed layer is provided on the source and drain electrodes.

[0014] A top gate dielectric layer and a top gate control gate are disposed on the silicon oxide seed layer;

[0015] The bottom gate programming gate completely covers the channel layer, and the top gate control gate covers the middle region of the channel layer.

[0016] Preferably, the materials of the bottom gate programming gate and the top gate control gate are independently selected from any one or more of tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide;

[0017] Preferably, the thickness of the bottom gate programming gate is 20 nm, and the width of the bottom gate programming gate is 30 μm to 50 μm.

[0018] Preferably, the bottom gate programming gate material is titanium nitride and / or tungsten metal.

[0019] Preferably, the ferroelectric dielectric layer comprises a hafnium-based ferroelectric material layer, wherein the hafnium-based ferroelectric material comprises HfZrO. X HfAlO X HfSiO X HfTiO X and HfYO X Any one of them.

[0020] Preferably, the ferroelectric dielectric layer includes a passivation layer deposited on top of the hafnium-based ferroelectric material layer, and the passivation film includes hafnium oxide and / or zirconium oxide.

[0021] Preferably, the thickness of the ferroelectric dielectric layer is 10–20 nm.

[0022] Preferably, the thickness of the bipolar semiconductor thin film is 5-15 nm; the bipolar semiconductor thin film is a Wse2 / MoTe2 thin film.

[0023] Preferably, the source and drain materials are independently selected from any one of the following: gold, tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide.

[0024] Preferably, the thickness of the top gate dielectric layer is 10 nm, and the width of the top gate dielectric layer is 20–30 μm;

[0025] Preferably, the thickness of the top gate control gate is 30 nm, and the width of the top gate control gate is 5 μm.

[0026] This invention also provides a method for fabricating a reconfigurable dual-gate transistor based on nano-ferroelectric materials, comprising the following steps:

[0027] After photolithography and development on an insulating substrate, the bottom gate layer is prepared by magnetron sputtering;

[0028] A ferroelectric dielectric layer was deposited on the bottom gate layer using atomic deposition.

[0029] A channel layer is formed by transferring bipolar semiconductor thin film material over a ferroelectric dielectric layer;

[0030] After photolithography is used to develop a semiconductor material layer, metal is deposited on both sides by thermal evaporation or electron beam evaporation to obtain the source and drain electrodes.

[0031] A silicon oxide seed layer and a top gate dielectric layer are sequentially prepared above the source and drain electrodes using electron beam evaporation.

[0032] The top gate control gate is fabricated above the top gate dielectric layer using photolithography.

[0033] Beneficial effects:

[0034] This invention provides a reconfigurable dual-gate transistor based on nano-ferroelectric materials, comprising a bottom-gate programming gate and a top-gate control gate. The use of two discrete gates minimizes crosstalk between transistor programming and control operations, improving the transistor's non-volatile characteristics and practicality. Furthermore, the bottom-gate programming gate completely covers the channel layer, while the top-gate control gate covers the middle region of the channel layer. The partial coverage of the top-gate control gate, combined with the adjustable polarity of the bipolar material in the channel layer, and the dielectric layer, allows for non-volatile control of the uncovered area of ​​the channel, while providing no control over the uncovered area. This achieves different conduction polarities in the middle and on both sides of the channel, enabling the construction of a PNP / NPN rectifier structure in the same semiconductor material without complex doping or heterogeneous integration processes. This results in a device exhibiting excellent P / N transfer characteristic curves while reducing the device's subthreshold swing.

[0035] This invention allows the channel conductivity to be flexibly switched between PNP and NPN by changing the pulse voltage of the bottom gate and the bias voltage of the top gate. This reconfigurability enables a single transistor to perform multiple logic functions, reducing the number of transistors required in the circuit and improving integration and flexibility. Attached Figure Description

[0036] Figure 1 This is a front view of the reconfigurable transistor structure of the present invention.

[0037] Figure 2 This is a top view of the reconfigurable transistor structure of the present invention.

[0038] Figure 3 The diagram shows the reconfigurable transistor structure prepared in Example 1.

[0039] Figure 4 The graph shows the variation of the bottom-gate programming gate transfer characteristic curve of the reconfigurable transistor prepared in Example 1 with the polarization state of the ferroelectric dielectric layer.

[0040] Figure 5 The graph shows the change in the gate transfer characteristic curve of the top gate control gate of the reconfigurable transistor prepared in Example 1 as a function of the polarization state of the ferroelectric dielectric layer.

[0041] Wherein: 1-substrate, 2-insulating layer, 3-ferroelectric dielectric layer, 4-bottom gate programming gate, 5-channel layer, 6-source and drain, 7-silicon oxide seed layer, 8-top gate dielectric layer, 9-top gate control gate. Detailed Implementation

[0042] like Figure 1 and 2 As shown, a specific embodiment of the present invention provides a reconfigurable dual-gate transistor based on nano-ferroelectric materials, including...

[0043] Substrate 1,

[0044] An insulating layer 2 is disposed on the substrate 1.

[0045] A bottom-gate programming gate 4 is disposed on the insulating layer 2.

[0046] A ferroelectric dielectric layer 3 is disposed on the bottom gate programming gate 4.

[0047] A channel layer 5 is disposed on the ferroelectric dielectric layer 3. The channel layer 5 is a bipolar semiconductor thin film. A source electrode 6 and a drain electrode 6 are disposed on the left and right sides above the channel layer 5.

[0048] A silicon oxide seed layer 7 is disposed on the source electrode 6 and the drain electrode 6.

[0049] The silicon oxide seed layer 7 is provided with a top gate dielectric layer 8 and a top gate control gate 9.

[0050] The bottom gate programming gate 4 completely covers the channel layer, and the top gate control gate 9 covers the middle region of the channel layer.

[0051] This invention employs two separate gates for the bottom-gate programming gate and the top-gate control gate, which greatly reduces crosstalk between device programming and device control operations, and improves the non-volatile characteristics and practicality of the device.

[0052] In this invention, the substrate 1 is preferably a silicon substrate, such as a silicon wafer; an insulating layer 2 is disposed on the substrate 1, and the two constitute an insulating substrate; the insulating layer 2 is preferably a silicon oxide insulating layer, and the thickness of the silicon oxide insulating layer is preferably 200nm to 400nm, more preferably 300nm; the insulating substrate selected in this invention is to provide a support layer with a flat surface for the fabrication of the entire transistor device, which facilitates subsequent fabrication.

[0053] In this invention, the bottom gate programming gate 4 is disposed on the upper layer of the insulating layer 2, located in the middle region. In this invention, the material of the bottom gate programming gate is selected from any one or more of tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide. In one embodiment of this invention, the material of the bottom gate programming gate is preferably titanium oxide and / or tungsten. In this invention, the thickness of the bottom gate programming gate is preferably 20 nm, and the width of the bottom gate programming gate is preferably 30 μm to 50 μm. In this invention, the bottom gate programming gate 4 completely covers the channel layer 5. The bottom gate programming gate is disposed above the insulating layer to completely cover the semiconductor channel layer. This allows the bottom gate to uniformly affect the conductivity characteristics of the entire channel. The pulse voltage of the bottom gate programming gate changes the polarization state of the ferroelectric dielectric layer, and then changes the conductivity polarity of the channel through the polarization electric field of the ferroelectric dielectric layer. Applying a positive voltage can make the channel region N-type, while applying a negative voltage can make it P-type. This control is non-volatile, and the polarity state of the channel is still retained even after power is turned off.

[0054] In this invention, a ferroelectric dielectric layer 3 is disposed on the bottom gate programming gate 4;

[0055] In this invention, the ferroelectric dielectric layer 3 preferably comprises a hafnium-based ferroelectric material layer, wherein the hafnium-based ferroelectric material comprises HfZrO. X HfAlO X HfSiO X HfTiO X and HfYO X Any one of the following; In this invention, the ferroelectric dielectric layer mainly serves as the dielectric material between the bottom-gate programming gate and the channel layer. Due to its non-volatile ferroelectric properties, the ferroelectric layer will flip when a programming gate voltage is applied to the bottom-gate programming gate. After the programming gate voltage is removed, it still possesses a certain ferroelectric polarization field, which can continuously control the conductivity and carrier concentration of the channel layer material. In this invention, the hafnium-based ferroelectric material is further preferably HfZrO. XThe zirconium-doped hafnium-based oxide ferroelectric layer used in this invention has good potential for thickness scaling. It can still maintain good ferroelectric properties at a thickness of less than 10 nm. When combined with two-dimensional van der Waals semiconductor materials, it has good potential for transistor size scaling.

[0056] In this invention, the ferroelectric dielectric layer preferably further includes a passivation layer, which is deposited on top of the hafnium-based ferroelectric material layer. The passivation layer preferably comprises hafnium oxide and / or zirconium oxide. The main purpose of providing the passivation layer in this invention is to provide a defect charge storage interface at the junction of the hafnium-based ferroelectric material layer and the passivation layer, thereby achieving co-regulation of ferroelectricity and defects and optimizing the non-volatile characteristics of the transistor device.

[0057] In this invention, the thickness of the ferroelectric dielectric layer is preferably 10-20 nm, and when a passivation layer is present, the thickness of the ferroelectric dielectric layer is the sum of the thicknesses of the hafnium-based ferroelectric material layer and the passivation layer.

[0058] This invention provides a channel layer 5 on the ferroelectric dielectric layer 3, wherein the channel layer 5 is a bipolar semiconductor thin film. In this invention, the thickness of the bipolar semiconductor thin film is preferably 5–15 nm; the bipolar semiconductor thin film is preferably a Wse2 / MoTe2 thin film. This invention fully utilizes the advantages of two-dimensional bipolar semiconductor thin film materials in terms of tunable carrier concentration and polarity, and combines it with nano-ferroelectric materials to achieve reconfigurable threshold voltage, carrier concentration, and semiconductor conductivity polarity through a single device.

[0059] In this invention, a source electrode 6 and a drain electrode 6 are disposed on the left and right sides above the channel layer 5. In this invention, the source electrode 6 and the drain electrode 6 are respectively disposed on the left and right sides and are in close contact with the channel layer 5. In this invention, the source electrode and the drain electrode material are independently any one of gold, tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide. In one embodiment of this invention, gold or platinum is preferred. In this invention, the source electrode and the drain electrode are in contact with the channel layer and realize circuit interconnection, and provide test electrodes.

[0060] In this invention, a silicon oxide seed layer 7 is provided on the source and drain electrodes 6. The main function of the silicon oxide seed layer in this invention is to isolate the channel layer from the external environment, protect the channel layer, reduce performance degradation in subsequent processing, and at the same time provide reaction sites for the atomic layer deposition growth of the top gate dielectric layer, improve film quality, and increase the breakdown field strength of the top gate dielectric layer.

[0061] The present invention provides a top gate dielectric layer 8 and a top gate control gate 9 on the silicon oxide seed layer 7;

[0062] In this invention, the material of the top gate dielectric layer 8 is preferably an HFO thin film, the thickness of the top gate dielectric layer is preferably 10 nm, and the width of the top gate dielectric layer is preferably 20-30 μm.

[0063] In this invention, the top gate control gate covers the middle region of the channel layer. In this invention, the top gate control gate is preferably any one or more of the following metals: gold, tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide.

[0064] In one embodiment of the present invention, the top gate control gate material is preferably gold or platinum; in the present invention, the thickness of the top gate control gate is preferably 30 nm, and the width of the top gate control gate is preferably 5 μm. The top gate control gate of the present invention partially covers the middle of the channel layer, and the dielectric layer between it and the channel layer is a High-k ferroelectric dielectric material. This allows for volatile regulation of a portion of the middle region of the channel, while providing no regulation effect on the uncovered channel region. Therefore, it is possible to achieve different conduction polarities in the middle of the channel compared to the two sides, forming a PNP or NPN rectifier structure and optimizing the transistor's electrical performance.

[0065] When the bottom-gate programming gate modulates the entire channel into N-type and the top-gate control gate modulates the middle of the channel into P-type, a PNP rectifier structure is formed. In this case, the sides of the channel are N-type and the middle is P-type, similar to the structure of a PNP transistor. Conversely, when the bottom-gate programming gate modulates the entire channel into P-type and the top-gate control gate modulates the middle of the channel into N-type, an NPN rectifier structure is formed. In this case, the sides of the channel are P-type and the middle is N-type, similar to the structure of an NPN transistor.

[0066] This invention also provides a method for fabricating a reconfigurable dual-gate transistor based on nano-ferroelectric materials, comprising the following steps:

[0067] After photolithography and development on an insulating substrate, the bottom gate layer is prepared by magnetron sputtering;

[0068] A ferroelectric dielectric layer was deposited on the bottom gate layer using atomic deposition.

[0069] A channel layer is formed by transferring bipolar semiconductor thin film material over a ferroelectric dielectric layer;

[0070] After photolithography is used to develop a semiconductor material layer, metal is deposited on both sides by thermal evaporation or electron beam evaporation to obtain the source and drain electrodes.

[0071] A silicon oxide seed layer and a top gate dielectric layer are sequentially prepared above the source and drain electrodes using electron beam evaporation.

[0072] The top gate control gate is fabricated above the top gate dielectric layer using photolithography.

[0073] The fabrication method of the reconfigurable dual-gate transistor based on nano-ferroelectric materials of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0074] Example 1

[0075] Step A: After photolithography and development on the insulating substrate, the bottom gate programming gate is prepared by magnetron sputtering;

[0076] A1: Cleaning of the insulating substrate

[0077] Select a silicon wafer with a silicon oxide insulating layer on its surface as the substrate. The thickness of the silicon oxide insulating layer is 300nm. Place the substrate in an ultrasonic cleaner and clean it with acetone, isopropanol and deionized water for 5 minutes in sequence. Finally, blow it dry with a nitrogen gun for later use.

[0078] A2: Apply the base photoresist

[0079] Place the target substrate from step A1 into a spin coating machine. Apply LOR10A photoresist to the target substrate using a dropper. Spin coat the substrate at 600 rpm for 5 seconds. In the second stage, increase the initial speed of 4000 rpm by 1000 rpm every 5 seconds to 4000 rpm and maintain this speed for 40 seconds. After coating, bake the substrate at 150°C for 180 seconds using a heater. After baking, apply AZ5214E ​​photoresist to the target substrate using a dropper. Spin coat the substrate at 600 rpm for 5 seconds. In the second stage, increase the initial speed of 4000 rpm by 1000 rpm every 5 seconds to 4000 rpm and maintain this speed for 40 seconds. After coating, bake the substrate at 100°C for 90 seconds using a heater.

[0080] A3: Ultraviolet Lithography

[0081] Place the target substrate from step A2 into the contact exposure machine system, perform alignment, gap elimination and other correction actions, and then perform the exposure operation. After exposure, the sample is used as the target substrate for later use.

[0082] A4: Development

[0083] Prepare two beakers, pour developer into one and deionized water into the other. The developer used in this step is SUN-238D. After immersing the target substrate from step A3 in the developer for a few seconds, rinse it in deionized water to remove any remaining developer and dry it with a nitrogen gun for later use.

[0084] A5: Magnetron sputtering

[0085] Using a magnetron sputtering instrument, 20 nm of TiN / W is sputtered onto the target substrate in step A4 for later use;

[0086] A6: Lift-off peeling

[0087] Place the target substrate from step A5 into a petri dish filled with N-methylpyrrolidone (NMP) for about 0.5 hours to dissolve the photoresist and wash away all the undeveloped coating. Rinse again with deionized water to remove any remaining metal and organic solvents. Then dry the sample surface with a nitrogen gun to complete the stripping process and form the bottom gate programming gate.

[0088] Step B: Deposit a ferroelectric dielectric layer on the bottom gate layer using atomic deposition;

[0089] B1: Growth of zirconium-doped hafnium-based material layer

[0090] The substrate with a bottom-gate programming gate prepared in step A is placed in an atomic layer deposition (ALD) apparatus, the ratio of hafnium source to zirconium source is adjusted to 1:1, and an atomic layer deposition program is executed. After 100 deposition cycles, a zirconium-doped hafnium-based oxide ferroelectric material layer of approximately 10 nm is grown on the wafer for later use.

[0091] B2: Passivation layer growth

[0092] The substrate with the ferroelectric dielectric layer grown in step B1 is placed in the atomic layer deposition equipment again. The zirconium source pulse time is adjusted to about 100ms, and the atomic layer deposition program is executed. After 10 deposition cycles, a zirconium oxide layer of about 1nm is grown on the wafer as a passivation layer. The wafer is then removed, cooled, and set aside for later use.

[0093] B3: Rapid Annealing

[0094] The substrate of the passivation layer in step B2 is placed in a rapid annealing (RTP) apparatus to perform a rapid annealing process, so that ferroelectricity is generated in the zirconium-doped hafnium-based oxide dielectric layer, thus completing the preparation of the ferroelectric dielectric layer.

[0095] Step C: Transfer bipolar semiconductor thin film material over the ferroelectric dielectric layer to form a channel layer;

[0096] C1: Fabrication of bipolar semiconductor thin films

[0097] The layered bipolar semiconductor crystal blocks WSe2 and MoTe2 were transposed once using England Blue tape. Then, another piece of England Blue tape was peeled off from the transposed England Blue tape, splitting the semiconductor material in two. After repeating this process several times, the semiconductor material on the England Blue tape became relatively thin. Subsequently, the semiconductor material sheet was attached to a mechanically peelable PDMS gel film attached to a glass slide and then gently peeled off. The PDMS gel film was observed under an optical microscope. The semiconductor film was selected with a thickness of 5-15 nm, a uniform surface, and a length of 15-20 μm.

[0098] C2: Transfer of bipolar semiconductor thin films

[0099] Using a two-dimensional material transfer system and a matching microscope, the semiconductor thin film material on the PDMS gel film prepared in step C1 is transferred to the top of the bottom gate programming gate and the ferroelectric dielectric layer prepared in step B, thus completing the preparation and transfer of the bipolar semiconductor thin film material to form a channel layer.

[0100] Step D: Metal is deposited on both sides of the channel layer using photolithography to obtain the source and drain electrodes;

[0101] D1: Apply photoresist

[0102] Place the target substrate for which the trench layer is formed in step C into a spin coating machine. Drop electron beam MMA photoresist onto the target substrate using a dropper. Spin coat the substrate at 600 rpm for 10 seconds, followed by a second stage at 4000 rpm for 30 seconds. After coating, bake the substrate at 150°C for 60 seconds using a heater. Then, drop electron beam PMMA photoresist onto the target substrate using a dropper. Spin coat the substrate at 600 rpm for 10 seconds, followed by a second stage at 4000 rpm for 30 seconds. After coating, bake the substrate at 150°C for 60 seconds using a heater.

[0103] D2: Electron beam lithography

[0104] The target substrate from step D1 is placed in the electron beam lithography system, and current, image, and other correction actions are measured. The exposure dose is then set to 400 μC / cm. 2 After confirming the three alignment points, the instrument will automatically perform correction actions. At this time, the exposure operation will be carried out, and the exposed sample will be used as the target substrate for later use.

[0105] D3: Development

[0106] Prepare two beakers, one filled with developer and the other with IPA solution. The developer used in this step is a diluted solution of MIBK (4-methyl-2-pentanone) mixed in a 1:3 ratio. After immersing the target substrate in the developer for a few seconds, wash it in isoacetone to remove any remaining developer and dry it with a nitrogen gun for later use.

[0107] D4: Evaporation

[0108] Thermal evaporation of metal: Gold is deposited using a conventional vacuum thermal evaporation method with a current of 80-90A and a rate of 0.1-0.12nm / s. A 30nm layer of metallic gold is deposited on the target substrate in step D3 for later use.

[0109] D5: Lift-off peeling

[0110] The target substrate in step D4 was placed in a petri dish filled with acetone for about 0.5 hours to dissolve the photoresist and wash away all the undeveloped coating. The sample surface was then dried with a nitrogen gun to complete the stripping process. After electron beam lithography, the source and drain were fabricated, thus completing the reconfigurable ferroelectric transistor with source and drain and bottom gate programming gate.

[0111] Step E: A silicon oxide seed layer and a top gate dielectric layer are sequentially prepared above the source and drain electrodes using electron beam evaporation;

[0112] E1: Growth of silica seed layer

[0113] The ferroelectric transistor prepared in step D is placed in an electron beam evaporation apparatus. The beam current for evaporating silicon oxide is 1-2A and the rate is 0.1-0.12nm / s. A 2nm silicon oxide seed layer is grown on the source and drain for later use.

[0114] E2: Hafnium oxide dielectric layer growth

[0115] The ferroelectric transistor with the silicon oxide seed layer grown in step E1 is placed in an atomic layer deposition equipment. The hafnium source pulse time is adjusted to about 100ms, and the atomic layer deposition program is executed. After 100 deposition cycles, a hafnium oxide layer of about 10nm is grown on the wafer as the top gate dielectric layer. It is then removed, cooled, and set aside for later use.

[0116] Step F: Fabricate the top gate control gate above the top gate dielectric layer using photolithography;

[0117] F1: Apply photoresist

[0118] The ferroelectric transistor with the top gate dielectric layer in step E is placed in a spin coating machine. Electron beam MMA photoresist is dropped onto the target substrate using a dropper. The spin coating machine is used to rotate at 600 rpm for 10 seconds, followed by a second stage at 4000 rpm for 30 seconds. After coating, the heater controls the baking tray temperature to 150°C and bakes for 60 seconds. Then, electron beam MMA photoresist is dropped onto the target substrate again using a dropper. The spin coating machine is used to rotate at 600 rpm for 10 seconds, followed by a second stage at 4000 rpm for 30 seconds. After coating, the heater controls the baking tray temperature to 150°C and bakes for 60 seconds.

[0119] F2: Electron beam lithography

[0120] The ferroelectric transistor from step F1 is placed in an electron beam lithography system, and current, image, and other correction actions are measured. The exposure dose is then set to 400 μC / cm. 2 After confirming the three alignment points, the instrument will automatically perform a correction action. At this time, the exposure operation will be carried out, and the sample will be ready for use after exposure.

[0121] F3: Development

[0122] Prepare two beakers, one filled with developer and the other with IPA solution. The developer used in this step is a diluted solution of MIBK (4-methyl-2-pentanone) mixed evenly in a 1:3 ratio. After immersing the sample from step F2 in the developer for a few seconds, wash off the residual developer in isoacetone and dry it with a nitrogen gun for later use.

[0123] F4: Evaporation

[0124] Thermal evaporation of metal: Gold is deposited using a conventional vacuum thermal evaporation method with a current of 80-90A and a rate of 0.1-0.12nm / s. A 30nm thick and 5µm wide metallic gold layer is deposited on the sample after development in step F3 for later use.

[0125] F5: Lift-off peeling

[0126] The target substrate from step F4 was placed in a petri dish filled with acetone for approximately 0.5 hours to dissolve the photoresist and simultaneously rinse away any undeveloped coating. The sample surface was then dried with a nitrogen gun to complete the lift-off process. After electron beam lithography, the top-gate control gate was fabricated, ultimately resulting in a reconfigurable ferroelectric transistor with source and drain electrodes, a bottom-gate programming gate, and a top-gate control gate. The detailed structure is shown below. Figure 3 As shown.

[0127] This invention relates to a reconfigurable transistor designed based on semiconductor thin film materials and nano-ferroelectric materials. By controlling the polarization state of the ferroelectric dielectric layer through a bottom-gate programming gate, the polarity of the channel layer semiconductor is controlled. Furthermore, by using a partially covered control gate, a PNP / NPN rectification structure is achieved in the same channel, further improving the device's electrical performance and optimizing its non-volatility. This allows for better application in neuromorphic computing, reconfigurable logic circuits, and other scenarios, further simplifying circuit complexity and improving computational efficiency.

[0128] like Figure 4 As shown, the reconfigurable ferroelectric transistor prepared in Example 1 can exhibit different conduction polarities and threshold voltages under different ferroelectric polarization states.

[0129] like Figure 5 As shown, the reconfigurable ferroelectric transistor prepared in Example 1 can exhibit different conduction polarities and threshold voltages under different ferroelectric polarization states, while also exhibiting a negligible hysteresis window and a low subthreshold swing.

[0130] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any way. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A reconfigurable dual-gate transistor based on nano-ferroelectric materials, comprising: Substrate, An insulating layer is disposed on the substrate. A bottom-gate programming gate is disposed on the insulating layer. A ferroelectric dielectric layer is disposed on the bottom-gate programming gate. A channel layer is disposed on the ferroelectric dielectric layer, and the channel layer is a bipolar semiconductor thin film. Source and drain electrodes are disposed on the left and right sides above the channel layer. A silicon oxide seed layer is provided on the source and drain electrodes. A top gate dielectric layer and a top gate control gate are disposed on the silicon oxide seed layer; The bottom gate programming gate completely covers the channel layer, and the top gate control gate covers the middle region of the channel layer.

2. The reconfigurable dual-gate transistor according to claim 1, characterized in that, The materials of the bottom gate programming gate and the top gate control gate are independently selected from any one or more of the following: tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide. The thickness of the bottom gate programming gate is 20nm, and the width of the bottom gate programming gate is 30um to 50um.

3. The reconfigurable dual-gate transistor according to claim 2, characterized in that, The bottom gate programming gate material is titanium nitride and / or tungsten metal.

4. The reconfigurable dual-gate transistor according to claim 1, characterized in that, The ferroelectric dielectric layer includes a hafnium-based ferroelectric material layer, wherein the hafnium-based ferroelectric material includes HfZrO. X HfAlO X HfSiO X HfTiO X and HfYO X Any one of them.

5. The reconfigurable dual-gate transistor according to claim 1 or 4, characterized in that, The ferroelectric dielectric layer includes a passivation layer deposited on top of the hafnium-based ferroelectric material layer, and the passivation film includes hafnium oxide and / or zirconium oxide.

6. The reconfigurable dual-gate transistor according to claim 1 or 5, characterized in that, The thickness of the ferroelectric dielectric layer is 10–20 nm.

7. The reconfigurable dual-gate transistor according to claim 1, characterized in that, The thickness of the bipolar semiconductor thin film is 5-15 nm; the bipolar semiconductor thin film is a Wse2 / MoTe2 thin film.

8. The reconfigurable dual-gate transistor according to claim 1, characterized in that, The source and drain materials are independently selected from any one of the following: gold, tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide.

9. The reconfigurable dual-gate transistor according to claim 1, characterized in that, The thickness of the top gate dielectric layer is 10 nm, and the width of the top gate dielectric layer is 20–30 μm; The thickness of the top gate control gate is 30 nm, and the width of the top gate control gate is 5 μm.

10. A method for fabricating a reconfigurable dual-gate transistor as described in any one of claims 1 to 9, comprising the following steps: After photolithography and development on an insulating substrate, the bottom gate layer is prepared by magnetron sputtering; A ferroelectric dielectric layer was deposited on the bottom gate layer using atomic deposition. A channel layer is formed by transferring bipolar semiconductor thin film material over a ferroelectric dielectric layer; After photolithography is used to develop a semiconductor material layer, metal is deposited on both sides by thermal evaporation or electron beam evaporation to obtain the source and drain electrodes. A silicon oxide seed layer and a top gate dielectric layer are sequentially prepared above the source and drain electrodes using electron beam evaporation. The top gate control gate is fabricated above the top gate dielectric layer using photolithography.

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