Novel high-k gate dielectric source region extension double-gate tunnel field effect transistor

Abstract

The invention provides a novel high-k gate dielectric source region extending double-gate tunnel field effect transistor which comprises a source region, a channel region and a drain region which are sequentially arranged from left to right, the left side of the channel region is a thin end, the right side of the channel region is a thick end, the source region is embedded in the thin end of the channel region, a low-k insulator layer is arranged between the right side of the source region and the channel region, and the drain region is embedded in the low-k insulator layer. The thick end of the channel region is connected with the drain region with the same thickness; the upper side and the lower side of the channel region are both covered with high-k gate media. The left side of the source region is provided with a source electrode; one side, far away from the channel region, of the high-k gate dielectric layer is provided with a gate electrode; a drain electrode is arranged on the right side of the drain region; the low-k insulator layer is prepared from a low-k insulator material, and the high-k gate dielectric layer is prepared from a high-k insulator material; and the source region, the channel region and the drain region are prepared from silicon. The problems that the ratio of on-state current to switching current of the double-gate tunnel field effect transistor is small, and the sub-threshold swing is large can be solved.

Description

Technical Field

[0001] This invention relates to a dual-gate tunneling field-effect transistor, specifically to a novel high-k gate dielectric source region extended dual-gate tunneling field-effect transistor (HK-ES-DGTFET). Background Technology

[0002] In recent decades, the feature size of metal-oxide-semiconductor field-effect transistors (MOSFETs) has continued to shrink to maintain Moore's Law. However, due to the physical operating mechanism of MOSFETs, their subthreshold swing (SS) is limited to above 60mV / dec, which prevents the MOSFET's supply voltage (VDD) from continuously decreasing.

[0003] To overcome the subthreshold swing limitation of MOSFETs and perpetuate Moore's Law, researchers have proposed numerous solutions. Among them, tunneling field-effect transistors (TFETs) are considered one of the best alternatives to MOSFETs. TFETs have successfully reduced the current surge range (SS) to below 60mV / dec through inter-band tunneling. The dual-gate tunneling field-effect transistor (DGTFET) is a common TFET structure. However, the SS of DGTFETs is still quite high, and their on-state current is several orders of magnitude lower than that of MOSFETs, making it difficult to meet the demands of future ultra-low-power integrated circuits. Therefore, designing TFET device structures with superior performance is crucial for the development of future ultra-low-power integrated circuits.

[0004] like Figure 1 The diagram shows a schematic of a prior art silicon-based dual-gate tunneling field-effect transistor (Si-DGTFET), including a drain region 03, a channel region 02, and a source region 01 arranged sequentially from right to left. A low-k gate dielectric layer 04 is disposed at both the upper and lower ends of the channel region 02. As can be seen from the diagram, the gate electrode of the Si-DGTFET is located at the top of the upper low-k gate dielectric layer 04 and the bottom of the lower low-k gate dielectric layer 04, the drain electrode is located on the right side of the drain region, and the source electrode is located on the left side of the source region. Summary of the Invention

[0005] The purpose of this invention is to provide a novel high-k gate dielectric source region extended dual-gate tunnel field-effect transistor to improve the problems of small on-state current and switching current ratio and large SS of DGTFET.

[0006] The technical solution adopted in this invention is:

[0007] A novel high-k gate dielectric source-region extended dual-gate tunnel field-effect transistor includes a drain region, a channel region, and a source region arranged sequentially from right to left. Its distinctive feature is that:

[0008] The source region is buried in the middle of the left side of the trench region, and there is a low-k insulating layer between the right side of the source region and the trench region.

[0009] The thin end of the channel region is connected to the source region, and the length of the thin end of the channel region is equal to the sum of the lengths of the source region and the low-k insulating layer. The thick end of the channel region is connected to the drain region, and the two have the same thickness.

[0010] The channel region is covered by a high-k gate dielectric layer on both the upper and lower sides, and the length of the high-k gate dielectric layer is equal to the sum of the lengths of the thin end of the channel region and the thin end of the channel region.

[0011] The source electrode is located on the left side of the source region; the gate electrodes are located at the top of the upper high-k gate dielectric layer and the bottom of the lower high-k gate dielectric layer, respectively; and the drain electrode is located on the right side of the drain region.

[0012] The low-k insulating layer is fabricated using a low-k insulating material, and the high-k gate dielectric layer is fabricated using a high-k insulating material; the source region, channel region, and drain region are all fabricated using silicon.

[0013] Furthermore, the high-k gate dielectric material is a high-k insulator material such as HfO2 or Al2O3; the low-k insulating layer material is SiO2, where k represents the relative permittivity.

[0014] Furthermore, the source region has a length of 24 nm and a thickness of 10–14 nm.

[0015] Furthermore, the length of the low-k insulating layer is 1 nm.

[0016] Furthermore, the thickness of the low-k insulating layer is the same as the thickness of the source region, which is 10–14 nm.

[0017] Furthermore, the length of the thick end of the channel region is 25 nm and the thickness is 20 nm.

[0018] Furthermore, the length of the two thin ends on the left side of the channel region is 25 nm, and the thickness is 3-5 nm.

[0019] Furthermore, the length of the drain region is 10–20 nm.

[0020] Furthermore, the thickness of the drain region is the same as the thickness of the thick end of the channel region, which is 20 nm.

[0021] Furthermore, the length of the high-k gate dielectric layer is equal to the sum of the lengths of the thick end and the thin end of the channel region, which is 50 nm.

[0022] Furthermore, the thickness of the high-k gate dielectric layer is 2–4 nm.

[0023] Furthermore, the source region is P-type and the drain region is N-type; or the source region is N-type and the drain region is P-type; the doping type of the channel region is the same as that of the source region; wherein, the N-type dopant is arsenic or phosphorus, and the P-type dopant is boron.

[0024] Furthermore, the doping concentration of the drain region is 1×10⁻⁶. 17 ~1×10 18 cm -3 The source region doping concentration is 1×10⁻⁶. 19 ~1×10 20 cm -3 The doping concentration in the channel region is 1×10⁻⁶. 15 ~1×10 17 cm -3 .

[0025] Furthermore, the work function of the gate electrode material is set to 4.0–4.3 eV.

[0026] The beneficial effects of this invention are:

[0027] 1. In this invention, the source region is buried in the middle of the left side of the trench to form a double-line tunnel structure between the source region and the trench region;

[0028] A high-k gate dielectric layer structure is introduced by using a high-k insulating material;

[0029] An isolation layer structure is formed by setting a layer of SiO2 between the right side of the source region and the channel region.

[0030] The tunneling field-effect transistor in this invention has a lower subthreshold swing, a higher on-state current, and a higher switching current ratio compared to the traditional dual-gate tunneling field-effect transistor.

[0031] 2. In this invention, the double-line tunneling structure can effectively increase the on-state current by introducing double the line tunneling.

[0032] 3. In this invention, the high-k gate dielectric layer structure reduces the effective oxide layer thickness of the gate dielectric, which significantly reduces SS.

[0033] 4. In this invention, the isolation layer structure used makes the invention only have line tunneling mode, which suppresses the point tunneling current under low voltage and the SS is significantly reduced.

[0034] 5. This invention is applicable to the fabrication of semiconductor devices in the field of low-power integrated circuits. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the structure of a current silicon-based dual-gate tunneling field-effect transistor;

[0036] Figure 2 This is a schematic diagram of the structure of an embodiment of the novel high-k gate dielectric source region extended dual-gate tunnel field-effect transistor of the present invention;

[0037] Figure 3 This is a comparison graph (logarithmic scale) of the transfer characteristic curves of the embodiments of the present invention and the prior art in the gate voltage range of 0V to 1V;

[0038] Figure 4 This is an embodiment of the invention when the gate voltage is 1V. Figure 2 Band diagram at the tangent line (dashed line);

[0039] Figure 5 This is a graph (logarithmic scale) showing the transfer characteristics of the high-k gate dielectric layer thickness within the gate voltage range of 0V to 1V according to an embodiment of the present invention.

[0040] Figure 6 This is a graph (logarithmic scale) showing the transfer characteristics as a function of the gate metal work function within the gate voltage range of 0V to 1V according to an embodiment of the present invention.

[0041] Figure label:

[0042] 01: Source region; 02: Channel region; 03: Drain region; 04: Low-k gate dielectric layer;

[0043] 1: Source region; 2: Channel region; 3: Drain region; 4: High-k gate dielectric layer; 5: Low-k insulating layer. Detailed Implementation

[0044] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0045] The left and right in the text are... Figure 1 or Figure 2 Described from the perspective of [the author / organization].

[0046] Example 1

[0047] This invention proposes a novel high-k gate dielectric source region extended dual-gate tunneling field-effect transistor, such as... Figure 2 As shown, it includes source region 1, channel region 2, drain region 3, high-k gate dielectric layer 4, and low-k insulating layer 5;

[0048] Source region 1 is buried in the middle of the left side of trench region 2, and there is a low-k insulating layer 5 between the right side of source region 1 and trench region 2.

[0049] The thin end of the channel region 2 is connected to the source region 1. The length of the thin end of the channel region 2 is equal to the sum of the lengths of the source region 1 and the low-k insulating layer 5. The thick end of the channel region 2 is connected to the drain region 3, and the two have the same thickness.

[0050] Both the upper and lower sides of the channel region 2 are covered by a high-k gate dielectric layer 4, and the length of the high-k gate dielectric layer 4 is equal to the sum of the lengths of the thin end of the channel region 2 and the thin end of the channel region 2.

[0051] The source electrode is located on the left side of source region 1;

[0052] The gate electrodes are respectively disposed at the top of the upper high-k gate dielectric layer 5 and at the bottom of the lower high-k gate dielectric layer 5;

[0053] The drain electrode is located on the right side of drain region 3.

[0054] High-k gate dielectric materials include high-k insulator materials such as HfO2 and Al2O3; low-k gate dielectric materials include SiO2.

[0055] A novel high-k gate dielectric source region extended dual-gate tunnel field-effect transistor is symmetrical about the left and right directions as the axis of symmetry.

[0056] Silicon material is used in source region 1, channel region 2 and drain region 3.

[0057] Source region 1 and drain region 3 are doped with opposite types of impurities, i.e., source region 1 is P-type and drain region 3 is N-type; or source region 1 is N-type and drain region 3 is P-type. Channel region 2 is doped with the same type of impurities as source region 1, i.e., channel region 2 and source region 1 are both P-type or N-type. The N-type dopant is arsenic or phosphorus, and the P-type dopant is boron. For the novel N-type high-k gate dielectric source-extended dual-gate tunnel field-effect transistor, source region 1 is P-type doped with a doping concentration of 1 × 10⁻⁶. 19 ~1×10 20 cm -3 Drain region 3 is N-type doped with a doping concentration of 1×10⁻⁶. 17 ~1×10 18 cm -3 Channel region 2 is P-type doped with a doping concentration of 1×10⁻⁶. 15 ~1×10 17 cm -3 For the novel P-type high-k gate dielectric source-region extended dual-gate tunnel field-effect transistor, source region 1 is N-type doped with a doping concentration of 1×10⁻⁶. 19 ~1×10 20 cm -3 Drain region 3 is P-type doped with a doping concentration of 1×10⁻⁶. 17 ~1×10 18 cm -3 Channel region 2 is N-type doped with a doping concentration of 1×10⁻⁶. 15 ~1×10 17 cm -3 .

[0058] The source region 1 has a length of 24 nm and a thickness of 10–14 nm.

[0059] The length of the low-k insulating layer 5 is 1 nm.

[0060] The thickness of the low-k insulating layer 5 is the same as that of the source region 1, which is 10–14 nm.

[0061] The length of the thick end of the channel region 2 is 25 nm, and the thickness is 20 nm.

[0062] The length of the two thin ends on the left side of channel region 2 is 25 nm, and the thickness is 3-5 nm.

[0063] The length of drain region 3 is 10–20 nm.

[0064] The thickness of the drain region 3 is the same as the thickness of the thick end of the channel region 2, both being 20 nm.

[0065] The length of the high-k gate dielectric layer 4 is equal to the sum of the lengths of the thick end and the thin end of the channel region 2, which is 50 nm.

[0066] The thickness of the high-k gate dielectric layer 4 is 2–4 nm.

[0067] The basic structure of the device in this invention is a silicon-based dual-gate tunneling field-effect transistor. By constructing a double-line tunneling structure, double the line tunneling is introduced, which can effectively improve the on-state current. This invention constructs a high-k gate dielectric layer structure, which reduces the effective oxide layer thickness of the gate dielectric and significantly reduces SS. This invention constructs an isolation layer structure, so that this invention only has line tunneling mode, and SS is greatly improved.

[0068] Compared to traditional silicon-based dual-gate tunnel field-effect transistors, the on-state current of this invention is increased by three orders of magnitude, and the minimum SS is reduced to below 10mV / dec.

[0069] In this invention, a specific embodiment is given as follows:

[0070] The doping concentration of P-type source region 1 is 1×10⁻⁶. 20 cm -3 It has a length of 24 nm and a thickness of 14 nm, and is made of silicon (Si); the doping concentration of N-type drain region 3 is 1 × 10⁻⁶. 18 cm -3The drain region 3 has a length of 10 nm and a thickness of 20 nm, and is made of silicon (Si). The doping concentration of the P-type channel region 2 is 1 × 10¹⁷ cm⁻³, with a length of 25 nm and a thickness of 20 nm at the thick end, and a length of 25 nm and a thickness of 3 nm at the two thin ends on the left. The high-k gate dielectric layer 4 has a thickness of 2 nm and a length of 50 nm, and is made of high-k insulating material HfO₂. The low-k insulating layer 5 has a thickness of 14 nm and a length of 1 nm, and is made of low-k insulating material SiO₂. The N-type dopant is arsenic (As), and the P-type dopant is boron (B). The gate work function is set to 4.3 eV.

[0071] Figure 1 This is a schematic diagram of a silicon-based dual-gate tunneling field-effect transistor, including: source region 01, channel region 02, drain region 03, and low-k gate dielectric layer 04. Source region 01 and channel region 02 are P-type boron doped with doping concentrations of 1×10⁻⁶. 20 cm -3 and 1×10 17 cm -3 Drain region 03 is doped with N-type arsenic at a concentration of 1×10⁻⁶. 18 cm -3 The source region 01, channel region 02 and drain region 03 are all made of silicon with a thickness of 20nm. The lengths of the source region 01, channel region 02 and drain region 03 are 10nm, 50nm and 10nm respectively. The low-k gate dielectric layer 04 at the top and bottom ends of the channel region 2 is made of SiO2 with a thickness of 2nm. The gate work function is set to 4.3eV.

[0072] Figure 3 This is a comparison graph showing the transfer characteristics of the embodiments of the present invention and the background technology (silicon-based dual-gate tunneling field-effect transistor) within the gate voltage range of 0V to 1V. The comparison graph uses logarithmic coordinates. As can be seen from the graph, compared with the silicon-based dual-gate tunneling field-effect transistor, the transistor using the structure of the present invention has a higher on-state current and a lower SS.

[0073] Figure 4 This is an embodiment of the invention when the gate voltage is 1V. Figure 2 The energy band diagram at the tangent line (dashed line) shows band-to-band tunneling between the conduction and valence bands at the source and channel junctions. Compared to point tunneling, line tunneling has a higher tunneling probability, significantly increasing the on-state current.

[0074] Figure 5 This is a graph showing the transfer characteristics of the device as a function of the high-k gate dielectric layer thickness within a gate voltage range of 0V to 1V, using logarithmic coordinates. As can be seen from the graph, as the thickness of the high-k gate dielectric layer increases, the effective oxide layer thickness of the gate dielectric increases, thereby increasing the SS (susceptibility limit) of the device.

[0075] Figure 6 This is a graph showing the transfer characteristics of the device as a function of the gate metal work function within a gate voltage range of 0V to 1V, using logarithmic coordinates. As can be seen from the graph, as the gate metal work function decreases, the transfer characteristic curve shifts to the left, increasing the on-state current, but the average SS (superconducting current) also increases.

[0076] Furthermore, taking the novel N-type high-k gate dielectric source-region extended dual-gate tunneling field-effect transistor as an example, when the embodiment of the present invention is in the on-state (Vd = 1V, Vg = 1V), compared with the conventional silicon-based dual-gate tunneling field-effect transistor under the same operating conditions (Vd = 1V, Vg = 1V), the on-state current of the novel N-type high-k gate dielectric source-region extended dual-gate tunneling field-effect transistor is about three orders of magnitude higher. In addition, the minimum SS of the novel N-type heterojunction heterogate dielectric dual-gate tunneling field-effect transistor is less than 10mV / dec. These electrical characteristics demonstrate that the present invention has excellent operating characteristics and can meet the requirements of low-power devices.

[0077] This invention, through research on the structural optimization and performance prediction of novel high-k gate dielectric source region extended dual-gate tunnel field-effect transistors, has found a solution that helps improve subthreshold swing and on-state current, thus improving the problems of small on-state current and switching current ratio, and large subthreshold swing of dual-gate tunnel field-effect transistors.

[0078] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A novel high-k gate dielectric source-region extended dual-gate tunneling field-effect transistor, comprising a source region (1), a channel region (2), and a drain region (3) arranged sequentially from left to right, characterized in that: The left side of the channel region (2) is thin and the right side is thick. The source region (1) is buried in the thin end of the channel region (2). There is a low-k insulating layer (5) between the right side of the source region (1) and the channel region (2). The length of the thin end of the channel region (2) is equal to the sum of the lengths of the source region (1) and the low-k insulating layer (5). The thick end of the channel region (2) is connected to the drain region (3) of equal thickness. The channel region (2) is covered with a high-k gate dielectric layer (4) on both the upper and lower sides; A source electrode is disposed on the left side of the source region (1); a gate electrode is disposed on the side of the high-k gate dielectric layer (4) away from the channel region (2); and a drain electrode is disposed on the right side of the drain region (3). The low-k insulating layer (5) is made of low-k insulating material, and the high-k gate dielectric layer (4) is made of high-k insulating material; the source region (1), channel region (2) and drain region (3) are all made of silicon.

2. The novel high-k gate dielectric source region extended dual-gate tunneling field-effect transistor according to claim 1, characterized in that: The material of the high-k insulator is HfO2 or Al2O3; The material of the low-k insulator is SiO2.

3. The novel high-k gate dielectric source region extended dual-gate tunneling field-effect transistor according to claim 2, characterized in that: The length of the high-k gate dielectric layer (4) is equal to the sum of the lengths of the thin end of the channel region (2) and the thick end of the channel region (2); The thickness of the high-k gate dielectric layer (4) is 2-4 nm.

4. The novel high-k gate dielectric source region extended dual-gate tunneling field-effect transistor according to claim 3, characterized in that: The source region (1) has a length of 24 nm and a thickness of 10–14 nm.

5. The novel high-k gate dielectric source region extended dual-gate tunneling field-effect transistor according to claim 4, characterized in that: The thickness of the low-k insulating layer (5) is 10–14 nm; the length of the low-k insulating layer (5) is 1–3 nm.

6. The novel high-k gate dielectric source region extended dual-gate tunneling field-effect transistor according to claim 5, characterized in that: The length of the leak region (3) is 10-20 nm.

7. The novel high-k gate dielectric source region extended dual-gate tunneling field-effect transistor according to any one of claims 1-6, characterized in that: The source region (1) is P-type and the drain region (3) is N-type; or the source region (1) is N-type and the drain region (3) is P-type; the doping type of the channel region (2) is the same as that of the source region (1); wherein, the N-type doping element is arsenic or phosphorus, and the P-type doping element is boron.

8. The novel high-k gate dielectric source region extended dual-gate tunneling field-effect transistor according to claim 7, characterized in that: The doping concentration of the drain region (3) is 1×10⁻⁶. 17 ~1×10 18 cm -3 ; The doping concentration of the source region (1) is 1×10 19 ~1×10 20 cm -3 ; The doping concentration of the channel region (2) is 1×10 15 ~1×10 17 cm -3 .

9. The novel high-k gate dielectric source region extended dual-gate tunneling field-effect transistor according to claim 8, characterized in that: The work function of the gate electrode material is 4.0 to 4.3 eV.

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