Stacked device structure and forming method thereof

Abstract

An exemplary stacked device structure includes a semiconductor layer stack disposed over a substrate and a dual work function metal (DWFM) gate. The semiconductor layer stack includes a first semiconductor layer disposed over a second semiconductor layer. The DWFM gate includes a first gate dielectric layer, a second gate dielectric layer, a first type work function metal layer, and a second type work function metal layer. A first gate dielectric layer is disposed over the first semiconductor layer, and a second gate dielectric layer is disposed over the second semiconductor layer. A first type of work function metal layer is disposed over the first gate dielectric layer, and a second type of work function metal layer is disposed over the second gate dielectric layer. At least one of the first type of work function metal layer or the second type of work function metal layer has a gradient composition. The embodiment of the invention also relates to a stacked device structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of this application relate to stacked device structures and methods of forming the same. Background Technology

[0002] The electronics industry has experienced a growing demand for smaller, faster electronic devices capable of supporting a greater number of increasingly complex and sophisticated functions. To meet these demands, there is a persistent trend in the integrated circuit (IC) industry towards manufacturing low-cost, high-performance, and low-power ICs. To date, these goals have been largely achieved by reducing IC size (e.g., by reducing the size of the smallest IC component), and more recently, by introducing stacked device structures to achieve further density reduction. However, such scaling also increases the complexity of IC devices and manufacturing. Therefore, improvements are needed. Summary of the Invention

[0003] Some embodiments of this application provide a stacked device structure, including: a semiconductor layer stack disposed above a substrate, wherein the semiconductor layer stack includes a first semiconductor layer of a first device disposed above a second semiconductor layer of a second device, wherein the first device is disposed above the second device; and a gate comprising: a first gate dielectric layer and a second gate dielectric layer, wherein the first gate dielectric layer is disposed above the first semiconductor layer and the second gate dielectric layer is disposed above the second semiconductor layer; and a first type of work function metal layer and a second type of work function metal layer, wherein the first type of work function metal layer is disposed above the first gate dielectric layer and the second type of work function metal layer is disposed above the second gate dielectric layer, and at least one of the first type of work function metal layer or the second type of work function metal layer has a gradient composition.

[0004] Some other embodiments of this application provide a stacked device structure, including: a semiconductor layer stack disposed above a substrate, wherein the semiconductor layer stack includes a first semiconductor layer disposed above a second semiconductor layer; and a gate comprising: a first gate dielectric layer and a second gate dielectric layer, wherein the first gate dielectric layer is disposed above the first semiconductor layer, and the second gate dielectric layer is disposed above the second semiconductor layer; a p-type power function metal layer disposed above the second gate dielectric layer and around the second semiconductor layer; and an n-type power function metal layer disposed above the first gate dielectric layer and around the first semiconductor layer, wherein the n-type power function metal layer is disposed on the p-type power function metal layer, wherein the n-type power function metal layer includes a first metal and a second metal, the p-type power function metal layer includes the first metal and nitrogen, and the portion of the p-type power function metal layer adjacent to the n-type power function metal layer further includes a third metal.

[0005] Further embodiments of this application provide a method for forming a stacked device structure, comprising: forming a first gate dielectric over a lower channel structure and forming a second gate dielectric over an upper channel structure, wherein the channel stack includes the upper channel structure located above the lower channel structure; forming a first type of work function layer having a first gradient composition over the first gate dielectric; and forming a second type of work function layer having a second gradient composition over the second gate dielectric. Attached Figure Description

[0006] The embodiments of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale and are for illustrative purposes only. In practice, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A This is a partial or complete cross-sectional view of a stacked device structure having a bifunctional metal gate according to various aspects of embodiments of the present disclosure.

[0008] Figure 1B and Figure 1C It is based on various aspects of the embodiments of this disclosure. Figure 1A A partial or complete cross-sectional view of a stacked device structure.

[0009] Figures 2 to 7 The various aspects of embodiments according to this disclosure are described. Figures 1A to 1C Various configurations of partial or complete dual-function metal gates implemented in the gate of a stacked device structure.

[0010] Figure 8 and Figure 9 It is based on various aspects of the embodiments of this disclosure. Figure 1A A cross-sectional view of part or all of the other configurations of the bifunctional metal gate of the stacked device structure.

[0011] Figure 10 Gates (such as those for fabricating stacked device structures) according to various aspects of embodiments of this disclosure. Figures 1A to 1C A flowchart of part or all of the method for constructing a stacked device structure with a bifunctional metal gate.

[0012] Figure 11A This is a partial or complete cross-sectional view of another stacked device structure according to various aspects of embodiments of this disclosure.

[0013] Figure 11B and Figure 11C It is based on various aspects of the embodiments of this disclosure. Figure 11A A partial or complete cross-sectional view of a stacked device structure.

[0014] Figures 12 to 14 The various aspects of embodiments according to this disclosure are described. Figures 11A to 11C Various configurations of the p-type work function metal layer implemented in the gate of the stacked device structure.

[0015] Figure 15 The present disclosure describes various aspects of the fabrication of a stacked device structure, including gates (such as...) Figures 11A to 11C The deposition process can be partially or completely implemented when the gate of a stacked device structure is used.

[0016] Figure 16 Gates (such as those for fabricating stacked device structures) according to various aspects of embodiments of this disclosure. Figures 11A to 11C A flowchart of part or all of the method for constructing a stacked device structure with a bifunctional metal gate.

[0017] Figures 17A to 17E Stacked device structures (such as) according to various aspects of embodiments of this disclosure Figures 11A to 11C (Stacked device structure) in relation to Figure 16 The method involves partial or complete cross-sectional views of each manufacturing stage. Detailed Implementation

[0018] This disclosure generally relates to stacked device structures, such as transistor stacks having n-type transistors and p-type transistors (i.e., complementary field-effect transistors (CFETs)), and more particularly, to gate engineering techniques for stacked device structures.

[0019] The following disclosure provides numerous different embodiments or instances for implementing various features of the embodiments of this disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, spatially relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “above,” “below,” “under,” “upward,” “downward,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) are used to facilitate understanding of the relationship between one component and another in the embodiments of this disclosure. Spatially relative terms are intended to cover different orientations of the device including the components. Reference numerals and / or characters may also be repeated in various instances of the embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges, as understood by those skilled in the art, the term is intended to encompass a reasonable range of values ​​that takes into account variations inherent during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having characteristics related to the numerical value, a numerical value or range of values ​​encompasses a reasonable range including the described value, such as within + / - 10% of the described value. For example, a material layer with a thickness of "about 5 nm" can include a size range from 4.5 nm to 5.5 nm, where the manufacturing tolerance associated with the deposited material layer is + / - 10%, as known to those skilled in the art. Additionally, given the inherent variations in any manufacturing process, when a device component is described as having "substantially" properties and / or characteristics, such terms are intended to capture properties and / or characteristics within the tolerances of the manufacturing process. For example, a "substantially vertical" or "substantially horizontal" component is intended to capture approximately vertical and horizontal—but not mathematically or perfectly vertical and horizontal—components within a given tolerance of the manufacturing process used to manufacture such a component.

[0021] Stacked device structures offer further density reductions for advanced integrated circuit (IC) technology nodes (especially as they evolve to 3nm (N3) and below), particularly when the stacked device structure includes multi-gate devices such as fin field-effect transistors (FinFETs), gate-all-around (GAA) transistors comprising nanowires and / or nanosheets, and other types of multi-gate devices. Stacked device structures vertically stack devices, such as transistors. For example, a transistor stack may include a first transistor (e.g., a top transistor) disposed above a second transistor (e.g., a bottom transistor). When the first and second transistors have opposite conductivity types (i.e., an n-type transistor and a p-type transistor), the transistor stack can provide a complementary field-effect transistor (CFET).

[0022] This disclosure provides gate engineering techniques for stacked device structures, such as stacked transistors. For example, dual-function metal (DWFM) gate stacks with improved diffusion barrier capabilities (e.g., reduced diffusion of aluminum from the n-type to the p-type work function layer of a DWFM gate stack) are disclosed, which can improve overall device performance. Such improvements are achieved by providing the n-type and / or p-type work function layers of the DWFM gate stack with varying compositions (e.g., gradient compositions). Details of the disclosed DWFM gate stacks and methods for their fabrication are described herein.

[0023] Figure 1A This is a partial or complete cross-sectional view of the stacked device structure 10 according to various aspects of embodiments of the present disclosure. Figure 1B and Figure 1C The stacked device structure 10 according to various aspects of the embodiments of this disclosure is respectively along... Figure 1A A partial or complete cross-sectional view of lines BB and CC. Figures 2 to 7 Various dual-function metal (DWFM) configurations that can be implemented in the gate stack of the stacked device structure 10 according to various aspects of embodiments of the present disclosure are depicted. Figure 8 and Figure 9 The stacked device structure 10 according to various aspects of embodiments of this disclosure is along Figure 1A Cross-sectional views of some or all of other embodiments of line BB. For clarity, simplified diagrams have been provided. Figures 1A to 1C and Figures 2 to 9 To better understand the inventive concept of the embodiments of this disclosure. Additional components may be added to the stacked device structure 10, and in other embodiments of the stacked device structure 10, some of the components described below may be replaced, modified, or eliminated.

[0024] The stacked device structure 10 may include an upper device region 12U, a lower device region 12L, and a substrate 14. The upper device region 12U is disposed above the lower device region 12L, and the lower device region 12L is disposed above the substrate 14. The upper device region 12U and the lower device region 12L may each include at least one electrical functional device, and the device stack may be formed from the upper device in the upper device region 12U and the lower device in the lower device region 12L. For example, the transistor stack of the stacked device structure 10 may include an upper transistor 20U vertically stacked above the lower transistor 20L. In the depicted embodiment, transistors 20U and 20L have opposite conductivity types. For example, transistor 20U is an n-type transistor, and transistor 20L is a p-type transistor. In another example, transistor 20U is a p-type transistor, and transistor 20L is an n-type transistor. In such an embodiment, transistors 20U and 20L may form a CFET. In some embodiments, transistors 20U and 20L have the same conductivity type. For example, transistors 20U and 20L can both be n-type transistors or p-type transistors.

[0025] The upper device region 12U includes various components and / or assemblies, such as a semiconductor layer 25U, a gate spacer 30U, an internal spacer 34U, a source / drain 40U, a contact etch stop layer (CESL) 46U, an interlayer dielectric (ILD) layer 48U, a gate dielectric 50U (each of the gate dielectrics 50U may include a corresponding interface layer 52U and a corresponding high-k dielectric layer 54U), a gate electrode 56U, and a hard mask 58. The lower device region 12L includes various components and / or assemblies, such as a mesa 14' (which may be a protrusion from and / or an extension of the substrate 14), a substrate isolation structure 18, fin spacers, a semiconductor layer 25L, a gate spacer 30L, an internal spacer 34L, a source / drain 40L, a CESL 46L, an ILD layer 48L, a gate dielectric 50L (each of the gate dielectrics 50L may include a corresponding interface layer 52L and a corresponding high-k dielectric layer 54L), and a gate electrode 56L. The gate stack 60U of an upper transistor, such as transistor 20U, includes a corresponding gate dielectric 50U and a corresponding gate electrode 56U, and the gate stack 60L of a lower transistor, such as transistor 20L, includes a corresponding gate dielectric 50L and a corresponding gate electrode 56L. The gate stacks 60U and 60L may together form the gate 60 (also referred to as the gate stack) of a device stack (e.g., a transistor stack) of a stacked device structure. Gate 60 may provide a metal gate and / or a high-k / metal gate for a CFET. In the depicted embodiment, as further described below, when transistor 20U is an n-type transistor and transistor 20L is a p-type transistor, gate stacks 60U and 60L may be configured to have different types of work function materials (e.g., n-type and p-type work function), such that gate 60 is a dual-function metal (DWFM) gate.

[0026] Transistor 20L can be configured as a GAA transistor. For example, transistor 20L includes three channels (e.g., nanowires, nanosheets, nanorods, etc.) provided by semiconductor layer 25L (also called channel layers or channels), suspended above substrate 14 and extending between corresponding source / drain terminals, such as source / drain terminals 40L. In some embodiments, transistor 20L includes more or fewer channels (and therefore more or fewer semiconductor layers 25L). Transistor 20L also includes a gate stack 60L disposed above semiconductor layer 25L and between its source / drain terminals 40L. Figure 1A In this configuration, the gate stack 60L is located between the semiconductor layers 25L and between the bottommost semiconductor layer 25L and the substrate 14 (e.g., its mesa 14'). Figure 1BIn this configuration, the gate stack 60L encloses the semiconductor layer 25L. During operation, current can flow through the semiconductor layer 25L and between the source and drain 40L. Furthermore, the transistor 20L has a gate spacer 30L disposed along the uppermost sidewall of the gate stack 60L, an internal spacer 34L disposed between the gate stack 60L and the source / drain 40L, and a fin spacer disposed along the sidewall of the mesa 14'.

[0027] Transistor 20U can be configured as a GAA transistor. For example, transistor 20U has three channels (e.g., nanowires, nanosheets, nanorods, etc.) provided by semiconductor layer 25U (also called channel layers or channels), suspended above substrate 14 and extending between corresponding source / drain electrodes, such as source / drain electrodes 40U. In some embodiments, transistor 20U includes more or fewer channels (and therefore more or fewer semiconductor layers 25U). Transistor 20U also includes a gate stack 60U disposed above semiconductor layer 25U and between its source / drain electrodes 40U. Figure 1A In the middle, the gate stack 60U is located above the semiconductor layer 25U and between the bottom semiconductor layer 25U and the gate stack 60L. Figure 1B In this configuration, a gate stack 60U encloses a semiconductor layer 25U. During operation, current can flow through the semiconductor layer 25U and between the respective source / drain electrodes 40U. Furthermore, the transistor 20U has a gate spacer 30U disposed along the sidewall of the uppermost portion of the gate stack 60U, an internal spacer 34U disposed between the gate stack 60U and the source / drain electrodes 40U, and a corresponding hard mask 58 disposed above the gate stack 60U. The hard mask 58 may be disposed between the respective gate spacers 30U. In some embodiments, the hard mask 58 may be considered a portion of the gate stack 60U.

[0028] Substrate 14 (and mesa 14'), semiconductor layer 25U, and semiconductor layer 25L comprise: elemental semiconductors, such as silicon and / or germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or combinations thereof; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof; or combinations thereof. For example, substrate 14, semiconductor layer 25U, and semiconductor layer 25L are formed of silicon. In some embodiments, semiconductor layer 25U and semiconductor layer 25L are formed of different semiconductor materials, such as silicon and silicon germanium, or vice versa. In some embodiments, substrate 14 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Substrate 14 (and / or mesa 14' extending therefrom) may include various doped regions, such as p-type doped regions (e.g., p-wells), n-type doped regions (e.g., n-wells), or combinations thereof. n-type doped regions include n-type dopants, such as phosphorus, arsenic, other n-type dopants, or combinations thereof. p-type doped regions include p-type dopants, such as boron, indium, gallium, other p-type dopants, or combinations thereof. In some embodiments, the doped regions include both p-type and n-type dopants. In some embodiments, semiconductor layer 25U and / or semiconductor layer 25L include p-type dopants, n-type dopants, or combinations thereof. For ease of description herein, semiconductor layer 25U and semiconductor layer 25L may be collectively referred to as semiconductor layer 25.

[0029] A substrate isolation structure 18 is disposed above the substrate 14, and the substrate isolation structure 18 may be disposed adjacent to and / or around the mesa 14' (also referred to as a substrate extension, substrate fin, fin portion, protrusion, etched substrate portion, etc.). The substrate isolation structure 18 can electrically isolate active device regions (such as channel regions and / or source / drain regions) from other device regions. The substrate isolation structure 18 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (including silicon, oxygen, nitrogen, carbon, other suitable isolation components, or combinations thereof) or combinations thereof. The substrate isolation structure 18 may have a multilayer structure. For example, the substrate isolation structure 18 may include a bulk dielectric (e.g., an oxide layer) located above a dielectric pad (e.g., silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, or combinations thereof). In another example, the substrate isolation structure 18 may include a bulk dielectric, such as a borosilicate glass (BSG) pad and / or a phosphosilicate glass (PSG) pad, located above a doped pad. The dimensions and / or characteristics of the substrate isolation structure 18 can be configured to provide a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, a localized oxidation of silicon (LOCOS) structure, other suitable isolation structures, or combinations thereof.

[0030] Gate spacers 30U and 30L are disposed along the sidewall of the top portion of the gate stack 60U, respectively. Fin / mesa spacers may be disposed along the sidewall of mesa 14'. Internal spacers 34U are disposed below the gate spacers 30U and along the sidewall of the gate stack 60U, and internal spacers 34L are disposed below the gate spacers 30L and along the sidewall of the gate stack 60L. Along the gate height direction, internal spacers 34U and 34L are located between semiconductor layers 25U and 25L, respectively. Along the gate width direction, internal spacers 34U are located between the gate stack 60U and the source / drain 40U, and internal spacers 34L are located between the gate stack 60L and the source / drain 40L, respectively. Gate spacers 30U, 30L, fin spacers, internal spacers 34U, and 34L comprise a dielectric material that may include silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, or combinations thereof). Gate spacers 30U, 30L, fin spacers, 34U, 34L, or combinations thereof may comprise different materials and / or different configurations (e.g., different numbers of layers). In some embodiments, gate spacers 30U, 30L, fin spacers, 34U, 34L, or combinations thereof have a multilayer structure, such as two or more dielectric layers with different compositions. In some embodiments, gate spacers 30U and / or 30L comprise more than one group of spacers, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, main spacers, or combinations thereof. Each spacer assembly can have a different composition.

[0031] Gate 60 is disposed between respective source / drain stacks. Each source / drain stack includes a respective source / drain 40U, a respective source / drain 40L, and a respective isolation structure between them (here, formed by ILD layers 48L and CESL 46L). Source / drain 40U and source / drain 40L comprise semiconductor materials that may be doped with n-type and / or p-type dopants. In some embodiments, source / drain 40U and / or source / drain 40L comprise silicon doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., Si:C source / drain, Si:P source / drain, or Si:C:P source / drain). In some embodiments, source / drain 40U and / or source / drain 40L comprise silicon germanium or germanium doped with boron and / or other p-type dopants (e.g., Si:Ge:B source / drain). The source / drain 40U and / or source / drain 40L may have the same or different compositions and / or materials, depending on the configuration of their respective transistors. For example, in the case where transistor 20U is an n-type transistor and transistor 20L is a p-type transistor, source / drain 40U is configured for an n-type transistor, and source / drain 40L is configured for a p-type transistor. For example, source / drain 40U comprises silicon doped with an n-type dopant (e.g., carbon), and source / drain 40L comprises silicon germanium and / or germanium doped with a p-type dopant (e.g., boron). In some embodiments, source / drain 40U and / or source / drain 40L have a multilayer structure. For example, source / drain 40U and / or source / drain 40L may comprise semiconductor layers with different compositions, and different compositions can be achieved by configuring the semiconductor layers with different semiconductor materials, different dopants, different atomic percentages of their components, different dopant concentrations, or combinations thereof. In some embodiments, the source / drain 40L and / or source / drain 40U include materials and / or dopants that achieve desired tensile and / or compressive stresses in adjacent channel regions (e.g., formed by semiconductor layers 25U and 25L). Embodiments of this disclosure also contemplate embodiments where transistor 20U is a p-type transistor, transistor 20L is an n-type transistor, source / drain 40U is configured for a p-type transistor, and source / drain 40L is configured for an n-type transistor. As used herein, source / drain, source / drain region, epitaxial source / drain, epitaxial source / drain component, etc., can refer to the source of a device (e.g., transistor 20U or transistor 20L), the drain of a device (e.g., transistor 20U or transistor 20L), or the source and / or drain of multiple devices.

[0032] ILD layers 48U and 48L comprise dielectric materials that may include silicon oxide, silicon nitride, silicon oxynitride, oxides formed from tetraethyl orthosilicate (TEOS), carbon-doped silicon oxide, BSG, PSG, borosilicate glass (BPSG), fluorosilicate glass (FSG), degel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutenyl (BCB) dielectric materials, polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, ILD layer 48U and / or ILD layer 48L comprise low-k dielectric materials having a dielectric constant less than that of silicon dioxide (e.g., k < 3.9). In some embodiments, ILD layer 48U and / or ILD layer 48L comprise a dielectric material having a dielectric constant of less than about 2.5 (i.e., an extremely low k (ELK) dielectric material), such as porous silica, silicon carbide, carbon-doped oxides (e.g., SiCOH-based materials having, for example, Si-CH3 bonds), or combinations thereof, each of which may be tuned / configured to exhibit a dielectric constant of less than about 2.5. ILD layer 48U and ILD layer 48L may comprise different materials and / or different configurations (e.g., different numbers of layers). CESL 46U comprises a material different from that of ILD layer 48U, such as a dielectric material different from that of ILD layer 48U, and CESL 46L comprises a material different from that of ILD layer 48L, such as a dielectric material different from that of ILD layer 48L. For example, where ILD layers 48U and 48L comprise low-k dielectric materials containing silicon and oxygen, CESL 46U and CESL 46L may comprise silicon and nitrogen and / or carbon, such as silicon nitride, silicon carbonitride, silicon carbonitride, or combinations thereof. In some embodiments, CESL 46U and / or CESL 46L comprise metals and oxygen, nitrogen, carbon, or combinations thereof. CESL 46U and CESL 46L may comprise different materials and / or different configurations, such as different numbers of layers. ILD layers 48U, 48L, CESL 46U, CESL 46L, or combinations thereof may have a multilayer structure and / or comprise multiple dielectric materials.

[0033] A gate dielectric 50U is disposed on a semiconductor layer 25U, and a gate dielectric 50L is disposed on a semiconductor layer 25L. The gate dielectric 50U may be further disposed on a gate spacer 30U and / or an internal spacer 34U, and the gate dielectric 50L may be further disposed on a gate spacer 30L and / or an internal spacer 34L. Each of the gate dielectrics 50U and 50L includes at least one dielectric layer. For example, the gate dielectric 50U includes an interface layer 52U and a high-k dielectric layer 54U, and the gate dielectric 50L includes an interface layer 52L and a high-k dielectric layer 54L. The interface layer 52U is disposed between the high-k dielectric layer 54U and the semiconductor layer 25U, and the interface layer 52L is disposed between the high-k dielectric layer 54L and the semiconductor layer 25L. Each of the interface layers 52U and 52L includes a dielectric material, such as SiO2, SiGeO, HfSiO, SiON, other dielectric materials, or combinations thereof. Interface layer 52U and interface layer 52L may include the same or different materials and / or configurations, such as different numbers / compositions of layers.

[0034] A high-k dielectric layer 54U is disposed between the gate electrode 56U and the semiconductor layer 25U, between the gate electrode 56U and the gate spacer 30U, and between the gate electrode 56U and the internal spacer 34U. A high-k dielectric layer 54L is disposed between the gate electrode 56L and the semiconductor layer 25L, between the gate electrode 56L and the gate spacer 30L, between the gate electrode 56L and the internal spacer 34L, and between the gate electrode 56L and the substrate 14 (e.g., its mesa 14'). Each of the high-k dielectric layers 54U and 54L includes a high-k dielectric material, which typically refers to a dielectric material having a dielectric constant greater than that of silicon dioxide, such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, and HfAlO. x The high-k dielectric layer 54U and / or high-k dielectric layer 54L may include ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, LaO3, La2O3, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba,Sr)TiO3 (BST), HfO2-Al2O3, other high-k dielectric materials, or combinations thereof. In some embodiments, the high-k dielectric layer 54U and / or high-k dielectric layer 54L comprises a hafnium-based oxide (e.g., HfO2) layer. In some embodiments, the high-k dielectric layer 54U and / or high-k dielectric layer 54L comprises a zirconium-based oxide (e.g., ZrO2) layer. The high-k dielectric layer 54U and high-k dielectric layer 54L may include the same or different compositions and / or configurations.

[0035] Gate electrode 56U is disposed on gate dielectric 50U, and gate electrode 56L is disposed on gate dielectric 50L. Each of gate electrode 56U and gate electrode 56L includes at least one conductive layer. In the depicted embodiment, gate electrode 56L includes a p-type work function metal (PWFM) layer (also referred to as a p-metal layer), and gate electrode 56U includes an n-type work function metal (NWFM) layer (also referred to as an n-metal layer). The PWFM layer includes a p-type work function metal material, which generally refers to a conductive material having a p-type work function, and the NWFM layer includes an n-type work function metal material, which generally refers to a conductive material having an n-type work function. The p-type work function metal material may include titanium, tantalum, ruthenium, molybdenum, tungsten, palladium, platinum, iridium, other p-metals, alloys thereof, or combinations thereof. For example, the PWFM layer may be a titanium nitride layer, a molybdenum nitride layer, a palladium layer, a platinum layer, an iridium layer, a ruthenium layer, or combinations thereof. The n-type work function metal material may include aluminum, titanium, tantalum, zirconium, other n-metals, alloys thereof, or combinations thereof. For example, the NWFM layer may be a titanium aluminum layer, a titanium aluminum carbide layer, a tantalum layer, a tantalum aluminum layer, a tantalum aluminum carbide layer, or a combination thereof. In some embodiments, the PWFM layer has a multilayer structure (e.g., more than one PWFM layer), and / or the NWFM layer has a multilayer structure.

[0036] In the depicted embodiments, the NWFM layer (i.e., gate electrode 56U) comprises titanium and aluminum, and the PWFM layer (i.e., gate electrode 56L) comprises titanium and nitrogen. For example, the NWFM layer is a titanium-aluminum layer, and the PWFM layer is a titanium nitride layer. This disclosure recognizes that the diffusion of aluminum from the NWFM layer to the PWFM layer may reduce the aluminum content / concentration in the NWFM layer, and that introducing aluminum into the PWFM layer and / or increasing the aluminum content / concentration of the PWFM layer may undesirably alter (e.g., increase) the threshold voltage of the n-type transistor and / or the threshold voltage of the p-type transistor. This disclosure also recognizes that the mixing of the components (e.g., aluminum and nitrogen) of the NWFM and PWFM layers at their interface may also cause undesirable threshold voltage changes. To suppress the diffusion of components from the NWFM layer to the PWFM layer and / or the mixing of the components of the NWFM and PWFM layers, this disclosure provides NWFM and PWFM layers with gradient compositions. For example, the NWFM layer (i.e., gate electrode 56U) has a gradient aluminum / titanium (Al / Ti) ratio, such as an Al / Ti ratio that decreases from its top to its bottom, as indicated by arrow R1, and the PWFM layer (i.e., gate electrode 56L) has a gradient nitrogen / titanium (N / Ti) ratio, such as an N / Ti ratio that increases from its top to its bottom, as indicated by arrow R2. In some embodiments, the Al / Ti ratio decreases along the gate height direction from the top of the gate stack 60U (which may be connected to the hard mask 58) to the bottom of the gate stack 60U (which may be connected to the PWFM layer and / or the work function barrier layer between the PWFM layer and the NWFM layer), and the N / Ti ratio increases along the gate height direction from the top of the gate stack 60L (which may be connected to the NWFM layer and / or the work function barrier layer between the NWFM layer and the PWFM layer) to the bottom of the gate stack 60L (which may be connected to the portion of the high-k dielectric layer 54L located above the substrate 14 and / or the mesa 14'). Configuring the gate electrode 56U to have a top-heavy Al / Ti ratio and a bottom-light Al / Ti ratio, and configuring the gate electrode 56L to have a top-light N / Ti ratio and a bottom-heavy N / Ti ratio, reduces the amount (e.g., their concentration) of aluminum and nitrogen at the interface between the gate electrodes 56U and 56L (e.g., at the interface of their WFM layers). Reducing the amount of aluminum and / or nitrogen can reduce aluminum diffusion into gate electrode 56L and / or reduce the mixing of nitrogen in gate electrode 56L with components (e.g., aluminum) in gate electrode 56U. Therefore, configuring gate electrode 56U and gate electrode 56U with a gradient WFM layer can improve overall device performance and stability.

[0037] refer to Figure 2In the depicted embodiment, both the NWFM layer and the PWFM layer are configured to have a gradient composition. For example, the Al / Ti ratio in the NWFM layer can decrease from 0.8 to 0.4 from the top to the bottom of the gate electrode 56U. In other words, the Al / Ti ratio in the top portion of the NWFM layer (e.g., the portion above the topmost semiconductor layer 25U) is about 0.8, the Al / Ti ratio in the bottom portion of the NWFM layer (e.g., the portion above and / or below the bottommost semiconductor layer 25U) is about 0.4, and the Al / Ti ratio in the middle portion of the NWFM layer (e.g., the portion surrounding and / or near the middle semiconductor layer 25U) is between 0.8 and 0.4 (e.g., about 0.6). In a further embodiment of such an example, the N / Ti ratio in the PWFM layer can increase from 0.4 to 0.8 from the top to the bottom of the gate electrode 56L. In other words, the N / Ti ratio in the top portion of the PWFM layer (e.g., the portion above the topmost semiconductor layer 25L) is about 0.4, the N / Ti ratio in the bottom portion of the PWFM layer (e.g., the portion above and / or below the bottommost semiconductor layer 25L) is about 0.8, and the N / Ti ratio in the middle portion of the PWFM layer (e.g., the portion surrounding and / or near the middle semiconductor layer 25L) is between 0.8 and 0.4 (e.g., about 0.6). In some embodiments, the atomic percentage of aluminum may decrease along the thickness of the NWFM layer. In some embodiments, the atomic percentage of nitrogen may increase along the thickness of the PWFM layer. In some embodiments, the atomic percentage of aluminum in the NWFM layer and the atomic percentage of nitrogen in the PWFM layer may be lowest at the interface between the NWFM layer and the PWFM layer, and the interface may or may not include a work function blocking layer located between the NWFM layer and the PWFM layer, as described below.

[0038] refer to Figure 3 In some embodiments, the NWFM layer has a gradient composition, and the PWFM layer has a uniform composition. For example, the Al / Ti ratio in the NWFM layer may decrease from 0.8 to 0.4 from top to bottom, and the N / Ti ratio in the PWFM layer may be constant from top to bottom (e.g., about 0.5). In such examples, the atomic percentage of aluminum may decrease along the thickness of the NWFM layer, and / or the atomic percentage of nitrogen and / or titanium may be constant along the thickness of the PWFM layer. Reference Figure 4In some embodiments, the NWFM layer has a uniform composition, and the PWFM layer has a gradient composition. For example, the Al / Ti ratio in the NWFM layer can be constant from top to bottom (e.g., about 0.5), and the N / Ti ratio in the PWFM layer can increase from 0.4 to 0.8. In such instances, the atomic percentage of nitrogen can increase along the thickness of the NWFM layer, and / or the atomic percentages of aluminum and / or titanium can be constant along the thickness of the NWFM layer.

[0039] refer to Figures 5 to 7 This disclosure also considers embodiments in which transistor 20U and transistor 20L are configured as p-type transistors and n-type transistors, respectively. In such embodiments, gate electrode 56U includes and / or a PWFM layer, gate electrode 56L includes and / or an NWFM layer, and gate 60 may be configured to have: a PWFM layer and an NWFM layer having a gradient composition (…). Figure 5 ); PWFM layers with constant composition and NWFM layers with gradient composition ( Figure 6 ); or PWFM layers with gradient composition and NWFM layers with constant composition. Figure 7 In such an embodiment, the gradient composition can be... Figures 2 to 4 Different configurations are used in the embodiments to ensure that the amount of aluminum and / or nitrogen is reduced at the PWFM layer / NWFM layer interface. For example, in Figure 5 In the PWFM layer, the N / Ti ratio can decrease from 0.5 to 0.8 instead of increasing from 0.5 to 0.8, and the Al / Ti ratio in the NWFM layer can increase from top to bottom from 0.4 to 0.8 instead of decreasing from 0.4 to 0.8. Figure 6 In the PWFM layer, the N / Ti ratio can be constant from top to bottom (e.g., about 0.5), while the Al / Ti ratio in the NWFM layer can increase from 0.4 to 0.8 from top to bottom. Figure 7 In the PWFM layer, the N / Ti ratio can be reduced from 0.8 to 0.4, and the Al / Ti ratio in the NWFM layer can be constant from top to bottom (e.g., about 0.5).

[0040] Refer again Figures 1A to 1CThe gate 60 may include a barrier layer 62 located between the gate electrode 56U and the gate electrode 56L. The barrier layer 62 is formed of a material that inhibits the diffusion and / or mixing of components of opposite-type work function layers (such as NWFM layers and PWFM layers). For example, the barrier layer 62 may reduce and / or eliminate the diffusion of aluminum (and / or other components) from the NWFM layer into the PWFM layer, and the barrier layer 62 may reduce and / or eliminate the mixing of components (e.g., nitrogen and aluminum, respectively) in the PWFM and NWFM layers. In some embodiments, the barrier layer 62 includes titanium, tungsten, and nitrogen. For example, the barrier layer 62 is a tungsten-doped TiN layer, such as a TiWN layer. In some embodiments, the barrier layer 62 includes titanium, molybdenum, and nitrogen. For example, the barrier layer 62 is a molybdenum-doped TiN layer, such as a TiMoN layer. In some embodiments, the barrier layer 62 includes molybdenum and nitrogen. For example, the barrier layer 62 is a molybdenum nitride (MoN) layer. Tungsten and / or molybdenum can suppress the diffusion of aluminum and / or other components from the NWFM layer to the PWFM layer and vice versa, thereby minimizing undesirable variations in the threshold voltages of transistors 20U and 20L. Therefore, incorporating a tungsten- and / or molybdenum-containing film (such as barrier layer 62) at the interface between the NWFM and PWFM layers can improve overall device performance and stability. In some embodiments, barrier layer 62 has a multilayer structure, such as a TiWN layer and a MoN layer.

[0041] This disclosure also contemplates embodiments in which the barrier layer 62 is omitted, such as... Figure 8 As depicted above. In such embodiments, gate electrode 56U is adjacent to gate electrode 56L (e.g., an NWFM layer is adjacent to a PWFM layer), and component mixing between them can be reduced and / or eliminated by configuring gate electrode 56U and / or gate electrode 56L to have gradient compositions, as described above. For example, the NWFM layer may have a gradient Al / Ti ratio, and / or the PWFM layer may have a gradient N / Ti ratio.

[0042] This disclosure also contemplates embodiments in which the gate 60 includes a metal-filled / bulk layer 57, such as Figure 9As depicted in the figure. In such embodiments, at least one conductive gate layer of gate electrode 56U may include an NWFM layer (e.g., WFM layer 56U') as described above and a metal-filled / bulk layer 57, and at least one conductive gate layer of gate electrode 56L may include a PWFM layer (e.g., WFM layer 56L') as described above and a metal-filled / bulk layer 57. The metal-filled / bulk layer 57 includes aluminum, tungsten, cobalt, copper, other suitable conductive materials, alloys thereof, or combinations thereof. In some embodiments, a work function blocking layer (such as blocking layer 62) is located between WFM layer 56U' and WFM layer 56L'. In some embodiments, the metal-filled / bulk layer 57 encloses the WFM layer of gate 60 (e.g., formed by WFM layers 56U' and WFM layers 56L'). In some embodiments, gate 60 includes additional layers, such as caps (e.g., metal nitride caps and / or silicon caps) and / or other gate layers.

[0043] Refer again Figures 1A to 1C The hard mask 58 comprises a material different from the subsequently formed insulating layer (e.g., the insulating layer of the interconnect structure) to provide etch selectivity. In some embodiments, the hard mask 58 comprises silicon and nitrogen and / or carbon, such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, silicon carbonitride, silicon carbonitride, silicon carbonitride, other silicon nitrides, other silicon carbides, or combinations thereof. In some embodiments, the hard mask 58 comprises metal and oxygen and / or nitrogen, such as aluminum oxide (e.g., AlO or Al2O3), aluminum nitride (e.g., AlN), aluminum oxynitride (e.g., AlON), zirconium oxide, zirconium nitride, hafnium oxide (e.g., HfO or HFO2), aluminum zirconium oxide (e.g., ZrAlO), other metal oxides, other metal nitrides, or combinations thereof.

[0044] Device 10 may further include source / drain contacts (e.g., upper source / drain contacts 70U and lower source / drain contacts 70L), source / drain vias (e.g., source / drain via 72), and gate vias (e.g., gate via 74). Source / drain contacts 70U are disposed on at least one of the source / drain contacts 40U and electrically connected to at least one of the source / drain contacts 40U; source / drain contacts 70L are disposed on at least one of the source / drain contacts 40L and electrically connected to at least one of the source / drain contacts 40L; source / drain via 72 is disposed on source / drain contacts 70U and electrically connected to source / drain contacts 70U; and gate via 74 is disposed on gate 60 and electrically connected to gate 60. Source / drain contacts 70U may be disposed in ILD layer 48U. Figure 1C Furthermore, the source / drain contact 70U can be disposed between the gate spacers 30U. Figure 1A The source / drain contact 70L can be disposed in the substrate 14. Figure 1A Furthermore, the source / drain contacts 70L can be disposed between the substrate isolation structures 18. Figure 1C A source / drain via 72 is disposed in an insulating layer 76, a gate via 74 is disposed in an insulating layer 76, and the gate via 74 may extend through a hard mask 58 to a gate 60 (e.g., its gate electrode 56U). Source / drain contacts 70U, 70L, 72, and 74 comprise conductive materials, which may include tungsten, ruthenium, cobalt, molybdenum, copper, aluminum, titanium, tantalum, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof, or combinations thereof. The insulating layer 76 comprises an electrically insulating material, such as a dielectric material, as described herein, and the insulating layer 78 may have a multilayer structure (e.g., an ILD layer disposed above the CESL).

[0045] This disclosure also recognizes that the electric field applied to the gate 60 (which is provided by applying voltage to the gate 60 via the gate via 74) decreases with increasing distance from the gate via 74. For example, the electric field decreases from the top to the bottom of the gate 60, as depicted by arrow EF, such that the electric field strength is highest at the top of the gate 60 (i.e., closest to the gate via 74) and lowest at the bottom of the gate 60 (i.e., furthest from the gate via 74). Therefore, the electric field applied to the gate stack 60U (and thus the gate electrode 56U) can be greater than the electric field applied to the gate stack 60L, which may result in poor gate control of the transistor 20L. Configuring the gate electrode 56L to have a gradient composition (e.g., having a light N / Ti ratio at the top and a heavy N / Ti ratio at the bottom) can compensate for the lower electric field, for example, by increasing the conductivity of the upper portion of the gate electrode 56L (e.g., by configuring the upper portion to have a lower amount of nitrogen). In some embodiments, the amount and / or concentration of nitrogen increases from the top to the bottom of the gate electrode 56L, thereby reducing its overall resistance to the voltage applied via the gate via 74.

[0046] The stacked device structure 10 may further include a multilayer interconnect (MLI) structure disposed above the insulating layer 76. The MLI structure may electrically connect devices (e.g., transistors, resistors, capacitors, inductors, etc.), components of devices (e.g., gates and / or source / drains), devices within the MLI structure, components of the MLI structure, or combinations thereof, thereby enabling the devices and / or their components to operate as specified in design requirements. The MLI structure may include metallization layers for wiring signals between devices and / or their components and / or distributing signals (e.g., clock signals, voltage signals, ground signals, other signals, or combinations thereof) to devices and / or their components. In some embodiments, the metallization layer / hierarchy includes at least one interconnect structure disposed in the insulating layer, such as metal lines and vias disposed in dielectric layers (e.g., CESL and ILD layers), wherein the vias electrically connect the metal lines to the metal lines of interconnects in different metallization layers.

[0047] Figure 10 It is a gate stack of transistors (such as) for manufacturing transistor stacks according to various aspects of embodiments of this disclosure. Figures 1A to 1C The flowchart describes a method 100 for a stacked device structure 10, specifically a method for forming a gate 60 of a transistor stack. In block 105, method 100 includes forming a first gate dielectric (e.g., gate dielectric 50L) over a lower channel structure (e.g., semiconductor layer 25L) and a second gate dielectric (e.g., gate dielectric 50U) over an upper channel structure (e.g., semiconductor layer 25U). The channel stack may include an upper channel structure over the lower channel structure. In block 110, method 100 includes forming a first type of work function layer (e.g., a PWFM layer (which may be or form part of the gate electrode 56L), as described above) having a first gradient composition over the first gate dielectric. In block 115, method 100 may include a square work function blocking layer (e.g., blocking layer 62) on the first type of work function layer. In block 120, method 100 includes forming a second type of work function layer (e.g., an NWFM layer, which may be or form part of the gate electrode 56U, as described above) having a second gradient composition over the second gate dielectric. In block 125, method 100 may include forming a bulk / filled layer. The bulk / filled layer may be formed over the second type of work function layer and / or the first type of work function layer. For clarity, the following has been simplified. Figure 10 To better understand the inventive concept of embodiments of this disclosure. Additional steps may be provided before, during, and after method 100, and for additional embodiments of method 100, some of the described steps may be moved, replaced, or eliminated.

[0048] In some embodiments, the first type of function layer is formed by depositing a first type of function material over a first gate dielectric and reducing the thickness of the first type of function material (e.g., by etching back the first type of function material). The deposited first type of function material may be located over the first gate dielectric, the lower channel structure, the second gate dielectric, and the upper channel structure. In some embodiments, the first type of function material may be removed from over the second gate dielectric and / or the upper channel structure, such as when the thickness of the first type of function material is reduced. In some embodiments, the flow rate of a non-metallic precursor (e.g., a nitrogen-containing precursor), the flow rate of a metallic precursor (e.g., a titanium-containing precursor), other deposition parameters, or combinations thereof are adjusted to provide a first type of function material having a first gradient composition. For example, the ratio of the flow rate of the non-metallic precursor to the flow rate of the metallic precursor decreases with increasing deposition time and / or increasing thickness of the first type of function material. In some embodiments, the first type of work function layer is a titanium nitride layer, and the flow rate ratio of the nitrogen-containing precursor to the titanium-containing precursor can be varied during the deposition of the titanium nitride material (e.g., chemical vapor deposition (CVD)) to provide a titanium nitride layer with a gradient N / Ti ratio. In some embodiments, the N / Ti flow rate ratio decreases with increasing deposition time and / or increasing thickness of the titanium nitride material. In such embodiments, the N / Ti flow rate ratio is at its maximum at the start of the deposition process (e.g., CVD) and at its minimum at the end of the deposition process. In some embodiments, the N / Ti flow rate ratio is reduced in a manner that provides a titanium nitride layer with a gradient N / Ti ratio decreasing from 0.8 to 0.4 from bottom to top, as described herein.

[0049] In some embodiments, the second type of power function layer is formed by depositing a second type of power function material over the second gate dielectric and reducing the thickness of the second type of power function material (e.g., by planarizing the second type of power function material (e.g., by chemical mechanical planarization (CMP))). The deposited second type of power function material may be located over the second gate dielectric, the upper channel structure, the first type of power function layer, and the device-level dielectric layer (e.g., ILD layer 48U and / or CESL 46U), and the second type of power function material may be removed from over the device-level dielectric layer as its thickness is reduced. In some embodiments, when formed over the first gate dielectric and / or the lower channel structure, the first type of power function layer may be formed over the second gate dielectric and / or the upper channel structure. In such embodiments, the first type of power function layer is removed from over the second gate dielectric before the second type of power function material is formed. In some embodiments, the flow rate of a first metal-containing precursor (e.g., an aluminum-containing precursor), the flow rate of a second metal-containing precursor (e.g., a titanium-containing precursor), other deposition parameters, or combinations thereof, are adjusted to provide a second type of function material having a second gradient composition. For example, the ratio of the flow rate of the first metal-containing precursor to the flow rate of the second metal-containing precursor increases with increasing deposition time and / or increasing thickness of the second type of function material. In some embodiments, the second type of function layer is a titanium-aluminum layer, and the flow rate ratio of the aluminum-containing precursor to the titanium-containing precursor can be varied during the deposition of the titanium-aluminum material (e.g., CVD) to provide a titanium-aluminum layer with a gradient Al / Ti ratio. In some embodiments, the Al / Ti flow rate ratio increases with increasing deposition time and / or increasing thickness of the titanium-aluminum material. In such embodiments, the Al / Ti flow rate ratio may be at a minimum at the start of the deposition process (e.g., CVD) and at a maximum at the end of the deposition process. In some embodiments, the Al / Ti flow rate ratio is increased in a manner that provides a titanium-aluminum layer with a gradient Al / Ti ratio increasing from 0.4 to 0.8 from bottom to top, as described herein.

[0050] In some embodiments, the first type of power function layer (e.g., a PWFM layer) may not be formed entirely bottom-to-top. For example, the first type of power function layer may be formed around the lower channel structure (e.g., semiconductor layer 25L) before filling the lower portion of the gate opening and / or before reaching its total thickness / height (e.g., between its top and bottom). In such an example, the portion of the first type of power function layer surrounding the semiconductor layer 25L may have a gradient N / Ti ratio. For example, the N / Ti ratio of the portion of the first type of power function layer at the gate dielectric 50L (e.g., its high-k dielectric layer 54L) may be 0.8, and the N / Ti ratio of the portion of the first type of power function layer may decrease with increasing distance from the gate dielectric 50L. In other words, the first type of power function layer may have a gradient portion around the semiconductor layer 25L, such as a portion with a gradient N / Ti ratio. In a further embodiment of such an example, the N / Ti ratio in the portion of the first type of power function layer between the semiconductor layers 25L may decrease and then increase along the gate height direction (e.g., the z-direction). For example, along the gate height direction (e.g., the z-direction), the N / Ti ratio can decrease from a first ratio (e.g., 0.8) at the portion of the gate dielectric 50L located above the bottom of the top semiconductor layer 25L to a second ratio (e.g., less than 0.8 (e.g., 0.4)) at a point between the top semiconductor layer 25L and the intermediate semiconductor layer 25L (e.g., at equal distances from their bottom and top, respectively), and then increase from the second ratio to a third ratio (e.g., 0.8) at the portion of the gate dielectric layer 50L located above the top of the intermediate semiconductor layer 25L. Therefore, the portion of the first type of power function layer located between the semiconductor / channel layers of the lower channel structure can have an intermediate portion sandwiched between the upper and lower portions. The intermediate portion can have a first N / Ti ratio (e.g., a minimum N / Ti ratio), and the upper and lower portions can have a second N / Ti ratio greater than the first N / Ti ratio (e.g., a maximum N / Ti ratio). In some embodiments, the thickness of the intermediate portion can be greater than the thickness of the upper and lower portions.

[0051] In some embodiments, the second type of power function layer (e.g., an NWFM layer) may not be formed entirely from bottom to top. For example, the second type of power function layer may be formed around the upper channel structure (e.g., semiconductor layer 25U) before filling the upper portion of the gate opening and / or before reaching its total thickness / height (e.g., between its top and bottom). In such an example, the portion of the second type of power function layer surrounding the semiconductor layer 25U may have a gradient Al / Ti ratio. For example, the Al / Ti ratio of the portion of the second type of power function layer at the gate dielectric 50U (e.g., its high-k dielectric layer 54U) may be 0.4, and the Al / Ti ratio of the portion of the second type of power function layer may increase with increasing distance from the gate dielectric 50U. In other words, the second type of power function layer may have a gradient portion around the semiconductor layer 25U, such as a portion with a gradient Al / Ti ratio. In a further embodiment of such an example, the Al / Ti ratio in the portion of the second type of power function layer between the semiconductor layers 25U may increase and then decrease along the gate height direction (e.g., the z-direction). For example, along the gate height direction (e.g., the z-direction), the Al / Ti ratio can increase from a first ratio (e.g., 0.4) at the portion of the gate dielectric 50U located above the bottom of the top semiconductor layer 25U to a second ratio (e.g., greater than 0.4 (e.g., 0.8)) at a point between the top semiconductor layer 25U and the intermediate semiconductor layer 25U (e.g., at equal distances from their bottom and top, respectively), and then decrease from the second ratio to a third ratio (e.g., 0.4) at the portion of the gate dielectric layer 50U located above the top of the intermediate semiconductor layer 25U. Therefore, the portion of the second type of power function layer located between the semiconductor / channel layers of the upper channel structure can have an intermediate portion sandwiched between the upper and lower portions. The intermediate portion can have a first Al / Ti ratio (e.g., a maximum Al / Ti ratio), and the upper and lower portions can have a second Al / Ti ratio (e.g., a minimum Al / Ti ratio) that is less than the second Al / Ti ratio. In some embodiments, the thickness of the intermediate portion can be greater than the thickness of the upper and lower portions.

[0052] In some embodiments, the function blocking layer is formed by depositing a function blocking material over a first type of function blocking layer and reducing the thickness of the function blocking material (e.g., by etching back the function blocking material). The deposited function blocking material may be located over the first type of function blocking layer and the second gate dielectric, and the function blocking material may be removed from over the second gate dielectric as its thickness is reduced. In some embodiments, the first type of function blocking layer, the function blocking layer, and the second type of function blocking layer are formed in a gate opening and may partially or completely fill the gate opening. In some embodiments, the first gate dielectric and the second gate dielectric partially fill the gate opening. In some embodiments, the first gate dielectric partially fills the space between the lower channels of the lower channel structure, and the first type of function blocking layer may partially or completely fill the remaining portion of the space between the lower channels of the lower channel structure. In some embodiments, the second gate dielectric partially fills the space between the upper channels of the upper channel structure, and the second type of function blocking layer may partially or completely fill the remaining portion of the space between the upper channels of the upper channel structure. In some embodiments, the function blocking layer partially fills the space between the upper channels of the upper channel structure and the lower channels of the lower channel structure. In some embodiments, the bulk / fill layer is formed by depositing a bulk / fill material over a second type of power function layer and reducing the thickness of the bulk / fill material (e.g., by planarizing the bulk / fill material (e.g., by CMP)). In some embodiments, the bulk / fill material layer fills the remaining portion of the gate opening.

[0053] Figure 11A This is a partial or complete cross-sectional view of a stacked device structure 200 according to various aspects of embodiments of the present disclosure. Figure 11B and Figure 11C The stacked device structure 200 according to various aspects of the embodiments of this disclosure is respectively along... Figure 11A A partial or complete cross-sectional view of lines BB and CC. The stacked device structure 200 is similar in many respects to the stacked device structure 10. Therefore, for clarity and simplicity, Figures 11A to 11C Stacked device structure 200 and Figures 1A to 1C Similar components of the stacked device structure 10 are indicated by the same reference numerals. Figures 12 to 14 Various configurations of some or all of the gate layers that may be implemented in the stacked device structure 200 according to various aspects of embodiments of the present disclosure are depicted. For clarity, simplified details have been provided. Figures 11A to 11C and Figures 12 to 14 To better understand the inventive concept of embodiments of this disclosure. Additional components may be added to the stacked device structure 200, and in other embodiments of the stacked device structure 200, some of the components described below may be replaced, modified, or eliminated.

[0054] exist Figures 11A to 11CIn this embodiment, transistors 20U and 20L each include one channel layer (e.g., semiconductor layer 25U and semiconductor layer 25L, respectively), instead of three channel layers, and embodiments of this disclosure contemplate transistors 20U and 20L including more than Figures 11A to 11C Further channel layers are depicted. In the stacked device structure 200, a semiconductor layer 25M is disposed between semiconductor layers 25U and 25L, and semiconductor layer 25M (also referred to as a pseudo-channel layer and / or pseudo-channel) extends between corresponding source / drain isolation structures (e.g., ILD layer 48L and / or CESL 46L). Semiconductor layer 25M comprises semiconductor materials, such as those described herein (e.g., silicon, silicon germanium, or germanium), and the composition of semiconductor layer 25M may be the same as or different from that of semiconductor layers 25U and / or semiconductor layer 25L. In some embodiments, semiconductor layers 25U and 25M in device region 12U comprise the same semiconductor material, and semiconductor layers 25L and 25M in device region 12L comprise the same semiconductor material. Semiconductor layers 25U, 25M, and 25L may also be collectively referred to as semiconductor layer 25.

[0055] The stacked device structure 200 also includes an insulating structure 226 disposed between semiconductor layers 25M. The insulating structure 226 may extend between corresponding source / drain isolation structures (e.g., ILD layer 48L and / or CESL 46L). In some embodiments, the source / drain isolation structures may electrically isolate source / drain regions from each other (e.g., source / drain 40U and source / drain 40L), and / or the insulating structure 226 may electrically isolate channel regions from each other (e.g., semiconductor layer 25U and semiconductor layer 25L). In such embodiments, the insulating structure 226 may be referred to as a channel isolation structure. The insulating structure 226 includes an electrically insulating material. For example, the insulating structure 226 may include a dielectric material that may include silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonoxynitride, silicon carbonoxynitride, silicon carbonitride, or combinations thereof). The insulating structure 226 may include a single insulating layer or multiple insulating layers.

[0056] Furthermore, transistor 20U includes a gate stack 60U, which includes a gate dielectric 50U and a gate electrode 56U, and transistor 20L includes a gate stack 60L, which includes a gate dielectric 50L and a gate electrode 56L. In the stacked semiconductor structure 200, gate electrode 56L includes a PWFM layer 256A, an NWFM layer 256B, and a bulk / filled layer 258, and gate electrode 56U includes an NWFM layer 256B and a bulk layer 258. NWFM layer 256B is formed of an n-type work function metal material, which may include aluminum, titanium, tantalum, zirconium, other n-metals, alloys thereof, or combinations thereof. For example, NWFM layer 256B may be an aluminum titanium layer, an aluminum titanium carbide layer, a tantalum layer, an aluminum tantalum layer, an aluminum tantalum carbide layer, or a combination thereof. In the depicted embodiment, NWFM layer 256B is an aluminum titanium carbide layer. NWFM layer 256B may have a gradient composition or a uniform / constant composition. For example, the Al / Ti ratio in the NWFM layer 256B can be uniform along its thickness (e.g., the Al / Ti ratio can be substantially the same from the top of the NWFM layer 256B (which may be adjacent to / contact with the bulk layer 258) to the bottom of the NWFM layer 256B (which may be adjacent to / contact with the PWFM layer 256A)). In another example, the Al / Ti ratio in the NWFM layer 256B can be gradient along its thickness (e.g., the Al / Ti ratio may decrease from its top to its bottom), which can reduce aluminum diffusion from the NWFM layer 256B into the PWFM layer 256A, as described herein. In some embodiments, the NWFM layer 256B has a multilayer structure.

[0057] PWFM layer 256A is formed of a p-type work function metal material, which may include titanium, tantalum, ruthenium, molybdenum, tungsten, palladium, platinum, iridium, other p-metals, alloys thereof, or combinations thereof. In the depicted embodiment, PWFM layer 256A is a titanium nitride layer doped with a component that can inhibit the diffusion of a component (e.g., aluminum) from NWFM layer 256B into PWFM layer 256A. For example, PWFM layer 256A includes an aluminum-blocking component, such as tungsten and / or molybdenum, and the aluminum-blocking component reduces and / or prevents aluminum from diffusing from NWFM layer 256B into PWFM layer 256A. In some embodiments, PWFM layer 256A is a molybdenum-doped titanium nitride layer, a tungsten-doped titanium nitride layer, or a molybdenum and tungsten-doped titanium nitride layer.

[0058] To further enhance its diffusion blocking capability and provide threshold voltage adjustability (e.g., by obtaining different p-type work function characteristics), the amount of aluminum blocking component is maximized at the DWFM layer interface, such as in the portion of PWFM layer 256A adjacent to NWFM layer 256B. In some embodiments, the amount of aluminum blocking component decreases along the thickness of PWFM layer 256A from its top to its bottom. For example, the concentration of aluminum blocking component in PWFM layer 256A decreases from its top (which is adjacent / connected to NWFM layer 256B) to its bottom (which may be adjacent / connected to gate dielectric 50L). In such an example, the maximum concentration of aluminum blocking component is located in the portion of PWFM layer 256A adjacent to NWFM layer 256B, and the minimum concentration of aluminum blocking component (which may be virtually zero) is located in the portion of PWFM layer 256A adjacent to gate dielectric 50L (e.g., its high-k dielectric layer 54L). In some embodiments, the concentration of the aluminum blocking component in the PWFM layer 256A is gradient (e.g., increasing or decreasing along the thickness). In some embodiments, the concentration of the aluminum blocking component in the PWFM layer 256A is banded. For example, the PWFM layer 256A may have: a top portion (or band) with a first concentration of the aluminum blocking component, a middle portion with a second concentration of the aluminum blocking component, and a bottom portion with a third concentration of the aluminum blocking component. In such an example, the second concentration may be less than the first concentration and greater than the third concentration, thereby causing the concentration of the aluminum blocking component to decrease from top to bottom.

[0059] In some embodiments, because the PWFM layer 256A is formed around the lower channel structure (and may have sublayers as described below), the concentration distribution of the aluminum blocking component in the portion of the PWFM layer 256A along the sidewall of the lower channel structure (e.g., along the sidewall of its semiconductor (channel) layer) may differ from that in the portion of the PWFM layer 256A located between the top and bottom of the lower channel structure (e.g., between the top and bottom of its semiconductor (channel) layer). For example, the concentration of the aluminum blocking component in the portion of PWFM layer 256A along the sidewalls of semiconductor layers 25L and 25M can increase along the gate longitudinal direction (e.g., the y-direction) from the gate dielectric 50L (e.g., its high-k dielectric layer 54L) above it to NWFM layer 256B, such that the maximum concentration of the aluminum blocking component is located in the sidewall portion of PWFM layer 256A adjacent to NWFM layer 256B, and the minimum concentration of the aluminum blocking component is located in the sidewall portion of PWFM layer 256A adjacent to the portion of gate dielectric 50L (e.g., its high-k dielectric layer 54L) above the sidewalls of semiconductor layers 25L / 25M. Conversely, the concentration of the aluminum blocking component in the portion of PWFM layer 256A located between semiconductor layers 25M and 25L can increase and then decrease along the gate height direction (e.g., the z-direction) from the portion of gate dielectric 50L (e.g., its high-k dielectric layer 54L) above the bottom of semiconductor layer 25M to the portion of gate dielectric 50L (e.g., its high-k dielectric layer 54L) above the top of semiconductor layer 25L. For example, along the gate height direction (e.g., the z-direction), the concentration of the aluminum blocking component increases from a first concentration at the portion of gate dielectric 50L above the bottom of semiconductor layer 25M to a second concentration (e.g., the maximum concentration) at a point between semiconductor layers 25M and 25L (e.g., equidistant from their bottom and top, respectively), and then decreases from the second concentration to a third concentration at the portion of gate dielectric 50L above the top of semiconductor layer 25L. The first and third concentrations can be the same. Similarly, the concentration of the aluminum blocking component in the portion of the PWFM layer 256A located between the semiconductor layer 25L and the substrate 14 can increase and then decrease along the gate height direction (e.g., the z-direction) from the portion of the gate dielectric 50L (e.g., its high-k dielectric layer 54L) above the bottom of the semiconductor layer 25L to the portion of the gate dielectric 50L (e.g., its high-k dielectric layer 54L) above the substrate 14. Therefore, the portion of the PWFM layer 256A located between the semiconductor / channel layers of the lower channel structure can have an intermediate portion sandwiched between the upper and lower portions. The intermediate portion can have a first concentration (e.g., maximum concentration) of the aluminum blocking component, and the upper and lower portions can have a second concentration (e.g., minimum concentration) of the aluminum blocking component, which is less than the first concentration.In some embodiments, the thickness of the middle portion is greater than the thickness of the upper portion and the thickness of the lower portion.

[0060] The varying concentration of the aluminum blocking component can be provided by atomic layer deposition (ALD) instead of CVD to form the PWFM layer 256A, such that the PWFM layer 256A is formed of at least two sublayers, and at least the top one of the at least two sublayers includes the aluminum blocking component. In the depicted embodiment, the PWFM layer 256A is a molybdenum-doped titanium nitride layer, and Figure 12 A configuration of a molybdenum-doped titanium nitride layer is provided, which can be provided by an ALD and includes the desired aluminum blocking capability (e.g., the maximum aluminum concentration in a portion of the PWFM layer 256A adjacent to the NWFM layer 256B, which can be the top or bottom portion of the PWFM layer 256A, depending on the transistor stack configuration). Reference Figure 12 The PWFM layer 256A comprises a titanium nitride (TiN) sublayer 256A-1 formed by a corresponding ALD cycle, a molybdenum-doped titanium nitride (TiMoN) sublayer 256A-2 formed by a corresponding ALD cycle, and a molybdenum nitride (MoN) sublayer 256A-3 formed by a corresponding ALD cycle. In such an example, the molybdenum concentration (Mo%) decreases from the top of the PWFM layer 256A (formed by the MoN sublayer 256A-3) to the bottom of the PWFM layer 256A (formed by the TiN sublayer 256A-1). For example, the Mo% in the MoN sublayer 256A-3 is greater than the Mo% in the TiMoN sublayer 256A-2, and the Mo% in the TiMoN sublayer 256A-2 is greater than the Mo% in the TiN sublayer 256A-1.

[0061] This disclosure considers PWFM layer 256A with more or fewer sublayers. (See reference...) Figure 13 The PWFM layer 256A comprises two sublayers instead of three, such as a TiN sublayer 256A-1 formed by a corresponding ALD cycle and a TiMoN sublayer 256A-2 formed by a corresponding ALD cycle. In such an example, the Mo% decreases from the top of the PWFM layer 256A (formed by the TiMoN sublayer 256A-2) to the bottom of the PWFM layer 256A (formed by the TiN sublayer 256A-1). For example, the Mo% in the TiMoN sublayer 256A-2 is greater than the Mo% in the TiN sublayer 256A-1. (Reference) Figure 14The PWFM layer 256A comprises two sublayers, such as a TiMoN sublayer 256A-2 formed by a corresponding ALD cycle and a MoN sublayer 256A-3 formed by a corresponding ALD cycle. In such an example, the Mo% decreases from the top of the PWFM layer 256A (formed by the MoN sublayer 256A-3) to the bottom of the PWFM layer 256A (formed by the TiMoN sublayer 256A-2). For example, the Mo% in the MoN sublayer 256A-1 is greater than the Mo% in the TiMoN sublayer 256A-2. Various other sublayer configurations are considered, and the configuration of the PWFM layer 256A can be adjusted depending on the desired aluminum blocking capability, which can be determined based on the aluminum concentration (Al%) of the NWFM layer 256B. For example, when the NWFM layer 256B has a high aluminum concentration, the PWFM layer 256A can be configured as follows: Figure 14 The configuration described in the text (i.e., omitting the TiN sublayer 256A-1) is used to increase its ability to block aluminum diffusion, and when a less robust aluminum diffusion blocking capability is required, such as when the NWFM layer 256B has a lower aluminum concentration, the PWFM layer 256A can be configured as follows: Figure 13 The configuration is as depicted in the document (i.e., the MoN sublayer 256A-3 is omitted).

[0062] Mo% distribution in PWFM layer 256A (such as...) Figures 12 to 14 (As depicted in the text) is controlled via ALD. Figure 15 This is a flowchart of an exemplary ALD process 300 that can be implemented to form and provide a PWFM layer 256A with a desired Mo% variation according to various aspects of embodiments of this disclosure. The ALD process 300 includes a TiN ALD cycle 302-1, a TiMoN ALD cycle 302-2, and a MoN ALD cycle 302-3, and the PWFM layer 256A is formed by implementing at least two cycles of the ALD process 300. For example, as... Figure 12 The PWFM layer 256A depicted can be formed by implementing all three ALD cycles—TiN ALD cycle 302-1, followed by TiMoN ALD cycle 302-2, and then MoN ALD cycle 302-3. In another instance, as... Figure 13 The PWFM layer 256A depicted can be formed by implementing two of the three ALD cycles—TiN ALD cycle 302-1 and the subsequent TiMoN ALD cycle 302-2. In yet another example, as Figure 14 The PWFM layer 256A depicted can be formed by implementing two of the three ALD cycles—TiMoN ALD cycle 302-2 and the subsequent MoN ALD cycle 302-3. For clarity, the following has been simplified. Figure 15To better understand the inventive concept of embodiments of this disclosure. Additional steps may be provided before, during, and after ALD process 300 (and / or its cycles), and for additional embodiments of ALD process 300 (and / or its cycles), some of the described steps may be moved, replaced, or eliminated.

[0063] ALD process 300 includes loading a stacked device structure 200 into a process chamber prepared for an ALD process to form a PWFM layer, such as PWFM layer 256A. TiN ALD cycle 302-1 includes a titanium-containing pulse (which may include the inflow of a titanium-containing precursor into the process chamber and thus exposes the stacked device structure 200 therein), a cleanup process to remove any remaining titanium-containing precursor and any byproducts from the process chamber, a nitrogen-containing pulse (which may include the inflow of a nitrogen-containing precursor into the process chamber and thus exposes the stacked device structure 200 therein), and a cleanup process to remove any remaining nitrogen-containing precursor and any byproducts from the process chamber. The two deposition stages (titanium-containing pulse and nitrogen-containing pulse) and the two cleanup stages can constitute a TiN ALD sub-cycle, and the TiN ALD sub-cycle is a self-limiting process, wherein less than or equal to about one titanium and nitrogen monolayer can be deposited during a given TiN ALD sub-cycle. Therefore, TiN ALD cycle 302-1 repeats the TiN ALD sub-cycle until the TiN sublayer (such as TiN sublayer 256A-1) reaches the desired (target) thickness. For example, if the thickness of the TiN sublayer is equal to the target thickness (or within a given threshold of the target thickness), then TiN ALD cycle 302-1 ends. If the thickness of the TiN sublayer is not equal to the target thickness (or not within a given threshold of the target thickness), then TiN ALD cycle 302-1 begins another TiN ALD sub-cycle.

[0064] TiMoN ALD cycle 302-2 includes a titanium-containing pulse (which may include the inflow of a titanium-containing precursor into the process chamber and thus exposes the stacked device structure 200 therein), a cleanup process to remove any remaining titanium-containing precursor and any byproducts from the process chamber, a nitrogen-containing pulse (which may include the inflow of a nitrogen-containing precursor into the process chamber and thus exposes the stacked device structure 200 therein), a cleanup process to remove any remaining nitrogen-containing precursor and any byproducts from the process chamber, a molybdenum-containing pulse (which may include the inflow of a molybdenum-containing precursor into the process chamber and thus exposes the stacked device structure 200 therein), and a cleanup process to remove any remaining molybdenum-containing precursor and any byproducts from the process chamber. The three deposition stages (titanium-containing pulse, nitrogen-containing pulse, and molybdenum-containing pulse) and the three cleanup stages can constitute a TiMoNALD subcycle, and the TiMoNALD subcycle is a self-limiting process in which less than or equal to about one titanium-nitrogen and molybdenum monolayer can be deposited during a given TiMoNALD subcycle. Therefore, TiMoNALD loop 302-2 repeats the TiMoNALD sub-loop until the TiMoN sublayer (such as TiMoN sublayer 256A-2) reaches the desired (target) thickness. For example, if the thickness of the TiMoN sublayer is equal to the target thickness (or within a given threshold of the target thickness), then TiMoN ALD loop 302-2 ends. If the thickness of the TiMoN sublayer is not equal to the target thickness (or not within a given threshold of the target thickness), then TiMoNALD loop 302-2 begins another TiMoNALD sub-loop.

[0065] MoNALD cycle 302-3 includes a molybdenum-containing pulse (which may include the inflow of a molybdenum-containing precursor into the process chamber and thus exposes the stacked device structure 200 therein), a cleanup process to remove any remaining molybdenum-containing precursor and any byproducts from the process chamber, a nitrogen-containing pulse (which may include the inflow of a nitrogen-containing precursor into the process chamber and thus exposes the stacked device structure 200 therein), and a cleanup process to remove any remaining nitrogen-containing precursor and any byproducts from the process chamber. The two deposition stages (molybdenum-containing pulse and nitrogen-containing pulse) and the two cleanup stages can constitute a MoN ALD subcycle, and the MoN ALD subcycle is a self-limiting process in which less than or equal to about one molybdenum and nitrogen monolayer can be deposited during a given MoN ALD subcycle. Therefore, MoN ALD cycle 302-3 repeats the MoN ALD subcycle until the MoN sublayer (such as TiMoN sublayer 256A-3) reaches the desired (target) thickness. For example, if the thickness of the MoN sublayer is equal to the target thickness (or within a given threshold of the target thickness), then MoN ALD loop 302-3 ends. If the thickness of the MoN sublayer is not equal to the target thickness (or is not within a given threshold of the target thickness), then MoN ALD loop 302-3 begins another MoN ALD sub-loop.

[0066] In some embodiments, the titanium-containing precursor is titanium tetrachloride (TiCl4). In some embodiments, the nitrogen-containing precursor is ammonia (NH3). In some embodiments, the molybdenum-containing precursor is molybdenum chloride (V) (MOCl5). Other titanium-containing, nitrogen-containing, and molybdenum-containing precursors are considered in this disclosure. In some embodiments, a carrier gas is used to deliver the titanium-containing, nitrogen-containing, or molybdenum-containing precursor to the process chamber. The carrier gas may be an inert gas, such as argon-containing gas, helium-containing gas, other suitable inert gases, or combinations thereof. Various parameters of the ALD process 300 can be adjusted to achieve the desired Mo%, such as the flow rate of the deposition gas (e.g., the flow rate of the titanium-containing precursor gas, nitrogen-containing precursor gas, molybdenum-containing precursor gas, carrier gas, or combinations thereof), the concentration (or dosage) of the titanium-containing precursor gas, the concentration (or dosage) of the nitrogen-containing precursor gas, the concentration (or dosage) of the molybdenum-containing precursor gas, the concentration (or dosage) of the carrier gas, the pressure maintained in the process chamber, the duration of the deposition process (e.g., ALD cycle), the deposition temperature, other suitable deposition parameters, or combinations thereof. In some embodiments, the purification process employs an inert gas, such as an argon-containing gas, a helium-containing gas, other suitable inert gases, or combinations thereof.

[0067] Figure 16 It is a gate stack of transistors (such as) for manufacturing transistor stacks according to various aspects of embodiments of this disclosure. Figures 11A to 11C The flowchart of the method 400 for the stacked device structure 200 (gate 60 of the transistor stack) is shown. Figures 17A to 17E Stacked device structures (such as stacked device structure 200) according to various aspects of embodiments of this disclosure are in relation to Figure 16 Method 400 includes partial or complete cross-sectional views of various manufacturing stages. (Reference) Figures 17A to 17E The described method 400 can provide a stacked device structure 200 with an improved DWFM gate, as described herein. Figures 17A to 17E The cross-sectional view is cut along the longitudinal direction of the gate (e.g., the y-direction), like... Figure 11B The cross-sectional view is the same. For clarity, it has been simplified. Figure 16 and Figures 17A to 17E To better understand the inventive concept of embodiments of this disclosure. Additional steps may be provided before, during, and after method 400, and for additional embodiments of method 400, some of the described steps may be moved, replaced, or eliminated. Figures 17A to 17E Additional components may be added to the stacked device structure 200 depicted herein, and in other embodiments of the stacked device structure 200, some of the components described below may be replaced, modified, or eliminated.

[0068] refer to Figure 16 and Figure 17AMethod 400 includes forming a first gate dielectric (e.g., gate dielectric 50L) over a lower channel structure (e.g., semiconductor layer 25L) and forming a second gate dielectric (e.g., gate dielectric 50U) over an upper channel structure (e.g., semiconductor layer 25U). The channel stack may include an upper channel structure above the lower channel structure. In some embodiments, such as Figure 17A As depicted, a first gate dielectric (e.g., gate dielectric 50L) may be formed over the mesa 14' and / or the substrate isolation structure 18 (e.g., STI). In some embodiments, such as Figure 17A As depicted, a first gate dielectric (e.g., gate dielectric 50L) may be formed over a corresponding semiconductor layer 25M (e.g., those in device region 12L), and a second gate dielectric (e.g., gate dielectric 50U) may be formed over a corresponding semiconductor layer 25M (e.g., those in device region 12U). In some embodiments, such as Figure 17A As depicted, a first gate dielectric (e.g., a high-k dielectric layer 54L of gate dielectric 50L) and / or a second gate dielectric (e.g., a high-k dielectric layer 54U of gate dielectric 50U) may be formed over the insulating structure 226.

[0069] refer to Figure 16 and Figure 17A Method 400 includes forming a p-type power function layer, such as a PWFM layer 256A, over a first gate dielectric (e.g., gate dielectric 50L) and a second gate dielectric (e.g., gate dielectric 50U) in block 410. The PWFM layer 256A is referenced above. Figures 11A to 11C and Figures 12 to 15 The configuration and formation are as described. For example, in the depicted embodiment, PWFM layer 256A is a molybdenum-doped titanium nitride layer formed by an ALD process such as ALD process 300, and PWFM layer 256A has the highest molybdenum concentration at its top. In some embodiments, the molybdenum concentration in PWFM layer 256A is graded and / or banded, as described herein. In some embodiments, PWFM layer 256A is a tungsten-doped titanium nitride layer formed by an ALD process such as ALD process 300 (where tungsten may replace molybdenum as described herein), and PWFM layer 256A has the highest tungsten concentration at its top. In some embodiments, the tungsten concentration in PWFM layer 256A is graded and / or banded, as described herein. Molybdenum and / or tungsten can reduce the diffusion of aluminum from the subsequently formed n-type work function layer into PWFM layer 256A.

[0070] refer to Figure 16 , Figure 17A and Figure 17BMethod 400 includes forming a pseudo-layer DL over a p-type work function layer (e.g., PWFM layer 256A). For example, method 400 includes depositing a pseudo-layer (e.g., pseudo-layer DL) over a p-type work function layer (e.g., PWFM layer 256A) in block 415. Figure 17A ); and a portion of the second gate dielectric (e.g., gate dielectric 50U) that recesses the dummy layer (e.g., dummy layer DL) to expose the p-type power function layer (e.g., PWFM layer 256A) covering the upper channel structure (e.g., semiconductor layer 25U). Figure 17B ).exist Figure 17B In this configuration, a dummy layer DL covers the lower channel structure of the channel stack (e.g., semiconductor layer 25L). Specifically, the dummy layer DL covers the PWFM layer 256A surrounding the lower channel structure (e.g., semiconductor layer 25L), but leaves the PWFM layer 256A surrounding the upper channel structure (e.g., semiconductor layer 25U) exposed for subsequent processing. The composition of the dummy layer DL differs from that of the PWFM layer 256A and the subsequently formed n-type function layer (e.g., NWFM layer 256B) to enable selective removal / etching between them. In some embodiments, the dummy layer DL is a dielectric material comprising silicon and oxygen and / or carbon. For example, the dummy layer DL is a silicon oxide layer (e.g., SiO layer) and / or a silicon carbide oxide layer (e.g., SiOC layer). In some embodiments, the dummy layer DL is a bottom antireflective coating (BARC) that may comprise silicon and oxygen and / or carbon. In some embodiments, the dummy layer DL is formed by spin-coating deposition and / or other deposition processes (e.g., CVD). In some embodiments, the dummy layer DL is recessed by an etching process (e.g., back etching, such as BARC back etching).

[0071] refer to Figure 16 and Figure 17C Method 400 includes, in block 425, removing exposed portions of the p-type power function layer (e.g., PWFM layer 256A) to expose a second gate dielectric (e.g., gate dielectric 50U) above an upper channel structure (e.g., semiconductor layer 25U). In some embodiments, the etching process selectively removes the PWFM layer 256A relative to the dummy layer DL and the gate dielectric 50U (e.g., its high-k dielectric layer 54U). For example, the etching process etches the PWFM layer 256A without (or negligibly) etching the dummy layer DL and the high-k dielectric layer 54U. The etchant in the etching process can etch the PWFM layer 256A (e.g., a metallic material) at a higher rate than the dummy layer DL (e.g., a dielectric material) and the high-k dielectric layer 54U (e.g., another dielectric material). The etching process is dry etching, wet etching, other suitable etching, or a combination thereof.

[0072] refer to Figure 16 and Figure 17DMethod 100 includes removal of a dummy layer (e.g., dummy layer DL) in block 430. In some embodiments, the etching process selectively removes the dummy layer DL relative to the PWFM layer 256A and the gate dielectric 50U (e.g., its high-k dielectric layer 54U). For example, the etching process etches the dummy layer DL while not (or negligibly) etching the PWFM layer 256A and the high-k dielectric layer 54U. The etchant of the etching process may etch the dummy layer DL (e.g., a dielectric material with a first composition (e.g., silicon oxide or silicon carbide)) at a higher rate than that of the PWFM layer 256A (e.g., a metallic material) and the high-k dielectric layer 54U (e.g., a dielectric material having a second composition different from the first composition (e.g., hafnium oxide)). The etching process is dry etching, wet etching, other suitable etching, or a combination thereof.

[0073] refer to Figure 16 and Figure 17D Method 100 includes, in block 435, forming an n-type work function layer (e.g., NWFM layer 256B) over a second gate dielectric (e.g., gate dielectric 50U) and a p-type work function layer (e.g., PWFM layer 256A). The NWFM layer 256B can be configured (e.g., having a constant composition or a gradient composition) and formed (e.g., by CVD) as described herein. In the depicted embodiment, the NWFM layer 256B is a titanium aluminum carbide layer, and the NWFM layer 256B is formed directly on the PWFM layer 256A. As described herein, because the PWFM layer 256A is doped with molybdenum (and / or tungsten) and its concentration can be varied by the disclosed ALD process, the PWFM layer 256A can be used as an adjustable work function layer and an adjustable aluminum barrier layer, thereby eliminating the need for a work function barrier layer between the PWFM layer 256A and the NWFM layer 256B. Therefore, the PWFM layer 256A can simplify processing complexity and / or cost.

[0074] refer to Figure 16 and Figure 17E Method 100 includes forming a bulk / fill layer (e.g., bulk / fill layer 57) in block 440. The bulk / fill layer 57 may be formed over the NWFM layer 256B and / or the PWFM layer 256A. In some embodiments, forming the bulk / fill layer 57 includes depositing a conductive material over the NWFM layer 256B by ALD, CVD, physical vapor deposition (PVD), plating, other suitable processes, or combinations thereof. The conductive material may fill the remaining portion of the gate opening. In some embodiments, a planarization process (e.g., CMP) may be implemented to remove excess conductive material, such as conductive material disposed over the ILD layer 48U and / or CESL 46U.

[0075] In view of embodiments of this disclosure, stacked device structures (such as stacked device structure 10 and stacked device structure 200) can provide a CFET having a first transistor (e.g., transistor 20U, such as an n-type transistor) located above a second transistor (e.g., transistor 20L, such as a p-type transistor), and the gate electrodes of the first and second transistors comprising different types of work function materials configured to improve device performance. For example, the first transistor may include an NWFM layer as described herein, and the second GAA transistor may include a PWFM layer as described herein. The first transistor may have a first threshold voltage, and the second transistor may have a second threshold voltage. In some embodiments, the NWFM layer and the PWFM layer are configured to have the same features as referenced above. Figures 1A to 1C and Figures 2 to 10 The described gradient composition can reduce variations in the first and second threshold voltages. In some embodiments, the PWFM layer is doped with molybdenum and / or tungsten, as referenced above. Figures 11A to 11C , Figures 12 to 15 and Figures 17A to 17C As described, this can also reduce the variation in the first threshold voltage and the second threshold voltage. When the disclosed CFET is implemented in memory applications (e.g., in static random access memory (SRAM)), the reduction in aluminum provided by the disclosed DWFM gate configuration can reduce the threshold voltage variation observed in the CFET by about 10% to about 15%, reducing the minimum supply voltage (V) ccmin (For example, a reduction of up to 30mV to 60mV), improved overall performance, or a combination thereof. Different embodiments may have different advantages, and no particular advantage is required for any embodiment.

[0076] Stacked device structures 10, 200, 20U, 20L, etc., may be included in a microprocessor, memory, other devices, or combinations thereof. In some embodiments, the stacked device structures 10 and / or 200 described herein are part of an IC chip, a system-on-a-chip (SoC), or a portion thereof, which include various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type FETs (PFETs), n-type FETs (NFETs), metal-oxide-semiconductor FETs (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS transistors (LDMOS), high-voltage transistors, high-frequency transistors, other components, or combinations thereof.

[0077] This disclosure provides numerous different embodiments. Methods for fabricating gate stacks (e.g., high-k / metal gates) are described herein, and several advantages are provided, particularly for stacked device structures. The gate stacks disclosed herein can be implemented in a variety of device types. For example, the gate stacks described herein are suitable for stacking planar field-effect transistors (FETs), stacking multi-gate transistors such as stacked FinFETs, stacked GAA transistors, stacked fork-plate devices, stacked omega-gate (Ω-gate) devices, stacked pi-gate (π-gate) devices, or combinations thereof.

[0078] An exemplary stacked device structure includes a gate and a semiconductor layer stack. The semiconductor layer stack is disposed above a substrate and includes a first semiconductor layer disposed above a second semiconductor layer. The gate includes a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed above the first semiconductor layer, and the second gate dielectric layer is disposed above the second semiconductor layer. The gate also includes a first type of work function metal layer and a second type of work function metal layer. The first type of work function metal layer is disposed above the first gate dielectric layer, and the second type of work function metal layer is disposed above the second gate dielectric layer. At least one of the first type of work function metal layer or the second type of work function metal layer has a gradient composition.

[0079] In some embodiments, a first type of power function metal layer is disposed around a first semiconductor layer, and a second type of power function metal layer is disposed around a second semiconductor layer. In some embodiments, the second type of power function metal layer has a gradient composition, comprising nitrogen and titanium, and the nitrogen-to-titanium ratio increases from the top to the bottom of the second type of power function metal layer. In some embodiments, the first type of power function metal layer has a gradient composition, comprising nitrogen and titanium, and the nitrogen-to-titanium ratio decreases from the top to the bottom of the first type of power function metal layer. In some embodiments, the first type of power function metal layer has a gradient composition, comprising aluminum and titanium, and the aluminum-to-titanium ratio decreases from the top to the bottom of the first type of power function metal layer. In some embodiments, the second type of power function metal layer has a gradient composition, comprising aluminum and titanium, and the aluminum-to-titanium ratio increases from the top to the bottom of the second type of power function metal layer.

[0080] In some embodiments, a first type of power function metal layer has a first gradient composition, and a second type of power function metal layer has a second gradient composition. In some embodiments, the first type of power function metal layer includes a first metal and a second metal, wherein the amount of the second metal decreases along the gate height direction from the top to the bottom of the first type of power function metal layer, and the second type of power function metal layer includes a first metal and a non-metallic component, wherein the amount of the non-metallic component increases along the gate height direction from the top to the bottom of the second type of power function metal layer. The bottom of the first type of power function metal layer and the top of the second type of power function metal layer may share an interface. In some embodiments, the bottom of the first type of power function metal layer is adjacent to the top of the second type of power function metal layer. In some embodiments, the gate includes a power function barrier layer disposed between the first type of power function metal layer and the second type of power function metal layer. In some embodiments, the power function barrier layer is adjacent to the bottom of the first type of power function metal layer and the top of the second type of power function metal layer, and the interface includes the power function barrier layer. In some embodiments, the power function barrier layer includes a first metal, a non-metallic component, and a third metal.

[0081] Another exemplary stacked device structure includes a gate and a semiconductor layer stack. The semiconductor layer stack is disposed above a substrate and includes a first semiconductor layer disposed above a second semiconductor layer. The gate includes a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed above the first semiconductor layer, and the second gate dielectric layer is disposed above the second semiconductor layer. The gate also includes a p-type work function metal layer disposed above the second gate dielectric layer and around the second semiconductor layer. The gate also includes an n-type work function metal layer disposed above the first gate dielectric layer and around the first semiconductor layer. The n-type work function metal layer is disposed on the p-type work function metal layer. The n-type work function metal layer includes a first metal and a second metal, the p-type work function metal layer includes a first metal and nitrogen, and the portion of the p-type work function metal layer adjacent to the n-type work function metal layer also includes a third metal.

[0082] In some embodiments, the first metal is titanium, the second metal is aluminum, and the third metal is molybdenum. In some embodiments, the first metal is titanium, the second metal is aluminum, and the third metal is tungsten.

[0083] In some embodiments, the p-type power function metal layer is a molybdenum-doped titanium nitride layer comprising a titanium nitride sublayer and a titanium molybdenum nitride sublayer. In such embodiments, the titanium molybdenum nitride sublayer is a portion of the p-type power function metal layer adjacent to the n-type power function metal layer. In some embodiments, the p-type power function metal layer is a molybdenum-doped titanium nitride layer comprising a titanium nitride sublayer, a titanium molybdenum nitride sublayer disposed on the titanium nitride sublayer, and a molybdenum nitride sublayer disposed on the titanium molybdenum nitride sublayer. In such embodiments, the molybdenum nitride sublayer is a portion of the p-type power function metal layer adjacent to the n-type power function metal layer. In some embodiments, the p-type power function metal layer is a molybdenum-doped titanium nitride layer comprising a titanium molybdenum nitride sublayer and a molybdenum nitride sublayer. In such embodiments, the molybdenum nitride sublayer is a portion of the p-type power function metal layer adjacent to the n-type power function metal layer.

[0084] An exemplary method includes forming a first gate dielectric over a lower channel structure and a second gate dielectric over an upper channel structure. The channel stack includes an upper channel structure located above the lower channel structure. The method further includes: forming a first type of work function layer having a first gradient composition over the first gate dielectric; and forming a second type of work function layer having a second gradient composition over the second gate dielectric. In some embodiments, the method further includes forming a square work function blocking layer on the first type of work function layer before forming the second type of work function layer. In some embodiments, the first type of work function layer is a titanium nitride layer, and the titanium nitride layer has a nitrogen to titanium ratio that increases along the thickness of the first type of work function layer. In some embodiments, the second type of work function layer is a titanium-aluminum layer, and the titanium-aluminum layer has an aluminum to titanium ratio that decreases along the thickness of the second type of work function layer.

[0085] Some embodiments of this application provide a stacked device structure, including: a semiconductor layer stack disposed above a substrate, wherein the semiconductor layer stack includes a first semiconductor layer of a first device disposed above a second semiconductor layer of a second device, wherein the first device is disposed above the second device; and a gate comprising: a first gate dielectric layer and a second gate dielectric layer, wherein the first gate dielectric layer is disposed above the first semiconductor layer and the second gate dielectric layer is disposed above the second semiconductor layer; and a first type of work function metal layer and a second type of work function metal layer, wherein the first type of work function metal layer is disposed above the first gate dielectric layer and the second type of work function metal layer is disposed above the second gate dielectric layer, and at least one of the first type of work function metal layer or the second type of work function metal layer has a gradient composition.

[0086] In some embodiments, the second type of work-function metal layer has the gradient composition; the second type of work-function metal layer includes nitrogen and titanium; and the ratio of nitrogen to titanium increases from the top of the second type of work-function metal layer to the bottom of the second type of work-function metal layer. In some embodiments, the first type of work-function metal layer has the gradient composition; the first type of work-function metal layer includes nitrogen and titanium; and the ratio of nitrogen to titanium decreases from the top of the first type of work-function metal layer to the bottom of the first type of work-function metal layer. In some embodiments, the first type of work-function metal layer has the gradient composition; the first type of work-function metal layer includes aluminum and titanium; and the ratio of aluminum to titanium decreases from the top of the first type of work-function metal layer to the bottom of the first type of work-function metal layer. In some embodiments, the second type of work-function metal layer has the gradient composition; the second type of work-function metal layer includes aluminum and titanium; and the ratio of aluminum to titanium increases from the top of the second type of work-function metal layer to the bottom of the second type of work-function metal layer. In some embodiments, the first type of work-function metal layer has a first gradient composition; and the second type of work-function metal layer has a second gradient composition. In some embodiments, the first type of power function metal layer includes a first metal and a second metal, wherein the amount of the second metal decreases along the gate height direction from the top to the bottom of the first type of power function metal layer; and the second type of power function metal layer includes the first metal and a non-metallic component, wherein the amount of the non-metallic component increases along the gate height direction from the top to the bottom of the second type of power function metal layer, wherein the bottom of the first type of power function metal layer and the top of the second type of power function metal layer share an interface. In some embodiments, the bottom of the first type of power function metal layer is adjacent to the top of the second type of power function metal layer. In some embodiments, the gate includes a power function barrier layer, wherein the power function barrier layer is disposed between the first type of power function metal layer and the second type of power function metal layer, the power function barrier layer is adjacent to the bottom of the first type of power function metal layer and the top of the second type of power function metal layer, and the interface includes the power function barrier layer. In some embodiments, the power function barrier layer includes the first metal, the non-metallic component, and a third metal. In some embodiments, the first type of power function metal layer is disposed around the first semiconductor layer, and the second type of power function metal layer is disposed around the second semiconductor layer.

[0087] Some other embodiments of this application provide a stacked device structure, including: a semiconductor layer stack disposed above a substrate, wherein the semiconductor layer stack includes a first semiconductor layer disposed above a second semiconductor layer; and a gate comprising: a first gate dielectric layer and a second gate dielectric layer, wherein the first gate dielectric layer is disposed above the first semiconductor layer, and the second gate dielectric layer is disposed above the second semiconductor layer; a p-type power function metal layer disposed above the second gate dielectric layer and around the second semiconductor layer; and an n-type power function metal layer disposed above the first gate dielectric layer and around the first semiconductor layer, wherein the n-type power function metal layer is disposed on the p-type power function metal layer, wherein the n-type power function metal layer includes a first metal and a second metal, the p-type power function metal layer includes the first metal and nitrogen, and the portion of the p-type power function metal layer adjacent to the n-type power function metal layer further includes a third metal.

[0088] In some embodiments, the first metal is titanium, the second metal is aluminum, and the third metal is molybdenum. In some embodiments, the p-type work function metal layer is a molybdenum-doped titanium nitride layer, the molybdenum-doped titanium nitride layer comprising: a titanium nitride sublayer; and a titanium nitride molybdenum sublayer disposed on the titanium nitride sublayer, wherein the titanium nitride molybdenum sublayer is a portion of the p-type work function metal layer adjacent to the n-type work function metal layer. In some embodiments, the p-type work function metal layer is a molybdenum-doped titanium nitride layer, the molybdenum-doped titanium nitride layer comprising: a titanium nitride sublayer; a titanium nitride molybdenum sublayer disposed on the titanium nitride sublayer; and a molybdenum nitride sublayer disposed on the titanium nitride molybdenum sublayer, wherein the molybdenum nitride sublayer is a portion of the p-type work function metal layer adjacent to the n-type work function metal layer. In some embodiments, the p-type work function metal layer is a molybdenum-doped titanium nitride layer, the molybdenum-doped titanium nitride layer comprising: a titanium nitride molybdenum sublayer; and a molybdenum nitride sublayer disposed on the titanium nitride molybdenum sublayer, wherein the molybdenum nitride sublayer is the portion of the p-type work function metal layer adjacent to the n-type work function metal layer. In some embodiments, the first metal is titanium, the second metal is aluminum, and the third metal is tungsten.

[0089] Further embodiments of this application provide a method for forming a stacked device structure, comprising: forming a first gate dielectric over a lower channel structure and forming a second gate dielectric over an upper channel structure, wherein the channel stack includes the upper channel structure located above the lower channel structure; forming a first type of work function layer having a first gradient composition over the first gate dielectric; and forming a second type of work function layer having a second gradient composition over the second gate dielectric.

[0090] In some embodiments, the method further includes forming a square power function blocking layer on the first type of power function layer before forming the second type of power function layer. In some embodiments, the first type of power function layer is a titanium nitride layer having a nitrogen-to-titanium ratio that increases along the thickness of the first type of power function layer; and the second type of power function layer is a titanium-aluminum layer having an aluminum-to-titanium ratio that decreases along the thickness of the second type of power function layer.

[0091] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A stacked device structure, comprising: A semiconductor layer stack is disposed above a substrate, wherein the semiconductor layer stack includes a first semiconductor layer of a first device disposed above a second semiconductor layer of a second device, wherein the first device is disposed above the second device; and Gate, the gate comprising: A first gate dielectric layer and a second gate dielectric layer, wherein the first gate dielectric layer is disposed above the first semiconductor layer, and the second gate dielectric layer is disposed above the second semiconductor layer; A first type of power function metal layer and a second type of power function metal layer, wherein the first type of power function metal layer is disposed above the first gate dielectric layer, and the second type of power function metal layer is disposed above the second gate dielectric layer, and At least one of the first type of work function metal layer or the second type of work function metal layer has a gradient composition.

2. The stacked device structure according to claim 1, wherein: The second type of work-function metal layer has the gradient composition; The second type of work function metal layer includes nitrogen and titanium; and The ratio of nitrogen to titanium increases from the top of the second type of work function metal layer to the bottom of the second type of work function metal layer.

3. The stacked device structure according to claim 1, wherein: The first type of work-function metal layer has the gradient composition; The first type of work function metal layer includes nitrogen and titanium; and The ratio of nitrogen to titanium decreases from the top of the first type of work function metal layer to the bottom of the first type of work function metal layer.

4. The stacked device structure according to claim 1, wherein: The first type of work-function metal layer has the gradient composition; The first type of work-function metal layer includes aluminum and titanium; and The ratio of aluminum to titanium decreases from the top of the first type of work function metal layer to the bottom of the first type of work function metal layer.

5. The stacked device structure according to claim 1, wherein: The second type of work-function metal layer has the gradient composition; The second type of work-function metal layer includes aluminum and titanium; and The ratio of aluminum to titanium increases from the top of the second type of work function metal layer to the bottom of the second type of work function metal layer.

6. The stacked device structure according to claim 1, wherein: The first type of work-function metal layer has a first gradient composition; and The second type of work function metal layer has a second gradient composition.

7. The stacked device structure according to claim 6, wherein: The first type of power function metal layer includes a first metal and a second metal, wherein the amount of the second metal decreases along the gate height direction from the top to the bottom of the first type of power function metal layer; and The second type of power function metal layer includes the first metal and non-metal components, wherein the amount of non-metal components increases along the gate height direction from the top of the second type of power function metal layer to the bottom of the second type of power function metal layer, wherein the bottom of the first type of power function metal layer and the top of the second type of power function metal layer share an interface.

8. The stacked device structure according to claim 7, wherein, The bottom of the first type of power function metal layer is adjacent to the top of the second type of power function metal layer.

9. A stacked device structure, comprising: A semiconductor layer stack is disposed above a substrate, wherein the semiconductor layer stack includes a first semiconductor layer disposed above a second semiconductor layer; and Gate, the gate comprising: A first gate dielectric layer and a second gate dielectric layer, wherein the first gate dielectric layer is disposed above the first semiconductor layer, and the second gate dielectric layer is disposed above the second semiconductor layer; A p-type work function metal layer is disposed above the second gate dielectric layer and around the second semiconductor layer; An n-type work function metal layer is disposed above the first gate dielectric layer and around the first semiconductor layer, wherein the n-type work function metal layer is disposed on the p-type work function metal layer. The n-type work function metal layer includes a first metal and a second metal, the p-type work function metal layer includes the first metal and nitrogen, and the portion of the p-type work function metal layer adjacent to the n-type work function metal layer also includes a third metal.

10. A method for forming a stacked device structure, comprising: A first gate dielectric is formed above a lower channel structure, and a second gate dielectric is formed above an upper channel structure, wherein the channel stack includes the upper channel structure located above the lower channel structure; A first type of work function layer having a first gradient is formed above the first gate dielectric; and A second type of work function layer with a second gradient is formed above the second gate dielectric.

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