Acquisition and stimulation in-situ integrated capacitive coupling type active neural electrode array and preparation method thereof

Abstract

The invention discloses an acquisition and stimulation in-situ integrated capacitive coupling type active neural electrode array and a preparation method thereof. The electrode array comprises a flexible substrate and a plurality of neural electrode units on the flexible substrate, the neural electrode unit comprises two silicon nano films, a gate dielectric layer, a metal layer and a capacitive coupling dielectric layer, wherein the two silicon nanometer films are located on the flexible substrate, the gate dielectric layer covers the silicon nanometer films, and the metal layer comprises electrode metal, a metal bonding pad and a metal interconnection line; the electrode metal is matched with the two silicon nanometer films, the gate dielectric layer and the flexible substrate to form a selection transistor and a driving transistor, and the metal bonding pad is matched with the capacitance coupling dielectric layer to form an electrode contact; metal interconnects electrically connect the select transistors, the drive transistors, and the electrode contacts. The selection transistor and the driving transistor form an acquisition and stimulation closed-loop control unit, so that synchronous electroneurographic signal acquisition and electrical stimulation are realized, the experiment and treatment efficiency is improved, and the loss and interference in the signal transmission process are reduced.

Description

Technical Field

[0001] This invention belongs to the field of biomedical technology, specifically relating to a capacitively coupled active neural electrode array for in-situ acquisition of stimuli and its preparation method. Background Technology

[0002] In the field of neural interface technology, with the increasing demand for neural modulation and signal recording, contemporary neural implants are developing towards smaller size, greater flexibility, and higher electrode channel counts. High-channel-count electrode arrays have attracted much attention due to their ability to cover larger tissue areas and improve the spatial resolution and selectivity of neural recording and stimulation.

[0003] Currently, neural electrodes used to record neuronal activity can be divided into passive neural electrodes and active neural electrodes. The mainstream neural electrodes are still traditional passive electrodes. Traditional passive neural electrodes are limited by the fact that each electrode must be individually wired, resulting in low spatial resolution and difficulty in increasing integration density. Furthermore, passive neural electrodes can only perform simple signal acquisition and cannot process signals at the signal source, making them susceptible to external interference during transmission and reducing the signal-to-noise ratio. This limits the application of passive neural electrodes in scenarios requiring real-time signal processing and feedback. While active neural electrodes partially solve the wiring bottleneck by integrating transistors, existing active neural electrodes have limited functionality, only capable of unidirectional neural electrical signal acquisition or unidirectional neural stimulation. This functional separation leads to inherent defects in the resulting neuromodulation system: in treatment scenarios requiring real-time feedback (such as epileptic seizure suppression), signal perception and stimulus execution must rely on different devices or time-sharing operations, resulting in system response delays; at the same time, remote transmission and external processing of neural signals also introduce additional interference and power consumption, ultimately leading to slow overall treatment response and low modulation efficiency, making it difficult to meet the closed-loop neuromodulation requirements with extremely high real-time requirements.

[0004] Therefore, there is an urgent need to develop a closed-loop neural interface solution that can integrate real-time signal acquisition and electrical stimulation. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a capacitively coupled active neural electrode array for in-situ acquisition of stimuli and its fabrication method.

[0006] The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a capacitively coupled active neural electrode array for in-situ acquisition of stimuli, comprising: a flexible substrate and a plurality of neural electrode units formed on the flexible substrate; wherein the plurality of neural electrode units are arranged in a matrix. The neural electrode unit comprises: two silicon nanofilms, a gate dielectric layer, a metal layer, and a capacitive coupling dielectric layer; Two silicon nanofilms are located on the flexible substrate, and two N-type doped regions are provided on the silicon nanofilms; the gate dielectric layer covers the silicon nanofilms and forms a groove on each N-type doped region; The metal layer includes: electrode metal, metal pads, and metal interconnects; the electrode metal, in conjunction with two silicon nanofilms, a gate dielectric layer, and a flexible substrate, forms a select transistor and a drive transistor; the metal pads, in conjunction with the capacitive coupling dielectric layer, form electrode contacts; the metal interconnects are used to electrically connect the select transistor, the drive transistor, and the electrode contacts; wherein, the gate of the select transistor is connected to an external line select signal, the source of the select transistor is connected to one electrode contact, the drain of the select transistor is connected to the gate of the drive transistor, the drain of the drive transistor is connected to an electrical stimulation signal, and the source of the drive transistor is connected to another electrode contact; the gate, source, and drain are all formed by the electrode metal.

[0007] Optionally, the silicon nanofilm is doped with phosphorus at a concentration of 1. 10 18 / cm 3 ~1 10 22 / cm 3 The thickness of the silicon nanofilm is 200nm~300nm.

[0008] Optionally, the material of the capacitive coupling dielectric layer is MXene / Parylene C polymer, and the thickness of the capacitive coupling dielectric layer is 5μm~10μm; in the MXene / Parylene C polymer, the mass percentage of MXene is 1.0wt%~1.5wt%.

[0009] Optionally, the MXene / Parylene C polymer is prepared by solution casting, including the following steps: MXene was ultrasonically dispersed into a DMF solution to form an MXene-DMF solution; Under constant temperature and stirring conditions, Parylene C was added to the MXene-DMF solution in portions, and stirring was continued until a uniform gel-like sol was formed. The gel-like sol was allowed to stand and defoam to obtain the MXene / Parylene C polymer.

[0010] Optionally, the gate dielectric layer is an alumina / hafnium oxide stacked material, and the thickness of the gate dielectric layer is 8nm~12nm.

[0011] Optionally, the metal layer is made of Ti / Pt multilayer metal, wherein the thickness of Ti is 9nm~11nm and the thickness of Pt is 95nm~105nm.

[0012] Optionally, the flexible substrate is made of Parylene C and has a thickness of 5 μm to 8 μm.

[0013] Secondly, the present invention provides a method for fabricating a capacitively coupled active neural electrode array for in-situ stimulation acquisition, used to fabricate the aforementioned capacitively coupled active neural electrode array for in-situ stimulation acquisition, the method comprising: Step 1: Obtain a silicon-on-insulator (SiO2) epitaxial wafer, and grow a SiO2 layer on the epitaxial wafer as a mask; the SiO2 epitaxial wafer includes a bottom silicon layer, a SiO2 layer, and a top silicon layer from bottom to top; Step 2: Divide the SiO2 mask into multiple regions arranged in a matrix, and etch 4 grooves in each region to expose the underlying top silicon layer; Step 3: Perform N-type ion implantation and annealing on the top silicon layer at the bottom of the groove to form an N-type doped region; Step 4: Remove the SiO2 mask; separate the top silicon layer from the SiO2 layer using a wet etching process to form a suspended silicon nanofilm; Step 5: Transfer the silicon nanofilm onto a flexible substrate; Step 6: Etch the silicon nanofilm to isolate the mesa in each of the regions; Step 7: Use atomic deposition technology to grow a gate dielectric on the surface of the current sample, and etch the gate dielectric directly above the four N-type doped regions in each region to form four grooves; Step 8: Deposit a metal layer on the surface of the current sample using electron beam evaporation, with the deposition thickness exceeding the top of the groove; Step 9: Pattern the metal layer to form two sources, two drains, two gates, two metal pads, and metal interconnects in each region; wherein, in each region, one set of gates, sources, drains, and the underlying gate dielectric layer, silicon nanofilm, and flexible substrate forms a select transistor, and another set of gates, sources, drains, and the underlying gate dielectric layer, silicon nanofilm, and flexible substrate forms a drive transistor. The metal interconnects connect the gate of the select transistor to an external line select signal, connect the source of the select transistor to a metal pad, connect the drain of the select transistor to the gate of the drive transistor, connect the drain of the drive transistor to an electrical stimulation signal, and connect the source of the drive transistor to another metal pad. Step 10: Prepare a polymer film with both biocompatibility and dielectric properties on the surface of the current sample using solution casting method to form a capacitive coupling dielectric layer. The metal pads and the capacitive coupling dielectric layer together constitute electrode contacts, resulting in two electrode contacts for signal acquisition and electrical stimulation, respectively.

[0014] This invention provides a capacitively coupled active neural electrode array with in-situ integrated acquisition and stimulation. This electrode array uses a line-selection signal to control the conduction of a selection transistor, thereby selecting the acquisition-stimulation site. When an abnormal neural electrical signal is acquired, it is directly conducted to the gate of a driving transistor through the selection transistor, causing the driving transistor to conduct and thus applying an electrical stimulation signal to the abnormal site. Based on this integrated design, this invention achieves simultaneous neural electrical signal acquisition and stimulation, avoiding the cumbersome process of using different devices for neural electrical signal acquisition and stimulation in traditional methods. This significantly improves the efficiency of experiments and treatments, reduces signal loss and interference during transmission, and thus simultaneously enhances the spatiotemporal resolution of neural signal acquisition and the accuracy of closed-loop electrical stimulation.

[0015] Furthermore, this invention utilizes capacitive coupling for signal transmission, employing a biocompatible MXene / Parylene C polymer as the capacitive coupling dielectric layer between the metal electrode and neural tissue. This composite structure combines the advantages of both materials: Parylene C provides excellent chemical inertness, biocompatibility, and pinhole-free, dense protective properties, effectively preventing fluid penetration and ensuring stable operation of internal electronic devices in long-term implantation environments; MXene, as a two-dimensional conductive material, significantly enhances the dielectric response of the composite medium. The combination of these two materials enables the capacitive coupling dielectric layer to possess both good signal coupling efficiency and excellent biocompatibility, fundamentally avoiding the DC leakage current problem of traditional resistive contact electrodes, eliminating the risks of electrochemical corrosion and tissue damage, and laying the material foundation for safe and long-term neural interfaces.

[0016] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a capacitively coupled active neural electrode array that integrates in situ for acquiring stimuli, provided in an embodiment of the present invention. Figure 2 This is a circuit diagram of a capacitively coupled active neural electrode array for in-situ acquisition of stimuli provided in an embodiment of the present invention. Figures 3-8 This invention provides a process for preparing a capacitively coupled active neural electrode array that integrates in situ for acquiring stimuli. Detailed Implementation

[0018] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0019] To simultaneously acquire and stimulate neural electrical signals, improve the efficiency of experiments and treatments, reduce signal loss and interference during transmission, and obtain EEG signals with higher spatiotemporal resolution and signal-to-noise ratio, this invention provides a capacitively coupled active neural electrode array for in-situ acquisition and stimulation. See also... Figure 1 The neural electrode array includes: a flexible substrate and multiple neural electrode units formed on the flexible substrate; these neural electrode units are arranged in a matrix. The neural electrode unit comprises: two silicon nanofilms, a gate dielectric layer, a metal layer, and a capacitive coupling dielectric layer (i.e., Figure 1 (coupling medium layer in the middle). Two silicon nanofilms are located on a flexible substrate, and two N-type doped regions are provided on the silicon nanofilms; a gate dielectric layer covers the silicon nanofilms, and a groove is formed on each N-type doped region; The metal layer includes: electrode metal, metal pads, and metal interconnects; wherein, the electrode metal, together with two silicon nanofilms, a gate dielectric layer, and a flexible substrate, forms a select transistor and a drive transistor; the metal pads, together with a capacitive coupling dielectric layer, form electrode contacts; the metal interconnects are used to electrically connect the select transistor, the drive transistor, and the electrode contacts; wherein, the gate of the select transistor is connected to an external line select signal, the source of the select transistor is connected to one electrode contact, the drain of the select transistor is connected to the gate of the drive transistor, the drain of the drive transistor is connected to an electrical stimulation signal, and the source of the drive transistor is connected to another electrode contact; the gate, source, and drain are all formed of electrode metal.

[0020] See Figure 2 , Figure 2 The diagram illustrates a circuit schematic of a capacitively coupled active neural electrode array with in-situ integrated stimulation acquisition according to an embodiment of the present invention. The electrode array includes 4×4 neural electrode units. The electrode contacts connected to the source of the selection transistor are acquisition electrode contacts, used to acquire neural electrical signals; the electrode contacts connected to the source of the driving transistor are stimulation electrode contacts, used to release electrical stimulation signals to stimulate nerve tissue. Specifically, in each neural electrode unit, the selection transistor and the driving transistor together constitute a closed-loop control unit for acquisition-stimulation, realizing bidirectional communication between acquisition and stimulation. The selection transistor is used to determine the acquisition and stimulation sites based on the external line selection signal, and the driving transistor regulates the current flowing into the stimulation electrode contact. Specifically, the operating state of the selection transistor is determined by both the external line selection signal and the acquired neural electrical signal. When the external line selection signal is high, the selection transistor is turned on. When an abnormal neural electrical signal (such as an epileptic signal) is acquired, the selection transistor transmits the abnormal neural electrical signal to the gate of the driving transistor, causing the driving transistor to turn on. Thus, the electrical stimulation signal is transmitted through the driving transistor to the stimulation electrode contact and applied to the abnormal point, suppressing the abnormal neural electrical signal.

[0021] This invention utilizes a selection transistor and a driving transistor to form a closed-loop acquisition-stimulation control unit. Through bidirectional active multiplexing addressing, it achieves closed-loop control of synchronous neural electrical signal acquisition and electrical stimulation, improving the integration of the neural electrode circuit. This avoids the cumbersome process of using different devices for electrical stimulation and neural electrical signal acquisition in traditional methods, increasing the efficiency of experiments and treatments, reducing signal loss and interference during transmission, and enabling the acquisition of EEG signals with higher spatiotemporal resolution and signal-to-noise ratio. In practical medical applications, this invention uses the acquired abnormal neural electrical signals to control the real-time conduction of the driving transistor, allowing for real-time application of electrical stimulation based on the state of neural activity, achieving more precise and rapid neural modulation and improving treatment efficacy.

[0022] It is understood that, in practice, the neural electrode array provided in this embodiment of the invention is used as the front-end acquisition-stimulation section of the neural electrode, which is connected to an external system via metal interconnects and metal ports. Therefore, the metal interconnects are also used to form line selection signal input lines and electrical stimulation signal input lines, which are connected to an external circuit via metal ports to transmit line selection signals and electrical stimulation signals.

[0023] In this embodiment of the invention, the doping element of the silicon nanofilm is phosphorus, and the doping concentration is 1. 10 18 / cm 3 ~1 10 22 / cm 3 The thickness of the silicon nanofilm is 200nm~300nm.

[0024] In this embodiment of the invention, the material of the capacitive coupling dielectric layer is MXene / Parylene C polymer, and the thickness of the capacitive coupling dielectric layer is 5μm~10μm; in the MXene / Parylene C polymer, the mass percentage of MXene is 1.0wt%~1.5wt%.

[0025] In one implementation, the MXene / Parylene C polymer is prepared using a solution casting method, comprising the following steps: MXene was ultrasonically dispersed into a DMF solution to form an MXene-DMF solution; Under constant temperature and stirring conditions, Parylene C was added to the MXene-DMF solution in portions, and stirring was continued until a uniform gel-like sol was formed. The gel-like sol was allowed to stand and defoam to obtain the MXene / Parylene C polymer.

[0026] Understandably, this invention utilizes a capacitive coupling mechanism for signal transmission, employing a biocompatible MXene / Parylene C polymer as the capacitive coupling medium layer (i.e., coupling medium layer) between the electrode contacts and nerve tissue. This composite structure combines the advantages of both materials: Parylene C provides excellent chemical inertness, biocompatibility, and good protective properties, effectively blocking the penetration of bodily fluids and ensuring the stable operation of internal electronic devices in long-term implantation environments; MXene, as a two-dimensional conductive material, significantly enhances the dielectric response of the composite medium. The combination of these two materials enables the capacitive coupling medium layer to possess both good signal coupling efficiency and excellent biocompatibility (for example, when the mass percentage of MXene is 1.0 wt%, the relative permittivity of the MXene / Parylene C polymer can reach 15), fundamentally avoiding the DC leakage current problem of traditional resistive contact electrodes, eliminating the risk of electrochemical corrosion and tissue damage, and laying the material foundation for achieving safe and long-term neural interfaces.

[0027] Preferably, the gate dielectric layer is an alumina / hafnium oxide stacked material, and the thickness of the gate dielectric layer is 8nm~12nm.

[0028] Preferably, the metal layer is a Ti / Pt multilayer metal, wherein the thickness of Ti is 9nm~11nm and the thickness of Pt is 95nm~105nm. For example, the thickness of Ti can be 10nm and the thickness of Pt can be 100nm.

[0029] Preferably, the flexible substrate is made of Parylene C and has a thickness of 5 μm to 8 μm.

[0030] Based on the same inventive concept, embodiments of the present invention also provide a method for fabricating a capacitively coupled active neural electrode array for in-situ stimulation acquisition, comprising: Step 1: Obtain a silicon-on-insulator (SOI) epitaxial wafer and grow a layer of SiO2 on the epitaxial wafer as a mask; the SOI epitaxial wafer includes a bottom silicon layer, a SiO2 layer and a top silicon layer from bottom to top.

[0031] See Figure 3 For example, a 3cm×3cm P-type silicon-on-insulator epitaxial wafer is obtained, and a 200nm thick SiO2 layer is prepared on the epitaxial wafer as a mask by a thermal growth process.

[0032] Step 2: Divide the SiO2 mask into multiple regions arranged in a matrix, and etch four grooves in each region to expose the underlying top silicon layer.

[0033] Specifically, the SiO2 mask in each region is etched to form four spaced grooves in each region, exposing the underlying top silicon layer.

[0034] Step 3: Perform N-type ion implantation and annealing on the top silicon layer at the bottom of the groove to form an N-type doped region.

[0035] Specifically, exemplarily, phosphorus implantation is performed in the top silicon region (i.e., the groove) exposed in step two, with an implantation dose of 4 × 10¹. 5 cm - ², with an energy of 30 keV. Then, annealing at 950℃ for 30 minutes is performed to achieve annealing activation and form an N-type doped region, such as... Figure 4 As shown.

[0036] Optionally, the phosphorus doping concentration is 1. 10 18 / cm 3 ~1 10 22 / cm 3 .

[0037] Step 4: Remove the SiO2 mask, and then separate the top silicon layer from the SiO2 layer using a wet etching process to form a suspended silicon nanofilm.

[0038] In this step, the top layer of SiO2 mask is first removed. Then, an etched hole pattern is formed by photolithography; specifically, AZ6112 photoresist is used, and the etched hole pattern is formed on the top silicon surface through spin coating, drying, exposure, development, and hardening processes, as shown below. Figure 5As shown; the spin-coating parameters were: initial spin at 500 rpm for 10 seconds, followed by a subsequent spin at 4000 rpm for 30 seconds; drying conditions were 100°C for 120 seconds; exposure time was 1.8 seconds; development time was 32 seconds; and hardening conditions were 110°C for 5 minutes. Subsequently, reactive ion etching (RIE) was used to etch the top silicon layer to form etched holes. The etching process parameters were: gas composition of SF6 flow rate 15 sccm and He flow rate 150 sccm. Finally, the sample was placed in a 49% hydrofluoric acid solution and allowed to stand until the top silicon layer was suspended on the bottom silicon substrate by van der Waals forces, forming a silicon nanofilm, as shown. Figure 6 As shown, Figure 6 The NPN structure in it is a silicon nanofilm.

[0039] Optionally, the thickness of the silicon nanofilm is 200 nm to 300 nm.

[0040] Step 5: Transfer the silicon nanofilm onto a flexible substrate.

[0041] In this embodiment, a flexible substrate is fabricated on a temporary Si wafer. Specifically, AZ4620 photoresist is first spin-coated to form a 3μm thick sacrificial layer. Then, A174 is coated as an adhesive, and a 5μm thick Parylene C layer is grown as the flexible substrate. Subsequently, the suspended silicon nanofilm obtained in step four is separated from the underlying silicon substrate using a polydimethylsiloxane stamp and transferred to the adhesion layer (i.e., SU8) on the surface of the prepared flexible substrate.

[0042] Step 6: Etch silicon nanofilms to isolate the mesa in each region.

[0043] In this embodiment, a mesa isolation pattern is defined using photolithography. Specifically, firstly, using photoresist AZ6112, a mesa isolation pattern is formed on the surface of the silicon nanofilm through spin coating, drying, exposure, and development. The spin coating parameters are: first, a spin of 500 rpm for 10 seconds, followed by a spin of 4000 rpm for 30 seconds; drying conditions are: drying at 100°C for 120 seconds; exposure time is 1.8 seconds; and development time is 32 seconds. Then, the silicon nanofilm is etched using reactive ion etching (RIE) to achieve electrical isolation between the silicon nanofilms.

[0044] Step 7: Use atomic deposition technology to grow a gate dielectric on the surface of the current sample. Etch the gate dielectric directly above the four N-type doped regions in each region to form four grooves.

[0045] In this embodiment, an alumina-hafnium oxide stacked gate dielectric is grown on the surface of the current sample using atomic layer deposition (ALD). Then, via (i.e., groove) patterns are defined in the gate dielectric above the four N-type doped regions in each region using photolithography. Inductively coupled plasma reactive ion etching (ICP-IR) is then used to etch the gate dielectric using a mixture of Cl2 and BCl3 as the etching gas, forming one groove above each of the four N-type doped regions in each region. This groove serves as the source and drain grooves, respectively. Figure 7 As shown.

[0046] Step 8: Deposit a metal layer on the surface of the current sample using electron beam evaporation, with the deposition thickness exceeding the top of the groove.

[0047] Specifically, an electron beam evaporation process is used to deposit a metal layer on the surface of the current sample. The thickness of this metal layer is greater than the depth of the source and drain trenches etched in step seven.

[0048] For example, a Ti / Pt composite metal layer is formed by sequentially depositing a 10 nm thick Ti layer and a 100 nm thick Pt layer.

[0049] Step 9: Pattern the metal layer to form two sources, two drains, two gates, two metal pads, and metal interconnects in each region. In each region, one set of gates, sources, drains, and the underlying gate dielectric layer, silicon nanofilm, and flexible substrate forms a select transistor, and another set of gates, sources, drains, and the underlying gate dielectric layer, silicon nanofilm, and flexible substrate forms a drive transistor. The metal interconnects connect the gate of the select transistor to an external line select signal, connect the source of the select transistor to a metal pad, connect the drain of the select transistor to the gate of the drive transistor, connect the drain of the drive transistor to an electrical stimulation signal, and connect the source of the drive transistor to another metal pad.

[0050] Specifically, the metal layer deposited in step eight is patterned using a metal lift-off process to form the required metal electrodes, metal pads, and metal interconnects. The source and drain are located in the source and drain trenches obtained in step seven, respectively, while the gate is located on the gate dielectric layer between the drain and gate trenches, as shown below. Figure 8 As shown, Figure 8 The diagram shows a schematic of the fabricated flexible silicon nanofilm transistor (i.e., a select transistor, a drive transistor). It is understood that the metal interconnect also forms a line-select signal input line and an electrical stimulation signal input line, which are connected to an external circuit via metal ports to transmit the line-select signal and the electrical stimulation signal.

[0051] Step 10: Prepare a polymer film with both biocompatibility and dielectric properties on the surface of the current sample using solution casting method to form a capacitive coupling dielectric layer. The metal pads and the capacitive coupling dielectric layer together constitute electrode contacts, resulting in two electrode contacts for signal acquisition and electrical stimulation, respectively.

[0052] Preferably, the material of the capacitive coupling dielectric layer is MXene / Parylene C polymer, and the thickness of the capacitive coupling dielectric layer is 5μm~10μm; in the MXene / Parylene C polymer, the mass percentage of MXene is 1.0wt%~1.5wt%.

[0053] In this embodiment of the invention, the thickness of the capacitive coupling dielectric layer is 5 μm, and the mass percentage of MXene in the MXene / Parylene C polymer is 1.5 wt%.

[0054] Specifically, MXene / Parylene C polymer was prepared by solution casting and then spin-coated onto the surface of the current sample. The sample was then dried in an oven at 50°C for 2 hours to form a smooth MXene / Parylene C composite capacitor coupling dielectric layer.

[0055] Taking the preparation of an MXene / Parylene C polymer with an MXene mass ratio of 1.5 wt% as an example, the specific steps include: Place 100 ml of DMF solution in a beaker, and ultrasonically disperse approximately 1.5 g of MXene in the DMF solution for 30 minutes to obtain an MXene-DMF solution. Store the MXene-DMF solution in a 50°C constant temperature water bath. Under this constant temperature condition, add approximately 8 g of Parylene C white powder to the MXene-DMF solution in portions, stirring magnetically to achieve uniform dispersion. After all Parylene C has been added, continue stirring until the viscosity of the mixture increases. Then, reduce the stirrer speed and continue stirring until the mixture in the beaker becomes a gel-like solution without obvious particles or impurities. Place the gel-like solution on a clean bench for defoaming until the bubbles completely disappear, yielding the MXene / Parylene C polymer.

[0056] It should be noted that the relative permittivity of the MXene / Parylene C polymers in each doped system is significantly improved compared to pure Parylene C, and the higher the MXene content, the more significant the improvement in relative permittivity. This phenomenon can be effectively explained by diffusion theory. Specifically, when the MXene content is low, the filler content inside the composite material (i.e., the MXene / Parylene C polymer) has not yet reached the overperfusion limit of the system, and increasing the filler content allows the MXene materials to approach each other without contacting. At the abundant Parylene C-MXene interface, due to the obstruction and accumulation of charge carriers at the interface, the accumulation effect rapidly increases the permittivity of the composite material. However, when the MXene content exceeds a certain threshold, the connections between MXenes form conductive pathways, and therefore the improvement in permittivity no longer becomes significant.

[0057] After completing the above steps, the entire electrode array is separated from the temporary substrate Si wafer by laser cutting to obtain the final independent, implantable active neural electrode array.

[0058] This invention provides a capacitively coupled active neural electrode array with in-situ integrated acquisition and stimulation. The array uses a line-selection signal to control the conduction of a selection transistor, enabling the selection of the acquisition-stimulation site. When an abnormal neural electrical signal is acquired, it is directly conducted to the gate of a driving transistor via the selection transistor, causing the driving transistor to conduct and thus applying an electrical stimulation signal to the abnormal site. Based on this integrated design, this invention achieves simultaneous neural electrical signal acquisition and stimulation, avoiding the cumbersome process of using different devices for neural electrical signal acquisition and stimulation in traditional methods. This significantly improves the efficiency of experiments and treatments, reduces signal loss and interference during transmission, and thus obtains EEG signals with higher spatiotemporal resolution and signal-to-noise ratio.

[0059] Furthermore, this invention employs capacitive coupling for signal transmission, using a biocompatible MXene / Parylene C polymer as the capacitive coupling dielectric layer between the metal electrode and neural tissue. This composite structure combines the advantages of both materials: Parylene C provides excellent chemical inertness, biocompatibility, and pinhole-free, dense protective properties, effectively preventing fluid penetration and ensuring stable operation of internal electronic devices in long-term implantation environments; MXene, as a two-dimensional conductive material, significantly enhances the dielectric response of the composite medium. The combination of these two materials gives the capacitive coupling dielectric layer both good signal coupling efficiency and excellent biocompatibility, fundamentally avoiding the DC leakage current problem of traditional resistive contact electrodes, eliminating the risks of electrochemical corrosion and tissue damage, and laying the material foundation for safe and long-term neural interfaces.

[0060] In the description of this invention, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0061] In the description of this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0062] In the description of this invention, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0063] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.

[0064] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0065] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0066] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A capacitively coupled active neural electrode array for in-situ stimulation acquisition, characterized in that, include: A flexible substrate and multiple neural electrode units formed on the flexible substrate; The multiple neural electrode units are arranged in a matrix; The neural electrode unit comprises: two silicon nanofilms, a gate dielectric layer, a metal layer, and a capacitive coupling dielectric layer; Two silicon nanofilms are located on the flexible substrate, and two N-type doped regions are provided on the silicon nanofilms; the gate dielectric layer covers the silicon nanofilms and forms a groove on each N-type doped region; The metal layer includes: electrode metal, metal pads, and metal interconnects; the electrode metal, in conjunction with two silicon nanofilms, a gate dielectric layer, and a flexible substrate, forms a select transistor and a drive transistor; the metal pads, in conjunction with the capacitive coupling dielectric layer, form electrode contacts; the metal interconnects are used to electrically connect the select transistor, the drive transistor, and the electrode contacts; wherein, the gate of the select transistor is connected to an external line select signal, the source of the select transistor is connected to one electrode contact, the drain of the select transistor is connected to the gate of the drive transistor, the drain of the drive transistor is connected to an electrical stimulation signal, and the source of the drive transistor is connected to another electrode contact; the gate, source, and drain are all formed by the electrode metal.

2. The capacitively coupled active neural electrode array for in-situ stimulation acquisition as described in claim 1, characterized in that, The silicon nanofilm is doped with phosphorus at a concentration of 1. 10 18 / cm 3 ~1 10 22 / cm 3 The thickness of the silicon nanofilm is 200nm~300nm.

3. The capacitively coupled active neural electrode array for in-situ stimulation acquisition as described in claim 1, characterized in that, The material of the capacitive coupling dielectric layer is MXene / Parylene C polymer, and the thickness of the capacitive coupling dielectric layer is 5μm~10μm; in the MXene / Parylene C polymer, the mass percentage of MXene is 1.0wt%~1.5wt%.

4. The capacitively coupled active neural electrode array for in-situ acquisition of stimuli as described in claim 3, characterized in that, The MXene / Parylene C polymer was prepared by solution casting, including the following steps: MXene was ultrasonically dispersed into a DMF solution to form an MXene-DMF solution; Under constant temperature and stirring conditions, Parylene C was added to the MXene-DMF solution in portions, and stirring was continued until a uniform gel-like sol was formed. The gel-like sol was allowed to stand and defoam to obtain the MXene / Parylene C polymer.

5. The capacitively coupled active neural electrode array for in-situ acquisition of stimuli according to claim 1, characterized in that, The gate dielectric layer is an alumina / hafnium oxide stacked material, and the thickness of the gate dielectric layer is 8nm~12nm.

6. The capacitively coupled active neural electrode array for in-situ stimulation acquisition as described in claim 1, characterized in that, The metal layer is made of Ti / Pt multilayer metal, wherein the thickness of Ti is 9nm~11nm and the thickness of Pt is 95nm~105nm.

7. The capacitively coupled active neural electrode array for in-situ acquisition of stimuli according to claim 1, characterized in that, The flexible substrate is made of Parylene C and has a thickness of 5 μm to 8 μm.

8. A method for fabricating a capacitively coupled active neural electrode array for in-situ stimulation acquisition, characterized in that, The method for fabricating the capacitively coupled active neural electrode array for in-situ integration of stimuli as described in any one of claims 1 to 7 comprises: Step 1: Obtain a silicon-on-insulator (SiO2) epitaxial wafer, and grow a SiO2 layer on the epitaxial wafer as a mask; the SiO2 epitaxial wafer includes a bottom silicon layer, a SiO2 layer, and a top silicon layer from bottom to top; Step 2: Divide the SiO2 mask into multiple regions arranged in a matrix, and etch 4 grooves in each region to expose the underlying top silicon layer; Step 3: Perform N-type ion implantation and annealing on the top silicon layer at the bottom of the groove to form an N-type doped region; Step 4: Remove the SiO2 mask; separate the top silicon layer from the SiO2 layer using a wet etching process to form a suspended silicon nanofilm; Step 5: Transfer the silicon nanofilm onto a flexible substrate; Step 6: Etch the silicon nanofilm to isolate the mesa in each of the regions; Step 7: Use atomic deposition technology to grow a gate dielectric on the surface of the current sample, and etch the gate dielectric directly above the four N-type doped regions in each region to form four grooves; Step 8: Deposit a metal layer on the surface of the current sample using electron beam evaporation, with the deposition thickness exceeding the top of the groove; Step 9: Pattern the metal layer to form two sources, two drains, two gates, two metal pads, and metal interconnects in each region; wherein, in each region, one set of gates, sources, drains, and the underlying gate dielectric layer, silicon nanofilm, and flexible substrate forms a select transistor, and another set of gates, sources, drains, and the underlying gate dielectric layer, silicon nanofilm, and flexible substrate forms a drive transistor. The metal interconnects connect the gate of the select transistor to an external line select signal, connect the source of the select transistor to a metal pad, connect the drain of the select transistor to the gate of the drive transistor, connect the drain of the drive transistor to an electrical stimulation signal, and connect the source of the drive transistor to another metal pad. Step 10: Prepare a polymer film with both biocompatibility and dielectric properties on the surface of the current sample using solution casting method to form a capacitive coupling dielectric layer. The metal pads and the capacitive coupling dielectric layer together constitute electrode contacts, resulting in two electrode contacts for signal acquisition and electrical stimulation, respectively.

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