A method for preparing a dielectric layer of a field effect transistor device and a method for preparing a field effect transistor device using the same

Abstract

The application belongs to the technical field of field effect transistor devices, and discloses a preparation method of a dielectric layer of a field effect transistor device and a method for preparing a field effect transistor device by using the same. The preparation method of the dielectric layer of the field effect transistor device is as follows: stripping hafnium sulfide to obtain a thin layer of hafnium sulfide; then transferring the thin layer of hafnium sulfide to a polydimethylsiloxane stamp, and performing thermal oxidation treatment to obtain a hafnium oxide dielectric layer. The dielectric layer of the field effect transistor device prepared by the application has the characteristics of no wrinkle on the surface, uniform distribution and atomic-level flatness, is a high-k dielectric layer with good natural oxide contact, is used as a high-k dielectric layer, and can significantly improve the subthreshold swing and other performances of the field effect transistor device. The structure of the field effect transistor device prepared by the application is simple, the performance is excellent, and the preparation method is simple.

Description

Technical Field

[0001] This invention belongs to the field of field-effect transistor device technology, specifically relating to a method for preparing a dielectric layer of a field-effect transistor device and a method for preparing a field-effect transistor device using the dielectric layer. Background Technology

[0002] The history of electronics is generally comprised of three main electronic devices: vacuum tubes, bipolar junction transistors (BJTs), and metal-oxide-semiconductor field-effect crystals (MOSFETs). While the first two played crucial roles in advancing modern computing, it was the MOSFET, and particularly the rise of complementary metal-oxide-semiconductor (CMOS) technology, that truly propelled the explosive growth of information technology over the past 60 years. CMOS has been a powerful engine of contemporary technological advancement. For very large-scale integrated circuit (VLSI) applications, the most attractive advantage of MOSFETs is that their ever-shrinking physical size has driven improvements in every key metric—cost, performance, power consumption, etc.—towards efficiency. Furthermore, the field-effect nature of CMOS and its complementary circuit topology (comprising n-type and p-type MOSFETs) results in ultra-low leakage power, making them highly advantageous in low-power applications. Therefore, after the early major bottleneck, the silicon (Si) / silicon dioxide (SiO2) interface (defect) problem, was solved, complementary metal-oxide-semiconductor (CMOS) technology rapidly replaced bipolar transistors in the growing digital market, paving the way for the information technology era based on very large-scale integrated circuits (VLSI).

[0003] A typical metal-oxide-semiconductor field-effect crystal (MOSFET) functions similarly to a regular faucet. In a faucet, the flow of water is controlled by a mechanical knob; similarly, in a MOSFET, charge carriers (electrons or holes) are controlled to move from the source to the drain via a "field-effect" or capacitively coupled gate. From a semiconductor energy band perspective, gate bias is used to modulate the energy band of the channel below the gate. The performance of a MOSFET is typically assessed by data such as on / off ratio and subthreshold swing. At room temperature (T = 300 K), the MOSFET's subthreshold swing satisfies:

[0004]

[0005] Where V G I is the gate voltage. D Drain current, Let be the surface potential, k be the relative permittivity, T be the temperature, q be the charge, and C be the capacitance.ox For dielectric layer capacitance, C D This is the drain capacitance.

[0006] Therefore, the theoretical minimum value is:

[0007] log(10)·kT / q=59.6mV / dec≈60mV / dec

[0008] In a FET device, the closer the measured subthreshold swing is to 60 mV / dec, the stronger the gate's control over the channel, and vice versa. Therefore, by selecting a high-k dielectric layer, the device's subthreshold swing can be reduced, improving its performance. Currently, the mainstream dielectric layer is a nanoscale hafnium oxide (HfO2) thin film obtained by atomic layer deposition (ALD). However, hafnium oxide films obtained by ALD have atomic defects, surface flatness cannot be guaranteed, and there are contact problems between the dielectric layer and the two-dimensional material. Therefore, the dielectric layer of FET devices prepared by ALD theoretically has more room for performance optimization. Moreover, the process of preparing hafnium oxide by ALD is very cumbersome, and the experiment cannot be carried out in an experimental environment without ALD equipment. Therefore, a simple, economical, and effective method to obtain high-quality hafnium oxide as the dielectric layer of field-effect transistor devices is needed. Summary of the Invention

[0009] The present invention aims to at least solve one of the technical problems existing in the prior art. To this end, the present invention proposes a method for fabricating a dielectric layer for a field-effect transistor (FET) device and a method for fabricating FET devices using the dielectric layer. The fabrication method provided by the present invention can easily, economically, and effectively obtain a high-quality hafnium oxide dielectric layer, and the FET devices fabricated using it exhibit excellent performance, with a significant reduction in subthreshold swing.

[0010] This invention provides a method for fabricating the dielectric layer of a field-effect transistor device.

[0011] Specifically, a method for fabricating a dielectric layer of a field-effect transistor device includes the following steps:

[0012] Hafnium sulfide is stripped to obtain a thin layer of hafnium sulfide; then the thin layer of hafnium sulfide is transferred onto a polydimethylsiloxane (PMDS) stamp and subjected to thermal oxidation to obtain a hafnium oxide dielectric layer, which is the dielectric layer of a field-effect transistor device.

[0013] Preferably, the peeling method is mechanical peeling. For example, using blue adhesive tape to peel off hafnium sulfide (HfS2) using a mechanical peeling method.

[0014] Preferably, the thickness of the thin hafnium sulfide layer is 20–30 nm.

[0015] Preferably, the temperature of the thermal oxidation treatment is 130–170°C, and the time of the thermal oxidation treatment is 1.5–3.0 h. More preferably, the temperature of the thermal oxidation treatment is 140–160°C, and the time of the thermal oxidation treatment is 2–2.5 h.

[0016] Preferably, before the thermal oxidation treatment step, a cleaning and cutting step is included. The cleaning process involves removing unevenly thick hafnium sulfide from the polydimethylsiloxane stamp, except for the thin layer of hafnium sulfide. The cutting process involves cutting the polydimethylsiloxane stamp with the thin layer of hafnium sulfide attached to it to the target size.

[0017] The present invention also provides a method for fabricating a field-effect transistor device.

[0018] A method for fabricating a field-effect transistor device includes the following steps:

[0019] Hafnium sulfide is peeled off to obtain a thin layer of hafnium sulfide; then the thin layer of hafnium sulfide is transferred onto a polydimethylsiloxane stamp and subjected to thermal oxidation treatment to obtain a hafnium oxide dielectric layer.

[0020] The hafnium oxide dielectric layer is transferred onto a carbon nanotube substrate, and then a transistor channel is fabricated; the source electrode, drain electrode, and gate electrode are then fabricated to obtain a field-effect transistor device.

[0021] The hafnium oxide dielectric layer includes a hafnium sulfide layer and a hafnium oxide layer; the carbon nanotube substrate includes a carbon nanotube layer, and during the transfer process, the hafnium oxide layer in the hafnium oxide dielectric layer is disposed on the carbon nanotube layer.

[0022] Preferably, the carbon nanotube substrate comprises a silicon layer, a silicon dioxide layer, and a carbon nanotube layer (CNT) in sequence.

[0023] Preferably, the thickness of the silicon dioxide layer is 200–400 nm.

[0024] Preferably, the fabrication process of the source electrode and the drain electrode is as follows: using photoresist, patterning processing of laser direct writing lithography technology and electron beam evaporation, the source electrode and the drain electrode are fabricated at the left and right ends of the carbon nanotube substrate.

[0025] Preferably, the source electrode and the drain electrode are Pd.

[0026] Preferably, the gate is fabricated as follows: using photoresist, patterning is performed by laser direct writing technology and electron beam evaporation to fabricate the gate on the hafnium sulfide layer of the hafnium oxide dielectric layer.

[0027] Preferably, the gate is Ti or Au.

[0028] This invention addresses the issues of inhomogeneity and contact problems between the hafnium oxide dielectric layer and the two-dimensional material encountered in atomic layer deposition (ALD) methods for preparing hafnium oxide dielectric layers. It utilizes a high-k dielectric gate MOS structure formed by the oxidation of hafnium sulfide surface to form a hafnium sulfide-hafnium oxide (HfS2-HfO2) layer. This results in a densely connected, atomically flat hafnium oxide layer used as the dielectric layer for carbon nanotube-field-effect transistor (FET) devices, significantly resolving the contact problem. The FET devices prepared by this invention exhibit excellent performance, with a significantly reduced subthreshold swing of up to 73 mV / dec, and the on-off state also meets the requirements of high-performance FETs, reaching 10. 6 .

[0029] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0030] (1) The hafnium oxide dielectric layer (i.e., the dielectric layer of field-effect transistor device) prepared by the present invention has no wrinkles on its surface, is uniformly distributed, and has the characteristics of atomic-level flatness. It is a high-k dielectric layer with good contact with natural oxides. When used as a high-k dielectric layer, it can significantly improve the performance of field-effect transistor devices such as subthreshold swing.

[0031] (2) The present invention can prepare a high-quality hafnium oxide dielectric layer (i.e., the dielectric layer of a field-effect transistor device) simply by thermal oxidation, without the need for atomic layer deposition equipment. This ensures both economic efficiency and significant results, effectively reducing the preparation cost. At the same time, the prepared field-effect transistor device has a simple structure and a simple fabrication method. Attached Figure Description

[0032] Figure 1 This is a surface morphology diagram of hafnium sulfide;

[0033] Figure 2 This is a schematic planar view of the field-effect transistor device prepared in Example 1;

[0034] Figure 3 This is a flowchart illustrating the fabrication process of the field-effect transistor device prepared in Example 1.

[0035] Figure 4 A TEM image of the cross-section of the dielectric layer of the field-effect transistor device prepared in Example 1;

[0036] Figure 5 The transfer characteristic curve of the field-effect transistor device prepared in Example 1;

[0037] Figure 6 A photoluminescent view of the field-effect transistor prepared in Example 1;

[0038] Figure 7 The transfer characteristic curve of the field-effect transistor device prepared in Example 2;

[0039] Figure 8 This is a photoluminescent view of the field-effect transistor device prepared in Example 2;

[0040] Figure 9 The transfer characteristic curves of the field-effect transistor device prepared for Comparative Example 1 are shown.

[0041] Explanation of icon numbers:

[0042] Thin hafnium sulfide layer -100, hafnium oxide layer -200, carbon nanotube substrate -300, carbon nanotube layer (CNT) -310, silicon dioxide layer -320, silicon layer -330, drain electrode -400, source electrode -500, gate electrode -600. Detailed Implementation

[0043] To enable those skilled in the art to more clearly understand the technical solutions described in this invention, the following embodiments are provided for illustration. It should be noted that the following embodiments do not constitute a limitation on the scope of protection claimed by this invention.

[0044] Unless otherwise specified, the raw materials, reagents or apparatus used in the following examples and comparative examples are available from conventional commercial sources or can be obtained by existing known methods.

[0045] This invention provides a method for preparing a dielectric layer for a field-effect transistor device, comprising the following steps: peeling off hafnium sulfide to obtain a thin layer of hafnium sulfide; then transferring the thin layer of hafnium sulfide onto a polydimethylsiloxane (PMDS) stamp and performing thermal oxidation treatment to obtain a hafnium oxide dielectric layer.

[0046] In some embodiments of the present invention, hafnium sulfide is peeled off using a mechanical method. For example, hafnium sulfide (HfS2) is peeled off using a blue adhesive tape, and then transferred to a polydimethylsiloxane (PMDS) stamp. Hafnium sulfide is a two-dimensional transition metal sulfide, possessing the nanoscale thin-layer characteristics of two-dimensional materials and excellent light transmittance. Scanning the surface morphology of hafnium sulfide using an atomic force microscope (AFM) reveals that the sample surface roughness is extremely low (e.g., ...). Figure 1 As shown in the figure, since hafnium sulfide is obtained by mechanical stripping, the thin hafnium sulfide layers obtained by this method can maintain high surface flatness.

[0047] In some embodiments of the present invention, the thickness of the thin hafnium sulfide layer obtained after peeling is 20–30 nm. By controlling the thickness of the thin hafnium sulfide layer and the temperature and time of the thermal oxidation treatment, a dielectric layer for field-effect transistor devices with excellent performance can be prepared.

[0048] Furthermore, during the transfer process, a large-area thin-layer polydimethylsiloxane (PMDS) stamp can be adhered to a slightly larger glass slide, depending on the requirements. The large-area thin-layer polydimethylsiloxane stamp makes it easier to obtain a large area of ​​thin-layer hafnium sulfide, while the glass slide, which is slightly larger than the polydimethylsiloxane stamp, can ensure that the stress generated during the peeling process of the polydimethylsiloxane stamp does not affect the material. This minimizes damage to the thin-layer material during material transfer and can significantly reduce wrinkles in the sample material.

[0049] In some embodiments of the present invention, a cleaning and cutting step is included before the thermal oxidation treatment step. The cleaning process involves removing the unevenly thick hafnium sulfide from the polydimethylsiloxane stamp, excluding the thin hafnium sulfide layer. The cutting process involves cutting the polydimethylsiloxane stamp with the attached thin hafnium sulfide layer to the target size. More specifically, after obtaining the hafnium sulfide on a large-area thin-layer polydimethylsiloxane stamp, a polydimethylsiloxane-assisted transfer method is used. A microscopic system and transfer stage are employed to clean the unevenly thick HfS2 from the large-area thin-layer polydimethylsiloxane stamp, excluding the thin hafnium sulfide layer. Because the thin-layer polydimethylsiloxane stamp has strong adhesion and is extremely thin, cleaning other unevenly thick materials can prevent air bubbles caused by excessively thick material from interfering with the subsequent transfer process. After cleaning, use a blade to cut the large-area thin-layer polydimethylsiloxane stamp into a smaller size, leaving only the target thin-layer hafnium sulfide area. This prevents excessive adhesion between the carbon nanotube (CNT) sample substrate and the polydimethylsiloxane stamp, which could prevent the polydimethylsiloxane stamp from being lifted during transfer.

[0050] In some embodiments of the present invention, the temperature of the thermal oxidation treatment is 130–170°C, and the treatment time is 1.5–3.0 h. Further, the temperature of the thermal oxidation treatment is 140–160°C, and the treatment time is 2–2.5 h. The obtained sample is placed on a heating table in a cleanroom for thermal oxidation treatment. By controlling the stable thermal oxidation temperature and time, a controllable hafnium oxide layer (dielectric layer) can be obtained. Further, to obtain a more perfect hafnium oxide dielectric layer, HfS2 with a thickness of approximately 20–30 nm is selected, and thermal oxidation is performed for 2–2.5 h. If the oxidation time is too short, the hafnium oxide dielectric layer formed by thermal oxidation will be too thin, which will reduce its breakdown voltage and affect the capacitance characteristics of the field-effect transistor (FET). If the oxidation time is too long, the hafnium oxide dielectric layer will be too thick, which will weaken the gate's control over the channel electric field, reduce the influence of the gate voltage on the charge carriers in the channel, and thus affect the switching speed and performance of the FET. Therefore, the thickness of the hafnium oxide dielectric layer is crucial.

[0051] This invention also provides a method for fabricating a field-effect transistor device, comprising the following steps:

[0052] Hafnium sulfide was stripped to obtain a thin layer of hafnium sulfide; then the thin layer of hafnium sulfide was transferred onto a polydimethylsiloxane stamp and subjected to thermal oxidation to obtain a hafnium oxide dielectric layer.

[0053] A hafnium oxide dielectric layer was transferred onto a carbon nanotube substrate, and then a transistor channel was fabricated; the source electrode, drain electrode, and gate electrode were then fabricated to obtain a field-effect transistor device.

[0054] The hafnium oxide dielectric layer includes a hafnium sulfide layer and a hafnium oxide layer; the carbon nanotube substrate includes a carbon nanotube layer, and during the transfer process, the hafnium oxide layer in the hafnium oxide dielectric layer is disposed on the carbon nanotube layer.

[0055] In some embodiments of the present invention, the carbon nanotube substrate comprises a silicon layer, a silicon dioxide layer and a carbon nanotube layer in sequence.

[0056] In some embodiments of the present invention, the thickness of the silicon dioxide layer is 200–400 nm, such as 300 nm.

[0057] In some embodiments of the present invention, the source electrode and drain electrode are fabricated as follows: using photoresist, patterning processing of laser direct writing lithography technology and electron beam evaporation, the source electrode and drain electrode are fabricated at the left and right ends of the carbon nanotube substrate.

[0058] In some embodiments of the present invention, the source electrode and the drain electrode are Pd.

[0059] In some embodiments of the present invention, the gate fabrication process is as follows: using photoresist (such as photoresist AZ5214), the gate is fabricated on the hafnium sulfide layer of the hafnium oxide dielectric layer by patterning processing of laser direct writing technology and electron beam evaporation.

[0060] In some embodiments of the present invention, the gate is Ti or Au.

[0061] Example 1

[0062] A dielectric layer for a field-effect transistor (FET) and a method for fabricating the FET are disclosed. A flowchart of the FET fabrication process is shown below. Figure 3 As shown, it includes the following steps:

[0063] (1) Hafnium sulfide was peeled off using a mechanical peeling method to obtain a thin layer of hafnium sulfide. Then, the thin layer of hafnium sulfide was transferred onto a polydimethylsiloxane stamp to obtain a large area of ​​hafnium sulfide on the polydimethylsiloxane stamp. Then, a polydimethylsiloxane-assisted transfer method was used to clean the uneven thickness of HfS2 on the large area of ​​the polydimethylsiloxane stamp, except for the thin layer of hafnium sulfide, using a microscopic system and a transfer stage. After cleaning, the polydimethylsiloxane stamp was cut into small pieces using a blade to retain only the area of ​​the target thin layer of hafnium sulfide, to avoid excessive adhesion between the carbon nanotube substrate and the polydimethylsiloxane stamp, which would prevent the polydimethylsiloxane stamp from being lifted during the subsequent transfer. After cleaning and cutting, the larger glass slide bearing the dimethylsiloxane stamp is placed on a heating table in the cleanroom for thermal oxidation treatment. The heating temperature is set to 150°C and the thermal oxidation treatment is carried out for 2 hours to obtain a hafnium oxide dielectric layer (i.e., the dielectric layer of a field-effect transistor device). The obtained hafnium oxide dielectric layer includes a hafnium sulfide layer and a hafnium oxide layer. In this structure, the hafnium oxide is obtained by oxidizing the hafnium sulfide layers in a sandwich structure.

[0064] (2) Take a carbon nanotube substrate, which consists of a silicon layer (525 micrometers thick), a silicon dioxide layer (300 nm thick), and a carbon nanotube layer (2-3 nm thick). Use a transfer stage to transfer the hafnium oxide dielectric layer onto the carbon nanotube substrate, so that the hafnium oxide layer in the hafnium oxide dielectric layer is disposed on the carbon nanotube layer.

[0065] (3) The transistor channel was fabricated using plasma surface treatment. Then, using AZ5214 photoresist, palladium electrodes were fabricated at both ends of the carbon nanotube substrate using laser direct-write lithography for patterning and electron beam evaporation (e-beam), serving as the source and drain electrodes. Annealing and cleaning were then performed. Finally, using photolithography nesting technology, the gate electrode was patterned using AZ5214 photoresist via laser direct-write lithography. Then, titanium gate electrodes were deposited within the gate pattern using electron beam evaporation to obtain the field-effect transistor device. A schematic diagram of the field-effect transistor device is shown below. Figure 2 A full optical display image of the field-effect transistor device is shown below. Figure 6 .

[0066] Focused ion beam microscopy (FIB) was used to micro-cut hafnium oxide dielectric layers (i.e., the dielectric layers of field-effect transistor devices). FIB is a micro-cutting instrument that uses an electric lens to focus an ion beam into a very small size. It typically uses an ion beam generated by a liquid metal (such as gallium) ion source, which is accelerated and focused by an ion gun before illuminating the sample surface. After obtaining the cross-section, the sample is characterized using transmission electron microscopy (TEM). TEM uses an accelerated and focused electron beam as the illumination source. When the electron beam is projected onto a very thin sample, the electrons collide with atoms in the sample and change direction, resulting in solid-angle scattering. The size of the scattering angle is related to the sample's density and thickness, thus forming images of varying brightness. These images are magnified and focused, and finally displayed on an imaging device. In the semiconductor industry, TEM is widely used to observe and analyze the microstructure and composition of semiconductor materials. The test results are as follows: Figure 4 As shown, the entire sample is clearly divided into two layers. The upper layer is standard hafnium sulfide with a lattice spacing of 0.59–0.61 nm. The lower layer exhibits a distinct color difference from the upper layer, and its lattice spacing is 0.53–0.54 nm, displaying lattice characteristics different from hafnium sulfide, thus confirming it as hafnium oxide. The hafnium oxide formed by thermal oxidation shows clear layering, a wrinkle-free, uniformly distributed surface, and atomically smooth characteristics. This invention obtains a high-k dielectric layer with good contact with the natural oxide through thermal oxidation, which can be used as a high-k dielectric layer in FET devices to improve performance such as subthreshold swing.

[0067] The transfer characteristic curves of the field-effect transistor device obtained using the 4200 electrical test platform are as follows: Figure 5 As shown. By Figure 5 It can be seen that the subthreshold swing of the field-effect transistor device prepared by thermal oxidation for 2 hours in this embodiment is 94mV / dec.

[0068] Example 2

[0069] The difference between Example 2 and Example 1 is that in Example 2, the thermal oxidation treatment time for the dielectric layer of the field-effect transistor device is 2.5 hours, while the rest of the preparation process is the same as in Example 1. A full-view optical image of the field-effect transistor device prepared in Example 2 is shown below. Figure 8 As shown.

[0070] The transfer characteristic curves of the field-effect transistor device obtained using the 4200 electrical test platform are as follows: Figure 7 As shown. By Figure 7 It can be seen that the subthreshold swing of the field-effect transistor device prepared by thermal oxidation for 2.5 hours in this embodiment is 73 mV / dec.

[0071] Comparative Example 1

[0072] The difference between Comparative Example 1 and Example 1 is that the thermal oxidation treatment time of Comparative Example 1 in preparing the dielectric layer of the field-effect transistor device is 1 hour, while the rest of the preparation process is the same as in Example 1.

[0073] The transfer characteristic curves of the field-effect transistor device obtained using the 4200 electrical test platform are as follows: Figure 9 As shown. By Figure 9 It can be seen that the subthreshold swing of the field-effect transistor device prepared by thermal oxidation for 1 hour in this comparative example is 347mV / dec.

[0074] In the fabrication of hafnium oxide dielectric layers (i.e., dielectric layers of field-effect transistor devices), if the oxidation time is too short, the resulting hafnium oxide dielectric layer will be too thin, leading to a low breakdown voltage and uneven hafnium oxide distribution. During thermal oxidation, the surface hafnium sulfide reacts with O2 in the air, gradually oxidizing to a hafnium sulfide-hafnium oxide structure. Depending on the oxidation time, the subthreshold swing exhibited by the device varies. Comparing Examples 1 and 2 with Comparative Example 1, the subthreshold swings of devices thermally oxidized for 2–2.5 hours are 94 mV / dec and 73 mV / dec, respectively, significantly better than the 347 mV / dec subthreshold swing of the device thermally oxidized for 1 hour. The different oxidation times result in varying thicknesses of the hafnium oxide dielectric layer, which in turn affects the gate capacitance. Miniaturized devices require higher gate capacitance to improve device performance and reduce power consumption.

[0075] In summary, the field-effect transistor devices fabricated in the embodiments of the present invention exhibit excellent subthreshold swing and 10 6 The high on-off state is due to the fact that hafnium oxide in the hafnium oxide dielectric layer obtained by thermal oxidation is a two-dimensional semiconductor of insulating natural oxide, which is crucial for further simplifying the manufacturing process and achieving good interface quality. It ensures excellent contact of the dielectric layer, that is, the natural insulating oxide layer obtained by thermal oxidation, avoiding damage to transistor performance caused by voids or atomic defects in the dielectric layer contact.

[0076] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method of fabricating a field effect transistor device, characterized by, The method comprises the following steps: peeling off hafnium sulfide to obtain a thin layer of hafnium sulfide; then transferring the thin layer of hafnium sulfide to a polydimethylsiloxane stamp, and performing thermal oxidation treatment to obtain a hafnium oxide dielectric layer; transferring the hafnium oxide dielectric layer to a carbon nanotube substrate, and then making a transistor channel; further making a source electrode, a drain electrode and a gate electrode to obtain a field effect transistor device; the hafnium oxide dielectric layer comprises a hafnium sulfide layer and a hafnium oxide layer; the carbon nanotube substrate comprises a silicon layer, a silicon dioxide layer and a carbon nanotube layer in sequence, and the hafnium oxide layer in the hafnium oxide dielectric layer is arranged on the carbon nanotube layer during the transferring process; the thermal oxidation treatment is performed at a temperature of 140-160℃ for 2.0-2.5h.

2. The method of claim 1, wherein the method further comprises: the thickness of the thin layer of hafnium sulfide is 20-30nm.

3. The method of claim 1, wherein the method further comprises: the thickness of the silicon dioxide layer is 200-400nm.

4. The method of claim 1, 2 or 3, wherein the source electrode and the drain electrode are made by using a photoresist, a patterning process of a laser direct writing lithography technology and an electron beam evaporation method to make the source electrode and the drain electrode on the left and right ends of the carbon nanotube substrate.

5. The method of claim 4, wherein the step of forming the gate electrode is performed by forming a gate electrode comprising a metal oxide semiconductor. the source electrode and the drain electrode are Pd.

6. The method of claim 1, 2, or 3, wherein the method further comprises: the gate electrode is made by using a photoresist, a patterning process of a laser direct writing technology and an electron beam evaporation method to make the gate electrode on the hafnium sulfide layer of the hafnium oxide dielectric layer.

7. The method of claim 6, wherein the method further comprises: the gate electrode is Ti or Au.

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