A double-gate junction field effect transistor and a method for manufacturing the same

Abstract

The application relates to a high-performance double-gate junction field effect transistor and a preparation method thereof, which comprises a double P-N junction composed of two-dimensional Te and two-dimensional MoS2 in a preferred embodiment, and is composed of a three-layer structure, the upper and lower layers are two-dimensional MoS2 layers, and the middle layer is a two-dimensional Te layer; the layers are in a cross structure, and the electrodes shared by the MoS2 layers are used as the gate; the Te layer is used as a carrier channel layer, and the two electrodes are used as the source and the drain. The device structure realizes the opening and closing of the JFET by regulating the positive and negative bias of the P-N junction and the width of the depletion region of the Te channel layer. Since the structure does not have a dielectric layer, an ideal subthreshold swing is realized, and the carrier concentration of the two-dimensional Te is high, so that a large current response can be realized under a small source-drain voltage. The JFET designed in the application has a small subthreshold swing and a large on-state current, and is crucial for devices requiring low power consumption and large current design.

Description

Technical Field

[0001] This invention relates to the field of microelectronic devices, specifically a dual-gate junction field-effect transistor (JFET) and its fabrication method. Background Technology

[0002] Low power consumption is crucial for future mobile and IoT devices. To further reduce power consumption or supply voltage V... DD Subthreshold swing current (SS) should be optimized to avoid high leakage current while reducing device size. For traditional metal-oxide-semiconductor field-effect transistors (MOSFETs), significant efforts have been made in past dielectric engineering to maintain gate controllability, i.e., achieving low SS, including high-dielectric-constant oxides, ferroelectric materials, or negative-capacitance dielectrics. However, engineered dielectrics are often plagued by inhomogeneous dielectric surfaces, which trap charge and cause ferromagnetic hysteresis, thus degrading charge transport. JFETs operate by altering the depletion region in a channel with a reverse-biased pn junction, thus eliminating the dielectric or related challenges.

[0003] Recent research on two-dimensional materials has revealed the superior electronic properties of various two-dimensional semiconductors. Two-dimensional semiconductors are particularly attractive for JFETs because ultrathin two-dimensional bodies can reduce source channel capacitance to minimize channel resistance (SS) and lower the turn-on voltage V, which is proportional to the channel thickness. P Therefore, the dangling-bond-free van der Waals interface formed by two different two-dimensional semiconductors in this invention may have a trapping interface, thereby ensuring near-ideal junction characteristics. Summary of the Invention

[0004] The primary objective of this invention is to provide a dual-gate junction field-effect transistor and its fabrication method. This invention utilizes a two-dimensional material Te (P-type material) layer and a two-dimensional material MoS2 (N-type material) layer to form a heterogeneous PN structure to build a dual-gate junction field-effect transistor. The obtained JFET has advantages such as large current response, excellent photoelectric performance, and low subthreshold swing.

[0005] To achieve the above objectives, the present invention provides at least the following technical solutions:

[0006] A dual-gate field-effect transistor includes a substrate and a heterojunction disposed on the substrate. The heterojunction is composed of a first two-dimensional material layer of a first semiconductor type, a second two-dimensional material layer of a second semiconductor type, and a third two-dimensional material layer of a first semiconductor type, which are stacked sequentially. The first two-dimensional material layer and the third two-dimensional material layer are respectively arranged in a cross structure with the second two-dimensional material layer. The first two-dimensional material layer and the third two-dimensional material layer have opposing first ends and second ends. A first electrode is disposed between their first ends, and a second electrode is disposed between their second ends. The first electrode and the second electrode do not contact each other. The second two-dimensional material layer has opposing first ends and second ends. A third electrode is disposed at the first end, and a fourth electrode is disposed at the second end.

[0007] The first two-dimensional material layer and / or the third two-dimensional material layer are selected as two-dimensional material MoS2 layers, and the second two-dimensional material layer is selected as two-dimensional material Te layers; or the first two-dimensional material layer and / or the third two-dimensional material layer are selected as two-dimensional material Te layers, and the second two-dimensional material layer is selected as two-dimensional material MoS2 layers.

[0008] Furthermore, the thickness of the two-dimensional material Te layer is 50-100 nm, and the thickness of the two-dimensional material MoS2 layer is 50-100 nm.

[0009] Furthermore, the first electrode is a first gate electrode, the second electrode is a second gate electrode, the third electrode is a source electrode, and the fourth electrode is a drain electrode.

[0010] Furthermore, the electrode is an Au electrode layer with a thickness of 20–80 nm.

[0011] Furthermore, the substrate is a silicon substrate, and an insulating layer is disposed on the surface of the silicon substrate, the thickness of the insulating layer being 100–500 nm.

[0012] Another aspect of the present invention provides a method for fabricating a dual-gate junction field-effect transistor, comprising the following steps:

[0013] A first electrode, a second electrode, a third electrode, and a fourth electrode are formed on a substrate, wherein the first electrode and the second electrode are disposed opposite to each other, and the third electrode and the fourth electrode are disposed opposite to each other.

[0014] A first two-dimensional material layer of a first semiconductor type, connected to the first electrode and the second electrode, is transferred between the first electrode and the second electrode;

[0015] A second two-dimensional material layer of a second semiconductor type is transferred onto the third and fourth electrodes;

[0016] A third two-dimensional material layer of a first semiconductor type, connected to the first electrode and the second electrode, is transferred onto the first electrode and the second electrode;

[0017] The second two-dimensional material layer of the second semiconductor type is sandwiched between the first two-dimensional material layer of the first semiconductor type and the third two-dimensional material layer of the first semiconductor type to form a heterojunction. The first two-dimensional material and the third two-dimensional material are respectively arranged in a cross structure with the second two-dimensional material.

[0018] The first two-dimensional material layer and / or the third two-dimensional material layer are selected as two-dimensional material MoS2 layers, and the second two-dimensional material layer is selected as two-dimensional material Te layers; or the first two-dimensional material layer and / or the third two-dimensional material layer are selected as two-dimensional material Te layers, and the second two-dimensional material layer is selected as two-dimensional material MoS2 layers.

[0019] Another aspect of the present invention provides a method for fabricating a dual-gate junction field-effect transistor, comprising the following steps:

[0020] A first two-dimensional material layer of a first semiconductor type is transferred and formed on a substrate;

[0021] A first electrode, a second electrode, a third electrode, and a fourth electrode are formed on the substrate, wherein the first electrode and the second electrode are respectively disposed at both ends of a first two-dimensional material layer of the first semiconductor type;

[0022] A third two-dimensional material layer of a second semiconductor type is transferred onto the third and fourth electrodes;

[0023] A second two-dimensional material layer of a first semiconductor type, which is connected to the first and second electrodes, is transferred onto the first and second electrodes.

[0024] A second two-dimensional material layer of the second semiconductor type is sandwiched between a first two-dimensional material layer of the first semiconductor type and a third two-dimensional material layer of the first semiconductor type to form a heterojunction. The first two-dimensional material layer and the third two-dimensional material layer are respectively arranged in a cross structure with the second two-dimensional material layer.

[0025] The first two-dimensional material layer and / or the third two-dimensional material layer are selected as two-dimensional material MoS2 layers, and the second two-dimensional material layer is selected as two-dimensional material Te layers; or the first two-dimensional material layer and / or the third two-dimensional material layer are selected as two-dimensional material Te layers, and the second two-dimensional material layer is selected as two-dimensional material MoS2 layers.

[0026] Furthermore, in the step of transferring the two-dimensional material layer, the medium used for the transfer is a PDMS board with a PVA adhesive layer.

[0027] Furthermore, the thickness of the two-dimensional material Te layer is 50-100 nm, and the thickness of the two-dimensional material MoS2 layer is 50-100 nm.

[0028] Furthermore, the first electrode is a first gate electrode, the second electrode is a second gate electrode, the third electrode is a source electrode, and the fourth electrode is a drain electrode; the electrodes are selected from Au electrode layers, and the thickness of the Au electrode layer is 20-80 nm.

[0029] Compared with the prior art, the present invention has at least the following advantages:

[0030] The JFET provided by this invention is formed by sequentially stacking a first two-dimensional material layer, a second two-dimensional material layer, and a third two-dimensional material layer to form a PN junction. A cross structure is formed between the third two-dimensional material layer and the first and second two-dimensional material layers. In a preferred embodiment, the first and third two-dimensional materials are two-dimensional MoS2 layers, and the second two-dimensional material is a two-dimensional Te layer, forming a double PN junction. A shared dual gate, a first gate and a second gate, are disposed between the first and third two-dimensional material layers. The first and second gates are not in contact with each other. The two ends of the second two-dimensional material layer have non-contact source and drain electrodes. When there is no voltage on the first and second gates, a space charge region is formed inside the PN junction, and the two-dimensional Te layer is partially depleted, resulting in an on state. By changing the voltage of the first and second gates, a positive bias narrows the space charge region, and a negative bias widens it, thereby controlling the width of the space charge region and realizing the switching of the JFET. Because this device structure has no dielectric layer, it achieves a near-ideal subthreshold swing (SS), and the high carrier concentration of the two-dimensional Te layer allows for a large current response even with small source-drain voltages. This JFET exhibits advantages such as large current response, excellent photoresponse performance, and low subthreshold swing.

[0031] Furthermore, the JFET structure provided by this invention is simple, easy to fabricate, and beneficial for application. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the structure of a JFET device according to a preferred embodiment of the present invention.

[0033] Figure 2 This is a schematic diagram of the fabrication process of a JFET device according to a preferred embodiment of the present invention.

[0034] Figure 3 This is the output curve measured by a JFET device according to a preferred embodiment of the present invention.

[0035] Figure 4 This is a transfer curve measured by a JFET device according to a preferred embodiment of the present invention.

[0036] Figure 5 This is the transconductance curve extracted from the transfer curve of a JFET device according to a preferred embodiment of the present invention.

[0037] Figure 6 This is the subthreshold swing curve of a JFET device according to a preferred embodiment of the present invention.

[0038] Figure 7 This is a photoresponse diagram of a JFET device according to a preferred embodiment of the present invention under 405nm laser irradiation.

[0039] Figure 8 This describes the responsivity and detectivity of a JFET device under 405nm laser irradiation according to a preferred embodiment of the present invention.

[0040] Figure 9 This is the IT curve of a JFET device according to a preferred embodiment of the present invention under 405nm laser irradiation and a reverse bias voltage of 0.5V.

[0041] Figure 10 This is the IT curve of a JFET device according to a preferred embodiment of the present invention with a voltage of 0V under 405nm laser irradiation. Detailed Implementation

[0042] The technical solutions in the embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings. The described embodiments are merely some, not all, of the embodiments of the present invention. Other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are all within the scope of protection of the present invention. Unless otherwise specified, the experimental methods described in the following embodiments are conventional methods; the reagents and materials, unless otherwise specified, can be obtained from publicly available commercial channels.

[0043] This specification uses spatially relative terms such as “below,” “under,” “down,” “above,” “above,” and “upper” to explain the positioning of one element relative to a second element. These terms are intended to cover different orientations of the device, except for those different from those shown in the figures.

[0044] Furthermore, the use of terms such as "first" and "second" to describe various elements, layers, regions, and sections is not intended to be restrictive. The use of terms such as "having," "containing," "including," and "comprises" are open-ended terms, indicating the presence of the stated elements or features, but not excluding additional elements or features, unless the context explicitly states otherwise.

[0045] One embodiment of the present invention provides a dual-gate junction field-effect transistor (JFET), such as... Figure 1The embodiment includes a substrate and a heterojunction located on the substrate. In this preferred embodiment, the substrate is selected with a crystal orientation of <100> The silicon substrate has a thickness of 200–1000 μm, and an insulating layer with a thickness of 100–500 nm is disposed on the upper surface of the silicon substrate.

[0046] The heterojunction is composed of a first two-dimensional material layer of a first semiconductor type, a second two-dimensional material layer of a second semiconductor type, and a third two-dimensional material layer of the same type, stacked sequentially. The first semiconductor type is the opposite of the second semiconductor type; for example, the first semiconductor type is N-type and the second semiconductor type is P-type; or the first semiconductor type is P-type and the second semiconductor type is N-type.

[0047] In a preferred embodiment, the first two-dimensional material layer is a two-dimensional MoS2 layer, the second two-dimensional material layer is a two-dimensional Te layer, and the third two-dimensional material layer is a two-dimensional MoS2 layer. In another preferred embodiment, the first two-dimensional material layer is a two-dimensional Te layer, the second two-dimensional material layer is a two-dimensional MoS2 layer, and the third two-dimensional material layer is a two-dimensional Te layer. The thickness of the two-dimensional MoS2 layer is 50–100 nm. The thickness of the two-dimensional Te layer is 50–100 nm. In other embodiments, when one of the first and third two-dimensional material layers is a two-dimensional MoS2 layer, the other two-dimensional material layer is another suitable N-type two-dimensional material layer, and the second two-dimensional material layer is a two-dimensional Te layer; or when one of the first and third two-dimensional material layers is a two-dimensional Te layer, the other two-dimensional material layer is another suitable P-type two-dimensional material layer, and the second two-dimensional material layer is a two-dimensional MoS2 layer.

[0048] The first and third two-dimensional material layers share a gate electrode. By controlling the forward and reverse bias of the PN junction, the depletion region width of the second two-dimensional material channel layer is controlled, thereby enabling the JFET to turn on and off. The first and third two-dimensional material layers are arranged in a cross structure, and the third and second two-dimensional material layers are also arranged in a cross structure. The first and third two-dimensional material layers have opposing first and second ends. A first electrode is disposed between the first ends, and a second electrode is disposed between the second ends. The first and second electrodes do not contact each other. The first and second electrodes are the first gate electrode and the second gate electrode, respectively.

[0049] like Figure 1 As shown, the first gate electrode and the second gate electrode are Au1 electrode and Au2 electrode, respectively, and the thickness of Au1 electrode and Au2 electrode is 20-80 nm.

[0050] The second two-dimensional material layer has a first end and a second end, with a third electrode disposed at the first end (the third electrode being the source electrode) and a fourth electrode disposed at the second end (the fourth electrode being the drain electrode). For example... Figure 1 As shown, the source electrode and drain electrode are Au3 and Au4 electrodes, respectively, with thicknesses of 20–80 nm.

[0051] This dual-gate junction field-effect transistor (JFET) structure has no dielectric layer, achieving a near-ideal subthreshold swing (SS). In a preferred embodiment, the high carrier concentration of the two-dimensional Te layer enables a large current response even with a small source-drain voltage. The JFET designed in this invention features an extremely small subthreshold swing and a large on-state current, which is crucial for devices requiring low power consumption and high current design.

[0052] A preferred embodiment of the present invention describes a method for fabricating this dual-gate junction field-effect transistor, such as... Figure 2 As shown, silicon is selected. <100> The substrate, a silicon substrate, has a SiO2 insulating layer on its surface. First, photoresist is spin-coated onto the surface of the silicon substrate to form a photoresist layer with a thickness of 2 micrometers. Subsequently, photolithography processes such as soft baking, exposure, and development are performed, and after the photoresist is removed, patterned electrode patterns are formed.

[0053] Next, a 50 nm thick gold layer was deposited on the silicon substrate using an electron beam evaporation device. The substrate was then immersed in an acetone solution, and the excess gold was automatically removed, resulting in a substrate with a first electrode Au 1, a second electrode Au 2, a third electrode Au 3, and a fourth electrode Au 4.

[0054] A PDMS plate was selected, and a PVA solution was evenly coated onto it. The plate was then heated at 50°C for 5 minutes to form a PVA adhesive layer. Using a transfer platform, a two-dimensional MoS2 layer was transferred onto the PVA adhesive layer via mechanical peeling. The target area of ​​the MoS2 layer was selected and adhered to the first electrode Au1 and the second electrode Au2. After heating, the PDMS plate was peeled off from the substrate, and then the PVA adhesive layer was removed after soaking in water.

[0055] Subsequently, using a transfer platform, the two-dimensional material Te layer was transferred to the PVA adhesive layer by mechanical peeling. The target two-dimensional material Te layer area was selected and adhered to the third electrode Au 3 and the fourth electrode Au 4. After heating, the PDMS plate was peeled off from the substrate, and then the PVA adhesive layer was removed after soaking in water.

[0056] Continuing with the transfer platform, the two-dimensional material MoS2 layer was transferred onto the PVA adhesive layer using a mechanical peeling method. The target two-dimensional material MoS2 layer region was selected and adhered to the first electrode Au1 and the second electrode Au2. After heating, the PDMS plate was peeled off from the substrate. Subsequently, the PVA adhesive layer was removed after soaking in water, thus completing the fabrication of the device.

[0057] The optoelectronic performance of a JFET provided in a preferred embodiment of the present invention (where the first and third two-dimensional material layers are two-dimensional MoS2 layers and the second two-dimensional material layer is a two-dimensional Te layer) was tested using original measurements. Figure 3 The output curve of the JFET provided by this invention shows that the source-drain voltage ranges from -1.5V to 0V, and the gate voltage is tested under the conditions of 0V, -0.2V, -0.4V, -0.6V, -0.8V and -1V. The maximum source-drain current of this device reaches more than 15uA, which shows that it has good controllability. Figure 4 The following is a transfer curve obtained from a JFET according to a preferred embodiment of the present invention. The six transfer curves were obtained when the gate voltage was from -1V to 1.5V and the source-drain voltages were 0.5V, 0.6V, 0.7V, 0.8V, 0.9V and 1V, respectively. It can be seen from the curve that the threshold voltage of the device is around 1V and the on-state voltage is on the negative axis. Figure 5 From Figure 4 The transconductance extracted from the measured transfer curve has a maximum value of 1.6 x 10⁻⁶. -5 S. Figure 6 The figure shows a subthreshold swing curve according to an embodiment of the present invention. As can be seen from the figure, the minimum subthreshold swing is approximately 238 mv / dec. Figure 7 The JFET device according to one embodiment of the present invention, under the applied voltage conditions of -3V to 3V, exhibits a power density of 0.0141mw / cm² in both dark and 405nm laser environments. 2 0.0888mw / cm 2 0.187mw / cm 2 0.288mw / cm 2 and 0.391mw / cm 2 The current response under these conditions has a dark current of 4.48 x 10⁻⁶. -11 A, the maximum photocurrent is 1.06 x 10⁻⁶. -7 A, the switching ratio is 10 3 above. Figure 8 The JFET of this invention, under 405nm laser irradiation, extracts detectivity and responsivity from the photoresponse, with a maximum detectivity reaching 10. 14 Jones and above, with a responsiveness of 5x10. 2 A / W. Figure 9The time-resolved optical switching (IT) curve of a JFET under 405nm laser irradiation and a reverse bias voltage of 0.5V, according to an embodiment of the present invention, is shown below. Figure 10 The time-resolved optical switching (IT) curve of a JFET under 405nm laser irradiation and with a voltage of 0V, according to an embodiment of the present invention, is shown below. Figure 9 and Figure 10 As can be seen, the dual-gate junction field-effect transistor of this invention exhibits good stability and repeatability under 405nm illumination. The above photoelectric performance test results demonstrate that the JFET provided by this invention has advantages such as low subthreshold swing and high current.

[0058] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A dual-gate field-effect transistor, comprising a substrate and a heterojunction disposed on the substrate, characterized in that, The heterojunction is composed of a first two-dimensional material layer of a first semiconductor type, a second two-dimensional material layer of a second semiconductor type, and a third two-dimensional material layer of a first semiconductor type, which are stacked sequentially. The first two-dimensional material layer and the third two-dimensional material layer are respectively arranged in a cross structure with the second two-dimensional material layer. The first two-dimensional material layer and the third two-dimensional material layer have opposite first ends and second ends. A first electrode is disposed between their first ends and a second electrode is disposed between their second ends. The first electrode and the second electrode do not contact each other. The second two-dimensional material layer has opposite first ends and second ends. A third electrode is disposed at the first end and a fourth electrode is disposed at the second end. The first two-dimensional material layer and the third two-dimensional material layer are selected as two-dimensional material MoS2 layers, and the second two-dimensional material layer is selected as a two-dimensional material Te layer; or the first two-dimensional material layer and the third two-dimensional material layer are selected as two-dimensional material Te layers, and the second two-dimensional material layer is selected as a two-dimensional material MoS2 layer.

2. The field-effect transistor according to claim 1, characterized in that, The thickness of the two-dimensional material Te layer is 50~100nm, and the thickness of the two-dimensional material MoS2 layer is 50~100nm.

3. The field-effect transistor according to claim 1 or 2, characterized in that, The first electrode is the first gate electrode, the second electrode is the second gate electrode, the third electrode is the source electrode, and the fourth electrode is the drain electrode.

4. The field-effect transistor according to claim 1, characterized in that, The electrode is an Au electrode layer with a thickness of 20~80nm.

5. The field-effect transistor according to claim 1, characterized in that, The substrate is a silicon substrate, and an insulating layer is disposed on the surface of the silicon substrate, the thickness of the insulating layer being 100~500nm.

6. A method for fabricating a dual-gate junction field-effect transistor, characterized in that, Includes the following steps: A first electrode, a second electrode, a third electrode, and a fourth electrode are formed on a substrate, wherein the first electrode and the second electrode are disposed opposite to each other, and the third electrode and the fourth electrode are disposed opposite to each other. A first two-dimensional material layer of a first semiconductor type, connected to the first electrode and the second electrode, is transferred between the first electrode and the second electrode; A second two-dimensional material layer of a second semiconductor type is transferred onto the third and fourth electrodes; A third two-dimensional material layer of a first semiconductor type, connected to the first electrode and the second electrode, is transferred onto the first electrode and the second electrode; The second two-dimensional material layer of the second semiconductor type is sandwiched between the first two-dimensional material layer of the first semiconductor type and the third two-dimensional material layer of the first semiconductor type to form a heterojunction. The first two-dimensional material and the third two-dimensional material are respectively arranged in a cross structure with the second two-dimensional material. The first two-dimensional material layer and the third two-dimensional material layer are selected as two-dimensional material MoS2 layers, and the second two-dimensional material layer is selected as a two-dimensional material Te layer; or the first two-dimensional material layer and the third two-dimensional material layer are selected as two-dimensional material Te layers, and the second two-dimensional material layer is selected as a two-dimensional material MoS2 layer.

7. A method for fabricating a dual-gate junction field-effect transistor, characterized in that, Includes the following steps: A first two-dimensional material layer of a first semiconductor type is transferred and formed on a substrate; A first electrode, a second electrode, a third electrode, and a fourth electrode are formed on the substrate, wherein the first electrode and the second electrode are respectively disposed at both ends of a first two-dimensional material layer of the first semiconductor type; A second two-dimensional material layer of a second semiconductor type is transferred onto the third and fourth electrodes; A third two-dimensional material layer of a first semiconductor type, which is connected to the first and second electrodes, is transferred onto the first and second electrodes. A second two-dimensional material layer of the second semiconductor type is sandwiched between a first two-dimensional material layer of the first semiconductor type and a third two-dimensional material layer of the first semiconductor type to form a heterojunction. The first two-dimensional material layer and the third two-dimensional material layer are respectively arranged in a cross structure with the second two-dimensional material layer. The first two-dimensional material layer and the third two-dimensional material layer are selected as two-dimensional material MoS2 layers, and the second two-dimensional material layer is selected as a two-dimensional material Te layer; or the first two-dimensional material layer and the third two-dimensional material layer are selected as two-dimensional material Te layers, and the second two-dimensional material layer is selected as a two-dimensional material MoS2 layer.

8. The preparation method according to claim 6 or 7, characterized in that, In the step of transferring the two-dimensional material layer, the medium used for the transfer is a PDMS board with a PVA adhesive layer.

9. The preparation method according to claim 6 or 7, characterized in that, The thickness of the two-dimensional material Te layer is 50~100nm, and the thickness of the two-dimensional material MoS2 layer is 50~100nm.

10. The preparation method according to claim 6 or 7, characterized in that, The first electrode is a first gate electrode, the second electrode is a second gate electrode, the third electrode is a source electrode, and the fourth electrode is a drain electrode; the electrodes are selected from Au electrode layers, and the thickness of the Au electrode layer is 20~80nm.

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