A two-dimensional material heterojunction field effect transistor, a preparation method and an application thereof

Abstract

This invention relates to a two-dimensional heterojunction field-effect transistor, its fabrication method, and its application, belonging to the field of transistor technology. The transistor includes a conductive substrate, an insulating dielectric layer disposed on the conductive substrate, a gate electrode disposed on the insulating dielectric layer, a first two-dimensional material layer disposed on the gate electrode, a second two-dimensional material layer disposed on the first two-dimensional material layer, and source and drain electrodes respectively disposed at both ends of the second two-dimensional material layer, with a channel region between the source and drain electrodes. The first and second two-dimensional material layers are made of different materials; the first two-dimensional material layer is a ferroelectric material. The second two-dimensional material layer can form ohmic contacts with the source and drain electrodes. The two-dimensional heterojunction field-effect transistor provided by this invention has a high strength of up to 10. 6 The on / off ratio is close to the theoretical limit of the subthreshold swing.

Description

Technical Field

[0001] This invention belongs to the field of transistor technology, and more specifically, relates to a two-dimensional material heterojunction field-effect transistor, its preparation method, and its application. Background Technology

[0002] A field-effect transistor (FET) is a semiconductor device that uses the electric field effect of the input circuit to control the output circuit. With technological advancements, the applications of FETs are constantly expanding. In recent years, ferroelectric materials, capable of spontaneous polarization, possess piezoelectric, thermoelectric, and photoelectric properties, and are widely used in various fields such as non-volatile memories, logic circuits, sensors, actuators, and electro-optic modulators. In particular, compared to industrialized ferroelectric random access memories (FRAMs), ferroelectric field-effect transistors have attracted increasing attention due to their non-destructive readout performance, simpler cell structure, and higher storage density.

[0003] As the earliest discovered two-dimensional nanomaterial, graphene has attracted considerable attention and research since its emergence in 2004 due to its unique physicochemical properties and enormous application potential in the field of nano-optoelectronics. However, its naturally zero-bandgap structure limits its widespread practical application in nanoelectronics. In recent years, two-dimensional transition metal chalcogenides (TMDs) have been gradually emerging. They possess unique structures and exhibit excellent optoelectronic properties, thus becoming an alternative to graphene as a two-dimensional material.

[0004] While ferroelectric materials and two-dimensional TMDs have been extensively studied, van der Waals heterojunctions formed by combining and stacking them, along with their corresponding electronic devices, have also garnered significant attention and research. Heterojunction systems composed of these two-dimensional materials exhibit unique properties and novel physical phenomena, sparking a new revolution in heterojunction structure design and integrated optoelectronic applications. Summary of the Invention

[0005] In view of this, the first objective of this application is to provide a two-dimensional material heterojunction field-effect transistor, the second objective is to provide a method for fabricating the above-mentioned two-dimensional material heterojunction field-effect transistor, and the third objective is to provide an application of the above-mentioned two-dimensional material heterojunction field-effect transistor. The two-dimensional material heterojunction field-effect transistor provided by this invention has a high strength of up to 10. 6 The on / off ratio is close to the theoretical limit of the subthreshold swing.

[0006] To achieve the above objectives, the specific solution adopted by the present invention is as follows:

[0007] A two-dimensional material heterojunction field-effect transistor includes: a conductive substrate, an insulating dielectric layer disposed on the conductive substrate, a gate electrode disposed on the insulating dielectric layer, a first two-dimensional material layer disposed on the gate electrode, a second two-dimensional material layer disposed on the first two-dimensional material layer, a source electrode and a drain electrode disposed at both ends of the second two-dimensional material layer, and a channel region between the source electrode and the drain electrode.

[0008] The first two-dimensional material layer and the second two-dimensional material layer are made of different materials. The first two-dimensional material layer is a ferroelectric material. The second two-dimensional material layer can form an ohmic contact with the source electrode and the drain electrode.

[0009] Preferably, the first two-dimensional material layer is selected from CuInP2S6, BaTiO3, or KH2PO4, and the second two-dimensional material layer is selected from WS2, WSe2, InSe, or MoS2. More preferably, the first two-dimensional material layer is selected from CuInP2S6 with a thickness of 30nm to 100nm; and the second two-dimensional material layer is selected from WS2 with a thickness of 10nm to 70nm.

[0010] Preferably, the conductive substrate is selected from a silicon substrate or a copper substrate.

[0011] Preferably, the insulating dielectric layer is made of SiO2, SiC, SiN, HfO2, or TiO2. SiO2 is preferred.

[0012] Preferably, the gate electrode, source electrode, and drain electrode are made of one or two of the metals Au, Cu, Ni, Ti, Cr, and Ag. Ti / Au is preferred.

[0013] This invention also provides a method for fabricating a two-dimensional heterojunction field-effect transistor, comprising the following steps:

[0014] S1: Fabricate a gate electrode on a substrate; the substrate includes a conductive substrate and an insulating dielectric layer;

[0015] S2: The first two-dimensional material layer is prepared on the gate electrode using a dry transfer method;

[0016] S3: Using a dry transfer method, a second two-dimensional material layer is prepared on the first two-dimensional material layer, such that the second two-dimensional material layer and the gate electrode are not in the same vertical direction.

[0017] S4: Source and drain electrodes are fabricated on the second two-dimensional material layer and annealed to form an ohmic contact between the second two-dimensional material layer and the source and drain electrodes, thereby obtaining a two-dimensional material heterojunction field-effect transistor.

[0018] Preferably, in step S1, the substrate is SiO2 / Si.

[0019] Preferably, in step S4, the annealing temperature is 150°C, the time is 30 minutes, and the annealing environment is nitrogen or argon.

[0020] The above-mentioned two-dimensional material heterojunction field-effect transistors have applications in the optoelectronic field.

[0021] Unlike traditional field-effect transistors where gate voltage controls source and drain current, this invention uses a ferroelectric material that spontaneously polarizes within a certain temperature range and whose polarization direction changes under an external electric field as the first two-dimensional material layer to act as the gate control. The polarization direction of the ferroelectric material is changed by altering the gate voltage, thereby controlling the source and drain current. Therefore, the first two-dimensional material layer and the gate electrode must be located on the same vertical plane, and the second two-dimensional material layer must be in contact with the first two-dimensional material layer but not on the same vertical plane as the gate electrode, thus eliminating the direct influence of the gate electrode on the second two-dimensional material layer.

[0022] Compared with existing technologies, the two-dimensional heterojunction field-effect transistor provided by this invention comprises, from bottom to top, a conductive substrate, an insulating dielectric layer, a gate electrode, a first two-dimensional material layer, a second two-dimensional material layer, a source electrode, and a drain electrode. It is important to note that the first two-dimensional material layer and the gate electrode are located on the same vertical plane, and the second two-dimensional material layer, while in contact with the first two-dimensional material layer, is not on the same vertical plane as the gate electrode. This invention first uses photolithography and metal evaporation techniques to fabricate the gate electrode, then places the first two-dimensional material on the gate electrode, and then places the second two-dimensional material on a portion of the first two-dimensional material to form a heterojunction. Finally, the source and drain electrodes are placed at both ends of the second two-dimensional material to form a channel region. This two-dimensional heterojunction field-effect transistor provided by this invention exhibits excellent performance, such as extremely small subthreshold swing and an on / off ratio as high as 10. 6 It is also easy to make and has a low cost. Attached Figure Description

[0023] Figure 1 This is a top view schematic diagram of a two-dimensional material heterojunction field-effect transistor provided by an example of the present invention; wherein, 1 is the substrate, 2 is the gate electrode, 3 is the first two-dimensional material layer, 4 is the second two-dimensional material layer, 5 is the source electrode, and 6 is the drain electrode.

[0024] Figure 2 This is a 3D structural schematic diagram of a two-dimensional material heterojunction field-effect transistor provided by an example of the present invention; wherein, 1 is the substrate, 2 is the gate electrode, 3 is the first two-dimensional material layer, 4 is the second two-dimensional material layer, 5 is the source electrode, and 6 is the drain electrode.

[0025] Figure 3This is a flowchart illustrating a method for fabricating a two-dimensional material heterojunction field-effect transistor, as provided in this invention.

[0026] Figure 4 This is a physical diagram of the CuInP2S6 / WS2 heterojunction field-effect transistor provided in this invention example;

[0027] Figure 5 The transfer curve is provided in the example of the present invention for the CuInP2S6 / WS2 heterojunction field-effect transistor. Detailed Implementation

[0028] The technical solution of the present invention will now be clearly and completely described in conjunction with the embodiments and accompanying drawings.

[0029] This invention provides a two-dimensional material heterojunction field-effect transistor, comprising:

[0030] Conductive substrate;

[0031] An insulating dielectric layer disposed on the conductive substrate;

[0032] Gate electrode disposed on the insulating dielectric layer;

[0033] The first two-dimensional material layer disposed on the gate electrode;

[0034] A second two-dimensional material layer disposed on part of the first two-dimensional material layer;

[0035] The source electrode and drain electrode are respectively disposed at both ends of the second two-dimensional material, and the channel region is formed between the source electrode and the drain electrode.

[0036] The first two-dimensional material layer and the second two-dimensional material layer are made of different materials; the second two-dimensional material layer can form an ohmic contact with the source electrode and the drain electrode.

[0037] The two-dimensional material heterojunction field-effect transistor provided by this invention has good performance, such as a large on / off ratio and a subthreshold swing close to the theoretical limit, and is low in cost and easy to apply.

[0038] See Figure 1 and Figure 2 , Figure 1 This is a top view schematic diagram of a two-dimensional material heterojunction field-effect transistor provided in an embodiment of the present invention. Figure 2 This is a perspective view of a two-dimensional heterojunction field-effect transistor provided in an embodiment of the present invention. In the diagram, 1 is the substrate (conductive substrate and insulating dielectric layer), 2 is the gate electrode, 3 is the first two-dimensional material layer, 4 is the second two-dimensional material layer, 5 is the source electrode, and 6 is the drain electrode.

[0039] The two-dimensional heterojunction junction field-effect transistor includes a conductive substrate and an insulating dielectric layer 1. The insulating dielectric layer is made of an insulating material, preferably SiO2, SiC, SiN, HfO2, or TiO2, and more preferably SiO2. Therefore, in this example, SiO2 is used as the insulating dielectric layer. The thickness of the insulating dielectric layer is preferably 20 nm to 500 nm; in this example, the thickness of the insulating dielectric layer is 300 nm.

[0040] This invention provides a junction field-effect transistor with a bottom-gate structure, as shown in the attached figure. Figure 1 and Figure 2 As shown, 2, 5, and 6 represent the gate electrode, source electrode, and drain electrode, respectively. The electrodes are selected from one or two of Au, Cu, Ni, Ti, Cr, and Ag; in this example, Ti / Au is used as the electrode metal. In the gate electrode, titanium contacts the insulating dielectric layer, with a thickness ranging from 1 nm to 50 nm (e.g., 10 nm), and gold contacts the first two-dimensional material, with a thickness ranging from 10 nm to 100 nm (e.g., 50 nm). In the source and drain electrodes, titanium contacts the second two-dimensional material, forming an ohmic contact between them, with the same thickness as the gate electrode. This invention does not impose any special limitations on the channel region, and its length can be 20 μm.

[0041] The first and second two-dimensional materials described in this invention are made of different materials. The first two-dimensional material is a ferroelectric material with ferroelectric properties, capable of spontaneous polarization within a certain temperature range and changing its polarization direction under an external electric field, such as CuInP2S6, BaTiO3, KH2PO4, etc. Preferably, in this example, CuInP2S6 is used as the first two-dimensional material layer, and its thickness is preferably 30nm to 100nm; in this example, a thickness of 60nm is used. The second two-dimensional material is a commonly used two-dimensional material in the art, such as WS2, WSe2, MoS2, InSe, etc. In this example, WS2 is used as the second two-dimensional material layer, and its thickness is preferably 10nm to 70nm; in this example, a thickness of 30nm is used.

[0042] by Figure 2 Taking the structure of the field-effect transistor shown as an example, this application also provides a method for fabricating a field-effect transistor. For the specific fabrication process, please refer to [reference needed]. Figure 3 This includes the following steps:

[0043] S1: Fabrication of the gate electrode on the substrate; it should be understood that this substrate includes a conductive substrate and an insulating dielectric layer, such as SiO2 / Si. First, 601 positive photoresist is spin-coated onto the insulating dielectric layer 1 at a spin-coating time of 60 s and a spin-coating speed of 4000 rpm. Then, an electrode pattern mask is fabricated on the insulating dielectric layer 1 by photolithography and development, wherein the developing solution used is tetramethylammonium hydroxide and the development time is 15 s. Finally, a Ti layer with a thickness of 10 nm and an Au layer with a thickness of 50 nm are sequentially deposited using an electron beam evaporation deposition machine, and then the metal electrode (Ti / Au) is obtained by rinsing with acetone to remove the photoresist and the metal layer outside the electrode area.

[0044] S2: Fabrication of the first two-dimensional material layer on the gate electrode; This application employs a dry transfer technique, specifically including: firstly, peeling CuInP2S6 from the bulk substrate using adhesive tape, then attaching it to a SiO2 / Si substrate; then uniformly dropping a pre-prepared PVA solution (4g of polyvinyl alcohol granules into a beaker containing 21ml of deionized water, adding a magnetic stir bar, and stirring on a magnetic stirrer at a speed of 600–1200 rpm for 10–12 hours) onto PDMS (polydimethylsiloxane) to ensure the PVA solution is horizontal; then curing the PVA solution on a heating platform at 55°C for 30 minutes; then attaching the cured PVA film to the CuInP2S6 sample and heating it on a heating platform at 90°C–100°C for 4–6 minutes, at which point CuInP2S6 is adhered to the PVA film; finally, attaching the PVA film with CuInP2S6 to the gate electrode completes the transfer.

[0045] S3: Fabricate a second two-dimensional material layer on the first two-dimensional material layer; similarly, this step also uses a dry transfer technique. It is important to note that the transferred second two-dimensional material layer partially contacts the first two-dimensional material layer, and the second two-dimensional material layer and the gate electrode are not on the same vertical plane. For detailed device structure and optical microscope images, please refer to [link to relevant documentation]. Figure 2 as well as Figure 4 .

[0046] S4: Fabricate source and drain electrodes on the second two-dimensional material layer; the specific fabrication of the source and drain electrodes is the same as in step S1, but it should be noted that the titanium layer metal obtained should be in contact with the second two-dimensional material so that the metal and the second two-dimensional material can directly form an ohmic contact.

[0047] A physical image of the CuInP2S6 / WS2 heterojunction field-effect transistor prepared by the above method is shown below. Figure 4 As shown; the transfer curve of the CuInP2S6 / WS2 heterojunction field-effect transistor is as follows. Figure 5 As shown.

[0048] It should be noted that the above-described embodiments should be understood as illustrative, not as limiting the scope of protection of this invention. The scope of protection of this invention is defined by the claims. For those skilled in the art, some non-essential improvements and adjustments made to this invention without departing from the essence and scope of this invention still fall within the scope of protection of this invention.

Claims

1. A two-dimensional material heterojunction field-effect transistor, characterized in that: include: A substrate (1) consisting of a conductive substrate and an insulating dielectric layer disposed on the conductive substrate, a gate electrode (2) disposed on the insulating dielectric layer, a first two-dimensional material layer (3) disposed on the gate electrode (2), a second two-dimensional material layer (4) disposed on the first two-dimensional material layer (3), a source electrode (5) and a drain electrode (6) disposed at both ends of the second two-dimensional material layer (4), and a channel region between the source electrode (5) and the drain electrode (6); The first two-dimensional material layer (3) and the second two-dimensional material layer (4) are made of different materials. The first two-dimensional material layer (3) is a ferroelectric material. The second two-dimensional material layer (4) can form an ohmic contact with the source electrode (5) and the drain electrode (6). The first two-dimensional material layer is located on the same vertical plane as the gate electrode, and the second two-dimensional material layer is in contact with the first two-dimensional material layer but not on the same vertical plane as the gate electrode. The first two-dimensional material layer is CuInP2S6 with a thickness of 30nm to 100nm; the second two-dimensional material layer is WS2 with a thickness of 10nm to 70nm.

2. The two-dimensional material heterojunction field-effect transistor according to claim 1, characterized in that: The conductive substrate is selected from silicon substrate or copper substrate; the insulating dielectric layer is selected from SiO2, SiC, SiN, HfO2 or TiO2.

3. The two-dimensional material heterojunction field-effect transistor according to claim 1, characterized in that: The metals used for the gate electrode, source electrode, and drain electrode are one or two of Au, Cu, Ni, Ti, Cr, and Ag.

4. The method for fabricating a two-dimensional heterojunction field-effect transistor according to any one of claims 1-3, characterized in that: Includes the following steps: S1: Fabricate a gate electrode on a substrate; the substrate includes a conductive substrate and an insulating dielectric layer; S2: The first two-dimensional material layer is prepared on the gate electrode using a dry transfer method; S3: Using a dry transfer method, a second two-dimensional material layer is prepared on the first two-dimensional material layer, such that the second two-dimensional material layer and the gate electrode are not in the same vertical direction. S4: Source and drain electrodes are fabricated on the second two-dimensional material layer and annealed to form an ohmic contact between the second two-dimensional material layer and the source and drain electrodes, thereby obtaining a two-dimensional material heterojunction field-effect transistor.

5. The preparation method according to claim 4, characterized in that: In step S1, the substrate is SiO2 / Si.

6. The preparation method according to claim 4, characterized in that: In step S4, the annealing temperature is 150°C, the time is 30 minutes, and the annealing environment is nitrogen or argon.

7. The application of the two-dimensional material heterojunction field-effect transistor according to any one of claims 1-3 in the optoelectronic field.

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