Display panel and driving method thereof

Abstract

The invention provides a display panel and a driving method thereof, the display panel comprises a plurality of sub-pixels, each sub-pixel comprises a light-emitting element and a pixel circuit which are electrically connected, and the pixel circuit is used for generating a driving current according to a data signal to drive the light-emitting element to emit light. A grid electrode of the driving transistor is electrically connected to a first node or connected to the first node through a first capacitor, and the pixel circuit further comprises a data writing transistor and a first reset transistor which are electrically connected to the first node and used for transmitting the data signal and the first reset signal. The driving transistor is an oxide transistor so as to at least reduce the power consumption of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a driving method thereof. Background Art

[0002] AMOLED (Active-Matrix Organic Light-Emitting Diode) display panel has the advantages of fast response speed, high contrast and wide viewing angle.

[0003] Among them, the driving transistor in the traditional pixel circuit of the AMOLED display panel is generally an LTPS TFT (Low Temperature Poly-Silicon) transistor, which causes the AMOLED display panel to have disadvantages such as high power consumption. Summary of the invention

[0004] The invention provides a display panel and a driving method thereof to reduce the power consumption of the AMOLED display panel.

[0005] An embodiment of the present invention provides a display panel, including a plurality of sub-pixels, wherein the sub-pixels include a light-emitting element and a pixel circuit that are electrically connected, and the pixel circuit includes:

[0006] a driving transistor, used to generate a driving current according to a data signal to drive the light-emitting element to emit light, wherein the driving transistor is an oxide transistor, and a gate of the driving transistor is electrically connected to the first node or is connected to the first node through a first capacitor;

[0007] a data writing transistor, electrically connected to the first node, for transmitting the data signal;

[0008] The first reset transistor is electrically connected to the first node and is used for transmitting a first reset signal.

[0009] An embodiment of the present invention further provides a method for driving a display panel, which is applied to any of the display panels described above, comprising:

[0010] controlling the first reset transistor to be turned on so that the first reset transistor transmits the first reset signal to the first node;

[0011] Controlling the data writing transistor to be turned on, so that the data writing transistor transmits the data signal to the gate of the driving transistor, so that the driving transistor is turned on;

[0012] The driving transistor is controlled to generate a driving current according to the data signal to drive the light emitting element to emit light.

[0013] The present invention provides a display panel and a driving method thereof, comprising a plurality of sub-pixels, wherein the sub-pixels include electrically connected light-emitting elements and pixel circuits, wherein the pixel circuit includes a driving transistor for generating a driving current according to a data signal to drive the light-emitting element to emit light, wherein a gate of the driving transistor is electrically connected to a first node or is connected to the first node through a first capacitor, wherein the pixel circuit also includes a data writing transistor and a first reset transistor electrically connected to the first node and respectively used to transmit the data signal and a first reset signal, wherein the driving transistor is an oxide transistor, which at least reduces the power consumption of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention.

[0015] Figure 2 and Figure 3 A schematic diagram of the structure of a pixel circuit provided by an embodiment of the present invention.

[0016] Figure 4 The present invention provides a flow chart of a method for driving a display panel.

[0017] Figure 5 and Figure 6 They are Figure 2 and Figure 3 Waveform diagram of some signals in the pixel circuit. DETAILED DESCRIPTION

[0018] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0019] In the description of the present invention, the terms "first", "second", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In this article, no distinction is made between the source and drain of the transistor, and the two can be interchangeably arranged. In addition, it should be noted that the drawings only provide structures that are closely related to the present invention, and some details that are not closely related to the invention are omitted. The purpose is to simplify the drawings so that the inventive point is clear at a glance, rather than to indicate that the actual device is the same as the attached structure. Figure 1 The same is not a limitation of the actual device.

[0020] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase at various times in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0021] The present invention provides a display panel, which includes but is not limited to the following embodiments and combinations of the following embodiments.

[0022] In some embodiments, in combination Figures 1 to 3 As shown, the display panel 100 includes a plurality of sub-pixels 101, wherein the sub-pixels 101 include an electrically connected light-emitting element Di and a pixel circuit 1011, wherein the pixel circuit 1011 includes: a driving transistor T1, for generating a driving current according to a data signal Data to drive the light-emitting element Di to emit light, wherein the driving transistor T1 is an oxide transistor, wherein a gate of the driving transistor T1 is electrically connected to a first node P (this case is not shown) or is connected to the first node P through a first capacitor C1; a data writing transistor T7, electrically connected to the first node P, for transmitting the data signal Data; and a first reset transistor T8, electrically connected to the first node P, for transmitting a first reset signal VI1.

[0023] The display panel 100 may be a self-luminous display panel, that is, the display panel 100 displays images through the self-luminescence of the light-emitting element Di in the sub-pixel 101 .

[0024] Specifically, Figure 1 As shown, the display panel 100 may further include a cascaded multi-stage gate driving unit (composed of a gate driving circuit 102); a timing controller 201, each of the gate driving units is electrically connected between the timing controller 201 and the corresponding plurality of pixel circuits 1011, and is used to output a gate signal Gate transmitted to the corresponding plurality of pixel circuits 1011; at least one source driver 202, each of the source drivers 202 is electrically connected between the timing controller 201 and the corresponding plurality of pixel circuits 1011, and is used to output the above-mentioned data signal Data transmitted to the corresponding plurality of pixel circuits 1011. The display panel 100 may include an electrically connected panel body 10 and a driving chip 20, the above-mentioned gate driving circuit 102 and a plurality of sub-pixels 101 are arranged on a substrate of the panel body 10, and the driving chip 20 may include a timing controller 201 and a source driver 202.

[0025] For ease of description, an example is given herein where a plurality of sub-pixels 101 are arranged in an array of n rows and m columns (n ​​and m are both positive integers).

[0026] The gate driving circuit 102 may include at least n-level gate driving units, such as Figure 1 As shown, each gate driving unit outputs a corresponding gate signal Gate according to the first control signal provided by the timing controller 201, and the n-level gate signals are respectively transmitted to the n-row sub-pixels 101 through the n gate lines (GL1 to GLn). The n gate pulses in the n-level gate signals respectively used to turn on the n-row sub-pixels 101 can be arranged in sequence on the time axis to turn on multiple rows of sub-pixels 101 in sequence.

[0027] The source driver 202 can generate m data signals Data that are output to m columns of sub-pixels 101 through m data lines (DL1 to DLm) according to the second control signal provided by the timing controller 201. Each data signal Data may include n data voltages corresponding to n sub-pixels 101 in the same column. When each row of sub-pixels 101 is turned on, multiple data lines respectively receive multiple data voltages of the multiple sub-pixels 101 located in the row, so that the multiple data voltages act on the multiple sub-pixels 101 in the row to realize the light emission of multiple light-emitting elements Di in the multiple sub-pixels 101 in the row. Similarly, the light-emitting elements Di of all rows can be controlled to emit light in turn to present a complete picture.

[0028] In combination with the above discussion, it can be known that the data writing transistor T7 in each pixel circuit 1011 in this embodiment is used to transmit the data signal Data to the gate of the driving transistor T1 through the first node P, and then the driving transistor T1 is used to generate a corresponding driving current according to the corresponding data voltage in the data signal Data to drive the corresponding light-emitting element Di to emit light. Among them, the gate signal Gate of each level can act on the corresponding row of pixel circuits 1011, including but not limited to the data writing transistor T7 and the first reset transistor T8, so as to realize at least one of transmitting the data signal Data to the gate of the driving transistor T1 in the corresponding period and generating the corresponding driving current in the corresponding period.

[0029] It can be understood that the driving transistor T1 used to generate the driving current in the present embodiment is an oxide transistor. On the one hand, it has a lower leakage rate, so that the potential of its gate is less likely to change due to leakage, thereby reducing the risk of screen flickering. On the other hand, the hysteresis effect of the threshold voltage of the driving transistor T1 is smaller, thereby improving the afterimage phenomenon. On the other hand, the operating voltage divider of the driving transistor T1 is smaller, thereby reducing the power consumption of the display panel 100. On the other hand, the process uniformity of the oxide transistor is higher, thereby improving the uniformity of the screen display.

[0030] In some embodiments, Figure 2 As shown, the data write transistor T7 and the first reset transistor T8 are both oxide transistors. Combined with the above discussion, it can be seen that since the data write transistor T7 and the first reset transistor T8 are directly or indirectly connected to the gate of the driving transistor T1 through the first node P, both will affect the potential of the gate of the driving transistor T1 by affecting the potential of the first node P, thereby affecting the magnitude of the driving current. Similarly, in order to reduce the large leakage of the charge of the first node P through the path of at least one of the data write transistor T7 and the first reset transistor T8, the present embodiment also sets both of them as oxide transistors, thereby reducing the impact on the luminous brightness of the light-emitting element Di.

[0031] In some embodiments, Figure 3 As shown, the data writing transistor T7 and the first reset transistor T8 are both low temperature polysilicon transistors. It can be understood that in this embodiment, considering that the driving transistor T1 has a low leakage rate, and further considering that the electron mobility of low temperature polysilicon is high, that is, the electrons move faster in the two, the data writing transistor T7 and the first reset transistor T8 are set to be low temperature polysilicon, thereby accelerating the speed of transmitting the data signal Data and the first reset signal VI1 to the first node P, thereby accelerating the response speed of the display panel 100.

[0032] On this basis, if Figure 3 As shown, the pixel circuit 1011 further includes: a transfer transistor T9, which is electrically connected between the data writing transistor T7, the first reset transistor T8 and the first node P, and the transfer transistor T9 is an oxide transistor. It can be understood that here, on the basis that the data writing transistor T7 and the first reset transistor T8 are both low-temperature polysilicon, a transfer transistor T9 that is an oxide transistor is further set between the data writing transistor T7 and the first reset transistor T8 and the first node P. Since the transfer transistor T9 has a lower leakage rate, the risk of a large leakage of the charge of the first node P through the path of at least one of the data writing transistor T7 and the first reset transistor T8 can also be reduced.

[0033] Of course, one of the data writing transistor T7 and the first reset transistor T8 may be an oxide transistor, and the other may be a low-temperature polysilicon transistor. In combination with the above discussion, it can be seen that the one of the data writing transistor T7 and the first reset transistor T8 that is an oxide transistor can prevent the charge of the first node P from leaking significantly through the path where it is located, and the one of the data writing transistor T7 and the first reset transistor T8 that is a low-temperature polysilicon transistor can speed up the transmission speed of the data signal Data or the first reset signal VI1 to the first node P, thereby speeding up the response speed of the display panel 100.

[0034] In some embodiments, Figure 2 and Figure 3 As shown, the pixel circuit 1011 also includes: a compensation transistor T3, electrically connected between the gate of the driving transistor T1 and one of the source and the drain of the driving transistor T1; a second reset transistor T4, electrically connected to one of the anode and the cathode of the light-emitting element Di, and used to transmit a second reset signal VI2 to one of the anode and the cathode of the light-emitting element Di; wherein, at least one of the compensation transistor T3 and the second reset transistor T4 is an oxide transistor.

[0035] Among them, since the compensation transistor T3 is electrically connected between the gate of the driving transistor T1 and one of the source and drain of the driving transistor T1 (here, the compensation transistor T3 is electrically connected to the drain of the driving transistor T1 as an example), the charge between the gate and the source of the driving transistor T1 will be transferred through the compensation transistor T3, so that the potentials of the two will change, which will further affect the magnitude of the driving current. In addition, since the second reset transistor T4 is electrically connected to one of the anode and the cathode of the light-emitting element Di, here, the second reset transistor T4 is electrically connected to the anode of the light-emitting element Di as an example, the charge of the anode of the light-emitting element Di will also leak through the second reset transistor T4, thereby affecting the potential of the anode of the light-emitting element Di, and further affecting the brightness of the light-emitting element Di.

[0036] Therefore, in this embodiment, setting at least one of the compensation transistor T3 and the second reset transistor T4 as an oxide transistor can reduce the change in the potential of at least one of the gate, source, and drain of the driving transistor T1, thereby reducing the impact on the brightness of the light-emitting element Di.

[0037] In some embodiments, Figure 2 and Figure 3 As shown, the pixel circuit 1011 further includes: a second capacitor C2, a first plate of the second capacitor C2 is electrically connected to a first power line (for transmitting a first power signal VDD), and a second plate of the second capacitor C2 is electrically connected to the first node P. The first power signal VDD transmitted by the first power line is a constant voltage signal, so when the first node P is in a suspended state, the second capacitor C2 can maintain the stability of the potential of the first node P.

[0038] Specifically, when the pixel circuit 1011 includes the first capacitor C1, as Figure 2 and Figure 3As shown, the first capacitor C1 can be used to maintain the stability of the voltage difference between the first node P and the gate of the driving transistor T1 (i.e., the second node Q). When the potential of one of the two changes, due to the voltage stabilization effect of the first capacitor C1 or the coupling effect, the potential of the other of the two will also change in the same way. When the pixel circuit 1011 does not include the first capacitor C1, different from Figure 2 and Figure 3 As shown, the potentials of the second node Q and the first node P are the same. At this time, the data signal Data and the first reset signal VI1 can be directly transmitted to the gate of the driving transistor T1, and the second capacitor C2 can also directly maintain the stability of the potential of the second node Q.

[0039] In some embodiments, Figure 2 and Figure 3 As shown, the pixel circuit 1011 further includes: a first switch transistor T6, electrically connected between the other of the source and the drain of the driving transistor T1 and one of the anode and the cathode of the light-emitting element Di; a third reset transistor T2, electrically connected to the other of the source and the drain of the driving transistor T1 and the first switch transistor T6, for transmitting a third reset signal VI3 to the other of the source and the drain of the driving transistor T1. Here, the first switch transistor T6 and the third reset transistor T2 are electrically connected to the source of the driving transistor T1 as an example.

[0040] It can be understood that in this embodiment, by setting the first switch transistor T6 between the light emitting element Di and the driving transistor T1, the potential of the drain of the driving transistor T1 and the potential of the anode of the light emitting element Di can be cut off when the first switch transistor T6 is turned off, so as to reduce the interference between the two. Specifically, when the second reset transistor T4 resets the anode of the light emitting element Di through the second reset signal VI2, and when the third reset transistor T2 resets the drain of the driving transistor T1 through the third reset signal VI3, the first switch transistor T6 can be turned off; after the data signal Data is written to the driving transistor T1, the first switch transistor T6 can be turned on to enable the driving transistor T1 to form the above-mentioned driving current.

[0041] In some embodiments, Figure 2 and Figure 3 As shown, the pixel circuit 1011 further includes: a second switch transistor T5, electrically connected between one of the source and the drain of the driving transistor T1 and the first power line (for transmitting the first power signal VDD). Based on the above schematic diagram of the connection relationship between the source and the drain of the driving transistor T1, it can be considered here that the second switch transistor T5 is electrically connected to the drain of the driving transistor T1, that is, the second switch transistor T5 is electrically connected to the compensation transistor T3.

[0042] Similarly, since the second switch transistor T5 is electrically connected between the source of the driving transistor T1 and the first power line, the potential of the first power line and the potential between the source of the driving transistor T1 can be cut off when the second switch transistor T5 is turned off, so as to reduce the interference between the two. Specifically, the second reset transistor T4 can reset the anode of the light-emitting element Di through the second reset signal VI2, and the third reset transistor T2 can reset the drain of the driving transistor T1 through the third reset signal VI3, and the first switch transistor T6 can be turned off; after the data signal Data is written into the driving transistor T1, the first switch transistor T6 can be turned on to enable the driving transistor T1 to form the above-mentioned driving current.

[0043] In some embodiments, Figure 2 and Figure 3 As shown, the pixel circuit 1011 further includes: a storage capacitor Cst, a first plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor T1, and a second plate of the storage capacitor Cst is electrically connected to one of the anode and the cathode of the light-emitting element Di. Based on the above illustration of the connection relationship between the anode and the cathode of the light-emitting element Di, it can be considered here that the second plate of the storage capacitor Cst is electrically connected to the anode of the light-emitting element Di.

[0044] Similarly, since the two ends of the storage capacitor Cst are electrically connected to the second node Q and the third node C (i.e., the anode of the light-emitting element Di) respectively, the storage capacitor Cst is used to maintain the stability of the voltage difference between the second node Q and the third node C. Since neither the second node Q nor the third node C is constantly connected to the constant voltage signal, when both are suspended, a change in the potential of one of them will cause a change in the potential of the other.

[0045] In order to better explain the light emitting principle of the display panel 100 and the sub-pixel 101 therein, the present invention further provides a display panel driving method, which is applied to any of the display panels 100 described above. Figure 4 As shown, including but not limited to the following steps.

[0046] S1, controlling the first reset transistor to be turned on, so that the first reset transistor transmits the first reset signal to the first node.

[0047] Specifically, in Figure 2 In the embodiment, the first reset transistor T8 can be controlled to be turned on so that the first reset signal VI1 is transmitted to the first node P to reset it; Figure 3In the embodiment, the first reset transistor T8 and the transmission transistor T9 can be controlled to be turned on so that the first reset signal VI1 is transmitted to the first node P to reset it. The residual charge in the first node P can be released by resetting the first node P.

[0048] S2, controlling the data writing transistor to be turned on, so that the data writing transistor transmits the data signal to the gate of the driving transistor, so that the driving transistor is turned on.

[0049] Specifically, in Figure 2 In the embodiment, the data writing transistor T7 can be controlled to be turned on so that the data signal Data is transmitted to the first node P and is transmitted to the gate of the driving transistor T1 through the coupling effect of the first capacitor C1; Figure 3 In the embodiment, the data writing transistor T7 and the transmission transistor T9 can be controlled to be turned on so that the data signal Data is transmitted to the gate of the driving transistor T1 to turn on the driving transistor T1.

[0050] S3, controlling the driving transistor to generate a driving current according to the data signal to drive the light emitting element to emit light.

[0051] In combination with the above discussion, it can be seen that when the pixel circuit 1011 also includes at least one of the above-mentioned first switching transistor T6 and the second switching transistor T5, it is necessary to control its conduction to form a path between the first power line and the cathode of the light-emitting element Di. At this time, the driving transistor T1 can generate a driving current according to the data signal to drive the light-emitting element to emit light Di.

[0052] In order to better explain the above display panel, Figure 2 and Figure 3 The working stages of the i-th row of sub-pixels 101 in the circuit diagram of the two sub-pixels 101 are described respectively, where i is a positive integer greater than 0 and less than or equal to n-1. For ease of description, the present invention takes the example that all oxide transistors are N-type transistors and all low-temperature polysilicon transistors are P-type transistors. Figure 2 The driving transistor T1, the data writing transistor T7, the first reset transistor T8, the compensation transistor T3, and the second reset transistor T4 are all N-type transistors, and the first switch transistor T6, the third reset transistor T2, and the second switch transistor T5 are all P-type transistors. Figure 3 The driving transistor T1, the compensation transistor T3, and the second reset transistor T4 are all N-type transistors, and the first switch transistor T6, the third reset transistor T2, the second switch transistor T5, the data writing transistor T7, and the first reset transistor T8 are all P-type transistors.

[0053] Combination Figure 2 and Figure 5 As shown, Figure 2 The sub-pixel 101 shown may include but is not limited to the following working stages:

[0054] In stage t1, the first gate signal EM1[i], the second gate signal Nscan2[i], and the third gate signal Nscan1[i] are all corresponding effective potentials, thereby controlling the second switch transistor T5, the first reset transistor T8, the compensation transistor T3, and the second reset transistor T4 to be turned on, the first power supply signal VDD is transmitted to the drain of the driving transistor T1, and then transmitted to the gate of the driving transistor T1 through the compensation transistor T3, the second reset signal VI2 is transmitted to the third node C to reset it, and the first reset signal VI1 is transmitted to the first node P to reset it;

[0055] That is, the above step S1 may include but is not limited to the following steps:

[0056] S11, controlling the first reset transistor, the compensation transistor and the second switch transistor to be turned on, the first reset signal is transmitted to the first node, and the first power signal output by the first power line is transmitted to the drain and the gate of the driving transistor;

[0057] Referring to the discussion of stage t1, it can be seen that the first reset transistor T8 is turned on so that the first reset signal VI1 is transmitted to the first node P to reset it, and the second switch transistor T5 and the compensation transistor T3 are both turned on so that the first power supply signal VDD is transmitted to the drain and gate of the driving transistor T1. The second switch transistor T5;

[0058] Furthermore, the above step S1 may also include but is not limited to the following steps:

[0059] S12, controlling the second reset transistor to be turned on, and transmitting a second reset signal to one of the anode and the cathode of the light emitting element;

[0060] Referring to the discussion of stage t1, it can be known that the second reset transistor T4 is turned on so that the second reset signal VI2 is transmitted to the third node C to reset it;

[0061] In stage t2, the second gate signal Nscan2[i], the third gate signal Nscan1[i], and the fourth gate signal Pscan1[i] are all corresponding effective potentials, thereby controlling the first reset transistor T8, the compensation transistor T3, and the second reset transistor T4 to continue to be turned on, and the third reset transistor T2 is turned on, so the first node P, the second node Q, and the third node C are respectively maintained at the previous reset voltages. At the same time, the source of the driving transistor T1 is reset by the third reset signal VI3 so that the gate-source voltage of the driving transistor T1 is greater than its threshold voltage Vth, so the driving transistor T1 is turned on, and the third reset signal VI3 charges the second node Q through the driving transistor T1 and the compensation transistor T3 to reduce its potential until the driving transistor T1 is turned off, at which time the voltage VQ of the second node Q is VI3+Vth;

[0062] That is, the steps between step S1 and step S2 may include but are not limited to the following steps:

[0063] S13, controlling the third reset transistor to be turned on, transmitting a third reset signal to the other of the source and the drain of the driving transistor to turn on the driving transistor, and reducing the potential of the gate of the driving transistor by the third reset signal until the driving transistor is turned off;

[0064] Referring to the discussion of stage t2, it can be seen that the third reset transistor T2 is turned on, the source of the driving transistor T1 is reset by the third reset signal VI3, and then the driving transistor T1 is turned on and the voltage VQ of the second node Q decreases until the driving transistor T1 is turned off to be VI3+Vth;

[0065] In stage t3, the third gate signal Nscan1[i] and the fifth gate signal Nscan3[i] are both corresponding effective potentials, thereby controlling the second reset transistor T4 to continue to be turned on, and the data write transistor T7 to be turned on, the data signal Data is transmitted to the first node P, and the voltage of the first node P jumps from VI1 to Data. Since the potential of the third node C is maintained at VI2, through the coupling effect of the first capacitor C1, the voltage of the second node Q also jumps to the corresponding proportion in "Data-VI1" based on the original VI3+Vth in accordance with the capacitor series voltage division method. Therefore, the voltage VQ of the second node Q is VI3+Vth+(Data-VI1)*C10 / (Cst0+C10), where C10 and Cst0 are the capacitance values ​​of the first capacitor C1 and the storage capacitor Cst, respectively;

[0066] That is, based on step S13, the above step S2 may include but is not limited to the following steps:

[0067] S21, controlling the data writing transistor to be turned on, the data signal is transmitted to the first node, and through the coupling effect of the first capacitor, the potential of the gate of the driving transistor jumps accordingly;

[0068] Referring to the discussion of stage t3, it can be seen that the data writing transistor T7 is turned on, and through the coupling effect of the first capacitor C1, the voltage VQ of the second node Q becomes VI3+Vth+(Data-VI1)*C10 / (Cst0+C10);

[0069] In stage t4, the first gate signal EM1[i] and the sixth gate signal EM2[i] are both corresponding effective potentials, thereby controlling the second switch transistor T5 and the first switch transistor T6 to be turned on, and a path is formed between the first power line and the cathode of the light-emitting element Di. At this time, the voltage of the source of the driving transistor T1 is approximately equal to the voltage of the third node C, that is, the gate-source voltage of the driving transistor T1 is VQ-VC=VI3+Vth+(Data-VI1)*C10 / (Cst0+C10)-VI2, and the driving current I generated by the driving transistor T1 is I=k×(Vgs-Vth) 2 =k×[VI3+(Data-VI1)×C10 / (Cst0+C10)-VI2] 2 ,Since the driving current is not related to Vth, the Vth compensation function is realized;

[0070] That is, the above step S3 may include but is not limited to the following steps:

[0071] S31, controlling the first switch transistor and the second switch transistor to be turned on, so as to form a path for the drive current to flow between the first power line and the other of the anode and the cathode of the light-emitting element;

[0072] Referring to the discussion of stage t4, it can be known that the second switch transistor T5 and the first switch transistor T6 are turned on, and a driving current I=k×(Vgs-Vth) can be formed. 2 =k×[VI3+(Data-VI1)×C10 / (Cst0+C10)-VI2] 2 .

[0073] Combination Figure 3 and Figure 6 As shown, Figure 3 The sub-pixel 101 shown may include but is not limited to the following working stages:

[0074] In stage t1', the first gate signal EM1[i], the seventh gate signal Pscan3[i], and the third gate signal Nscan1[i] are all corresponding effective potentials, thereby controlling the second switch transistor T5, the first reset transistor T8, the compensation transistor T3, the second reset transistor T4, and the transmission transistor T9 to be turned on. Similarly, in the above stage t1, the first power supply signal VDD is transmitted to the drain and the gate of the driving transistor T1, the second reset signal VI2 is transmitted to the third node C to reset it, and the first reset signal VI1 is transmitted to the first node P to reset it;

[0075] That is, at least on the basis of step S11, the above step S1 may also include but is not limited to the following steps:

[0076] S14, controlling the first reset transistor and the transmission transistor to be turned on, and transmitting the first reset signal to the first node;

[0077] Referring to the discussion of stage t1', it can be seen that the difference from stage t1 is that, since the transmission transistor T9 is provided, the transmission transistor T9 is also turned on at this time, so that the first reset signal VI1 can be transmitted to the first node P to reset it;

[0078] The first reset transistor T8 is turned on so that the first reset signal VI1 is transmitted to the first node P to reset it, and the second switch transistor T5 and the compensation transistor T3 are both turned on so that the first power supply signal VDD is transmitted to the drain and gate of the driving transistor T1. The second switch transistor T5;

[0079] In stage t2', the seventh gate signal Pscan3[i], the third gate signal Nscan1[i], and the fourth gate signal Pscan1[i] are all corresponding effective potentials, thereby controlling the first reset transistor T8, the compensation transistor T3, and the second reset transistor T4 to continue to be turned on, and the third reset transistor T2 is turned on. Similarly to the above stage t2, the voltage VQ of the second node Q is VI3+Vth;

[0080] In stage t3', the third gate signal Nscan1[i] and the eighth gate signal Pscan2[i] are both corresponding effective potentials, thereby controlling the second reset transistor T4 to continue to be turned on, and the data writing transistor T7 and the transmission transistor T9 are both turned on. Similarly, in stage t3, the voltage VQ of the second node Q is VI3+Vth+(Data-VI1)*C10 / (Cst0+C10);

[0081] That is, at least on the basis of step S11, the data writing transistor T7 and the first reset transistor T8 are both low temperature polysilicon transistors, and the transmission transistor T9 is an oxide transistor, the above step S2 may also include but is not limited to the following steps:

[0082] S22, controlling the first reset transistor and the transmission transistor to be turned on, and transmitting the first reset signal to the first node;

[0083] Referring to the discussion of stage t3', it can be seen that the difference from stage t3 is that since the transmission transistor T9 is provided, the transmission transistor T9 is also turned on at this time, so that the data signal Data can be transmitted to the first node P;

[0084] In stage t4', the first gate signal EM1[i] and the sixth gate signal EM2[i] are both at corresponding effective potentials, thereby controlling the second switch transistor T5 and the first switch transistor T6 to be turned on. Similarly, in stage t4, the drive current I=k×(Vgs-Vth) generated by the drive transistor T1 2 =k×[VI3+(Data-VI1)×C10 / (Cst0+C10)-VI2] 2 ,Since the driving current is independent of Vth, the Vth compensation function is realized.

[0085] It should be noted that the present invention only takes the example that all other gate signals except the fifth gate signal Nscan3[i] or the eighth gate signal Pscan2[i] acting on the data writing transistor T7 are at least one-to-two. Figure 5 As shown, the i-th row sub-pixel 101 and the i+1-th row sub-pixel 101 respectively acted upon by the i-th level fifth gate signal Nscan3[i] and the i+1-th level fifth gate signal Nscan3[i+1] are both acted upon by the same set of first gate signal EM1[i], sixth gate signal EM2[i], second gate signal Nscan2[i], third gate signal Nscan1[i], and fourth gate signal Pscan1[i]. For another example Figure 6 As shown, the i-th row sub-pixel 101 and the i+1-th row sub-pixel 101, which are respectively acted upon by the i-th level eighth gate signal Pscan2[i] and the i+1-th level eighth gate signal Pscan2[i+1], are both acted upon by the same set of first gate signals EM1[i], sixth gate signals EM2[i], seventh gate signals Pscan3[i], third gate signals Nscan1[i], and fourth gate signals Pscan1[i].

[0086] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A display panel, characterized in that: The invention comprises a plurality of sub-pixels, wherein the sub-pixels include a light-emitting element and a pixel circuit electrically connected, and the pixel circuit includes: a driving transistor, used for generating a driving current according to a data signal to drive the light-emitting element to emit light, wherein the driving transistor is an oxide transistor, and a gate of the driving transistor is electrically connected to the first node or is connected to the first node through a first capacitor; a data writing transistor, electrically connected to the first node, for transmitting the data signal; The first reset transistor is electrically connected to the first node and is used for transmitting a first reset signal.

2. The display panel according to claim 1, characterized in that: The data writing transistor and the first reset transistor are both oxide transistors.

3. The display panel according to claim 1, characterized in that: The data writing transistor and the first reset transistor are both low temperature polysilicon transistors.

4. The display panel according to claim 3, characterized in that: The pixel circuit further includes: The transmission transistor is electrically connected between the data writing transistor, the first reset transistor and the first node, and the transmission transistor is an oxide transistor.

5. The display panel according to any one of claims 1 to 4, characterized in that: The pixel circuit further includes: A compensation transistor electrically connected between the gate of the driving transistor and one of the source and the drain of the driving transistor; a second reset transistor, electrically connected to one of the anode and the cathode of the light emitting element, and configured to transmit a second reset signal to one of the anode and the cathode of the light emitting element; Wherein, at least one of the compensation transistor and the second reset transistor is an oxide transistor.

6. The display panel according to any one of claims 1 to 4, characterized in that: The pixel circuit further includes: A second capacitor, wherein a first plate of the second capacitor is electrically connected to the first power line, and a second plate of the second capacitor is electrically connected to the first node.

7. The display panel according to any one of claims 1 to 4, characterized in that: The pixel circuit further includes: A first switch transistor electrically connected between the other of the source and the drain of the driving transistor and one of the anode and the cathode of the light emitting element; The third reset transistor is electrically connected to the other of the source and the drain of the driving transistor and the first switch transistor, and is used for transmitting a third reset signal to the other of the source and the drain of the driving transistor.

8. The display panel according to any one of claims 1 to 4, characterized in that: The pixel circuit further includes: The second switch transistor is electrically connected between one of the source and the drain of the driving transistor and the first power line.

9. The display panel according to any one of claims 1 to 4, characterized in that: The pixel circuit further includes: A storage capacitor, wherein a first plate of the storage capacitor is electrically connected to the gate of the driving transistor, and a second plate of the storage capacitor is electrically connected to one of the anode and the cathode of the light emitting element.

10. A method for driving a display panel, characterized in that: The display panel according to any one of claims 1 to 9 comprises: controlling the first reset transistor to be turned on so that the first reset transistor transmits the first reset signal to the first node; Controlling the data writing transistor to be turned on, so that the data writing transistor transmits the data signal to the gate of the driving transistor, so that the driving transistor is turned on; The driving transistor is controlled to generate a driving current according to the data signal to drive the light emitting element to emit light.

11. The method for driving a display panel according to claim 10, wherein: The pixel circuit further includes a compensation transistor and a second switch transistor, wherein the compensation transistor is electrically connected between the gate of the driving transistor and one of the source and the drain of the driving transistor, and the second switch transistor is electrically connected between one of the source and the drain of the driving transistor and the first power line; Wherein, the step of controlling the first reset transistor to be turned on comprises: The first reset transistor, the compensation transistor and the second switch transistor are all controlled to be turned on, the first reset signal is transmitted to the first node, and the first power signal output by the first power line is transmitted to the drain and the gate of the driving transistor.

12. The method for driving a display panel according to claim 11, characterized in that: The pixel circuit further includes a second reset transistor, the second reset transistor being electrically connected to one of the anode and the cathode of the light emitting element; Wherein, the step of controlling the first reset transistor to be turned on further includes: The second reset transistor is controlled to be turned on, and a second reset signal is transmitted to one of the anode and the cathode of the light emitting element.

13. The method for driving a display panel according to claim 12, wherein: The pixel circuit further includes a third reset transistor, the third reset transistor being electrically connected to the other of the source and the drain of the driving transistor and the first switch transistor; Among them, between the step of controlling the first reset transistor to be turned on and the step of controlling the data writing transistor to be turned on, the following steps are included: The third reset transistor is controlled to be turned on, and a third reset signal is transmitted to the other of the source and the drain of the driving transistor to turn on the driving transistor. The potential of the gate of the driving transistor is raised by the third reset signal until the driving transistor is turned off.

14. The method for driving a display panel according to claim 13, wherein: The gate of the driving transistor is connected to the first node through a first capacitor; Wherein, the step of controlling the data writing transistor to be turned on includes: The data writing transistor is controlled to be turned on, the data signal is transmitted to the first node, and through the coupling effect of the first capacitor, the potential of the gate of the driving transistor jumps accordingly.

15. The method for driving a display panel according to any one of claims 11 to 14, characterized in that: The pixel circuit further includes a first switch transistor, the first switch transistor being electrically connected between the other of the source and the drain of the driving transistor and one of the anode and the cathode of the light emitting element; The step of controlling the driving transistor to generate a driving current according to the data signal to drive the light-emitting element to emit light comprises: The first switching transistor and the second switching transistor are both controlled to be turned on, so as to form a path for the drive current to flow between the first power line and the other of the anode and the cathode of the light emitting element.

16. The method for driving a display panel according to any one of claims 11 to 14, characterized in that: The pixel circuit further includes a transfer transistor electrically connected between the data writing transistor, the first reset transistor and the first node; The data writing transistor and the first reset transistor are both low temperature polysilicon transistors, and the transmission transistor is an oxide transistor; Wherein, the step of controlling the first reset transistor to be turned on comprises: The first reset transistor and the transmission transistor are both controlled to be turned on, and the first reset signal is transmitted to the first node.

17. The method for driving a display panel according to any one of claims 11 to 14, characterized in that: The pixel circuit further includes a transfer transistor electrically connected between the data writing transistor, the first reset transistor and the first node; The data writing transistor and the first reset transistor are both low temperature polysilicon transistors, and the transmission transistor is an oxide transistor; The step of controlling the data writing transistor to be turned on comprises: The data writing transistor and the transmission transistor are both turned on, and the data writing transistor transmits the data to the gate of the driving transistor.

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