Cascade error correction coding method and device, and storage medium

Abstract

The invention discloses a cascading error correction coding method and device and a storage medium, relates to the technical field of error correction coding, and solves the technical problem that the transmission rate of information is reduced due to the fact that redundant information is added to a traditional cascading code in a communication scene with a small data size. The method comprises the following steps: carrying out Viterbi decoding on a soft decision result of received information to obtain a decoding bit sequence; performing cyclic redundancy check on the decoding bit sequence; if not, performing convolutional code coding on the decoding bit sequence to obtain a coding bit sequence; obtaining a high-frequency error pattern, and correcting the decoding bit sequence according to the high-frequency error pattern; performing cyclic redundancy check on the decoded bit sequence after error correction; and if the error-corrected decoding bit sequence and / or the decoding bit sequence passes the cyclic redundancy check, ending the cascade error correction coding. According to the invention, efficient and reliable transmission of information can be ensured in a communication scene with a small data volume.

Description

Technical Field

[0001] The present invention relates to the technical field of error correction coding, and in particular to a cascade error correction coding method, device and storage medium. Background Art

[0002] In modern communication systems, the reliability of data transmission is crucial. Due to the influence of factors such as channel noise and interference, errors often occur in the data at the receiving end. In order to improve the anti-interference ability of the system, error correction coding technology is widely used in the field of communication. The basic principle of error correction coding is to detect and correct errors in the transmission process by introducing redundant information, but this comes at the cost of reducing the information transmission rate. Therefore, the core goal of studying error correction coding is to improve the error detection and correction capabilities while minimizing redundancy.

[0003] Traditional error correction coding methods (such as linear block codes and convolutional codes) usually need to increase the code length (such as increasing the code length n of block codes or the information length k of convolutional codes) to further improve performance. However, the increase in code length will lead to a sharp increase in encoding and decoding complexity, even beyond the acceptable range of actual systems. To solve this problem, cascade code technology came into being. Cascade codes combine two or more coding methods (such as series or parallel) to achieve higher error correction performance while maintaining low complexity.

[0004] At present, convolutional code + RS (Reed-Solomon) code is a widely used cascade code scheme. In this scheme, RS coding is usually in the form of RS (8+k, k) or RS (16+k, k), resulting in 8 or 16 bytes of redundancy in the encoded data compared to when only convolutional code is used. Although this scheme can effectively improve the error correction capability, for communication scenarios with small data volumes (such as small data packets of only a few dozen bytes), the introduction of redundant information will significantly reduce the information transmission rate and affect communication efficiency.

[0005] In the process of implementing the present invention, the inventors found that there are at least the following problems in the prior art: For communication scenarios with smaller data volumes, traditional concatenated codes will increase redundant information, resulting in a decrease in the information transmission rate. Summary of the invention

[0006] The purpose of the present invention is to provide a cascade error correction coding method, device and storage medium to solve the technical problem in the prior art that for communication scenarios with small data volumes, traditional cascade codes increase redundant information, resulting in a decrease in the transmission rate of information.

[0007] The various technical effects that can be produced by the preferred technical solutions among the various technical solutions provided by the present invention are described in detail below.

[0008] To achieve the above object, the present invention provides the following technical solutions: The present invention provides a cascade error correction coding method, comprising the following steps: performing Viterbi decoding on the soft decision result of received information to obtain a decoded bit sequence; performing a cyclic redundancy check on the decoded bit sequence; if the decoded bit sequence fails the cyclic redundancy check, performing convolutional coding on the decoded bit sequence to obtain a coded bit sequence; obtaining a high-frequency error pattern, and correcting the decoded bit sequence according to the high-frequency error pattern; wherein the high-frequency error pattern includes a decoding error pattern of the decoding bit sequence and a coding error pattern of the coding bit sequence; performing a cyclic redundancy check on the decoded bit sequence after error correction; if the decoded bit sequence after error correction and / or the decoded bit sequence pass the cyclic redundancy check, then terminating the cascade error correction coding.

[0009] Optionally, the step of obtaining a high-frequency word error pattern of the decoding bit sequence and correcting the decoding bit sequence according to the high-frequency error pattern includes: obtaining a decoding error pattern of the decoding bit sequence and a coding bit sequence of the coding bit sequence; wherein the error bits in the decoding error pattern correspond one-to-one to the error bits in the coding error pattern; detecting the sequence number yi of the minimum value and the sequence number yj of the second minimum value in the coding bit sequence according to the coding error pattern; performing a cyclic redundancy check on the yi-th bit of the decoding bit sequence and the decoding error pattern after performing modulo-2 addition error correction; if the cyclic redundancy check passes, terminating the cascade error correction coding; otherwise, performing a modulo-2 addition error correction on the yj-th bit of the decoding bit sequence and the decoding error pattern.

[0010] Optionally, after performing modulo-2 addition error correction on the yj-th bit of the decoded bit sequence and the error pattern, a cyclic redundancy check is performed. If the cyclic redundancy check fails, error correction is performed on the next decoded bit sequence until error correction is completed on all the decoded bit sequences.

[0011] Optionally, detecting the minimum value subscript yi and the second minimum value subscript yj in the coding bit sequence according to the coding error pattern includes: performing sliding multiplication on the coding error pattern and the coding bit sequence and summing them to obtain a convolution sequence; calculating the sequence number of the minimum value and the sequence number of the second minimum value of the convolution sequence; and using the sequence number of the minimum value and the sequence number of the second minimum value of the convolution sequence as the sequence number yi and the sequence number yj of the minimum value of the coding bit sequence, respectively.

[0012] Optionally, after performing convolutional coding on the decoded bit sequence to obtain a coded bit sequence, the method further includes: mapping the coded bit sequence to obtain a mapping sequence; and performing point multiplication of the soft decision result and the mapping sequence to obtain the preprocessed coded bit sequence.

[0013] Optionally, mapping the coded bit sequence to obtain a mapping sequence includes: mapping "1" in the coded bit sequence to "+1" and "0" to "-1" to obtain the mapping sequence consisting of "+1" and "-1".

[0014] Optionally, the decoding error pattern of the decoding bit sequence is obtained through a Viterbi decoder; and the encoding error pattern of the encoding bit sequence is obtained through a convolutional encoder.

[0015] Optionally, in performing Viterbi decoding on the soft decision result of the received information to obtain a decoded bit sequence, soft decision Viterbi decoding is adopted and the decoding depth is 16.

[0016] A terminal device comprises: a decoding module, used for performing Viterbi decoding on the soft decision result of received information to obtain a decoded bit sequence; a check module, used for performing cyclic redundancy check on the decoded bit sequence or the decoded bit sequence after error correction; an encoding module, used for performing convolutional code encoding on the decoded bit sequence to obtain a coded bit sequence; and an error correction module, used for obtaining a high-frequency error pattern and correcting the decoded bit sequence according to the high-frequency error pattern.

[0017] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements any of the steps of the cascade error correction coding method described above.

[0018] Implementing one of the above technical solutions of the present invention has the following advantages or beneficial effects: The cascade error correction coding method provided by the present invention significantly reduces the system's requirements for the signal-to-noise ratio without increasing coding redundancy by utilizing the high-frequency error pattern classification after Viterbi decoding and combining it with the dynamic verification of the cyclic redundancy check. The method is particularly suitable for communication scenarios with a small amount of data and can ensure efficient and reliable transmission of information. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. It is obvious that the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work. In the drawings: Figure 1 is a flow chart of a cascade error correction coding method according to an embodiment of the present invention; Figure 2 is a diagram showing the proportion of decoding error patterns in the first embodiment of the present invention; Figure 3 is a flowchart of step S3 of the cascade error correction coding method according to an embodiment of the present invention; Figure 4 1 is a diagram showing the simulation results of the bit error rate BER of the first embodiment of the present invention; Figure 5 is a simulation result diagram of the packet error rate PER of the first embodiment of the present invention; Figure 6 It is a structural block diagram of a terminal device according to the second embodiment of the present invention. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of the present invention clearer, the various exemplary embodiments to be described below will refer to the corresponding drawings, which constitute a part of the exemplary embodiments, wherein various exemplary embodiments that may be used to implement the present invention are described. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation methods described in the following exemplary embodiments do not represent all implementation methods consistent with the present disclosure. It should be understood that they are only examples of processes, methods, devices, etc. that are consistent with some aspects of the present disclosure as detailed in the attached claims, and other embodiments may also be used, or the embodiments listed herein may be modified in structure and function without departing from the scope and essence of the present invention.

[0021] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", etc. indicate the orientation or positional relationship based on the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the elements referred to must have a specific orientation, be constructed and operated in a specific orientation. The terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. The term "multiple" means two or more. The terms "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, an integral connection, a mechanical connection, an electrical connection, a communication connection, a direct connection, an indirect connection through an intermediate medium, and can be the internal connection of two elements or the interaction relationship between two elements. The term "and / or" includes any and all combinations of one or more related listed items. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0022] In order to illustrate the technical solution of the present invention, a specific embodiment is used below for description, and only the parts related to the embodiment of the present invention are shown.

[0023] Embodiment 1: like Figure 1 As shown, the present invention provides a cascade error correction coding method, comprising the following steps: S1, performing Viterbi decoding on the soft decision result of the received information to obtain a decoded bit sequence; S2, performing a cyclic redundancy check on the decoded bit sequence; if the decoded bit sequence fails the cyclic redundancy check, performing convolutional coding on the decoded bit sequence to obtain a coded bit sequence; S3, obtaining a high-frequency error pattern, and correcting the decoded bit sequence according to the high-frequency error pattern; wherein the high-frequency error pattern includes a decoding error pattern of the decoding bit sequence and an encoding error pattern of the encoding bit sequence; S4, performing a cyclic redundancy check on the decoded bit sequence after error correction; if the decoded bit sequence after error correction and / or the decoded bit sequence passes the cyclic redundancy check, the cascade error correction coding is terminated.

[0024] The cascade error correction coding method provided in this embodiment significantly reduces the system's requirements for the signal-to-noise ratio without increasing coding redundancy by utilizing the high-frequency error pattern classification after Viterbi decoding and combining it with the dynamic verification of the cyclic redundancy check. It is particularly suitable for communication scenarios with small data volumes and can ensure efficient and reliable transmission of information.

[0025] Next, combine Figures 1 to 5 , to introduce in detail the specific implementation steps of the cascade error correction coding method provided by this embodiment: First, execute step S1, perform Viterbi decoding on the soft decision result of the received information, and obtain a decoded bit sequence. Soft decision means that the demodulator not only outputs the most likely bit value corresponding to each symbol, but also outputs the confidence information that the symbol belongs to each possible bit value. This output result with confidence information is the soft decision result of the received information. Compared with hard decision (only outputting the most likely bit value), soft decision retains more signal information, which helps to improve the error correction performance in the subsequent decoding process.

[0026] Viterbi decoding is a maximum likelihood decoding algorithm, commonly used for decoding convolutional codes. Its basic principle is to find a path in the grid graph so that the metric value (usually Hamming distance or Euclidean distance) between this path and the received soft decision result is the smallest. During the decoding process, the Viterbi algorithm will continuously extend, compare and backtrack the path, and gradually select the most likely path by calculating and comparing the metric values ​​of different paths. After Viterbi decoding, the optimal path found in the grid graph corresponds to the originally sent bit sequence. This sequence is the decoded bit sequence, which is the recovery of the original information at the sender.

[0027] Assume that the transmitter sends a string of binary information (i.e., received information). After transmission through the channel, the receiver obtains a signal interfered by noise. The receiver first makes a soft decision to obtain the confidence value of each symbol being "0" or "1". Then, the Viterbi decoding algorithm is used to find the optimal path in the grid diagram based on these confidence values. The binary sequence finally extracted from this optimal path is the decoded bit sequence.

[0028] Preferably, in this step, soft decision Viterbi decoding is used to decode the soft decision result of the received information, and the decoding depth is 16. Soft decision Viterbi decoding can more accurately reflect the possibility of sending a signal, thereby effectively reducing the bit error rate and improving the reliability of communication. Decoding depth is a key parameter in Viterbi decoding. The decoding depth is not too deep or too shallow. Setting the decoding depth to 16 can guarantee the decoding performance to a certain extent without making the computational complexity and delay too high.

[0029] Then, execute step S2, perform a cyclic redundancy check on the decoded bit sequence; if the decoded bit sequence does not pass the cyclic redundancy check, perform convolutional coding on the decoded bit sequence to obtain a coded bit sequence; if it passes the cyclic redundancy check, the cascade error correction coding is terminated. Cyclic redundancy check (CRC) is an error checking code with a data transmission error detection function. In this embodiment, a cyclic redundancy check is used to detect whether there are still error bits in the decoded bit sequence to ensure the integrity and reliability of the data. If there are error bits, convolutional coding is performed to prepare for subsequent error correction. If the cyclic redundancy check is passed, it means that there are no error bits in the decoded sequence.

[0030] As an optional implementation, after performing convolutional coding on the decoded bit sequence to obtain the coded bit sequence, the method further includes: mapping the coded bit sequence to obtain a mapping sequence; performing point multiplication of the soft decision result and the mapping sequence to obtain a preprocessed coded bit sequence. In the subsequent steps, the preprocessed coded bit sequence is used. Specifically, mapping the coded bit sequence to obtain a mapping sequence includes: mapping "1" in the coded bit sequence to "+1" and "0" to "-1" to obtain a mapping sequence composed of "+1" and "-1". In signal processing, it is more convenient to use "+1" and "-1" for calculations than using "0" and "1" because they can directly participate in multiplication and addition operations, avoiding additional logical conversions to improve signal processing efficiency.

[0031] Next, execute step S3, obtain a high-frequency error pattern, and correct the decoded bit sequence according to the high-frequency error pattern. During the information transmission or storage process, data may be erroneous. An error pattern refers to a specific pattern in which errors occur in the data. High-frequency error patterns are those error patterns that occur frequently. By performing statistical analysis on a large amount of decoded data, error patterns with a higher frequency of occurrence can be found. After obtaining the high-frequency error pattern, it is applied to the decoded bit sequence that needs to be processed currently. By comparing the decoded bit sequence with the known high-frequency error pattern, the position where the error may exist is identified, and then these errors are corrected according to the pre-set error correction rules, thereby improving the accuracy of decoding.

[0032] After the received information is decoded by Viterbi, if there are still error bits, there are some high-frequency error patterns in these error bits. Find these possible error patterns and use CRC check to achieve cascade error correction. The following simulation analysis is performed under the AWGN channel (abbreviation of Additive White Gaussian Noise, AWGN channel is additive white Gaussian noise channel, which is an idealized communication channel model), using BPSK modulation, the channel signal-to-noise ratio is set to [0, 0.5, 1.0, 1.5, 2.0, 2.5] dB, using (15, 17) convolutional code, soft decision Viterbi decoding, decoding depth of 16, and using a 100-byte data packet: First, the number of error bits after Viterbi decoding is analyzed: when the signal-to-noise ratio SNR is [0, 0.5, 1.0, 1.5, 2.0, 2.5] dB respectively, after Viterbi decoding, the number of data packets P14 with 1 to 4 error bits in the number of all data packets containing error bits Pall, the proportion P14 / Pall is [64.37%, 79.10%, 87.47%, 94.70%, 97.47%, 100%] respectively, among which the proportion is 64.37% when SNR=0dB, 79.10% when SNR=0.5dB, 87.47% when SNR=1.0dB, 94.70% when SNR=1.5dB, 97.47% when SNR=2.0dB, and 100% when SNR=2.5dB. Therefore, in most cases, the number of error bits of a data packet after Viterbi decoding is within 4. Correcting the data packets with 1 to 4 error bits can significantly improve system performance.

[0033] Then, the decoding error pattern of the decoded bit sequence is obtained through the Viterbi decoder, and the decoding error pattern after Viterbi decoding is analyzed: In all decoding error patterns with 1 to 4 error bits in the decoded bit sequence, such as Figure 2As shown, the proportion of decoding error patterns with 1 error bit is 16.61%.

[0034] The proportions of decoding error patterns with 2 error bits are [37.46%, 2.83%, 0.36%, 0.80%] respectively, among which the proportion of decoding error pattern

[11] is 37.46%; the proportion of decoding error pattern

[101] is 2.83%; the proportion of decoding error pattern

[1001] is 0.36%; the proportion of decoding error pattern [10…01] is 0.80%; the "0…0" in [10…01] indicates that there are more than or equal to 3 "0". Taking the decoding error pattern

[1001] as an example, the 2 "1"s indicate that there are 2 error bits, and the middle "00" indicates that there are 2 bits between the first error bit and the second error bit.

[0035] The proportions of decoding error patterns with 3 error bits are [9.87%, 9.67%, 0.66%, 0.13%, 0.80%, 2.61%, 0.43%, 0.52%] respectively, among which the proportion of decoding error patterns of

[111] is 9.87%; the proportion of decoding error patterns of

[1101] is 9.67%; the proportion of decoding error patterns of [110…01] and [10…011] is 2.61%; the proportion of decoding error patterns of [11 "0…01" and "10…011" in the decoding error pattern indicate that there are three or more "0"s; the decoding error pattern of

[11001] accounts for 0.66%; the decoding error pattern of

[1011] accounts for 0.13%; the decoding error pattern of

[10011] accounts for 0.80%; the decoding error pattern of

[10101] accounts for 0.43%; and 0.52% is the proportion of other decoding error patterns with three error bits. Taking the decoding error pattern

[10011] as an example, the three "1"s indicate that there are three error bits, the middle "00" indicates that there are two bits between the first error bit and the second error bit, and the following "11" indicates that the second error bit and the third error bit are consecutive.

[0036] The proportions of decoding error patterns with 4 error bits are [2.77%, 0.11%, 2.54%, 2.55%, 2.80%, 0.23%, 0.63%, 2.63%, 0.21%, 0.74%, 2.03%] respectively, among which the proportion of decoding error patterns of

[1111] is 2.77%; the proportion of decoding error patterns of [110011] is 2.54%; the proportion of decoding error patterns of [110…011] is 2.55%; the "0…0" in [110…011] means that there are more than or equal to 3 "0"s; the proportion of decoding error patterns of

[11101] is 2.80%; the proportion of decoding error patterns of [110101] is 2.63%; and 2.03% is The proportion of other decoding error patterns with 4 error bits; the proportion of decoding error patterns of

[11011] is 0.11%; the proportion of decoding error patterns of [111001] is 0.23%, the proportion of decoding error patterns of [1110…01] and [10…0111] is 0.63%, and the "0…0" in [1110…01] and [10…0111] means that there are more than or equal to 3 "0"s; the proportion of decoding error patterns of [1101001] is 0.21%; the proportion of decoding error patterns of [11010…01] and [10…01101] is 0.74%, and the "0…0" in [11010…01] and [10…01101] means that there are more than or equal to 3 "0"s. Taking the decoding error pattern [1101001] as an example, the 4 "1"s indicate that there are 4 error bits, the first "11" indicates that the first error bit and the second error bit are consecutive, the middle "0" indicates that there is a 1-bit interval between the second error bit and the third error bit, and the middle "00" indicates that there are 2 bits between the third error bit and the fourth error bit.

[0037] According to the above statistical results, there are 11 high-frequency error patterns that can be used for cascade error correction and account for more than 2%, as shown in Table 1: Table 1 High frequency error patterns for cascaded error correction Then, the error bits mentioned above need to be corrected. The decoded bit sequence is convolutionally encoded, and the encoding error pattern of the encoded bit sequence is obtained through the convolution encoder. If there is one error bit in the decoded bit sequence, the encoder will output multiple error bits from the time the error bit enters the convolution encoder to the time it moves out of the convolution encoder, and there is a fixed encoding error pattern. Taking the (15, 17) convolutional code as an example, the decoding error pattern EV after Viterbi decoding corresponds to the encoding error pattern EO output by the convolution encoder. The corresponding relationship is shown in Table 2: Table 2 Correspondence between decoding error pattern EV and encoding error pattern EO According to the above correspondence, the decoding error pattern EV and its starting position EV_i can be determined by detecting the coding error pattern EO, and then the decoding bit sequence and the decoding error pattern EV are modulo-2 added (also called XOR, a binary operation) starting from the EV_ith bit of the decoding bit sequence, and then a CRC check is performed. If the check passes, the error correction is successful. Figure 3 As shown, specifically, step S3 includes: S31. Obtain the decoding error pattern of the decoding bit sequence and the coding bit sequence of the coding bit sequence; wherein the error bits in the decoding error pattern correspond one to one with the error bits in the coding error pattern; S32. Detect the sequence number yi of the minimum value and the sequence number yj of the second minimum value in the coding bit sequence according to the coding error pattern; yi and yj are the possible positions of the error bits. S33. Perform modulo-two addition error correction on the yi-th bit of the decoding bit sequence and the decoding error pattern, and then perform a cyclic redundancy check; if the cyclic redundancy check passes, the cascade error correction coding is terminated; otherwise, perform modulo-two addition error correction on the yj-th bit of the decoding bit sequence and the decoding error pattern. If the check passes, it means that the error correction of all decoding bit sequences has been completed.

[0038] If the cyclic and redundancy check fails, the next decoded bit sequence is corrected until all decoded bit sequences are corrected. For example, to correct a 1-bit error: first detect the position of the error bit in the decoding error pattern EV=[1], that is, the minimum value sequence number yi and the second minimum value sequence number yj in the corresponding coding bit sequence; then correct the 1-bit error: first add the yi-th bit of the decoding bit sequence to the decoding error pattern EV=[1] modulo 2, and perform a CRC check. If the check passes, the error correction ends; if the check fails, add the yj-th bit of the decoding bit sequence to the decoding error pattern EV=[1] modulo 2, and perform a CRC check. If the check passes, the error correction ends; if the check fails, the next decoding bit sequence is corrected.

[0039] Assume that the next decoded bit sequence is to correct a 2-bit error. Similarly, to correct a 2-bit error, first detect the position of the error bit in the decoding error pattern EV=

[11] , use modulo-2 addition to correct the yi-th bit, and perform a CRC check. If the check passes, the error correction is terminated. Otherwise, correct the yj-th bit and perform a CRC check. If the check passes, the error correction is terminated. Otherwise, use the same method to correct the next decoded bit sequence until all decoded bit sequences with 1 to 4 error bits are corrected.

[0040] Further, step S32 includes: sliding multiplying the coding error pattern and the coding bit sequence and summing them to obtain a convolution sequence; calculating the sequence number of the minimum value and the sequence number of the second minimum value of the convolution sequence; using the sequence number of the minimum value and the sequence number of the second minimum value of the convolution sequence as the sequence number yi of the minimum value and the sequence number yj of the second minimum value of the coding bit sequence respectively. By processing and analyzing the convolution coding bit sequence, the position of the error bit in the decoded bit sequence is found, so as to facilitate error correction of the error bit.

[0041] Finally, execute step S4, perform a cyclic redundancy check on the decoded bit sequence after error correction; if the decoded bit sequence after error correction and / or the decoded bit sequence passes the cyclic redundancy check, the cascade error correction coding is terminated. In step S3, most of the decoded bit sequences with error bits have been corrected, and the error correction method does not increase the coding redundancy, and can significantly improve the performance while keeping the information transmission rate unchanged. Since in step S3, all the decoded bit sequences with 1 to 4 error bits have been corrected, and the proportion of decoded bit sequences with 1 to 4 error bits is relatively large, error correction of the decoded bit sequence with 1 to 4 error bits can significantly improve the communication quality, so if it fails to pass the check after error correction, it means that only individual error bits exist, which will not affect the system performance.

[0042] This embodiment uses (15, 17) convolutional code and CRC16 (16-bit cyclic redundancy check) cascade error correction. Under the AWGN channel, BPSK modulation, soft-decision Viterbi decoding, and decoding depth of 16 are adopted to simulate data packets of 50 bytes, 100 bytes, and 200 bytes in length, respectively, and the bit error rate BER and packet error rate PER are statistically compared with the error correction using only (15, 17) convolutional code. The results are as follows: Figure 4 and Figure 5 As shown in the figure, it can be seen that compared with using only (15, 17) convolutional code for error correction, the convolutional code + CRC cascade error correction has lower requirements for the signal-to-noise ratio SNR: when the bit error rate BER=1.0e-5, the SNR is about 0.7dB lower; when the packet error rate BER=10%, the SNR is about 0.6dB lower; when the packet error rate PER=1%, the SNR is about 0.8dB lower.

[0043] Embodiment 2: like Figure 6As shown, the present invention also provides a terminal device, including: a decoding module 1, used to perform Viterbi decoding on the soft decision result of the received information to obtain a decoded bit sequence; a check module 2, used to perform cyclic redundancy check on the decoded bit sequence or the decoded bit sequence after error correction; an encoding module 3, used to perform convolution code encoding on the decoded bit sequence to obtain a coded bit sequence; an error correction module 4, used to obtain a high-frequency error pattern, and correct the decoded bit sequence according to the high-frequency error pattern.

[0044] The terminal device provided in this embodiment adopts the cascaded error correction decoding method provided in Example 1 for decoding, which significantly reduces the system's requirements for the signal-to-noise ratio without increasing the coding redundancy. It is particularly suitable for communication scenarios with small data volumes and can ensure efficient and reliable transmission of information.

[0045] Embodiment three: Based on the same inventive concept, the third embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, the steps of any method of the cascade error correction coding method described in the first embodiment above are implemented.

[0046] The above description is only the preferred embodiment of the present invention. It is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application belong to the protection scope of the present invention.

Claims

1. A cascade error correction coding method, characterized in that: The following steps are involved: Perform Viterbi decoding on the soft decision result of the received information to obtain a decoded bit sequence; Performing a cyclic redundancy check on the decoded bit sequence; if the decoded bit sequence fails the cyclic redundancy check, performing convolutional coding on the decoded bit sequence to obtain a coded bit sequence; Acquire a high-frequency error pattern, and perform error correction on the decoded bit sequence according to the high-frequency error pattern; wherein the high-frequency error pattern includes a decoding error pattern of the decoded bit sequence and an encoding error pattern of the encoding bit sequence; Performing a cyclic redundancy check on the decoded bit sequence after error correction; If the decoded bit sequence after error correction and / or the decoded bit sequence passes the cyclic redundancy check, the cascade error correction coding is terminated.

2. A cascade error correction coding method according to claim 1, characterized in that: The obtaining of the high-frequency word error pattern of the decoded bit sequence and performing error correction on the decoded bit sequence according to the high-frequency error pattern comprises: Acquire a decoding error pattern of the decoding bit sequence and a coding bit sequence of the coding bit sequence; wherein the error bits in the decoding error pattern correspond one-to-one to the error bits in the coding error pattern; Detecting the sequence number yi of the minimum value and the sequence number yj of the second minimum value in the coded bit sequence according to the coding error pattern; After performing modulo-2 addition error correction on the yi-th bit of the decoding bit sequence and the decoding error pattern, a cyclic redundancy check is performed; if the cyclic redundancy check passes, the cascade error correction coding is terminated; otherwise, performing modulo-2 addition error correction on the yj-th bit of the decoding bit sequence and the decoding error pattern.

3. A cascade error correction coding method according to claim 2, characterized in that: After performing modulo-2 addition error correction on the yjth bit of the decoded bit sequence and the error pattern, a cyclic redundancy check is performed. If the cyclic redundancy check fails, error correction is performed on the next decoded bit sequence until error correction is completed on all the decoded bit sequences.

4. A cascade error correction coding method according to claim 2, characterized in that: The detecting the minimum value subscript yi and the second minimum value subscript yj in the coded bit sequence according to the coded error pattern comprises: Sliding multiplication of the coding error pattern and the coding bit sequence and summing the results to obtain a convolution sequence; Calculate the sequence number of the minimum value and the sequence number of the second minimum value of the convolution sequence; The sequence number of the minimum value and the sequence number of the second minimum value of the convolution sequence are respectively used as the sequence number yi of the minimum value and the sequence number yj of the second minimum value of the coded bit sequence.

5. The cascade error correction coding method according to claim 1, characterized in that: After performing convolutional coding on the decoded bit sequence to obtain a coded bit sequence, the method further includes: Mapping the coded bit sequence to obtain a mapping sequence; The soft decision result is point-multiplied by the mapping sequence to obtain the preprocessed coded bit sequence.

6. A cascade error correction coding method according to claim 5, characterized in that: Mapping the coded bit sequence to obtain a mapping sequence includes: The "1" in the coded bit sequence is mapped to "+1", and the "0" is mapped to "-1", so as to obtain the mapping sequence consisting of "+1" and "-1".

7. A cascade error correction coding method according to claim 1, characterized in that: The decoding error pattern of the decoding bit sequence is obtained through a Viterbi decoder; and the encoding error pattern of the encoding bit sequence is obtained through a convolutional encoder.

8. A cascade error correction coding method according to claim 1, characterized in that: In performing Viterbi decoding on the soft decision result of the received information to obtain a decoded bit sequence, soft decision Viterbi decoding is adopted, and the decoding depth is 16.

9. A terminal device, characterized in that: include: A decoding module, used for performing Viterbi decoding on the soft decision result of the received information to obtain a decoded bit sequence; A check module, used for performing a cyclic redundancy check on the decoded bit sequence or the decoded bit sequence after error correction; An encoding module, used for performing convolutional coding on the decoded bit sequence to obtain an encoded bit sequence; The error correction module is used to obtain a high-frequency error pattern and perform error correction on the decoded bit sequence according to the high-frequency error pattern.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of a cascade error correction coding method as claimed in any one of claims 1 to 8 are implemented.

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