Decoding apparatus and decoding method for decoding operation in channel coding

Abstract

The present disclosure relates to a decoding apparatus and a decoding method for decoding operations in channel coding. The decoding method comprises sequentially determining a series of source bits from a codeword by performing a first decoding operation and a second decoding operation. For example, a series of N source bits can be divided into a first bit group comprising X source bits and a second bit group comprising Y source bits. The first X source bits are sequentially determined in the first decoding operation and the remaining Y source bits are sequentially determined in the second decoding operation. The first decoding operation comprises sorting at least 2L reliability values calculated from L bit sequences, where L is an integer greater than 0. The second decoding operation comprises determining a source bit in each of the L bit sequences based on the at least 2L reliability values.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0023841 filed on February 26, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present inventive concept relates to channel coding, and more particularly, to an apparatus and method for codeword decoding operations. Background Art

[0004] Communication systems provide the ability to transmit information between wireless devices, such as between a base station and a user equipment (UE). In such communication systems, channel coding techniques can be performed by a transmitting device and a receiving device, where the transmitting device encodes a signal for transmission and the receiving device decodes the received signal. For example, a transmitting device can use channel coding techniques to encode information, such as a bit stream, into a codeword, which can then be sent to another wireless device. The receiving device can receive the transmitted signal and can use channel coding techniques to decode the codeword and detect and / or correct any errors in the received signal. Thus, codewords are used to provide more robust communication between wireless devices and reduce errors in the communication system.

[0005] In some examples, channel coding adds redundant bits to the bit stream to increase the reliability of the signal to prevent any information loss during transmission. For example, the transmitting device can encode the data to be sent (payload) together with the redundant bits into a codeword that is longer than the payload. After sending, the receiving device can decode the received codeword. Therefore, if there is noise or interference in the channel that causes any ambiguity or partial information loss, the receiving device can obtain the coded data (payload) due to channel coding (for example, due to the redundancy of the coding scheme). In some examples, the transmitting device and the receiving device can perform such encoding and decoding operations at high speed and as efficiently as possible to increase channel throughput and reduce the cost of encoding and decoding operations (for example, delay, power consumption, etc.).

[0006] As wireless communication systems evolve (e.g., with the development of fifth-generation new radio (5G NR) technology), it is desirable to improve the performance and efficiency of channel coding. Therefore, there is a need in the art for performing channel coding operations with higher performance to improve the performance of communication systems and reduce the demands on wireless devices. Summary of the Invention

[0007] The present inventive concept provides a decoding apparatus and a decoding method, which can simultaneously provide high performance and high efficiency in channel coding.

[0008] According to an aspect of the inventive concept, there is provided a decoding method for sequentially determining a series of source bits from a codeword. The method comprises a first decoding operation for sequentially determining a first X number of source bits in the series of source bits, and a second decoding operation for sequentially determining a remaining Y number of source bits in the series of source bits. The first decoding operation comprises sorting at least 2L reliability values computed from L bit sequences, where L is an integer greater than 0. The second decoding operation comprises determining a source bit in each of the L bit sequences based on the at least 2L reliability values.

[0009] According to another aspect of the inventive concept, there is provided an apparatus for polar decoding configured to sequentially determine a series of source bits from a codeword encoded based on a polar code. The apparatus comprises a reliability calculator configured to compute at least 2L reliability values from L bit sequences, where L is an integer greater than 0, a first processing circuit configured to sort the at least 2L reliability values and generate a first L number of new bit sequences respectively corresponding to L higher reliability values, a second processing circuit configured to determine a source bit in each of the L bit sequences based on the at least 2L reliability values and generate a second L number of new bit sequences, and a selection circuit configured to select one of the first processing circuit and the second processing circuit based on an index of a source bit included in the series of source bits.

[0010] According to another aspect of the inventive concept, there is provided a polar decoding method of obtaining a series of source bits from a codeword encoded based on a polar code. The method comprises a first decoding operation in which source bits included in a first bit group are sequentially determined from the codeword based on a successive cancellation list (SCL) decoding scheme. The method further comprises a second decoding operation in which source bits included in a second bit group are sequentially determined from the codeword based on a successive cancellation (SC) decoding scheme. The first bit group includes earliest determined source bits, and the second bit group includes latest determined source bits.

[0011] According to another aspect of the inventive concepts, a decoding method for sequentially determining a series of source bits from a codeword is provided. The method includes determining a plurality of reliability values, wherein the reliability values are determined based on a plurality of bit sequences. The method also includes ordering the reliability values and decoding a first set of source bits based on the ordered reliability values. The method also includes determining source bits in each of the plurality of bit sequences and decoding a second set of source bits based on the determined source bits in each of the plurality of bit sequences, wherein a source data block includes the second set of source bits and the first set of source bits. BRIEF DESCRIPTION OF DRAWINGS

[0012] Embodiments of the inventive concepts will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 is a block diagram of a communication system including a transmitter and a receiver according to example embodiments;

[0014] Figure 2 is a flowchart of an example of a decoding method according to example embodiments;

[0015] Figure 3 is a diagram of an example of source data formed using a decoding method according to example embodiments;

[0016] Figure 4A is a flowchart of an example of a decoding method according to example embodiments;

[0017] Figure 4B is a diagram of an example of a decoding tree formed using a decoding method according to example embodiments;

[0018] Figure 5A is a flowchart of an example of a decoding method according to example embodiments;

[0019] Figure 5B is a diagram of an example of a decoding tree formed using a decoding method according to example embodiments;

[0020] Figure 6A is a flowchart of an example of a decoding method according to example embodiments;

[0021] Figure 6B is a diagram of an example of a decoding tree formed using a decoding method according to example embodiments;

[0022] Figure 7A is a flowchart of an example of a decoding method according to example embodiments;

[0023] Figure 7Bis a diagram of an example of a decoded tree formed using a decoding method according to an example embodiment;

[0024] Figure 8 is a flowchart of an example of a decoding method according to an example embodiment;

[0025] Figure 9 is a flowchart of an example of a decoding method according to an example embodiment;

[0026] Figure 10 is a block diagram of an example of a decoder according to an example embodiment;

[0027] Figure 11 is a block diagram of an example of a selection circuit according to an example embodiment;

[0028] Figure 12 is a flowchart of an example of a decoding method according to an example embodiment; and

[0029] Figure 13 is a block diagram of a data processor according to an example embodiment. DETAILED DESCRIPTION

[0030] Various decoding processes have been developed for fifth generation new radio (5G NR) communications. In some cases, less complex (e.g., less computationally intensive) channel coding techniques can be associated with lower reliability, while more complex channel coding techniques can require higher computational intensity, but can be associated with improved reliability (e.g., fewer decoding errors at a receiver).

[0031] The present disclosure relates generally to an improved decoding method. In particular, embodiments of the present disclosure relate to channel coding techniques that enable more efficient or less computationally intensive decoding of data while maintaining reliable decoding performance.

[0032] Embodiments of the present disclosure sequentially determine source bits of a codeword through a list decoding scheme and a decision decoding scheme. In some cases, the decision decoding scheme can have lower complexity and be more cost effective than the list decoding scheme (e.g., but the decision decoding scheme can be associated with a relatively higher block error rate). However, as the source bits of a received codeword are sequentially determined, decoding reliability can gradually increase. For example, as the number of determined source bits increases, the disparity between reliability values of candidates can increase in subsequent determinations, and candidates having high reliability values can be determined as source bits. Based on using the decision decoding scheme later in the decoding process where decoding reliability is higher, techniques described herein can allow for effectively balancing sequentially determining source bits of a codeword through both the list decoding scheme and the decision decoding scheme. Thus, the less complex decision decoding scheme can be implemented as a more cost effective scheme later in the decoding process without significantly degrading decoding reliability.

[0033] For example, a receiving device can decode a received codeword to sequentially determine N source bits. The N source bits can be determined in two bit groups. A first bit group can include X source bits determined through a list decoding scheme, and a second bit group can include Y source bits determined through a decision decoding scheme (e.g., where X + Y = N). In some cases, the number of bits in each bit group (e.g., the number of X source bits and the number of Y source bits) can be determined based on the number N and the number of information bits included in N (e.g., N can include K information bits and a number of redundancy bits, such that K < N).

[0034] Thus, the first bit group including X source bits can be decoded through a list decoding scheme. The list decoding scheme can refer to a decoding scheme that sequentially determines X source bits while maintaining a plurality of bit sequences as candidates. In some examples, the list decoding scheme can include a successive cancellation list (SCL) decoding scheme or a simplified successive cancellation list (SSCL) decoding scheme. The second bit group including Y source bits can be decoded through a decision decoding scheme. The decision decoding scheme can refer to a scheme that determines a source bit based on a reliability value of a bit to be determined and adds the determined source bit to an existing bit sequence. In some examples, the decision decoding scheme can include a successive cancellation (SC) decoding scheme. However, as described above, because decoding reliability increases as the index of determined source bits increases (e.g., as the number of source bits determined for a codeword increases), the decoding reliability of the second bit group including Y source bits determined using the decision decoding scheme does not significantly degrade.

[0035] Figure 1is a block diagram of a communication system 100 including a transmitter 10 and a receiver 20 according to an example embodiment. As shown, the transmitter 10 and the receiver 20 can communicate with each other through a channel 30. Figure 1

[0036] The communication system 100 can be any communication system defining a communication protocol between the transmitter 10 and the receiver 20. In some embodiments, the channel 30 can be a wireless channel using radio resources, and the communication system 100 can be a wireless communication system. For example, the communication system 100 can be a wireless communication system using a cellular network (e.g., a Fifth Generation Wireless (5G) New Radio (NR) system, a Long Term Evolution (LTE) system, an LTE-Advanced system, a Code Division Multiple Access (CDMA) system, and a Global System for Mobile Communications (GSM) system), a Wireless Personal Area Network (WPAN) system, or other any wireless communication system. In some embodiments, the channel 30 can be a wired channel using electrical and / or optical signals, and the communication system 100 can be a wired communication system. Hereinafter, the communication system 100 will be mainly described with reference to a wireless communication system, particularly a 5G NR system which can be a wireless communication system using a cellular network, but the example embodiments are not limited thereto.

[0037] When the communication system 100 is a wireless communication system using a cellular network, the transmitter 10 and the receiver 20 can each be a Base Station (BS) or a User Equipment (UE). When the transmitter 10 is a BS and the receiver 20 is a UE, a downlink can be formed in the channel 30. Conversely, when the transmitter 10 is a UE and the receiver 20 is a BS, an uplink can be formed in the channel 30. Additionally or alternatively, when the transmitter 10 and the receiver 20 are each a UE, a sidelink can be formed in the channel 30.

[0038] ​A BS may generally refer to a fixed station configured to communicate with a UE and / or another BS. A BS may communicate with a UE and / or another BS, and may exchange data and control information with the UE and / or another BS. For example, a BS may be referred to as a Node B, an evolved Node B (eNB), a next generation Node B (gNB), a sector, a station, a base transceiver system (BTS), an access point (AP), a relay node, a remote radio head (RRH), a radio unit (RU), or a small cell. As used herein, a BS or a cell may be interpreted as a portion of an area or function covered by a base station controller (BSC) for CDMA, a Node-B for WCDMA, an eNB for LTE, a gNB for 5G, or a sector (station), and may cover various coverage areas, such as a megacell, a macrocell, a microcell, a picocell, a femtocell, a relay node, an RRH, an RU, and a small cell communication range. A UE may be fixed or mobile and may refer to any device capable of communicating with a base station (BS) and transmitting and receiving data and / or control information to and from the BS. For example, a UE may be referred to as a terminal, a terminal device, a mobile station (MS), a mobile terminal (MT), a user terminal (UT), a subscriber station (SS), a wireless device, or a handheld device.

[0039] The wireless communication network between the UE and the BS can share available network resources and support communication for multiple users. For example, in the wireless communication network, various multiple access methods such as code division multiple access (CDMA), frequency division multiple access (FDMA), time division multiple access (TDMA), orthogonal frequency division multiple access (OFDMA), single carrier frequency division multiple access (SC-FDMA), OFDM-FDMA, OFDM-TDMA and OFDM-CDMA can be used to transmit information.

[0040] The transmitter 10 may transmit a signal through the channel 30, and the receiver 20 may receive a signal through the channel 30. The communication system 100 may define channel coding. Thus, the transmitter 10 may transmit a coded signal through the channel 30, and the receiver 20 may decode the signal received through the channel 30. For example, the communication system 100 may define channel coding based on polar codes, Reed-Solomon codes, convolutional codes, or the like.

[0041] like Figure 1 As shown, the transmitter 10 may include an encoder 15 and the receiver 20 may include a decoder 25 to enable a channel coding scheme for communication from the transmitter 10 to the receiver 20 via a channel 30.Figure 1 As shown, the encoder 15 of the transmitter 10 can encode the source data SRC and generate a codeword CDW, while the receiver 20 can decode the codeword CDW' and generate the source data SRC'. Due to noise and interference caused in the channel 30, the codeword CDW generated by the transmitter 10 can be different from the codeword CDW' received by the receiver 20. However, the decoder 25 can generate the source data SRC' that matches the source data SRC of the transmitter 10 with high reliability. For example, the decoder 25 can determine source bits of the source data SRC' according to the techniques described herein. A source bit can refer to a unit of the source data SRC', where each source bit can have a single binary value of 0 or 1. Thus, the receiver 20 can generate the source data SRC' by determining the source bits. The source data SRC' can be generated to match the source data SRC, thereby effectively enabling communication between the transmitter 10 and the receiver 20. The encoder 15 and / or the decoder 25 can include logic blocks synthesized by logic synthesis, and can include software having a series of instructions and at least one core configured to execute the software. In some embodiments, the transmitter 10 can also include a decoder, and the receiver 20 can also include an encoder.

[0042] In the communication system 100, to achieve high throughput, the transmitter 10 and the receiver 20 can be used to process a large amount of data with high reliability in a short time. For example, a 5G NR communication system can define scenarios in which the transmitter 10 and the receiver 20 can be used, such as ultra-reliable low-latency communication (URLLC) and enhanced mobile broadband (eMBB). Thus, the encoder 15 of the transmitter 10 and the decoder 25 of the receiver 20 can be used to process data at high speed with high reliability. In particular, when the transmitter 10 and / or the receiver 20 are part of a UE in a wireless communication system, the transmitter 10 and / or the receiver 20 can be required to have high performance and high efficiency (e.g., small coverage area and low power consumption).

[0043] As described below with reference to the accompanying drawings, the decoder 25 of the receiver 20 can decode the codeword CDW' based on two different decoding schemes, thereby enabling high reliability and reduced complexity at the same time. For example, a decoding operation can generally refer to an operation of converting an encoded message (e.g., a received codeword CDW') into understandable source data SRC'. Different schemes or methods that can be used to perform a decoding operation can be associated with different computational operations, and thus can be associated with different levels of reliability (e.g., accuracy). According to the techniques described for efficiently using two different encoding schemes, the receiver 20 can support high throughput (e.g., through a faster, reduced complexity decoding scheme) and have improved efficiency (e.g., through a decoding scheme that improves reliability).

[0044] Figure 2 is a flowchart of an example of a decoding method according to an example embodiment. As shown, the decoding method can include operations S20 and S40. In some embodiments, Figure 2 the decoding method of Figure 2 may be performed by the decoder 25 of Figure 1 In the following, the decoding method of Figure 1 will be described with reference to Figure 2 .

[0045] In some embodiments, Figure 1 the source data SRC' can include a series of source bits, and the decoder 25 can decode the codeword CDW' by sequentially determining the series of source bits. As used herein, it can be assumed that the source data SRC' includes N source bits (N is an integer greater than 1). The decoder 25 can divide the series of source bits into at least two groups of bits, and determine the source bits of each of the divided groups of bits based on different decoding schemes.

[0046] Referring to Figure 2 , in operation S20, an operation of sequentially determining the first X source bits based on a first decoding scheme can be performed. For example, the decoder 25 can sequentially determine the first X source bits (N > X) among the N source bits included in the source data SRC' based on the first decoding scheme. In some embodiments, the complexity of the first decoding scheme can be higher than that of a second decoding scheme to be described below. Thus, the decoding process performed in operation S20 can provide high reliability, but the decoding process can take a relatively long time and consume a high power. As used herein, operation S20 can be referred to as a first decoding operation, and an example of operation S20 will be described below with reference to Figure 4A through Figure 6A .

[0047] In operation S40, an operation of sequentially determining the remaining Y source bits based on a second decoding scheme can be performed. For example, the decoder 25 can sequentially determine the remaining Y source bits (N = X + Y) among the N source bits included in the source data SRC' except for the X source bits determined in operation S20 based on the second decoding scheme. In some embodiments, the complexity of the second decoding scheme can be lower than that of the first decoding scheme. However, as will be described below with reference to Figure 3 , the reliability can be improved as the source bits are sequentially determined. Thus, the decoding process performed in operation S40 can provide a reliability that is not significantly reduced while taking a relatively short time and consuming a low power. Thus, the decoding method of Figure 2 may take a shorter time and consume less power while maintaining high reliability, as compared to a process of determining the N source bits based on the first decoding scheme. As used herein, operation S40 can be referred to as a second decoding operation, and an example of operation S40 will be described below with reference toFigure 5A and Figure 7A An example of operation S40 is described.

[0048] Figure 3 An example of source data generated using a decoding method according to an example embodiment is shown. Figure 1 and Figure 2 As described, the code word CDW' can be decoded to generate Figure 3 The source data SRC' may include source bits sequentially determined during the decoding process. Figure 3 In the example, Figure 2 The first decoding scheme may correspond to a list decoding scheme, and the second decoding scheme may correspond to a decision decoding scheme. Figure 1 and Figure 2 describe Figure 3 .

[0049] The source data SRC' may include N source bits. For example, the first source bit u1 to the Nth source bit u N The N source bits may include K information bits and (NK) redundant bits (0<K<N). The information bits may refer to bits indicating useful information. Figure 3 As shown, the code rate can be defined as K / N.

[0050] In some embodiments, the source data SRC' may include K information bits and (NK) frozen bits. For example, Figure 1 The communication system 100 can adopt polar codes as channel codes that can achieve Shannon capacity with relatively low coding / decoding complexity. Polar codes can use channel polarization to send information bits through good bit channels and frozen bits through bad bit channels. In channel polarization, the bit channel (or subchannel) observed at the transmitting side is polarized into a good bit channel and a bad bit channel. The transmitter 10 and the receiver 20 can jointly know the value and position (i.e., index) of the frozen bit of the source data SRC'. The decoder 25 of the receiver 20 can decode the codeword CDW' based on the value and index of the frozen bit.

[0051] Polar coding is a form of channel coding based on block coding methods. In polar coding, each data block to be coded has a set number of bits. Manipulation of the block is performed at the transmitter 10 and the receiver 20. For example, Channel Combining and Channel Splitting are performed on each data block. First, Channel Combining allocates and / or maps a combination of symbols to a channel. Then, Channel Splitting performs a conversion operation that converts the symbol combination to a time-domain vector used in the decoder. The decoding and encoding operations estimate a time-domain bit stream. This converts the bit block and channel to a polar bit stream (e.g., source bits) at the receiver 20. Polar codes have shown the ability to achieve the capacity of an additive white Gaussian noise (AWGN) channel and comparable performance to low-density parity-check codes (LDPC) using an SCL decoder 25 with a cyclic redundancy check (CRC) for finite-length codes. The SCL decoder 25 can have a high latency because each bit is decoded sequentially. In some cases, a neural network decoder 25 can be used in polar codes.

[0052] The N source bits (i.e., the first source bit u1to the Nth source bit u N ) can be sequentially determined. As Figure 3 indicated, the reliability can gradually increase in the process of sequentially determining the first source bit u1to the Nth source bit u N . For example, as the number of determined source bits increases, the bias between the reliability values of the candidates can increase in the subsequent determination process, and the candidate having a high reliability value can be determined as a source bit.

[0053] The source data SRC' can include a first bit group BG1and a second bit group BG2. The first bit group BG1may include X source bits (e.g., the first source bit u1to the Xth source bit u X ), which includes the first source bit u1as the earliest determined source bit, and the second bit group BG2may include Y source bits (e.g., the (X+1)th source bit u X+1 to the Nth source bit u N (N = X + Y)), which includes the Nth source bit u N as the last determined source bit. In some embodiments, the first bit group BG1and the second bit group BG2may be determined based on different decoding schemes. For example, as Figure 3 indicated, the first bit group BG1may be determined based on a list decoding scheme. The second bit group BG2may be determined based on a decision decoding scheme.

[0054] The list decoding scheme may refer to a decoding scheme that sequentially determines source bits while maintaining multiple bit sequences as candidates. For example, as shown below with reference to 4A and Figure 4B As described, Figure 1 When the communication system 100 adopts polar code, the source bits of the first bit group BG1 can be determined based on the SCL decoding scheme. Figure 6A and Figure 6B As described, the source bits of the first bit group BG1 can be determined based on the SSCL decoding scheme. As used herein, SCL decoding and SSCL decoding schemes may be collectively referred to as SCL decoding schemes, and the SSCL decoding scheme may be referred to as an example of an SCL decoding scheme. Compared to the decision decoding scheme to be described below, the list decoding scheme may have a higher complexity, provide higher reliability (e.g., a lower block error rate (BLER)), and be less cost-effective.

[0055] The decision decoding scheme may refer to a scheme of determining a source bit based on the reliability value of the bit to be determined and adding the determined source bit to the existing bit sequence. Figure 1 When the communication system 100 adopts polar code, the source bits of the second bit group BG2 can be determined based on the SC decoding scheme, as shown below. Figure 5A and Figure 7A Compared to the above-described list decoding scheme, the decision decoding scheme may have lower complexity, provide lower reliability (e.g., higher block error rate), and be more cost-effective. However, as described above, since the reliability increases with the increase of the index of the determined source bit, the reliability (which may be referred to as decoding reliability) of the second bit group BG2 determined using the decision decoding scheme does not significantly decrease.

[0056] Hereinafter, channel coding will be described mainly with reference to polar codes, but example embodiments are not limited thereto. For example, example embodiments may be applied to any channel coding scheme (e.g., Reed-Solomon codes and convolutional codes) to which both list decoding schemes and decision decoding schemes may be applied.

[0057] Figure 4A is a flowchart of an example of a decoding method according to an example embodiment. Figure 4B is a diagram of an example of a decoding tree formed using a decoding method according to an example embodiment. Specifically, Figure 4A The flow chart shows Figure 2 An example of operation S20, and Figure 4B Shows that due to Figure 4A An example of a decoding tree formed by operation S20a. Figure 2 As described, it can be found in Figure 4Athe operation S20a of FIG. 2A can be performed by the decoder 25 of FIG. 2A. In the following, the operation S20a of FIG. 2A will be described with reference to FIG. 2B. Figure 4A The operation S20a of FIG. 2A can be performed by the decoder 25 of FIG. 2A. In the following, the operation S20a of FIG. 2A will be described with reference to FIG. 2B. Figure 1 The operation S20a of FIG. 2A can be performed by the decoder 25 of FIG. 2A. In the following, the operation S20a of FIG. 2A will be described with reference to FIG. 2B. Figure 1 The operation S20a of FIG. 2A can be performed by the decoder 25 of FIG. 2A. In the following, the operation S20a of FIG. 2A will be described with reference to FIG. 2B. Figure 3 The operation S20a of FIG. 2A can be performed by the decoder 25 of FIG. 2A. In the following, the operation S20a of FIG. 2A will be described with reference to FIG. 2B. Figure 4A The operation S20a of FIG. 2A can be performed by the decoder 25 of FIG. 2A. In the following, the operation S20a of FIG. 2A will be described with reference to FIG. 2B. Figure 4B The operation S20a of FIG. 2A can be performed by the decoder 25 of FIG. 2A. In the following, the operation S20a of FIG. 2A will be described with reference to FIG. 2B. The operation S20a of FIG. 2A can be performed by the decoder 25 of FIG. 2A. In the following, the operation S20a of FIG. 2A will be described with reference to FIG. 2B.

[0058] Referring to FIG. 2B, in the operation S20a, X source bits included in the first bit group BG1 can be sequentially determined based on an SCL decoding scheme as an example of the first decoding scheme of FIG. 2A. In the example of FIG. 2B, the SCL decoding scheme can maintain L bit sequences or less as candidates (L is an integer greater than 1), and L can be assumed to be 4 (L = 4) in the decoding tree of FIG. 2B. As shown in FIG. 2B, the operation S20a can include a plurality of operations (e.g., S22a, S24a, and S26a). Figure 4A The operation S20a of FIG. 2A can be performed by the decoder 25 of FIG. 2A. In the following, the operation S20a of FIG. 2A will be described with reference to FIG. 2B. Figure 2 The operation S20a of FIG. 2A can be performed by the decoder 25 of FIG. 2A. In the following, the operation S20a of FIG. 2A will be described with reference to FIG. 2B. Figure 4A The operation S20a of FIG. 2A can be performed by the decoder 25 of FIG. 2A. In the following, the operation S20a of FIG. 2A will be described with reference to FIG. 2B. Figure 4B The operation S20a of FIG. 2A can be performed by the decoder 25 of FIG. 2A. In the following, the operation S20a of FIG. 2A will be described with reference to FIG. 2B. Figure 4A The operation S20a of FIG. 2A can be performed by the decoder 25 of FIG. 2A. In the following, the operation S20a of FIG. 2A will be described with reference to FIG. 2B. The operation S20a of FIG. 2A can be performed by the decoder 25 of FIG. 2A. In the following, the operation S20a of FIG. 2A will be described with reference to FIG. 2B.

[0059] The operation S20a of FIG. 2A can be performed by the decoder 25 of FIG. 2A. In the following, the operation S20a of FIG. 2A will be described with reference to FIG. 2B. Figure 4B The operation S20a of FIG. 2A can be performed by the decoder 25 of FIG. 2A. In the following, the operation S20a of FIG. 2A will be described with reference to FIG. 2B. The operation S20a of FIG. 2A can be performed by the decoder 25 of FIG. 2A. In the following, the operation S20a of FIG. 2A will be described with reference to FIG. 2B.

[0060] In operation S24a, an operation of sorting 2L reliability values can be performed. In some embodiments, the decoder 25 can sort the 2L reliability values calculated in operation S22a to generate L bit sequences as new candidates. For example, the decoder 25 can sort the first reliability value R1 to the eighth reliability value R8 to generate 4 bit sequences. Figure 4B

[0061] In operation S26a, an operation of generating L bit sequences can be performed. In some embodiments, the decoder 25 can generate L new bit sequences from values of source bits corresponding to L higher reliability values among the 2L reliability values and bit sequences corresponding to the values of the source bits. For example, as shown in Figure 4B , 4 higher reliability values (i.e., the first reliability value R1, the second reliability value R2, the fifth reliability value R5, and the eighth reliability value R8) can be selected from among the first reliability value R1 to the eighth reliability value R8. Accordingly, 4 new bit sequences (i.e., {0, 0, 0, 0}, {0, 0, 0, 1}, {0, 1, 0, 0}, and {0, 1, 1, 1}) can be generated as candidates.

[0062] As described above, operation S20a can provide high reliability by determining source bits while maintaining L candidates. Additionally or alternatively, operation S20a can include operation S24a of sorting 2L reliability values to select L higher reliability values. The complexity of the sorting of the reliability values can be calculated according to a sorting method by Equation 1 provided below, where K is the number of information bits and L is the number of candidates.

[0063] [Equation 1]

[0064] C serial = K·2L·log22L

[0065] C radix = K·L·(2L-1)

[0066]

[0067] As shown in Equation 1, the operation of sorting the reliability values can increase the complexity of the decoding method based on the SCL decoding scheme. However, as described below with reference to Figure 5A and Figure 5B , the decoding method based on the SC decoding scheme can omit the operation of sorting 2L reliability values.

[0068] Figure 5A is a flowchart of an example of a decoding method according to an example embodiment. Figure 5B ​is an example of a decoding tree formed using a decoding method according to an example embodiment. Specifically, Figure 5A The flowchart of Figure 2 shows an example of operation S40 of Figure 5B shows an example of a decoding tree formed due to Figure 5A operation S40a of Figure 2 As described above with reference to Figure 5A operation S40a of Figure 5A In some embodiments, Figure 1 operation S40a of Figure 1 and Figure 3 will be described below with reference to Figure 5A and Figure 5B . Figure 5A and Figure 5B The description of Figure 4A and Figure 4B will be omitted.

[0069] With reference to Figure 5A , in operation S40a, Y source bits included in the second bit group BG2 can be sequentially determined based on an SC decoding scheme as an example of the second decoding scheme of Figure 2 In an example of Figure 5A , the SC decoding scheme can perform a decision according to a reliability value corresponding to each bit sequence of L bit sequences generated based on the list decoding scheme (e.g., the SCL decoding scheme of Figure 2 ) employed in operation S20 of Figure 4A Additionally or alternatively, the SC decoding scheme can keep the L bit sequences as candidates. In the decoding tree of Figure 5B , it can be assumed that L is 4 (L=4). As shown in Figure 5A , operation S40a can include a plurality of operations (e.g., S42a, S44a, and S46a).

[0070] In operation S42a, an operation of calculating 2L reliability values can be performed. For example, as shown in Figure 5B , the decoder 25 can determine the (X-3)th source bit u X-3 to the (X-1)th source bit u X-1 based on the first decoding scheme (e.g., the SCL decoding scheme), and then attempt to determine the Xth source bit u X based on the second decoding scheme (e.g., the SC decoding scheme). Similar to the decoding tree of Figure 4B , the (X-3)th source bit u X-3may have a value "0" as a frozen bit, and the (X-2)th source bit u X-2 to the Xth source bit u X may be an information bit. The decoder 25 can calculate the first reliability value R1 to the eighth reliability value R8 from the 4-bit sequences (i.e., {..., 0, 0, 0}, {..., 0, 0, 1}, {..., 0, 1, 0}, and {..., 0, 1, 1}) including the (X-3)th source bit u X-3 to the (X-1)th source bit u X-1

[0071] In operation S44a, an operation of determining source bits in each of the L-bit sequences can be performed. In some embodiments, the decoder 25 can determine a value corresponding to a high reliability value among each of the L pairs of reliability values (corresponding to "0" and "1", respectively) as a source bit. For example, as shown in Figure 5B , the decoder 25 can perform a reliability value comparison in each of the four pairs of reliability values and determine a relatively high reliability value. Accordingly, four reliability values (i.e., the first reliability value R1, the fourth reliability value R4, the sixth reliability value R6, and the seventh reliability value R7) can be determined from among the first reliability value R1 to the eighth reliability value R8.

[0072] In operation S46a, an operation of generating the L-bit sequences can be performed. In some embodiments, the decoder 25 can determine values of the source bits corresponding to high reliability values in each of the L pairs of reliability values and generate the L-bit sequences. For example, as shown in Figure 5B , based on the first reliability value R1, the fourth reliability value R4, the sixth reliability value R6, and the seventh reliability value R7 determined in operation S44a, four new bit sequences (i.e., {..., 0, 0, 0, 0}, {..., 0, 0, 1, 1}, {..., 0, 1, 0, 1}, and {..., 0, 1, 1, 0}) can be generated as candidates. As a result, in operation S40a, in order to generate the L-bit sequences based on the 2L reliability values, the increased complexity can be proportional to L, and the complexity proportional to L corresponds to a complexity much lower than that of the sorting operation represented by Equation 1.

[0073] Figure 6A is a flowchart of an example of a decoding method according to an example embodiment. Figure 6B is a diagram of an example of a decoding tree formed using a decoding method according to an example embodiment. Specifically, Figure 6A the flowchart of Figure 2 an example of operation S20 of Figure 6B illustrates that Figure 6A ​An example of a decoding tree formed by operation S20b. Figure 2 As described, it can be found in Figure 6A In operation S20b, the operation of sequentially determining the first X source bits based on the first decoding scheme is performed. In some embodiments, Figure 6A Operation S20b may be performed by Figure 1 The decoder 25 is used to perform the above operations. Figure 1 and Figure 3 describe Figure 6A and Figure 6B .

[0074] Reference Figure 6A In operation S20b, the Figure 2 The SSCL decoding scheme of the example of the first decoding scheme is used to sequentially determine the X source bits included in the first bit group BG1. In the SSCL decoding scheme, the nodes of the decoding tree can be divided into: a Rate-0 node where the source bit is a frozen bit, a repetition (REP) node where the last source bit is an information bit, a single parity check (SPC) node where the first source bit is a frozen bit, and a Rate-1 node where the source bit is an information bit, and subsequent operations can be performed differently according to the node type. Figure 6A In the example of , the SSCL decoding scheme may maintain L bit sequences or less as candidates and determine at least two source bits simultaneously. Figure 6B In the decoding tree of , we can assume that L is 2 (L=2). Figure 6A As shown, operation S20b may include multiple operations (eg, S22b, S24b, and S26b).

[0075] In operation S22b, an operation of calculating 4L reliability values ​​may be performed. Figure 6B As shown, the decoder 25 can determine the first source bit u1 and the second source bit u2 based on the SSCL decoding scheme, and then attempt to determine the third source bit u3 and the fourth source bit u4. The first source bit u1 can have a value of "0" as a frozen bit, and the second source bit u2 to the fourth source bit u4 can be information bits. The decoder 25 can calculate the first reliability value R1 to the eighth reliability value R8 from the two bit sequences (i.e., {0,0} and {0,1}) corresponding to the first source bit u1 and the second source bit u2.

[0076] In operation S24b, an operation of sorting the 4L reliability values ​​may be performed. In some embodiments, the decoder 25 may sort the 4L reliability values ​​calculated in operation S22b to generate L bit sequences as new candidate items. For example, the decoder 25 may sort Figure 6Bthe first reliability value R1 to the eighth reliability value R8 to generate 2-bit sequences.

[0077] In operation S26b, an operation of generating L-bit sequences can be performed. In some embodiments, the decoder 25 can generate L new bit sequences from values of source bits corresponding to L higher reliability values among the 4L reliability values and bit sequences corresponding to the values of the source bits. For example, as shown in Figure 6B two higher reliability values (i.e., the first reliability value R1 and the sixth reliability value R6) can be selected from the first reliability value R1 to the eighth reliability value R8. Accordingly, two new bit sequences (i.e., {0, 0, 0, 0} and {0, 1, 0, 1}) can be generated as candidates.

[0078] As described above, the SSCL decoding scheme can determine two source bits at the same time. Additionally or alternatively, the SSCL decoding scheme can include the operation S24b of sorting the 4L reliability values. Accordingly, similar to the above description with reference to Figure 4A the operation of sorting the reliability values can increase the complexity of the decoding method based on the SSCL decoding scheme. Further, as described below with reference to Figure 7A and Figure 7B the decoding method based on the SC decoding scheme can omit the sorting (e.g., the operation S24b) of the 4L reliability values.

[0079] Figure 7A is a flowchart of an example of a decoding method according to an example embodiment. Figure 7B is a diagram of an example of a decoding tree formed using a decoding method according to an example embodiment. Specifically, Figure 7A the flowchart shows an example of the operation S40 of Figure 2 , the operation S40b of Figure 7B shows an example of a decoding tree formed due to the operation S40b of Figure 7A As described above with reference to Figure 2 , the operation of sequentially determining the remaining Y source bits based on the second decoding scheme can be performed in the operation S40b of Figure 7A In some embodiments, the operation S40b of Figure 7A may be performed by the decoder 25 of Figure 1 In the following, the operation S40b of Figure 1 and Figure 3 will be described with reference to Figure 7A and Figure 7B . Figure 7A and Figure 7B The description of Figure 6A and Figure 6B will be omitted.

[0080] Referring toFigure 7A In operation S40b, the Figure 2 The SC decoding scheme of the example of the second decoding scheme sequentially determines the Y source bits included in the second bit group BG2. Figure 7A In the example of , the SC decoding scheme can perform a decision based on the reliability value corresponding to each bit sequence in the L bit sequences, wherein the L bit sequences are based on the reliability value corresponding to each bit sequence in the L bit sequences. Figure 2 The list decoding scheme (eg, Figure 6A Alternatively or in addition, the SC decoding scheme may retain L bit sequences as candidates. The decoding tree formed by operation S40b may include a simplified Rate-0 (SRate-0) node, a simplified REP (SREP) node, a simplified SPC (SSPC) node, and a simplified Rate-1 (SRate-1) node corresponding to the Rate-0 node, REP node, SPC node, and Rate-1 node of the SSCL decoding scheme, respectively. Figure 7B In the decoding tree of , we can assume that L is 2 (L=2). Figure 7A As shown, operation S40b may include multiple operations (eg, S42b, S44b, and S46b).

[0081] In operation S42b, an operation of calculating 4L reliability values ​​may be performed. Figure 7B As shown, the decoder 25 may determine the (X-2)th source bit u based on a first decoding scheme (eg, an SSCL decoding scheme). X-2 and the (X-1)th source bit u X-1 , and then try to determine the Xth source bit u based on the SC decoding scheme X and the (X+1)th source bit u X+1 . Similar to Figure 5B The decoding tree of the (X-2)th source bit u X-2 may have a value of "0" as a frozen bit, and the (X-1)th source bit u X-1 To the (X+1)th source bit u X+1 The decoder 25 can be an information bit. X-2 and the (X-1)th source bit u X-1 For the corresponding two bit sequences (ie, {..., 0, 0} and {..., 0, 1}), the first reliability value R1 to the eighth reliability value R8 are calculated.

[0082] In operation S44b, an operation of determining at least two source bits in each of the L bit sequences may be performed. In some embodiments, the decoder 25 may determine a bit stream including at least two bits (e.g., a bit stream corresponding to a high reliability value among a set of reliability values ​​corresponding to "00", "01", "10", and "11", respectively) as the value of the source bit. For example, Figure 7B As shown, the decoder 25 can determine the first reliability value R1 having the highest value from the group including the first reliability value R1 to the fourth reliability value R4, and determine the sixth reliability value R6 having the highest value from the group including the fifth reliability value R5 to the eighth reliability value R8.

[0083] In operation S46b, an operation of generating L bit sequences may be performed. In some embodiments, the decoder 25 may determine the value of the source bit corresponding to the highest reliability value among each set of reliability values ​​and generate L bit sequences. For example, Figure 7B As shown, two new bit sequences (i.e., {..., 0, 0, 0, 0} and {..., 0, 1, 0, 1}) can be generated as candidates based on the first reliability value R1 and the sixth reliability value R6 determined in operation S44b. As a result, in order to generate L bit sequences based on 4L reliability values, the operation of searching for the highest reliability value from 2L reliability values ​​can be performed twice. In this case, the complexity can be reduced compared to Figure 6A The 4L reliability values ​​are much lower when sorting them in operation S24b.

[0084] Figure 8 is a flowchart of an example of a decoding method according to an example embodiment. Figure 8 As shown, the decoding method may include multiple operations (eg, S10, S20', S30, and S40'). Figure 2 Compared with the decoding method, Figure 8 The decoding method may further include: an operation S10 of determining a position of a source bit for switching a decoding scheme, and an operation S30 of switching a decoding scheme based on the determined position. In some embodiments, Figure 8 The decoding method can be obtained by Figure 1 In the following, reference will be made to the decoder 25. Figure 1 and Figure 3 describe Figure 8 ,and Figure 8 The description will be omitted with Figure 1 Same description.

[0085] In operation S10, an operation of calculating the number of information bits included in the second bit group BG2 may be performed. For example, the decoder 25 may calculate the number T of information bits included in the second bit group BG2 based on the number N of source bits included in the source data SRC' and the number of information bits included in the source data SRC'. In some embodiments, the number T of information bits included in the second bit group BG2 may be limited to less than or equal to half the number K of information bits included in the source data SRC' (T≤K / 2). In some embodiments, because the decoder 25 knows the index of the frozen bits (or information bits) in the source data SRC', the decoder 25 can calculate the number T of information bits included in the second bit group BG2. Alternatively or alternatively, the decoder may calculate the size X of the first bit group BG1, the number of information bits included in the first bit group BG1, the size Y of the second bit group BG2, and the indexes of the information bits (or frozen bits) in the first bit group BG1 and the second bit group BG2. In addition, in some embodiments, the decoder 25 may obtain T corresponding to N and K by referring to a lookup table. Additionally or alternatively, the decoder 25 may obtain T by substituting at least one of N and K as an independent variable into a predetermined function. Figure 9 An example of operation S10 is described.

[0086] In operation S20', an operation of sequentially determining source bits based on the first decoding scheme may be performed. Next, in operation S30, an operation of determining whether to switch the decoding scheme may be performed. As described above, when the number T of information bits included in the second bit group BG2 is calculated in operation S10, because the receiver 20 (or decoder 25) knows the position of the frozen bits included in the source data SRC', the start index (i.e., (X+1)) of the second bit group BG2 including the source bits determined based on the second decoding scheme may be determined. The decoder 25 may determine X+1 as the index of the information bit or the index of the frozen bit based on the number T of information bits included in the second bit group BG2 and the position of the frozen bit. The decoder 25 may determine whether to switch the decoding scheme based on the index of the source bit. As Figure 8 As shown, when the index of the source bit to be determined is less than or equal to X, operation S20' may be performed again. Otherwise, when the index of the source bit to be determined is greater than (X+1), operation S40' may be performed subsequently. In operation S40', an operation of sequentially determining the source bits based on the second decoding scheme may be performed.

[0087] Figure 9 is a flowchart of an example of a decoding method according to an example embodiment. Specifically, Figure 9 The flow chart shows Figure 8 As shown above with reference to the example of operation S10.Figure 8 As described, it can be found in Figure 9 In operation S10', an operation of calculating the number T of information bits included in the second bit group BG2 is performed. Figure 9 As shown, operation S10' may include operations S12 and S14. Figure 3 describe Figure 9 .

[0088] In operation S12, an operation of selecting one of a plurality of polynomials based on N may be performed. For example, the decoder 25 may include a plurality of polynomials (each polynomial having the number K of information bits included in the source data SRC' as a variable), and selects one of the plurality of polynomials based on the size of the source data SRC (e.g., the number N of source bits included in the source data SRC'). For example, a plurality of polynomials may correspond to different values ​​of N, respectively. In some embodiments, a plurality of polynomials may be predefined. The receiver 20 may include a memory (e.g., a non-volatile memory) configured to store a plurality of polynomials. The decoder 25 may access the memory and view the plurality of polynomials. In some embodiments, as N increases, the plurality of polynomials may include polynomials of higher order. For example, in a polar code, N may match 2 P (P is an integer greater than 0), and the multiple polynomials may include a 1st-order polynomial corresponding to N being 64 and a 2nd-order polynomial corresponding to N being 128.

[0089] In operation S14, an operation of calculating the number of information bits included in the second bit group BG2 may be performed based on the selected polynomial and K. For example, the decoder 25 may calculate the number T of information bits included in the second bit group BG2 by substituting the number K of information bits included in the source data SRC′ into the polynomial selected in operation S12.

[0090] Figure 10 is a block diagram of an example of a decoder 200 according to an example embodiment. Figure 10 As shown, the decoder 200 may include a reliability calculator 220, a first processing circuit 240, a second processing circuit 260, and a selection circuit 280. However, Figure 1 The decoder 25 is not limited to Figure 10 Decoder 200.

[0091] The reliability calculator 220 may receive a plurality of bit sequences QS' from the selection circuit 280. Alternatively or alternatively, the reliability calculator 220 may calculate a plurality of reliability values ​​RS corresponding to the plurality of bit sequences QS'. Figure 4A and Figure 5AAs described above, the reliability calculator 220 can calculate 2L reliability values from the L bit sequences. In some embodiments, as described above with reference to Figure 6A and Figure 7A As described above, the reliability calculator 220 can calculate at least 4L reliability values from the L bit sequences. As shown in FIG. 2, the reliability calculator 220 can provide a plurality of reliability values RS to the first processing circuit 240 and the second processing circuit 260. Figure 10

[0092] The first processing circuit 240 can generate a plurality of first bit sequences QS1 based on the plurality of reliability values RS according to a first decoding scheme. In some embodiments, as described above with reference to Figure 4A The first processing circuit 240 can sort the 2L reliability values and generate L bit sequences as the plurality of first bit sequences QS1 based on the L higher reliability values. In some embodiments, as described above with reference to Figure 6A The first processing circuit 240 can sort the 4L reliability values and generate L bit sequences as the plurality of first bit sequences QS1 based on the L higher reliability values.

[0093] The second processing circuit 260 can generate a plurality of second bit sequences QS2 based on the plurality of reliability values RS according to a second decoding scheme. In some embodiments, as described above with reference to Figure 5A The second processing circuit 260 can select a reliability value from each pair of reliability values of the L pairs of reliability values and generate L bit sequences as the plurality of second bit sequences QS2. Further, in some embodiments, as described above with reference to Figure 7A The second processing circuit 260 can select a reliability value from each group of reliability values and generate L bit sequences as the plurality of second bit sequences QS2.

[0094] Because the complexity of the first decoding scheme is higher than the complexity of the second decoding scheme, the cost of the first processing circuit 240 can be higher than the cost of the second processing circuit 260. For example, the first processing circuit 240 can have a larger area, higher power consumption, and longer processing time than the second processing circuit 260. For example, the first processing circuit 240 can include a circuit configured to perform an operation of sorting the 2L reliability values or the at least 4L reliability values. Thus, the cost of the first processing circuit 240 can be higher than the cost of the second processing circuit 260. In some embodiments, the first processing circuit 240 and the second processing circuit 260 can operate synchronously with a clock, and the number of clock cycles for the first processing circuit 240 to generate the plurality of first bit sequences QS1 can be greater than the number of clock cycles for the second processing circuit 260 to generate the plurality of second bit sequences QS2. ​

[0095] The selection circuit 280 can receive the plurality of first bit sequences QSl from the first processing circuit 240 and the plurality of second bit sequences QS2 from the second processing circuit 260. The selection circuit 280 can select one of the plurality of first bit sequences QSl and the plurality of second bit sequences QS2 and provide the selected plurality of bit sequences QS' to the reliability calculator 220. For example, the selection circuit 280 can select the plurality of first bit sequences QSl during operation S20 (or operation S20') of the method 2000, and select the plurality of second bit sequences QS2 during operation S40 (or operation S40') of the method 2000. Figure 2 Figure 8 Figure 2 Figure 8

[0096] In some embodiments, the selection circuit 280 can deactivate the processing circuit configured to generate the plurality of bit sequences that are not selected, thereby reducing the power consumption of the decoder 200. For example, the second processing circuit 260 can be deactivated during operation S20 (or operation S20') of the method 2000, and the first processing circuit 240 can be deactivated during operation S40 (or operation S40') of the method 2000. Examples of the selection circuit 280 will be described below with reference to FIGS. 2A and 2B. For example, the processing circuit can be deactivated based on clock gating or blocking power supply. Figure 2 Figure 8 Figure 2 Figure 8 Figure 11

[0097] Figure 11 is a block diagram of an example of a selection circuit 280' according to an example embodiment. As described above with reference to the selection circuit 280 of FIG. 2A, Figure 10 Figure 11 the selection circuit 280' of the method 2000 can select one of the plurality of first bit sequences QSl and the plurality of second bit sequences QS2 and output the selected plurality of bit sequences QS'. As shown in FIG. 2B, the selection circuit 280' can include a counter 282, a threshold generator 284, a comparator 286, and a multiplexer (MUX) 288. In the following, the selection circuit 280' will be described with reference to the method 2000. Figure 11 Figure 3 Figure 11

[0098] The counter 282 can count the source bits determined in the decoding process. For example, the counter 282 can be an incrementing counter and generate a count signal CNT that increases from 1 to N in the process of sequentially determining the source bits. In some embodiments, the counter 282 can generate the count signal CNT by counting the frozen bits or the information bits instead of counting the source bits. To this end, the counter 282 can receive the index of the frozen bits (or the index of the information bits) included in the source data SRC' from the outside. ​​​​​​​​​​​​​

[0099] The threshold generator 284 can generate a threshold value THR to be compared with the count signal CNT by the comparator 286. Additionally or alternatively, the threshold value THR can define a time point at which the decoding scheme is switched from the first decoding scheme to the second decoding scheme. In some embodiments, the counter 282 can be an up-counter, and the threshold value THR can have a value related to the first bit group BG1. For example, when the count signal CNT indicates the number of determined source bits, the threshold value THR can correspond to the size (i.e., X) of the first bit group BG1. Additionally or alternatively, when the count signal CNT indicates the number of determined frozen bits, the threshold value THR can correspond to the number of frozen bits included in the first bit group BG1. Additionally or alternatively, when the count signal CNT indicates the number of determined information bits, the threshold value THR can correspond to the number of information bits included in the first bit group BG1. In some embodiments, the counter 282 can be a down-counter, and the threshold value THR can have a value related to the second bit group BG2. In some embodiments, as described above with reference to FIG. 2, the threshold generator 284 can calculate the number T of information bits included in the second bit group BG2, and generate the threshold value THR based on the number T. Figure 9

[0100] The comparator 286 can compare the value of the count signal CNT with the threshold value THR, and generate a comparison signal CMP. The multiplexer 288 can select one of the plurality of first bit sequences QS1 and the plurality of second bit sequences QS2 in response to the comparison signal CMP, and output the plurality of bit sequences QS'. For example, when the value of the count signal CNT is less than or equal to the threshold value THR, the comparator 286 can generate an inactive comparison signal CMP, and the multiplexer 288 can select the plurality of first bit sequences QS1 in response to the inactive comparison signal CMP. Additionally or alternatively, when the value of the count signal CNT exceeds the threshold value THR, the comparator 286 can generate an active comparison signal CMP, and the multiplexer 288 can select the plurality of second bit sequences QS2 in response to the active comparison signal CMP. In some embodiments, the comparison signal CMP or an enable signal generated from the comparison signal CMP can be provided to each of the first processing circuit 240 and the second processing circuit 260 of FIG. 2, and the first processing circuit 240 and the second processing circuit 260 can be enabled or disabled in response to the comparison signal CMP. Figure 10

[0101] Figure 12 is a flowchart of an example of a decoding method according to an example embodiment. Specifically, Figure 12 decoding methods based on the SCL decoding scheme and the SC decoding scheme are shown. In some embodiments, Figure 12 ​​The decoding method can be obtained by Figure 1 In the following, reference will be made to the decoder 25. Figure 1 and Figure 3 describe Figure 12 . Figure 12 The same description as that provided above with reference to the accompanying drawings will be omitted.

[0102] In operation S110, an initialization operation may be performed. For example, Figure 12 As shown, a variable i indicating the index of the source bit may be initialized to 1.

[0103] In operation S120, determining the i-th source bit u may be performed. i The operation of whether to include in set A. Set A may be a set of source bits corresponding to information bits among the source bits included in the source data SRC'. Figure 12 As shown, when the i-th source bit u i When not included in set A, for example, when the i-th source bit u i If the bit is a frozen bit, an operation of generating L bit sequences including the value of the frozen bit may be performed in operation S130.

[0104] When the i-th source bit u i When included in set A, for example, when the i-th source bit u i When the information bit is an information bit, an operation of calculating 2L reliability values ​​may be performed in operation S140. The 2L reliability values ​​may include a reliability value corresponding to a case where the subsequent information bit is "0" and a reliability value corresponding to a case where the subsequent information bit is "1" in each bit sequence of the L bit sequences.

[0105] In operation S150, determining the i-th source bit u may be performed. i Whether to include the operation in set B. Set B may be a set of source bits determined based on the SC decoding scheme among the information bits included in the source data SRC'. For example, the source bits included in set B may correspond to the information bits included in the second bit group BG2.

[0106] When the i-th source bit u i When not included in set B, an operation of sorting the 2L reliability values ​​may be performed in operation S160. Next, an operation of generating L bit sequences may be performed in operation S170. The 2L reliability values ​​may be sorted to determine L higher reliability values, and L new bit sequences corresponding to the L higher reliability values ​​may be generated.

[0107] Otherwise, when the i-th source bit u iWhen included in set B, an operation of determining the source bits in each of the L bit sequences may be performed in operation S180. Next, an operation of generating the L bit sequences may be performed in operation S190. A reliability value may be selected from each pair of L pairs of reliability values, and L new bit sequences corresponding to the selected L reliability values ​​may be generated. Therefore, the operation of sorting the 2L reliability values ​​may be omitted in operations S180 and S190.

[0108] In operation 200, the variable i may be increased by 1 to determine the next source bit. In operation S210, it may be determined whether the variable i is less than or equal to the number N of source bits included in the source data SRC'. Figure 12 As shown, when the variable i is less than or equal to N, for example, when there are source bits left to be determined, operation S120 may be subsequently performed. Otherwise, when N source bits are determined, the operation ends. Figure 12 Decoding method.

[0109] Figure 13 is a block diagram of a data processor 50 according to an example embodiment. In some embodiments, Figure 1 Decoder 25 or Figure 10 The decoder 200 can be implemented in Figure 13 In the data processor 50.

[0110] like Figure 13 As shown, the data processor 50 may include an application specific integrated circuit (ASIC) 51, an application specific instruction set processor (ASIP) 53, a memory 55, a main processor 57, and a main memory 59. In some embodiments, at least two of the ASIC 51, the ASIP 53, and the main processor 57 may communicate with each other. In some embodiments, at least two of the ASIC 51, the ASIP 53, the memory 55, the main processor 57, and the main memory 59 may be embedded in one semiconductor chip.

[0111] ASIP 53 may be a customized IC that supports a dedicated instruction set for a specific application and executes the instructions included in the instruction set. Memory 55 may communicate with ASIP 53 and serve as a non-transitory storage device configured to store a plurality of instructions executed by ASIP 53. For example, non-limiting examples of memory 55 may include any type of memory accessible by ASIP 53, such as random access memory (RAM), read-only memory (ROM), tape, magnetic disk, optical disk, volatile memory, non-volatile memory, and combinations thereof. In some embodiments, memory 55 may store data used to calculate the above reference. Figure 8 and Figure 9Data (e.g., look-up tables and / or polynomials) that describe the number of information bits included in the second set of bits.

[0112] The host processor 57 can execute a plurality of instructions and control the data processor 50. For example, the host processor 57 can control the ASIC 51 and the ASIP 53 or process user inputs to the receiver (e.g., the receiver 20 in Figure 1 The host memory 59 can be in communication with the host processor 57 and include any type of memory accessible by the host processor 57. In some embodiments, the host memory 59, as a non-transitory storage device, can store a plurality of instructions executed by the host processor 57.

[0113] In some embodiments, the decoding method for channel coding can be performed by at least one of the components included in the data processor 50 of Figure 13 For example, at least some of the operations of the decoder 25 of Figure 1 The decoding method of some embodiments can be implemented as a plurality of instructions stored in the memory 55. Additionally or alternatively, the ASIP 53 can execute a plurality of instructions stored in the memory 55 and perform at least one operation of the decoding method. In some embodiments, at least one operation of the decoding method can be performed by a hardware block (e.g., the 200 of Figure 10 The hardware block 200 can be included in the ASIC 51. In some embodiments, at least one operation of the decoding method can be implemented as a plurality of instructions stored in the host memory 59. The host processor 57 can perform at least one operation of the decoding method by executing a plurality of instructions stored in the host memory 59.

[0114] While the present inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A decoding method for sequentially determining a series of source bits from a codeword, the method comprising: performing a first decoding operation to sequentially determine first X source bits of the series of source bits; as well as performing a second decoding operation to sequentially determine the remaining Y source bits in the series of source bits, The performing of the first decoding operation comprises: sorting at least 2L reliability values ​​calculated from L bit sequences, where L is an integer greater than 0, and The performing of the second decoding operation includes: determining a source bit in each of the L bit sequences based on the at least 2L reliability values, Wherein, the codeword is encoded based on a polar code, wherein the first decoding operation is performed based on a successive elimination list decoding scheme, and The second decoding operation is performed based on a successive elimination decoding scheme.

2. The method according to claim 1, further comprising: The number of the first X source bits or the number of the remaining Y source bits is calculated based on the number of source bits included in the series of source bits and the number of information bits included in the series of source bits.

3. The method according to claim 2, wherein The calculating the number of the first X source bits or the number of the remaining Y source bits includes: selecting a polynomial from a plurality of polynomials based on a number of source bits included in the series of source bits; and The number of the first X source bits or the number of the remaining Y source bits is calculated based on the selected polynomial and the number of information bits included in the series of source bits.

4. The method according to claim 3, wherein: The selecting polynomial includes: when the number of source bits included in the series of source bits is 64, selecting a first-order polynomial including the number of information bits as a variable.

5. The method according to claim 2, wherein The number of information bits included in the remaining Y source bits is less than or equal to half the number of information bits included in the series of source bits.

6. The method according to claim 1, wherein The performing of the first decoding operation further includes: generating first L new bit sequences corresponding to L higher reliability values ​​respectively based on the sorted at least 2L reliability values, and The performing of the second decoding operation further includes: generating second L new bit sequences based on the source bits in each of the determined L bit sequences.

7. An apparatus for polar decoding, the apparatus being configurable to sequentially determine a series of source bits from a codeword encoded based on a polar code, the apparatus comprising: a reliability calculator configured to calculate at least 2L reliability values ​​from the L bit sequences, where L is an integer greater than 0; a first processing circuit configured to sort the at least 2L reliability values ​​based on a successive elimination list decoding scheme and generate first L new bit sequences corresponding to L higher reliability values, respectively; a second processing circuit configured to determine, based on a successive erasure decoding scheme, source bits in each of the L bit sequences based on the at least 2L reliability values, and generate a second L new bit sequence; and A selection circuit is configured to select one of the first processing circuit and the second processing circuit based on an index of a source bit included in the series of source bits.

8. The device according to claim 7, wherein The selection circuit includes: a counter configured to count sequentially determined source bits; a comparator configured to generate an activated comparison signal when an output of the counter exceeds a threshold; and A multiplexer configured to select the second L new bit sequences generated by the second processing circuit in response to the activated comparison signal.

9. The device according to claim 8, wherein The selection circuit further includes a threshold generator configured to generate the threshold based on the number of source bits included in the series of source bits and the number of information bits included in the series of source bits.

10. The device according to claim 9, wherein The threshold generator is configured to select a polynomial based on the number of source bits included in the series of source bits, and calculate the threshold based on the selected polynomial and the number of information bits included in the series of source bits.

11. The device according to claim 10, wherein When the number of source bits included in the series of source bits is 64, the threshold generator selects a 1st-order polynomial including the number of information bits as a variable.

12. A polar decoding method for obtaining a series of source bits from a codeword encoded based on a polar code, the method comprising: performing a first decoding operation in which source bits included in a first bit group are sequentially determined from the codeword based on a successive elimination list decoding scheme; as well as performing a second decoding operation in which source bits included in a second bit group are sequentially determined from the codeword based on a successive erasure decoding scheme, wherein the first bit group includes the first determined source bits, and The second bit group includes the most recently determined source bits.

13. The method according to claim 12, further comprising: It is determined that the first decoding operation ends and the second decoding operation starts based on the determined index of the source bit included in the first bit group and the number of source bits included in the second bit group.

14. The method according to claim 12, further comprising: The number of source bits included in the second bit group is calculated based on the number of source bits included in the series of source bits and the number of information bits included in the series of source bits.

15. The method according to claim 14, wherein Calculating the number of source bits included in the second bit group includes: selecting a polynomial from a plurality of polynomials based on a number of source bits included in the series of source bits; and The number of source bits included in the second bit group is calculated based on the selected polynomial and the number of information bits included in the series of source bits.

16. The method according to claim 15, wherein The selecting polynomial includes: when the number of source bits included in the series of source bits is 64, selecting a first-order polynomial including the number of information bits as a variable.

17. The method according to claim 14, wherein: The number of information bits included in the second bit group is less than or equal to half the number of information bits included in the series of source bits.

18. The method according to claim 12, wherein The performing of the first decoding operation includes: Calculating 2L reliability values ​​from the L bit sequences, where L is an integer greater than 0; and By sorting the 2L reliability values, generating first L new bit sequences corresponding to L higher reliability values ​​respectively, and The performing of the second decoding operation includes: Calculating 2L reliability values ​​from the L bit sequences; and Second L new bit sequences are generated by determining a source bit in each of the L bit sequences based on the 2L reliability values.

19. The method according to claim 12, wherein The performing of the first decoding operation includes: Calculating at least 4L reliability values ​​from the L bit sequences, where L is an integer greater than 0; and By sorting the at least 4L reliability values, generating first L new bit sequences corresponding to L higher reliability values ​​respectively, and The performing of the second decoding operation includes: Compute at least 4L reliability values ​​from the L bit sequences; and Second L new bit sequences are generated by determining at least two source bits in each of the L bit sequences based on the at least 4L reliability values.

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