Hybrid LDO regulator with fine loop presetting

Abstract

The invention provides a low dropout regulator with fine loop presetting. The low dropout regulator includes a coarse resolution regulator and a fine resolution regulator. The coarse resolution regulator adjusts the digital control value in response to the output transient to control the coarse output driver to adjust the output voltage at the coarse resolution. The coarse resolution regulator finally enters a limited cyclic oscillation mode at a corresponding duty ratio. The fine resolution regulator is deactivated when the digital control value initially changes, and the duty cycle based on the digital control value is preset when in the limited cycle oscillation mode. And after being preset, are reactivated to drive at least one fine output driver to adjust the output voltage at a fine resolution. When turned on after the output load transient, the presetting provides a closer estimate of the supplemental current required to meet the output load level to achieve a smaller output ripple voltage.

Description

Technical Field

[0001] The present disclosure generally relates to low-dropout (LDO) regulators, and more particularly to a hybrid LDO regulator having a fine loop preset to reduce output voltage overshoot or undershoot. Background Art

[0002] Conventional hybrid low-dropout (LDO) regulators including a coarse digital loop and a fine analog loop can be used to power digital loads in a system-on-chip (SoC) configuration. Compared with state-of-the-art analog LDO regulators, hybrid LDO regulators can respond faster to fast load transients by consuming fewer resources (such as less area and current consumption). In a system with limited decoupling capacitance, during an output load transient, only the fast coarse digital loop is turned on while the slow fine loop is turned off, which can improve the load transient performance. When the digital coarse loop enters the limit cycle oscillation mode, the fine loop is turned on to improve the accuracy of the regulator output voltage. Through this combination of the fine loop and the coarse loop, the hybrid LDO regulator can utilize both the digital (coarse) loop and the analog (fine) loop. However, simply turning on the fine loop after the transient may result in large output voltage undershoot or overshoot voltage, which will ultimately reduce the dynamic accuracy of the LDO regulator output, especially for configurations with small load capacitance or no load capacitance. Summary of the Invention

[0003] According to one embodiment, a low-dropout regulator includes:

[0004] A coarse resolution regulator including:

[0005] A coarse output driver coupled to an output node that generates an output voltage, wherein the coarse output driver is configured to be controlled by a digital control value; and

[0006] A digital controller configured to adjust the digital control value in response to an output transient so as to regulate the output voltage at a coarse resolution, wherein the digital controller is configured to enter a limit cycle oscillation mode by switching the digital control value at a corresponding duty cycle; and

[0007] A fine resolution regulator including:

[0008] A fine output driver that receives an analog control value and is coupled to the output node;

[0009] An analog controller configured to adjust the analog control value so as to regulate the output voltage at a fine resolution; and

[0010] A preset controller, which is configured to deactivate the fine-resolution regulator when the digital control value changes in response to an output transient, is configured to calculate the duty cycle of the digital control value during the limit cycle oscillation mode, and is configured to preset the fine output current driver and re-enable the fine-resolution regulator based on the calculated duty cycle.

[0011] Exemplarily, the coarse-resolution regulator includes:

[0012] The coarse output driver, which includes:

[0013] A plurality of coarse current devices, each having a current terminal coupled between a source voltage and the output node, and each having a control input; and

[0014] A gate driver, which is coupled to the control input of each of the plurality of coarse current devices, wherein the gate driver is configured to turn on a certain number of the plurality of coarse current devices based on the digital control value; and

[0015] Wherein the digital controller is configured to adjust the digital control value based on the detected level of the output voltage.

[0016] Exemplarily, the digital controller is configured to enter the limit cycle oscillation mode by switching only one bit of the digital control value at the duty cycle when the detected level of the output voltage has not reached a reference level, and is configured to stop switching the digital control value when the detected level has reached the reference level.

[0017] Exemplarily, the fine-resolution regulator includes:

[0018] The fine output driver, which includes a first fine current device, the first fine current device having a current terminal coupled between the source voltage and the output node and having a control input;

[0019] The analog controller, which includes an error amplifier, the error amplifier having an input receiving a feedback voltage indicating the output voltage and having an output providing the analog control value to the control input of the first fine current device; and

[0020] A preset circuit system, which includes:

[0021] The fine output driver, which further includes a plurality of second fine current devices, the plurality of second fine current devices each having a current terminal coupled between the source voltage and the output node and each having a control input; and

[0022] The preset controller has an input for receiving the digital control value and has an output coupled to the control input of each of the plurality of second fine current devices.

[0023] Exemplarily, the preset controller is configured to deactivate the error amplifier and turn off the plurality of second fine current devices when the digital control value changes in response to an output transient, turn on a certain number of the plurality of second fine current devices based on the calculated duty cycle of the digital control value during the limit cycle mode to preset the fine resolution regulator, and then re-enable the error amplifier.

[0024] Exemplarily, the preset controller is configured with a margin in which the number of the plurality of second fine current devices turned on based on the calculated duty cycle is determined to avoid exceeding a reference level of the output voltage.

[0025] Exemplarily, the preset controller includes:

[0026] A change detector that can provide a load change indication in response to a change in the digital control value;

[0027] A limit cycle oscillation mode detector that can monitor the digital control value to detect the limit cycle oscillation mode and can provide a limit cycle oscillation mode signal indicating the limit cycle oscillation mode; and

[0028] A duty cycle calculator that can calculate the duty cycle of the digital control value in response to the limit cycle oscillation mode signal and can provide a duty cycle value indicating the duty cycle;

[0029] Wherein the preset controller is configured to: deactivate the remainder of the fine resolution regulator in response to the load change indication, including turning off the plurality of second fine current devices and deactivating the error amplifier; set a preset level by turning on a certain number of the plurality of fine current devices based on the duty cycle value; and re-enable the remainder of the fine resolution regulator including the error amplifier.

[0030] Exemplarily, the fine resolution regulator includes:

[0031] The fine output driver, which includes a fine current device having a current terminal coupled between the source voltage and the output node and having a control input;

[0032] The analog controller includes an error amplifier having an input that receives a feedback voltage indicative of the output voltage and an output that provides the analog control value to the control input of the fine current device; and

[0033] The preset controller has an input that receives the digital control value and an output coupled to the control input in the fine current device.

[0034] Exemplarily, the preset controller is configured to deactivate the error amplifier when the digital control value changes in response to an output transient, drive the analog control value to a preset level based on the calculated duty cycle of the digital control value, and then reactivate the error amplifier.

[0035] Exemplarily, the preset controller includes:

[0036] A change detector that can provide a load change indication in response to a change in the digital control value;

[0037] A limit cycle oscillation mode detector that can monitor the digital control value to detect the limit cycle oscillation mode and can provide a limit cycle oscillation mode signal indicative of the limit cycle oscillation mode;

[0038] A duty cycle calculator that can calculate the duty cycle of the digital control value in response to the limit cycle oscillation mode signal and can provide a duty cycle value indicative of the duty cycle; and

[0039] Wherein the preset controller is configured to deactivate the remaining part of the fine resolution regulator including the error amplifier in response to the load change indication, drive the analog control value to a preset level based on the duty cycle of the digital control value, and release the analog control value and reactivate the remaining part of the fine resolution regulator including the error amplifier.

[0040] According to one embodiment, a method of operating a low dropout regulator including a coarse resolution regulator and a fine resolution regulator includes:

[0041] Adjust the digital control value in response to an output transient to control a coarse output driver to regulate the output voltage on an output node at a coarse resolution;

[0042] After detecting that the digital control value is adjusted, deactivate the fine resolution regulator;

[0043] Detect when the digital control value indicates a limit cycle oscillation mode in which the digital control value switches at a corresponding duty cycle;

[0044] Calculate the duty cycle of the digital control value during the limited cycle oscillation mode;

[0045] Preset the fine resolution regulator based on the calculated duty cycle; and

[0046] After presetting the fine resolution regulator, re-enable the fine resolution regulator to drive at least one fine output driver to adjust the output voltage with a fine resolution.

[0047] Exemplarily, the method further includes:

[0048] Compare the detected level of the output voltage with a reference level;

[0049] The adjustment includes entering the limited cycle oscillation mode by switching only one bit of the digital control value at the duty cycle when the detected level of the output voltage has not reached the reference level; and

[0050] When the detected level has reached the reference level, stop switching the digital control value.

[0051] Exemplarily, the deactivating the fine resolution regulator includes:

[0052] Deactivate an error amplifier that drives a first fine current device coupled to the output node; and

[0053] Turn off a plurality of second fine current devices coupled to the output node, the plurality of second fine current devices being used to preset the fine resolution regulator.

[0054] Exemplarily, the presetting the fine resolution regulator includes turning on a certain number of the plurality of second fine current devices based on the calculated duty cycle of the digital control value during the limited cycle mode.

[0055] Exemplarily, the method further includes determining the number of the plurality of second fine current devices for presetting the fine resolution regulator with a sufficient margin to avoid overshooting the reference level of the output voltage.

[0056] Exemplarily, the deactivating the fine resolution regulator includes deactivating an error amplifier that provides an analog control voltage to drive a fine current device coupled to the output node.

[0057] Exemplarily, the presetting the fine resolution regulator includes presetting the analog control voltage to a preset level based on the calculated duty cycle of the digital control value.

[0058] Exemplarily, the re-enabling of the fine resolution regulator includes re-enabling the error amplifier to adjust the analog control voltage so as to regulate the output voltage at a fine resolution.

[0059] According to one embodiment, a low dropout regulator includes:

[0060] A coarse resolution regulator configured to adjust a digital control value in response to an output transient to control a coarse output driver to regulate an output voltage at a coarse resolution at an output node, wherein the coarse resolution regulator is configured to enter a limit cycle oscillation mode when the digital control value switches at a corresponding duty cycle; and

[0061] A fine resolution regulator configured to be deactivated when the digital control value changes in response to an output transition, configured such that a duty cycle of the digital control value is preset, and configured to be re-enabled after being preset to drive at least one fine output driver to regulate the output voltage at a fine resolution.

[0062] Exemplarily, the fine resolution regulator is configured to be preset to a level as close as possible to a reference level of the output voltage without overshooting the reference level. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Embodiments of the present invention are shown by way of example in the drawings, and the embodiments of the present invention are not limited by the drawings. Like reference numerals in the figures may indicate like elements. For simplicity and clarity, the elements in the figures are shown, and these elements are not necessarily drawn to scale.

[0064] Figure 1 is a simplified block diagram of a hybrid low dropout (LDO) regulator with fine loop preset according to one embodiment.

[0065] Figure 2 is a more detailed block diagram of an LDO regulator with fine loop preset according to one embodiment.

[0066] Figure 3 is a table listing the duty cycle range of D_ON of the LDO regulator according to one embodiment Figure 2 and the corresponding values of VPG with M = 4 to show the margin used by the preset controller.

[0067] Figure 4 is a more detailed block diagram of an LDO regulator with fine loop preset according to another embodiment.

[0068] Figure 5 is a simplified block diagram showing the configuration of a digital controller and a preset controller according to one embodiment.

[0069] Figure 6 is a flowchart showing the operation of a hybrid LDO regulator according to various embodiments. DETAILED DESCRIPTION

[0070] The fine-resolution loop of the hybrid LDO is preset according to the duty cycle of a digital control signal provided by the coarse-resolution loop during the limit cycle oscillation mode. In this way, when turned on after an output load transient, the fine loop can initially provide a closer estimate of the supplementary current required to meet the output load level. Then, the analog part of the fine-resolution loop provides any final adjustment required for the output load level. Thus, the hybrid LDO has a smaller output ripple voltage during load transients. The solution described in the present disclosure is independent of the load capacitance, which varies not only at different process corners and temperatures but also greatly between different applications.

[0071] Figure 1 is a simplified block diagram of a hybrid low-dropout (LDO) regulator 100 implemented according to an embodiment with a fine loop preset. The LDO regulator 100 includes a coarse-resolution regulator 102 that provides a coarse output current IC to an output node 106 and a fine-resolution regulator 104 that provides a fine output current IF to the output node 106, thereby generating an output voltage VOUT. In one embodiment, VOUT has a predetermined fixed target voltage level for driving an output load (not shown) coupled to the output node 106. A pair of resistors R1 and R2 are serially coupled between the output node 106 and a voltage supply reference node such as ground (GND). The resistors R1 and R2 have an intermediate feedback node 108 that generates a feedback voltage VFB based on the resistance ratio of R1 and R2. VFB is provided to the respective feedback inputs of the coarse-resolution regulator 102 and the fine-resolution regulator 104 to close the two loops.

[0072] The coarse-resolution regulator 102 includes a digital controller 110 that receives a clock signal CLK, a reference voltage VREF, and the feedback voltage VFB, and outputs a digital control value D_ON to control the activation of a number of the coarse output current drivers 112 in a set of coarse output current drivers 112. The coarse output current drivers 112 include a plurality of drivers, each of which contributes a coarse unit current level to IC when turned on by the digital controller 110 via D_ON. CLK has a high enough frequency level to enable the coarse-resolution regulator 102 to respond very quickly to output load transients between different load levels. VREF has a voltage level indicating the target voltage level of VOUT, where the resistance values of R1 and R2 are selected such that VFB should equal VREF when VOUT is at the predetermined target voltage level.

[0073] The fine resolution regulator 104 includes an analog controller 114 that receives VREF and VFB and outputs an analog control value (ACV) to the fine output current driver 116, or alternatively, to one of a plurality of fine output current drivers 116 (shown and described as the fine output current driver 116, intended to cover both cases). The fine output current driver 116 generates a fine output current IF provided to the output node 106 to supplement the coarse output current IC to meet the output load level, as further described herein. The fine resolution regulator 104 also includes a preset controller 118 that receives D_ON from the digital controller 110. The preset controller 118 outputs an enable signal EN to the enable input of the analog controller 114 to enable or disable the analog controller 114. The EN signal is also provided to the fine output current driver 116 such that when the analog controller 114 is disabled, the fine output current driver 116 is also turned off, causing IF to drop to zero. In one embodiment, the preset controller 118 uses the EN signal to enable or disable the remainder of the fine resolution regulator 204 other than the preset controller 218 itself, including disabling power transistors and the like. The preset controller 118 is used to preset the (one or more) fine output current drivers 116 represented by the PRE signal.

[0074] The digital controller 110 is configured to compare VFB with VREF and quickly respond to load transients by turning on or off one or more of the coarse output current drivers 112 during each cycle of CLK to quickly adjust IC according to the new load level. Thus, the coarse resolution regulator 102 can quickly respond to load changes but does not have the resolution accuracy to adjust IC to fully meet every possible load level. As an example, if the coarse output current drivers 112 include eight coarse current drivers each providing 30 milliamps (mA) of current, the coarse output current drivers 112 can adjust IC from 0 mA to 240 mA in 30 mA increments. If the output load exhibits a load transient that changes from less than 30 mA to 200 mA, the fine resolution regulator 104 is turned off, as further described herein, and the digital controller 110 detects a decrease in VFB and quickly turns on one or more of the coarse current drivers in successive CLK cycles to increase IC until VFB increases back to the level indicated by VREF. For example, the digital controller 110 can turn on seven coarse current drivers to adjust IC to 210 mA to meet the new load level. However, since 210 mA is too high, VFB rises above its target level, causing the digital controller 110 to turn off one of the coarse output current drivers 112 to reduce IC to an overly low 180 mA.

[0075] In the case where the output load lies between the quantized coarse current levels of the coarse output current driver 112, the final digital controller 110 switches D_ON between two different states (e.g., switches the activation of one of the coarse output drivers), where the first state does not provide sufficient current, and the second state provides too much current. In the above example, the digital controller 110 keeps 6 coarse current drivers on while it switches one bit of D_ON in consecutive CLK cycles to switch the activation (on and off) of the seventh coarse current driver. The digital controller 110 switches D_ON between the first state and the second state, where the IC switches between two current levels on either side of the actual load, which is referred to herein as the limit cycle oscillation (LCO) mode of the coarse resolution regulator 102.

[0076] When the digital controller 110 reaches the LCO mode, the duty cycle of D_ON between the two states is approximately equal to the ratio of the difference between the actual load request and the low current output level of the IC to the difference between the low output level and the high output level of the IC provided by the coarse output current driver 112. Thus, when the digital controller 110 enters the LCO mode (in which it switches one bit of D_ON to switch the activation of one coarse output driver, thereby switching the IC between the low current level (LCL) and the high current level (HCL) on either side of the actual load level (LL)), the D_ON bit switches with a certain duty cycle (DC), which can be estimated as DC≈(LL - LCL) / (HCL - LCL). In the above example, for LL = 200 mA, LCL = 180 mA, and HCL = 210 mA, then DC=(200 - 180) / (210 - 180)=0.666, which represents a duty cycle of approximately 67% for the example shown. It should be understood that during the LCO mode, the IC may not actually drop to 180 mA or actually rise to 210 mA, but the digital controller 110 oscillates D_ON with a duty cycle of approximately 67% to meet the load conditions.

[0077] The preset controller 118 is configured to detect any change in D_ON indicative of a load transient, where the preset controller 118 responds by temporarily deactivating the operation of the fine resolution regulator 104. As shown, for example, the preset controller 118 de-asserts EN to deactivate the fine resolution regulator 104 including the analog controller 114 and turn off the fine output driver 116, such that IF goes to zero during an output load transient. Thus, the coarse resolution regulator 102 can respond quickly to the output load transient without competing with the fine resolution regulator 104. In one embodiment, the preset controller 118 is configured to detect the LCO mode of the coarse resolution regulator 102 by monitoring D_ON. As previously described, the LCO mode occurs when D_ON is stable such that only 1 bit in D_ON switches at a stable duty cycle. In response to detecting the LCO mode, the preset controller 118 is further configured to measure or otherwise calculate the oscillating duty cycle of D_ON (meaning the duty cycle of the switching bit). The preset controller 118 can be configured with, for example, a counter or timer and limited arithmetic logic to calculate the duty cycle. When the preset controller 118 determines the duty cycle, it presets the fine output driver 116 based on the measured duty cycle of D_ON. The preset controller 118 then re-asserts the EN signal to re-enable the remainder of the fine resolution regulator 204 including the analog controller 114 and releases the operation of the fine output driver 116.

[0078] The collective output current of the fine output current drivers 116 is at least as large as one quantization level (coarse unit current level) of the coarse output current drivers 112, such that the fine resolution regulator 104 can adjust IF with a high enough resolution to supplement IC to meet the actual output load. Since the fine output driver 116 is preset based on the duty cycle of D_ON, when released by the preset controller 118, the level of IF quickly supplements the current level of IC to a level closer to the actual load level. The re-enabled analog controller 114 then adjusts ACV to adjust IF to more accurately meet the actual load conditions. When the digital controller 110 switches D_ON to turn off the last coarse output driver to a lower IC level, the fine resolution regulator 104 adjusts IF to meet the actual load conditions before the last coarse output driver is turned back on. The digital controller 110 detects the adjusted load conditions via VFB and stops switching D_ON. The collective current IC+IF provided by the coarse resolution regulator 102 and the fine resolution regulator 104 together meet the requested output load conditions.

[0079] Summarizing the operation of the LDO regulator 100, in response to a load transient, the preset controller 118 quickly deactivates the fine-resolution regulator 104 to allow the coarse-resolution regulator 102 to respond to the new load as soon as possible. The load transient can change in either direction, for example, from a low-load condition to a high-load condition, or from a high-load condition to a low-load condition. When the coarse-resolution regulator 102 reaches the LCO mode, the preset controller 118 presets the fine output driver 116 based on the duty cycle of D_ON, and then re-enables the fine-resolution regulator 104 to supplement the output current with IF. Presetting the fine output driver 116 of the fine-resolution regulator 104 according to the duty cycle of D_ON has the advantage of limiting the undershoot / overshoot voltage of the regulator output, which significantly improves the output dynamic accuracy of the LDO regulator 100.

[0080] As further described herein, the fine-resolution regulator 104 can be implemented according to any one of the different embodiments. In one embodiment, the fine output current driver 116 includes a plurality of fine current drivers, where the preset controller 118 controls and presets a subset of the plurality of fine current drivers (e.g., all but one of the fine current drivers). The analog controller 114 controls the last fine current driver to compensate for the difference between the preset amount and the final output load level. In another embodiment, the fine output current driver 116 includes only a single fine output current driver that is capable of providing any amount of current between 0 and the full quantization level of the coarse output current driver 112 or the coarse unit current level. The preset controller 118 is configured to directly preset the ACV based on the measured duty cycle of D_ON, and then re-enable the analog controller 114 to more finely tune the ACV based on the actual output load level.

[0081] Figure 2 is a more detailed block diagram of an LDO regulator 200 implemented according to an embodiment with a fine loop preset. The LDO regulator 200 includes features similar to those of the LDO regulator 100, which include a coarse-resolution regulator 202 (implementing the coarse-resolution regulator 102) and a fine-resolution regulator 204 (implementing the fine-resolution regulator 104), both of which are provided in corresponding control loops for providing a corresponding one of IC and IF to regulate VOUT generated at the output node 106. Again, the resistors R1 and R2 are serially coupled between the output node 106 and GND, where the intermediate feedback node 108 generates VFB, which is provided to the respective feedback inputs of the coarse-resolution regulator 202 and the fine-resolution regulator 204. As previously described, VOUT can be a predetermined fixed target voltage level for driving an output load (not shown) coupled to the output node 106.

[0082] The coarse resolution regulator 202 includes a digital controller 210 that is configured to operate in a manner similar to the digital controller 110. In a manner similar to that previously described, the digital controller 210 receives CLK, VREF, and VFB, and outputs D_ON, which is shown as a set of N digital control signals D_ON[N-1:0] provided to corresponding inputs of the gate driver 211. Again, CLK has a frequency high enough to respond quickly to output load transients, VREF indicates the target voltage level of VOUT, and VFB indicates the actual voltage level of VOUT used to regulate VOUT to the target voltage level. The gate driver 211 converts each of the digital control signals D_ON[N-1:0] into a corresponding gate drive voltage VSG[N-1:0] in a set of gate drive voltages provided to a common set of N coarse output current drivers 212 of the IC.

[0083] In one embodiment, each of the coarse output current drivers 212 is configured as a P-type transistor device, such as a set of exemplary N P-channel MOS (PMOS) transistors MPCi, each PMOS transistor having a source terminal coupled to the upper supply voltage VDD, a drain terminal coupled to the output node 106, and a gate terminal receiving a corresponding gate drive voltage in the set of gate drive voltages VSG[N-1:0], where "i" is an index from 0 to N-1. Each PMOS transistor MPCi has a magnitude for driving the least significant bit (LSB) coarse current level ISLB_C, which contributes to the coarse output current IC provided to the output node 106 when turned on by a corresponding gate drive voltage in the set of N gate drive voltages VSG[N-1:0]. The coarse output current IC is shown as IC = kC(ILSB_C), where kC is a number from 0 to N that identifies the number of the N coarse output current drivers 212 turned on by the gate driver 211.

[0084] The fine resolution regulator 204 includes an error amplifier (EA) 214 for implementing the analog controller 114. The EA 214 includes a negative input receiving VREF, a positive input receiving VFB, and an output providing an analog control value ACV. In this embodiment, the ACV is provided to the control input of a single fine output current driver 215. The fine output current driver 215 can also be implemented as a PMOS transistor MPFM having a source terminal coupled to VDD, a drain terminal coupled to provide a current IFA to the output node 106, and a gate terminal receiving the ACV. A pull-up resistor RPU is shown coupled between the output of the EA 214 and VDD. The EA 214 also includes an enable input receiving an enable signal EN. When enabled, the EA 214 drives the MPFM via the ACV to adjust the IFA in an attempt to make VFB and VREF equal. When disabled, the output of the EA 214 floats or is tri-stated such that the ACV is pulled high to VDD via the resistor RPU to turn off the MPFM such that the IFA is zero (or a minimum current). The RPU is shown as a resistor but can be implemented in an alternative manner such as a MOS switch (not shown).

[0085] The fine resolution regulator 204 also includes a preset controller 218, which implements the preset controller 218 in the illustrated embodiment. The preset controller 218 receives D_ON in the form of a D_ON[N-1:0] signal and provides an enable signal EN for enabling or disabling the remainder of the fine resolution regulator 204 including the EA 214. The preset controller 218 also outputs a set of M gate drive voltages VPG[M-1:0] to the control inputs of a set of M fine output current drivers 216. In one embodiment, each of the fine output current drivers 216 is configured as a set of M PMOS transistors MPFj, each PMOS transistor having a source terminal coupled to VDD, a drain terminal coupled to the output node 106, and a gate terminal receiving a respective one of the gate drive voltages VPG[M-1:0], where "j" is an index from 0 to M-1. In one embodiment, the preset controller 218 turns on any number of the M fine output current drivers 216 in a manner similar to the gate driver 211 turning on the coarse output current driver 212. Each PMOS transistor MPFj has a magnitude for driving a least significant bit (LSB) fine current level ISLB_F, which contributes to the fine output current IF provided to the output node 106 when turned on by the preset controller 218. The fine output current IF is shown as IF = IFA + kF*ILSB_F, where kF is a number from 0 to M that identifies the number of the M fine output current drivers 216 turned on by the preset controller 218, and the asterisk "*" represents multiplication.

[0086] In one embodiment, the maximum current output of the MPFM is approximately equal to each of the M fine output current drivers 216, such that the maximum output current level is IF≈(M + 1)ILSB_F. Additionally, ILSB_C≈(M + 1)ILSB_F, which means that the current output of each of the coarse output current drivers 212 is approximately the same as the combined current capacity of all M fine output current drivers 216 and the fine output current driver 215. Also, the current ILSB_C is selected such that the maximum expected output load current of the LDO regulator 200 is less than N*ILSB_C.

[0087] The operation of the LDO regulator 200 will now be briefly described. The digital controller 210 responds quickly to load transients by adjusting D_ON[N - 1:0] to adjust the IC in order to meet the new output load. The preset controller 218 detects the change in D_ON[N - 1:0] and, in response, de-asserts EN to deactivate the remainder of the fine resolution regulator 204 including the EA 214, and pulls high each of the VPG[M - 1:0] signals to turn off any of the turned-on transistors MPFj. When the EA 214 is deactivated, the RPU pulls high the ACV to turn off the MPFM. In this way, the IF drops to zero. At the same time, the digital controller 210 eventually reaches the LCO mode, in which only one of the D_ON[N - 1:0] signals switches with a relatively stable duty cycle. The preset controller 218 detects the LCO mode, calculates the duty cycle of the switched bit of D_ON[N - 1:0], and applies the corresponding preset of the fine output current driver 216. In one embodiment, the preset controller 218 controls the VPG[M - 1:0] signals to turn on a number of transistors MPFj of the fine output current driver 216 to drive the preset current kF(ISLB_F) as much as possible without exceeding the actual output load current when combined with the IC. Then, the preset controller 218 asserts EN to re-enable the fine resolution regulator 204 including the EA 214, such that the EA 214 drives the MPFM via the ACV to generate the output current IFA to supplement the preset current and thus meet the actual output load current.

[0088] Note that since the preset controller 218 and the fine output driver 216 are not in the control loop for regulating VOUT, the preset controller 218 is configured with sufficient margin to prevent too many transistors MPFj from being activated. If an excessive number of fine output drivers 216 are turned on, the preset current +IC overshoots the actual load current level, such that the EA 214 may not be able to regulate VOUT. The preset controller 218 includes a margin to prevent this, as further described herein. The advantage of presetting the fine output driver 216 of the fine resolution regulator 104 according to the duty cycle of D_ON is to limit the undershoot / overshoot voltage of the regulator output, which significantly improves the output dynamic accuracy of the LDO regulator 200.

[0089] Figure 3 is a table diagram listing the duty cycle range of D_ON of the LDO regulator 200 according to one embodiment and the corresponding values of VPG[M-1:0] for M = 4, to show the margin used by the preset controller 218. The first column lists the duty cycle range of D_ON in percentages. The second column lists VPG[3:0] as the corresponding 4-bit binary values (i.e., 4b'BBBB, where "B" represents an individual bit), indicating the number of transistors MPFj that are turned on within the corresponding duty cycle. In one embodiment, ISLB_F is approximately equal to (1 / (M+1))ISLB_C, and MPFM can drive IFA to at least (1 / M)ISLB_C, such that the activation of all the fine output drivers 216 and MPFM is at least equal to ILSB_C. In this way, the fine resolution regulator 204 is able to generate IF, an amount that sufficiently supplements IC for any expected output load level. For M = 4, the fine output driver 216 includes four transistors MPF[3:0], each transistor providing a current ISLB_F = (1 / 5)ILSB_C when turned on, for a total of (4 / 5)ILSB_C. The last 1 / 5 is provided by MPFM that generates IFA.

[0090] For M = 4, the coarse unit current level represented by ILSB_C is subdivided into 5 ranges: 0 to 20%, 20% to 40%, 40% to 60%, 60% to 80%, and 80% to 100%. In this way, each of the 4 transistors MPFj can contribute 20% of the additional current added to the IC to meet the output load condition. The duty cycle of D_ON is related to each of these ranges to inform the preset controller 218 of the number of fine output drivers 216 to be turned on to reach a sufficient preset level. For example, a duty cycle of 40% can be related to the activation of two of the transistors MPFj. However, the duty cycle measurement performed by the preset controller 218 may not be accurate enough such that if the duty cycle is actually only 39% but read as 40% by the preset controller 218, the preset controller 218 may turn on two of the transistors MPFj when only one transistor is needed. If so, the resulting output current IC + IF may overshoot the actual load amount, leading to incorrect operation. This output current overshoot may not be properly absorbed by the load, ultimately resulting in an overcurrent condition.

[0091] Figure 3 The table shown illustrates a 5% margin for M = 4. The first range is not up to 20% but up to 25% or "<25%", where none of the transistors MPFj are turned on and VPG[3:0] = 4b'1111. The second range is not 20% to 40% but 25% to 45%, where only one of the transistors MPFj is turned on and VPG[3:0] = 4b'1110. The third range is not 40% to 60% but 45% to 65%, where only two of the transistors MPFj are turned on and VPG[3:0] = 4b'1100. The fourth range is not 60% to 80% but 65% to 85%, where only three of the transistors MPFj are turned on and VPG[3:0] = 4b'1000. The fifth range is not >80% but >85%, where all four transistors MPFj are turned on and VPG[3:0] = 4b'0000. It should be noted that when the duty cycle is less than 25%, the number of transistors MPFj turned on (e.g., the number of fine current devices) is zero.

[0092] Note that the transistors MPFM of the EA 214 and the fine output current driver 215 also have a margin to drive more than 1 / 5 of the ISLB_C (e.g., at least 20% more current). In this way, the EA 214 can drive the transistor MPFM up to at least 40% of the coarse unit current level represented by the ILSB_C, such that the final control loop of the EA 214 driving the MPFM meets the new output current level. If a subsequent load transient occurs causing the digital controller 210 to respond by adjusting D_ON, the entire process is repeated to update the operation of the LDO regulator 200.

[0093] Figure 4 FIG. 4 is a more detailed block diagram of an LDO regulator 400 implemented according to another embodiment with a fine loop preset. The LDO regulator 400 includes features similar to those of the LDO regulator 200, which features include a coarse resolution regulator 202 and a fine resolution regulator 404 (implementing the fine resolution regulator 104), both of which are disposed in respective control loops for providing a respective one of the IC and IF to regulate the VOUT generated at the output node 106. Again, resistors R1 and R2 are serially coupled between the output node 106 and GND, where an intermediate feedback node 108 generates the VFB, which is provided to the respective feedback inputs of the coarse resolution regulator 202 and the fine resolution regulator 204. As described above, the VOUT may be a predetermined fixed target voltage level for driving an output load (not shown) coupled to the output node 106.

[0094] In this case, the fine resolution regulator 204 is replaced by the fine resolution regulator 404. The fine resolution regulator 404 includes an error amplifier (EA) 414 generally similar to the EA 214. The EA 414 includes a negative input receiving the VREF, a positive input receiving the VFB, and an output providing an analog control value ACV to the control input of a single fine output current driver 415. The fine output current driver 415 may also be implemented as a PMOS transistor MPF having a source terminal coupled to the VDD, a drain terminal coupled to provide a current IFA to the output node 106, and a gate terminal receiving the ACV. A pull-up resistor RPU (implemented as a resistor or a MOS switch, etc.) is coupled between the output of the EA 414 and the VDD, and the EA 414 also includes an enable input receiving an enable signal EN.

[0095] EA 414 and the fine output current driver 415 implemented by MPF are generally similar in configuration and operation to EA 214 and the fine output current driver 215 implemented by MPFM. The difference is that the fine output current driver 415 implemented by MPF is configured to drive IFA at least up to ILSB_C, because a set of M fine output current drivers 216 of the fine resolution regulator 204 is eliminated.

[0096] The preset controller 218 is replaced by a preset controller 418, and the preset controller 418 also receives D_ON[N-1:0] from the coarse resolution regulator 202. The preset controller 418 operates in a similar manner, where it is configured to de-assert EN to deactivate the remainder of the fine resolution regulator 404 including EA 414 (except for the current controller 418 itself) after detecting any change in D_ON[N-1:0] in response to a load transient. Thereafter, the preset controller 418 monitors D_ON[N-1:0] to detect when the digital controller 210 enters the LCO mode as previously described. When the LCO mode is detected, the preset controller 418 is configured to calculate the duty cycle of D_ON to determine the preset level. In this embodiment, the preset controller 418 is configured with a driver or the like that can preset IF by driving ACV to a preset level via a preset drive signal PRE before activating EA 414. Once ACV is set to the preset level, the preset controller 418 re-asserts EN to re-enable the fine resolution regulator 404 and EA 414, and then releases or opens PRE to enable EA 414 to control the loop and regulate VOUT by adjusting IF based on the new load level.

[0097] In one embodiment, the preset controller 418 may have a set of predetermined preset voltage levels, each voltage level based on a corresponding duty cycle range similar to that illustrated in a Figure 3 table. The predetermined preset voltage levels can be determined by an empirical analysis performed prior to operation. In another embodiment, the preset controller 418 uses a predetermined conversion algorithm or formula, which can also be determined empirically in advance, to convert the measured duty cycle into a corresponding preset value of ACV. The advantage of directly presetting ACV instead of using a separate set of fine output current drivers 216 in any of these embodiments is that the preset can be more accurate and can be closer to the actual final value. Additionally, margin is not an issue because a small amount of overshoot is allowed, as EA 414 operates to correct any preset deviation in either direction.

[0098] Figure 5is a simplified block diagram showing the configuration of a digital controller 510 and a preset controller 518 implemented according to an embodiment. The digital controller 510 is configured to operate in a manner substantially similar to that in which digital controllers 110 or 210 receive CLK, VREF, and VFB and provide D_ON in a manner similar to that previously described. The preset controller 518 is configured to operate in a manner substantially similar to any of the previously described preset controllers 118, 218, or 418. In this case, the preset controller 518 includes a D_ON change detector 502 that monitors D_ON during steady-state operation. When any change in D_ON indicating a load transient occurs, the D_ON change detector 502 asserts a load transient detection (LTD) signal, and the preset controller deactivates the applicable fine-resolution regulators (104, 204, 404) in the same manner as previously described. The preset controller 518 also includes an LCO mode detector 504 that monitors D_ON to determine when the digital controller 510 enters a limit cycle oscillation mode. When the LCO mode is detected, the LCO mode detector 504 asserts an LCO signal indicating the LCO mode. The preset controller 518 further includes a D_ON duty cycle calculator 506 that receives the LCO signal. In response to receiving the LCO signal, the D_ON duty cycle calculator 506 calculates the duty cycle of D_ON in a manner similar to that previously described and provides a duty cycle (DC) value indicating the duty cycle. Once the duty cycle of D_ON is determined, the preset controller 518 presets and enables the applicable fine-resolution regulators (104, 204, 404) in the same manner as previously described.

[0099] Figure 6 is a flowchart showing the operation of a hybrid LDO regulator including LDO regulators 100, 200, and 400 according to various embodiments. After power-on, a reset or restart (POR) operation proceeds to a first block 602 where circuit system initialization is performed. Additionally, the coarse-resolution regulator loop is enabled to start regulating the output voltage VOUT. In this manner, the digital controller of the applicable embodiment monitors VFB and compares it with VREF and correspondingly adjusts the respective digital control value D_ON. The operation proceeds to block 604 where the fine-resolution regulator loop and preset are deactivated. For example, the applicable preset controller de-asserts the enable signal EN to deactivate the fine regulator loop of the respective error amplifier including the control loop. For the LDO regulator 200, the preset controller 218 also asserts the VPG signal to turn off each of the fine output current drivers 216. In this manner, the fine current output from the fine-resolution regulator is zero.

[0100] The operation proceeds to block 606, in which the preset controller monitors D_ON to detect limit cycle oscillation or LCO mode. As previously described, the LCO mode occurs when only 1-bit D_ON switches between two states with a relatively stable duty cycle. At the next query block 608, if the LCO mode is not detected, the operation loops back to block 606, and the operation loops between blocks 606 and 608 while the coarse resolution regulator attempts to regulate VOUT. When the LCO mode is detected at block 608, the operation changes to proceed to block 610, in which the duty cycle of D_ON (or the switching bit) is calculated and the corresponding preset is determined. For example, for the LDO regulator 200, the preset controller 218 determines the number of fine output current drivers 216 to be turned on among the M fine output current drivers 216 without overshooting the applicable output load. As previously described, for M = 4, the preset controller 218 may include a margin as shown in Figure 3 For the LDO regulator 400, the preset controller 418 determines the value of ACV sufficient to apply the applicable preset.

[0101] At the next block 612, the applicable preset controller applies the fine resolution regulator preset, for example, driving VPG[M-1:0] to the determined preset amount or driving ACV to the determined voltage level. At the next block 614, the applicable preset controller enables the fine resolution regulator loop, for example, by re-asserting the enable signal to enable the loop including the corresponding error amplifier and power transistor to start fine loop regulation. It should be noted that the preset application and enabling of the analog error amplifier (e.g., the fine resolution regulator loop) can be performed approximately simultaneously. At the next block 616, the applicable preset controller then monitors D_ON to see any change indicating an output load transient. If, as determined at the next query block 618, no change in D_ON is detected, the operation loops back to block 616. The operation loops between blocks 616 and 618 while the operation is stable without any load transients. After a change in D_ON is detected at block 618, the operation changes to loop back to block 604 to deactivate the fine resolution regulator loop and preset again, as previously described.

[0102] The operation loops between blocks 604 and 618 in response to any load transients during operation. After POR and initialization and after responding to the initial load reaching steady-state operation, the operation loops between blocks 616 and 618. When D_ON changes, the fine-resolution loop and preset (block 604) are disabled, D_ON is monitored to detect the LCO mode (blocks 606 and 608), the duty cycle of D_ON is calculated, and the preset is determined after detecting the LCO mode (block 610), the preset is applied to the fine-resolution regulator (block 612), the fine-loop resolution regulator is re-enabled (block 614), and during steady-state operation, the operation returns to loop between blocks 616 and 618.

[0103] In any of the described embodiments and those in accordance with the embodiments described herein, the fine-resolution loop of the hybrid LDO is preset according to the duty cycle of the digital control signal provided by the coarse-resolution loop during the limit-cycle oscillation mode. In this way, when turned on after an output load transient, the fine loop can initially provide a closer estimate of the supplementary current required to meet the output load level. Then, the analog part of the fine-resolution loop provides any final adjustment required for the output load level. Thus, the hybrid LDO has a smaller output ripple voltage during loop transients. The solution described in the present disclosure is independent of the load capacitance, which varies not only at different process corners and temperatures but also greatly between different applications.

[0104] Although the invention has been described in connection with several embodiments, the invention is not intended to be limited to the specific forms set forth herein. Rather, the present disclosure is intended to cover such alternatives, modifications, and equivalents as may reasonably be included within the scope of the invention as defined by the appended claims. For example, in various embodiments where the invention is not limited to a particular circuit system polarity, device type, or voltage or error levels, etc., variations of positive or negative circuit systems may be used. For example, circuit system states such as circuit system low and circuit system high may be reversed depending on whether a pin or signal is implemented in a positive or negative circuit system, etc. In some cases, the circuit system state may be programmable, where the circuit system state may be reversed for a given circuit system function.

[0105] As used herein, the term "a" is defined as one or more than one. Also, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed to imply that the introduction of another claim element by the indefinite article "a / an" limits any particular claim containing such introduced claim element to an invention having only one such element, even when the same claim includes the introductory phrase "one or more" or "at least one" and an indefinite article such as "a / an". This also applies to the use of definite articles. Unless stated otherwise, terms such as "first" and "second" are used to arbitrarily distinguish the elements so described. Thus, these terms are not necessarily intended to indicate a temporal or other priority of such elements.

Claims

1. A low voltage dropout regulator, characterized in that: include: A coarse resolution adjuster comprising: a coarse output driver coupled to an output node producing an output voltage, wherein the coarse output driver is configured to be controlled by a digital control value; and a digital controller configured to adjust the digital control value in response to an output transient to regulate the output voltage with a coarse resolution, wherein the digital controller is configured to enter a limited cycle oscillation mode by switching the digital control value at a corresponding duty cycle; and A fine resolution adjuster comprising: a fine output driver receiving an analog control value and coupled to the output node; an analog controller configured to adjust the analog control value to regulate the output voltage with fine resolution; and a preset controller configured to deactivate the fine resolution regulator when the digital control value changes in response to an output transient, configured to calculate the duty cycle of the digital control value during the limited cycle oscillation mode, and configured to preset the fine output current driver and re-enable the fine resolution regulator based on the calculated duty cycle.

2. The low voltage dropout regulator according to claim 1, characterized in that: The coarse resolution adjuster comprises: The coarse output driver comprises: a plurality of coarse current devices each having a current terminal coupled between a source voltage and the output node and each having a control input; and a gate driver coupled to the control input of each of the plurality of coarse current devices, wherein the gate driver is configured to turn on a number of the plurality of coarse current devices based on the digital control value; and Wherein the digital controller is configured to adjust the digital control value based on the detected level of the output voltage.

3. The low voltage dropout regulator according to claim 1, characterized in that: The fine resolution adjuster comprises: the fine output driver including a first fine current device having a current terminal coupled between the source voltage and the output node and having a control input; the analog controller including an error amplifier having an input receiving a feedback voltage indicative of the output voltage and having an output providing the analog control value to the control input of the first fine current device; and A preset circuit system, comprising: the fine output driver further comprising a plurality of second fine current devices each having a current terminal coupled between the source voltage and the output node and each having a control input; and The preset controller has an input for receiving the digital control value and has an output coupled to the control input of each of the plurality of second fine current devices.

4. The low voltage dropout regulator according to claim 3, characterized in that: The preset controller comprises: a change detector capable of providing a load change indication in response to a change in said digital control value; a limited cycle oscillation pattern detector capable of monitoring the digital control value to detect the limited cycle oscillation pattern and capable of providing a limited cycle oscillation pattern signal indicative of the limited cycle oscillation pattern; and a duty cycle calculator capable of calculating the duty cycle of the digital control value in response to the limited cycle oscillation mode signal and capable of providing a duty cycle value indicative of the duty cycle; The preset controller is configured to: deactivate the remainder of the fine resolution regulator in response to the load change indication, including turning off the plurality of second fine current devices and deactivating the error amplifier; set a preset level by turning on a certain number of the plurality of fine current devices based on the duty cycle value; and re-enable the remainder of the fine resolution regulator including the error amplifier.

5. The low voltage dropout regulator according to claim 1, characterized in that: The fine resolution adjuster comprises: the fine output driver comprising a fine current device having a current terminal coupled between the source voltage and the output node and having a control input; the analog controller including an error amplifier having an input receiving a feedback voltage indicative of the output voltage and having an output providing the analog control value to the control input of the fine current device; and The preset controller has an input for receiving the digital control value and has an output coupled to the control input in the fine current device.

6. A method of operating a low dropout regulator comprising a coarse resolution regulator and a fine resolution regulator, characterized in that The method comprises: adjusting a digital control value in response to an output transient to control a coarse output driver to regulate an output voltage on an output node with a coarse resolution; upon detecting that the digital control value has been adjusted, disabling the fine resolution adjuster; detecting when the digital control value indicates a limited cycle oscillation mode in which the digital control value switches at a corresponding duty cycle; calculating the duty cycle of the digital control value during the limited cycle oscillation mode; presetting the fine resolution adjuster based on the calculated duty cycle; and The fine resolution adjuster is re-enabled after the fine resolution adjuster is preset to drive at least one fine output driver to adjust the output voltage with fine resolution.

7. The method according to claim 6, characterized in that Also includes: comparing the detected level of the output voltage with a reference level; The adjusting includes entering the limited cycle oscillation mode by switching only one bit of the digital control value at the duty cycle when the detected level of the output voltage has not reached the reference level; as well as When the detected level has reached the reference level, switching of the digital control value is stopped.

8. The method according to claim 6, characterized in that The deactivating the fine resolution adjuster comprises: disabling an error amplifier driving a first fine current device coupled to the output node; and A plurality of second fine current devices coupled to the output node are turned off, the plurality of second fine current devices being used to preset the fine resolution adjuster.

9. A low voltage dropout regulator, characterized in that: include: a coarse resolution regulator configured to adjust a digital control value in response to an output transient to control a coarse output driver to regulate an output voltage on an output node with a coarse resolution, wherein the coarse resolution regulator is configured to enter a limited cycle oscillation mode when the digital control value switches with a corresponding duty cycle; as well as A fine resolution regulator is configured to be disabled when the digital control value changes in response to an output transition, is configured to be preset based on the duty cycle of the digital control value, and is configured to be re-enabled after being preset to drive at least one fine output driver to adjust the output voltage with fine resolution.

10. The low voltage dropout regulator according to claim 9, characterized in that: The fine resolution adjuster is configured to be preset to a level as close as possible to a reference level of the output voltage without overshooting the reference level.

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