A random triggered data stream transmission method and device based on XDMA

Abstract

The present application provides a random triggered data stream transmission method and device based on XDMA, the method comprising: allocating DDR SDRAM space of a board card to obtain a data record storage area for storing data records generated by the board card for each trigger event and a shared control word storage area for storing control word information; after a host computer controls to start data acquisition, the XDMA of the board card writes the control word information to the shared control word storage area based on a preset interrupt cycle to generate a periodic PCIe interrupt; after the board card generates a PCIe interrupt, the host computer promptly receives the PCIe interrupt and promptly responds to the PCIe interrupt to read the control word information in the shared control word storage area, promptly clear the interrupt, and read the corresponding data record in the DDR SDRAM space based on the control word information in the shared control word storage area.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a random triggered data stream transmission method and device based on XDMA. Background Art

[0002] XDMA (Xilinx's DMA / Bridge Subsystem for PCI Express) is a data transfer engine designed specifically for the PCIe bus. It encapsulates the PCIe protocol and provides a simplified API, making data transfer between the FPGA and the host more intuitive and efficient.

[0003] At present, for boards based on PCIe interface, the XDMA solution is basically adopted in FPGA logic software. This is mainly because XDMA provides an efficient and flexible data transmission method that can meet the needs of complex application scenarios such as large data volume and low latency.

[0004] However, previous XDMA systems generated PCIe interrupts based on data volume. This was triggered by the FPGA only when the sampled data volume reached a certain value. If the data volume failed to meet the interrupt triggering condition, even if only a few bytes of sampled data were missing, the stored valid records could not be uploaded to the host computer. In random trigger applications, a large amount of sampled data records might be generated suddenly within a certain period of time, or only a single sampled data record might be generated. Previous XDMA systems struggled to handle data transmission in such scenarios, making it difficult for the host computer to clearly understand the status of the valid data records currently stored on the board. Consequently, the host computer was unable to read the board's currently stored data records in a timely manner. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a random triggered data stream transmission method and device based on XDMA, which uses the data record storage area in the DDR SDRAM space of the board to store the data records generated by the board for each trigger event, and the shared control word storage area to store the control word information, thereby generating and responding to interrupts, and reading the corresponding data records based on the control word information. This can more flexibly upload small data volume collection records to the host computer, without the need to generate a PCIe interrupt only when the collected data volume reaches a certain value, thereby improving the real-time and integrity of the data, and can be applied to random trigger collection scenarios. At the same time, the host computer can clearly obtain more detailed board storage data record status information through the control word information.

[0006] In a first aspect, an embodiment of the present application provides a random triggered data stream transmission method based on XDMA, which is applied to a random triggered data stream transmission device, wherein the random triggered data stream transmission device includes a host computer and a board; the board has XDMA and DDR SDRAM space, and the DDR SDRAM space represents a DDR address space; the method includes:

[0007] Allocate the DDR SDRAM space of the board to obtain a data record storage area for storing data records generated by the board for each trigger event and a shared control word storage area for storing control word information; wherein the data record storage area is used to store the data records generated by the board for each trigger event, and stores them in sequence according to the DDR storage address of the board until the data records fill the area, and then stop storing; the shared control word storage area is used to store the control word information of the data record written by the current board;

[0008] After the host computer controls to start data acquisition, the XDMA of the board writes the control word information into the shared control word storage area based on a preset interrupt cycle to generate a periodic PCIe interrupt;

[0009] After the board generates a PCIe interrupt, the host computer promptly receives the PCIe interrupt and promptly responds to the PCIe interrupt to read the control word information in the shared control word storage area, promptly clear the interrupt, and read the corresponding data record in the DDR SDRAM space based on the control word information in the shared control word storage area.

[0010] In a possible implementation, storing the data records generated by the board each time an event is triggered includes:

[0011] For a data record generated by the board in response to a trigger event, the XDMA of the board stores the data record into the DDR SDRAM space;

[0012] For the data records generated by the board in the next trigger event, the XDMA of the board writes the data records into the DDR SDRAM space in sequence, so as to sequentially store the data records generated by each trigger event into the DDR SDRAM space.

[0013] In one possible implementation, the method further includes:

[0014] After the host computer controls and starts data acquisition, the board monitors the trigger events that meet the preset trigger conditions;

[0015] When the trigger event meets the trigger condition, the host computer collects data records of corresponding length based on the pre-configured data collection length, and writes the data records into the DDR SDRAM space of the board.

[0016] In one possible implementation, the method further includes:

[0017] Writing a first data record to a first starting address of the DDR SDRAM space of the board, and writing a second data record to a second starting address of the DDR SDRAM space; wherein the difference between the first starting address and the second starting address is the data length of each data record; and the interval between the first starting address and the second starting address is the shortest time interval between two random trigger events configured by the host computer;

[0018] In response to writing the target data record into the target start address of the DDR SDRAM space, the control word information is written into the shared control word storage area, and a corresponding PCIe interrupt signal is generated to generate a PCIe interrupt.

[0019] In a possible implementation, the host computer promptly receives the PCIe interrupt and promptly responds to the PCIe interrupt to read the control word information in the shared control word storage area, promptly clear the interrupt, and read the corresponding data record in the DDR SDRAM space based on the control word information in the shared control word storage area, including:

[0020] After receiving the PCIe interrupt, the host computer immediately clears the PCIe interrupt and generates a corresponding semaphore to notify the interrupt response thread of the host computer;

[0021] In the interrupt response thread, the host computer reads the control word information from the shared control word storage area in the DDR SDRAM space, and parses the control word information to obtain the data record currently stored in the DDR SDRAM space of the board.

[0022] In one possible implementation, the method further includes:

[0023] The host computer obtains necessary data record information stored in the current board based on the control word information; wherein the necessary data record information includes at least the data record, the total length of all data records, and the starting address of the last data record stored in the DDR SDRAM space;

[0024] The host computer calculates the starting address of each data record in the DDRSDRAM space of the board and the total length of all data records based on the necessary information of the data record, and moves all data records through one or more DMAs.

[0025] In a possible implementation manner, the control word information is stored in a shared control word storage area in the DDR SDRAM space of the board;

[0026] The starting address and size of the DDR SDRAM space are configured by the host computer; the shared control word storage area is the last continuous area of the DDR SDRAM space;

[0027] The board has read and write permissions to the shared control word storage area, and the host computer has read permissions to the shared control word storage area.

[0028] In a possible implementation manner, the board corresponds to a control program; and the method further includes:

[0029] When the host computer controls and starts data acquisition, the shared control word storage area is cleared through the control program of the board;

[0030] Before the board generates a PCIe interrupt, the board updates the control word information;

[0031] When the host computer responds to the PCIe interrupt, the control word information in the shared control word storage area is read by the host computer.

[0032] In one possible implementation, the method further includes:

[0033] In response to the fact that the DDR SDRAM space of the board contains data records that have not been read by the host computer, the host computer continuously reads the unread data records through DMA.

[0034] In a second aspect, an embodiment of the present application further provides a random triggered data stream transmission device based on XDMA, the random triggered data stream transmission device based on XDMA comprising a host computer and a board; the board has XDMA and DDR SDRAM space, the DDR SDRAM space represents a DDR address space;

[0035] The XDMA-based random triggered data stream transmission device is used to execute the XDMA-based random triggered data stream transmission method provided by the embodiment of the first aspect.

[0036] An embodiment of the present application provides a random triggered data stream transmission method and device based on XDMA, which allocates the DDR SDRAM space of the board to obtain a data record storage area for storing the data records generated by the board for each trigger event and a shared control word storage area for storing control word information. After the host computer controls to start data acquisition, the XDMA of the board writes the control word information to the shared control word storage area based on a preset interrupt cycle to generate a periodic PCIe interrupt. After the board generates a PCIe interrupt, the host computer promptly receives the PCIe interrupt and responds to the PCIe interrupt in a timely manner to read the control word information in the shared control word storage area, clear the interrupt in a timely manner, and read the corresponding data record in the DDR SDRAM space based on the control word information in the shared control word storage area. This application uses the data record storage area in the board's DDR SDRAM space to store the data records generated by each trigger event board, and the shared control word storage area to store control word information, thereby generating and responding to interrupts, and reading the corresponding data records based on the control word information. This allows for more flexible uploading of small amounts of data collection records to the host computer, eliminating the need to generate a PCIe interrupt only when the amount of collected data reaches a certain value. This improves the real-time and integrity of the data and can be applied to random trigger collection scenarios. At the same time, the host computer can clearly obtain more detailed information about the board's stored data record status through the control word information.

[0037] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 Flowchart of a random triggered data stream transmission method based on XDMA provided in an embodiment of the present application;

[0040] Figure 2 This is a schematic diagram of DDR SDRAM space allocation;

[0041] Figure 3 This is a diagram of the interaction between trigger records and control word messages between Card / DDR / Host;

[0042] Figure 4 It is a schematic diagram of the shared control word description. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of illustration and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowcharts can be implemented out of sequence, and steps without logical context can be reversed or implemented simultaneously. In addition, those skilled in the art, under the guidance of the contents of this application, can add one or more other operations to the flowchart, or remove one or more operations from the flowchart.

[0044] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0045] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0046] Consider that XDMA (Xilinx's DMA / Bridge Subsystem for PCI Express) is a data transfer engine designed specifically for the PCIe bus. It encapsulates the PCIe protocol and provides a simplified API, making data transfer between the FPGA and the host more intuitive and efficient. Currently, XDMA is widely used in FPGA logic software for PCIe-based boards. This is primarily due to its efficient and flexible data transfer method, which meets the requirements of complex application scenarios such as large data volumes and low latency.

[0047] However, previous XDMA systems generated PCIe interrupts based on data volume. This was triggered by the FPGA only when the sampled data volume reached a certain value. If the data volume failed to meet the interrupt triggering condition, even if only a few bytes of sampled data were missing, the stored valid records could not be uploaded to the host computer. In random trigger applications, a large amount of sampled data records might be generated suddenly within a certain period of time, or only a single sampled data record might be generated. Previous XDMA systems struggled to handle data transmission in such scenarios, making it difficult for the host computer to clearly understand the status of the valid data records currently stored on the board. Consequently, the host computer was unable to read the board's currently stored data records in a timely manner.

[0048] To address this issue, the present application provides a random-triggered data stream transmission method and device based on XDMA. The data record storage area in the board's DDR SDRAM space stores the data records generated by each trigger event board, and the shared control word storage area stores control word information, thereby generating and responding to interrupts. The corresponding data records are read based on the control word information, enabling more flexible uploading of small amounts of collected data to the host computer. This eliminates the need to generate a PCIe interrupt only after the amount of collected data reaches a certain value, improving the real-time and integrity of the data and enabling application in random-trigger collection scenarios. At the same time, the host computer can clearly obtain more detailed board storage data record status information through the control word information.

[0049] Figure 1 This is a flow chart of a random-triggered data stream transmission method based on XDMA according to an embodiment of the present application. The random-triggered data stream transmission method based on XDMA according to an embodiment of the present application is applied to a random-triggered data stream transmission device. The random-triggered data stream transmission device includes a host computer and a board; the board has XDMA and DDR SDRAM space, where the DDR SDRAM space represents the DDR address space; and the host computer and board are connected, for example, by a communication connection or a physical connection.

[0050] like Figure 1 As shown, the random triggered data stream transmission method based on XDMA in the embodiment of the present application may specifically include:

[0051] S101 , allocating the DDR SDRAM space of the board to obtain a data record storage area for storing data records generated by the board for each trigger event and a shared control word storage area for storing control word information.

[0052] S102 : After the host computer starts controlling data acquisition, the XDMA of the board writes the control word information into the shared control word storage area based on a preset interrupt period to generate a periodic PCIe interrupt.

[0053] S103. After the board generates a PCIe interrupt, the host computer promptly receives the PCIe interrupt and promptly responds to the PCIe interrupt to read the control word information in the shared control word storage area, promptly clear the interrupt, and read the corresponding data record in the DDR SDRAM space based on the control word information in the shared control word storage area.

[0054] In the aforementioned XDMA-based random-triggered data stream transmission method, the data record storage area in the board's DDR SDRAM space stores the data record generated by each trigger event board, and the shared control word storage area stores control word information, thereby generating and responding to interrupts. Based on the control word information, the corresponding data record is read. This allows for more flexible uploading of small amounts of collected data to the host computer, eliminating the need to generate a PCIe interrupt only after the collected data volume reaches a certain value. This improves the real-time and integrity of the data and can be applied to random-triggered collection scenarios. At the same time, the host computer can clearly obtain more detailed information about the board's stored data record status through the control word information.

[0055] The above exemplary steps of the embodiment of the present application are described below with reference to specific examples:

[0056] S101, allocating the DDR SDRAM space of the board to obtain a data record storage area for storing data records generated by the board for each trigger event and a shared control word storage area for storing control word information.

[0057] In the embodiment of the present application, the data record storage area is used to store the data records generated by the board for each trigger event, and is stored in sequence according to the DDR storage address of the board until the data record fills the area, and then stops storing (stops recording), or records in a loop from the DDR starting address; the shared control word storage area is used to store the control word information of the data record written by the current board, and only stores the control word information, but does not store the data record; the DDR SDRAM space of the board is allocated to obtain a data record storage area for storing the data record generated by the board for each trigger event and a shared control word storage area for storing the control word information. Among them, the data record storage area and the shared control word storage area each occupy an independent DDR address space and do not overlap; the control word information includes at least the data length of a single data record, the pre-trigger length, the number of trigger events, the total length of the trigger event data record, and the DDR starting address (Start_addr) of the data record most recently written to the DDR SDRAM space (DDR for short). For example, if Figure 2 As shown, the DDR SDRAM space is allocated as a data record storage area and a shared control word (Ctrl word) storage area, that is, Figure 2The sampled data area and control word area shown in the figure, 1 to N on the left represent N data records in the data record (represented by Rec) storage area, namely the sampled data, and the right part represents the shared control word storage area. Rec length represents the total length of the data record, CW (Ctrl word, control word) length represents the control word length, and Start_addr represents the DDR starting address.

[0058] It should be noted that the control word information is stored in the shared control word storage area within the board's DDR SDRAM space. The starting address and size of the DDR SDRAM space are configured by the host computer. The shared control word storage area is the last contiguous area in the DDR SDRAM space. The board has read and write permissions to the shared control word storage area, while the host computer has read permissions to the shared control word storage area. That is, the host computer only has read permissions to the shared control word storage area, not write permissions. The board's XDMA has both write and read permissions to this area.

[0059] Optionally, when storing the data records generated by the board for each trigger event, the board's XDMA stores the data records generated by the board for the first trigger event into the board's DDR SDRAM space. For the data records generated by the board for the next trigger event, the board's XDMA writes the data records sequentially, incrementally, into the board's DDR SDRAM space (DDR address space), thereby sequentially storing the data records generated by each trigger event into the board's DDR SDRAM space. It is understood that after trigger processing begins, the trigger event generates a data record, and the XDMA stores the acquisition record into the board's DDR SDRAM space. The data record generated by the next trigger event is sequentially written incrementally into the DDR address space, and so on, with the data records generated by each trigger event being sequentially stored into the board's DDR SDRAM space.

[0060] S102: After the host computer starts controlling data collection, the XDMA of the board writes the control word information into the shared control word storage area based on a preset interrupt period to generate a periodic PCIe interrupt.

[0061] In the embodiment of the present application, the interrupt period is configured by the host computer, for example, 100ms. After the host computer controls and starts data acquisition, the board XDMA writes the control word information to the shared control word storage area based on the interrupt period to generate a periodic PCIe interrupt for subsequent processing. For example, the board XDMA periodically writes the control word information to the shared control word storage area and then generates a PCIe interrupt. For example, Figure 3For example, if the PCIe interrupt cycle is set to 100ms, the card (card) and host (host computer) can handle the interrupt handshake process normally within 100ms. Here, Rd represents Read, Wr represents Write, Wr Rec represents a read trigger record (data record), Wr CW represents a write control word, Rd Rec represents a write trigger record (data record), Read CW represents a read control word, PCIe INT (Interrupt) indicates a PCIe interrupt, and INT clear indicates an interrupt clear. Furthermore, within 100ms, even the maximum amount of stored data will not cause data in the DDR to be overwritten. If data record trigger acquisition is completed within 1 second, the data record storage area and the address space for storing control word information are shown in Table 1 below. In this case, since there are 9 PCIe interrupts in 1 second, the shared control word address space on the card will be updated 9 times. The host obtains control word information from the shared control word address space after each PCIe interrupt.

[0062] Table 1

[0063]

[0064] It should be noted that before an interrupt is generated, the total amount of data recorded, the number of trigger events, the address of the most recent trigger event written into the DDR and other information will be written into the shared control word storage area of the DDR.

[0065] It's also important to note that after processing a trigger event, XDMA will periodically generate interrupts, and the interrupt period must be calculated. Specifically, the interrupt period at which the Card generates XDMA interrupts (PCIe interrupts) is configured by the host computer and is independent of whether a trigger event occurs within the interrupt period. In an extreme example, there may not be a trigger event that satisfies the trigger conditions between two PCIe interrupts. Assuming the host computer sets the PCIe interrupt period to 100ms, the Card will periodically generate PCIe interrupts at 100ms intervals after data acquisition begins.

[0066] S103, after the board generates a PCIe interrupt, the host computer promptly receives the PCIe interrupt and promptly responds to the PCIe interrupt to read the control word information in the shared control word storage area, and promptly clear the interrupt, and read the corresponding data record in the DDR SDRAM space based on the control word information in the shared control word storage area.

[0067] In the embodiment of the present application, after the board generates a PCIe interrupt in step S102, the host computer promptly receives the PCIe interrupt and promptly responds to the PCIe interrupt to read the control word information in the shared control word storage area, and promptly clears the interrupt, and reads the corresponding data record in the DDR SDRAM space based on the control word information in the shared control word storage area. That is, after the host computer obtains the control word information, it initiates the operation of reading the data record from the board DDR. For example, Figure 3 Specifically, the host computer receives the PCIe interrupt in a timely manner through the XDMA driver.

[0068] It should be noted that when the host computer receives the PCIe interrupt in a timely manner and responds to the PCIe interrupt in a timely manner to read the control word information in the shared control word storage area and clear the interrupt in a timely manner, and when the corresponding data record is read in the DDR SDRAM space based on the control word information in the shared control word storage area, the host computer clears the PCIe interrupt immediately after receiving the PCIe interrupt and generates a corresponding semaphore to notify the interrupt response thread of the host computer; in the interrupt response thread, the host computer reads the control word information from the shared control word storage area in the DDR SDRAM space, parses the control word information, and obtains the data record stored in the DDR SDRAM space of the current board.

[0069] Specifically, after the card generates a PCIe interrupt, the host XDMA driver promptly receives the interrupt and responds to it (host int response). Generally speaking, upon receiving the interrupt, the host immediately clears the interrupt and generates a semaphore notification (interrupt response thread). In the host interrupt response thread, the host first initiates a read operation from the shared control word space in the card's DDR. The host parses the control word information and retrieves the current collection record stored in the card's DDR. If the card's DDR contains unread data records on the host side, the host continuously reads the valid unread data records to the host side via DMA.

[0070] The random triggered data stream transmission method based on XDMA provided in the embodiment of the present application allocates the DDR SDRAM space of the board to obtain a data record storage area for storing the data records generated by the board for each trigger event and a shared control word storage area for storing control word information. After the host computer controls to start data acquisition, the XDMA of the board writes the control word information to the shared control word storage area based on a preset interrupt cycle to generate a periodic PCIe interrupt. After the board generates a PCIe interrupt, the host computer receives the PCIe interrupt in a timely manner and responds to the PCIe interrupt in a timely manner to read the control word information in the shared control word storage area, clear the interrupt in a timely manner, and read the corresponding data record in the DDR SDRAM space based on the control word information in the shared control word storage area. The XDMA-based random trigger data stream transmission method of the present application uses the data record storage area in the board's DDR SDRAM space to store the data records generated by the board for each trigger event, and the shared control word storage area to store control word information, thereby generating and responding to interrupts. The corresponding data records are read based on the control word information. This method can more flexibly upload small data collection records to the host computer, eliminating the need to generate a PCIe interrupt only when the collected data volume reaches a certain value. This improves the real-time and integrity of the data and can be applied to random trigger collection scenarios. At the same time, the host computer can clearly obtain more detailed information about the board's stored data record status through the control word information.

[0071] Furthermore, after the host computer controls the start of data acquisition, the board monitors for trigger events that meet the preset trigger conditions. When a trigger event meets the trigger condition, the host computer collects a data record of the corresponding length based on the pre-configured data acquisition length and writes the data record to the board's DDR SDRAM space. It should be noted that the data record length can be set by the host computer for each trigger event. For example, if the board's ADC sampling rate is 1GS / s and the data bit width of each sampling point is 16 bits, the data duration of the trigger record can be set to 1u~4us, and this time range can be accurate to 0.5us. Since 1us corresponds to the number of sampling points for a single channel, 1us / 0.5ns = 2000, 2000 samples, each sample is 16 bits, the data volume is 4000 bytes, that is, 4000 bytes, which is the data acquisition length.

[0072] It should be noted that after the host computer starts to collect data, the Card monitors the trigger events that meet the trigger conditions. Once the trigger conditions are met, data records of a certain length are collected and written into the Card DDR. The length of the data collected each time is configured by the host computer.

[0073] Furthermore, the first data record is written to the first starting address of the board's DDR SDRAM space, and the second data record is written to the second starting address of the DDR SDRAM space; in response to writing the target data record to the target starting address of the DDR SDRAM space, the control word information is written to the shared control word storage area, and a corresponding PCIe interrupt signal is generated to generate a PCIe interrupt. The difference between the first starting address and the second starting address is the data length of each data record; the interval between the first starting address and the second starting address is the shortest time interval between two random trigger events configured by the host computer; the target data record represents the Nth data record, that is, the last data record written before the interrupt is generated, and the target starting address represents the Nth starting address, that is, the last starting address written before the interrupt is generated. For example, Figure 3 shown.

[0074] For example, Figure 2 As shown, the Rec1 data record is written to the starting address addr1 of the DDR address space, and the Rec2 data record is written to the starting address addr2 of the DDR address space. The difference between addr1 and addr2 is generally set to the data length of each data record. The interval between Rec1 and Rec2, that is, the shortest time interval between two random triggers, is configured by the host computer. When RecN is written to the starting address addrN of the DDR, the time dimension coincides with the time condition for generating a PCIe interrupt, namely the interrupt cycle (whether RecN is generated does not affect the generation of the PCIe interrupt). The control word information must first be written to the DDR SDRAM space, specifically the shared control word storage area, and then a PCIe interrupt signal is generated to the host computer.

[0075] Furthermore, the host computer obtains the necessary data record information stored on the current board based on the control word information. Based on this necessary data record information, the host computer calculates the starting address of each data record in the board's DDR SDRAM space and the total length of all data records, and then moves all data records through one or more DMA operations. The necessary data record information includes at least the data record, the total length of all data records, and the starting address of the last data record stored in the DDR SDRAM space.

[0076] It should be noted that since the content in the control word information can indicate necessary information such as the data records stored in the current Card DDR, the total length of the data records, the DDR address of the most recent data record, etc., this application can clearly obtain more detailed board storage data record status information.

[0077] Specifically, for example, during the first PCIe interrupt response, the host can use the control word information to determine that the card currently has N data records stored. The total length of these N data records, as well as the starting address of the last RecN stored in the DDR, can also be obtained from the control word information. The host can then calculate the starting address of the N data records in the card's DDR and the total length of these N data records. It can then initiate DMA data transfers to the host using one or more DMA operations. The host needs to cache necessary information, such as the number of data records read in this interrupt response operation and the start and end locations of the DDR address space read, for use in the next interrupt response. Continuing with this, for example, during the second PCIe interrupt response, another M data records are stored in the card's DDR. By analogy, the host can determine from the shared control word message that the total number of data records is N+M, and that the most recent data record, RecN+M, was stored in the DDR starting at address addrN+M. The host, combined with the operation record information from the first interrupt response, clearly needs to read a total of M data records from the DDR address space addrN+1 to addrN+M, rather than reading all N+M data records. This is because the first N data records were already read in the first interrupt response. The subsequent data record reading process is similar and will not be further described in this application.

[0078] It should be noted that the board corresponds to the control program; when the host computer controls and starts data acquisition, the shared control word storage area is cleared through the control program of the board; before the board generates a PCIe interrupt, the board updates the control word information; when the host computer responds to the PCIe interrupt, the control word information in the shared control word storage area is read through the host computer.

[0079] Furthermore, in response to the fact that the DDR SDRAM space of the board contains data records that have not been read by the host computer, the host computer continuously reads the unread data records through DMA.

[0080] The following describes in detail the control word information of the present application, namely the shared control word information, which is stored in the fixed starting address area of the Card-side DDR, namely the shared control word storage area. The starting address of this address space is configured by the host computer, and the size of the address space is also configured by the host computer. Generally, the last continuous area of the Card-side DDR SDRAM space can be configured as the shared control word storage area. Since the host computer has a minimum data amount limit for the amount of data to be moved from the Card-side DDR at a time, the shared control word space should be at least 4096 bytes without wasting DDR storage space. (Address alignment operations need to be considered). For the shared control word space (also known as the shared control word storage area), the Card side has the authority to read and write this area; the Host side only has read permission but not write permission. The Card side needs to complete the clearing operation of the shared control word space when starting data acquisition. Before the Card side generates a PCIe interrupt, the Card side updates the control word information. When the Host side responds to the PCIe interrupt, the Host side reads the control word information.

[0081] In this way, the write operation and the read operation of the shared control word address space are separated in time, avoiding the occurrence of simultaneous reading and writing, thereby ensuring the correctness of the control word information obtained by the host end.

[0082] Continuing, since the effective information actually used by the shared control word occupies a small number of bytes, this application exemplarily proposes the following shared control data structure, which occupies a total of 16 32-bit DDR storage spaces. The data structure of the shared control word is described as follows:

[0083] typedef struct{

[0084] U32magicCode; / *Message code: defined as a constant, such as 0x5555AAAA* /

[0085] U32intCnt; / *Interrupt counter: Each time XDMA generates an interrupt, the counter increases by 1* /

[0086] U32trigCnt; / *Trigger counter: Each time an external trigger or channel trigger occurs, the counter increases by 1* /

[0087] U32preTrigLen; / *Pre-trigger length: unit Byte * /

[0088] U32singleRecLen; / *Single trigger sampling data record length: Unit: Byte* /

[0089] U32totalRecLen_Hi; / *Total sampling data record length: unit Byte, high 32 bits* /

[0090] U32totalRecLen_Lo; / *Total sampling data record length: unit Byte, lower 32 bits * /

[0091] U32curRecDDRaddr_Hi; / *The address where the most recent data record is stored in DDR, high 32 bits, byte address* /

[0092] U32curRecDDRaddr_Lo; / *The address where the most recent data record is stored in DDR, lower 32 bits, byte address* /

[0093] U32resv[7]; / *reserved field* /

[0094] }PCIeIntCtrlWord_t;

[0095] Furthermore, the shared control word is described as follows Figure 4 shown.

[0096] It should be noted that in the case of frequent random trigger events within a short period of time, the maximum amount of data that can be stored in the DDR SDRAM space can be limited. Once the DDR SDRAM space is full, it will no longer respond to subsequent trigger event records. Once the trigger storage is met, the XDMA will periodically generate a hardware interrupt. The generation of this interrupt signal is unrelated to the number of accumulated trigger events.

[0097] Therefore, this application is based on user scheduling (initiated by the host computer, the user develops the host computer software, and implements different implementation methods). Through the interrupt handshake mechanism, the shared control word between the FPGA and the host computer is used as a message communication channel to realize the uploading of FPGA random trigger event data records to the host computer. Compared with the previous interrupt handshake mechanism based on data volume to transmit data, the host computer can clearly obtain more detailed board storage data record status information through control word information, and can more flexibly upload small data volume collection records to the host computer, and can be applied to random trigger collection scenarios. At the same time, the PCIe interrupt handshake mechanism is continued to be used to ensure that the shared control word message can be correctly obtained by the host computer.

[0098] It should be noted that the random triggered data stream transmission method based on XDMA of the present application is a triggered stream data acquisition and transmission method based on XDMA, that is, a random triggered data stream processing method based on XDMA.

[0099] The present application also provides an XDMA-based random-triggered data stream transmission device, comprising a host computer and a board; the board has XDMA and DDR SDRAM space, where the DDR SDRAM space represents the DDR address space. The XDMA-based random-triggered data stream transmission device is used to execute the XDMA-based random-triggered data stream transmission method.

[0100] The XDMA-based random triggered data stream transmission device provided in the embodiment of the present application allocates the DDR SDRAM space of the board to obtain a data record storage area for storing the data records generated by the board for each trigger event and a shared control word storage area for storing control word information. After the host computer controls to start data acquisition, the XDMA of the board writes the control word information to the shared control word storage area based on a preset interrupt cycle to generate a periodic PCIe interrupt. After the board generates a PCIe interrupt, the host computer receives the PCIe interrupt in a timely manner and responds to the PCIe interrupt in a timely manner to read the control word information in the shared control word storage area, clear the interrupt in a timely manner, and read the corresponding data record in the DDR SDRAM space based on the control word information in the shared control word storage area. The XDMA-based random trigger data stream transmission device of the present application uses the data record storage area in the board's DDR SDRAM space to store the data records generated by each trigger event board, and the shared control word storage area to store control word information, thereby generating and responding to interrupts. The corresponding data records are read based on the control word information, which can more flexibly upload small data collection records to the host computer, eliminating the need to generate PCIe interrupts only when the collected data volume reaches a certain value. This improves the real-time and integrity of the data and can be applied to random trigger collection scenarios. At the same time, the host computer can clearly obtain more detailed information about the board's stored data record status through the control word information.

[0101] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiment, and will not be repeated in this application. In the several embodiments provided in this application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0102] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed across multiple network elements. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0103] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0104] If the functions are implemented as software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of this application, or the portion that contributes to the prior art, or the portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the deployment method described in each embodiment of this application. The aforementioned storage medium includes various media that can store program code, such as a USB flash drive, a mobile hard drive, ROM, RAM, a magnetic disk, or an optical disk.

[0105] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A random triggered data stream transmission method based on XDMA, characterized in that: The invention is applied to a random triggered data stream transmission device, the random triggered data stream transmission device includes a host computer and a board; the board has XDMA and DDR SDRAM space, and the DDR SDRAM space represents the DDR address space; the method includes: The DDR SDRAM space of the board is allocated to obtain a data record storage area for storing the data record generated by the board for each trigger event and a shared control word storage area for storing control word information; wherein, the data record storage area is used to store the data record generated by the board for each trigger event, and is stored in sequence according to the DDR storage address of the board until the data record fills the area and stops storing; the shared control word storage area is used to store the control word information of the data record written by the current board; the board end has the authority to read and write the shared control word storage area, and the host end only has the read authority but not the write authority for the shared control word storage area; when the host control starts data acquisition, the shared control word storage area is cleared by the control program of the board; before the board generates a PCIe interrupt, the board updates the control word information; when the host responds to the PCIe Interrupt, read the control word information of the shared control word storage area through the host computer; after the host computer controls to start data acquisition, the XDMA of the board writes the control word information to the shared control word storage area based on a preset interrupt cycle to generate a periodic PCIe interrupt; After the board generates a PCIe interrupt, the host computer promptly receives the PCIe interrupt and promptly responds to the PCIe interrupt to read the control word information in the shared control word storage area, promptly clear the interrupt, and read the corresponding data record in the DDR SDRAM space based on the control word information in the shared control word storage area.

2. The random triggered data stream transmission method based on XDMA according to claim 1, characterized in that: The storing of data records generated by the board each time a trigger event occurs includes: For a data record generated by the board in response to a trigger event, the XDMA of the board stores the data record into the DDRSDRAM space of the board; For the data records generated by the board for the next trigger event, the XDMA of the board writes the data records incrementally into the DDRSDRAM space of the board in sequence, so as to sequentially store the data records generated by each trigger event into the DDRSDRAM space of the board.

3. The random triggered data stream transmission method based on XDMA according to claim 2, characterized in that: The method further comprises: After the host computer controls and starts data acquisition, the board monitors the trigger events that meet the preset trigger conditions; When the trigger event meets the trigger condition, the host computer collects data records of corresponding length based on the pre-configured data collection length, and writes the data records into the DDR SDRAM space of the board.

4. The random triggered data stream transmission method based on XDMA according to claim 3, characterized in that: The method further comprises: Writing a first data record to a first starting address of the DDR SDRAM space of the board, and writing a second data record to a second starting address of the DDR SDRAM space; wherein the difference between the first starting address and the second starting address is the data length of each data record; and the interval between the first starting address and the second starting address is the shortest time interval between two random trigger events configured by the host computer; In response to writing the target data record into the target start address of the DDR SDRAM space, the control word information is written into the shared control word storage area, and a corresponding PCIe interrupt signal is generated to generate a PCIe interrupt.

5. The random triggered data stream transmission method based on XDMA according to claim 4, characterized in that: The host computer promptly receives the PCIe interrupt and promptly responds to the PCIe interrupt to read the control word information of the shared control word storage area, and promptly clears the interrupt, and reads the corresponding data record in the DDR SDRAM space based on the control word information of the shared control word storage area, including: After receiving the PCIe interrupt, the host computer immediately clears the PCIe interrupt and generates a corresponding semaphore to notify the interrupt response thread of the host computer; In the interrupt response thread, the host computer reads the control word information from the shared control word storage area in the DDR SDRAM space, and parses the control word information to obtain the data record currently stored in the DDR SDRAM space of the board.

6. The random triggered data stream transmission method based on XDMA according to claim 5, characterized in that: The method further comprises: The host computer obtains necessary data record information stored in the current board based on the control word information; wherein the necessary data record information includes at least the data record, the total length of all data records, and the starting address of the last data record stored in the DDR SDRAM space; The host computer calculates the starting address of each data record in the DDR SDRAM space of the board and the total length of all data records based on the necessary data record information, and moves all data records through one or more DMAs.

7. The random triggered data stream transmission method based on XDMA according to claim 6, characterized in that: The control word information is stored in a shared control word storage area in the DDR SDRAM space of the board; The starting address and size of the DDR SDRAM space are configured by the host computer; the shared control word storage area is the last continuous area of the DDR SDRAM space; The board has read and write permissions to the shared control word storage area, and the host computer has read permissions to the shared control word storage area.

8. The random triggered data stream transmission method based on XDMA according to claim 7, characterized in that: The board corresponds to a control program; the method further includes: When the host computer controls and starts data acquisition, the shared control word storage area is cleared through the control program of the board; Before the board generates a PCIe interrupt, the board updates the control word information; When the host computer responds to the PCIe interrupt, the control word information in the shared control word storage area is read by the host computer.

9. The random triggered data stream transmission method based on XDMA according to claim 8, characterized in that: The method further comprises: In response to the fact that the DDR SDRAM space of the board contains data records that have not been read by the host computer, the host computer continuously reads the unread data records through DMA.

10. A random triggered data stream transmission device based on XDMA, characterized in that: The random triggered data stream transmission device based on XDMA includes a host computer and a board card; the board card has XDMA and DDR SDRAM space, and the DDR SDRAM space represents the DDR address space; The XDMA-based random triggered data stream transmission device is used to execute the XDMA-based random triggered data stream transmission method according to any one of claims 1-9.

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