Optimization method and system for multi-chip photoelectric hybrid interconnection

Abstract

The invention discloses a multi-chip photoelectric hybrid interconnection optimization method and system, and belongs to the technical field of computers. The method comprises the following steps: determining optical interconnection power consumption data of each chip; determining electric interconnection power consumption data of each chip; determining an optical wavelength multiplexing factor of each chip; determining the optical channel capacity of each chip; calculating an overall photoelectric interconnection transmission energy efficiency ratio; and if the overall photoelectric interconnection transmission energy efficiency ratio is higher than a preset energy efficiency threshold, determining a photoelectric interconnection optimization scheme through a preset optimization model, and optimizing each chip according to the photoelectric interconnection optimization scheme. According to the scheme, optimization is carried out based on the energy efficiency threshold value, it is ensured that the system operates in a high-energy-efficiency state, unnecessary power consumption is reduced, and the operation cost is reduced. Through intelligent optimization, calculation and communication loads of different chips can be adjusted, and the throughput of the whole system is improved. Meanwhile, manual intervention is reduced, and the self-adaptive capacity of the system is improved.

Description

Technical Field

[0001] This application belongs to the field of computer technology, and particularly relates to an optimization method and system for multi-chip optoelectronic hybrid interconnection. Background Art

[0002] In multi-chip systems, with the rapid growth of data communication requirements and the continuous improvement of performance requirements, traditional single interconnection methods have become difficult to meet the high-performance and low-power consumption requirements of modern computing systems. As a technical solution that combines the high-speed and low-latency characteristics of optical interconnection and the flexibility and easy integration advantages of electrical interconnection, optoelectronic hybrid interconnection has gradually become an important trend in multi-chip system interconnection.

[0003] Currently, in multi-chip optoelectronic hybrid interconnection, mainly static configuration and simple management strategies are adopted, using optical interconnection for high-speed data transmission and electrical interconnection for low-speed control and short-distance communication.

[0004] However, the advantages of dynamic power management, flexible resource allocation, and global optimization strategies have not been fully utilized in multi-chip optoelectronic hybrid interconnection nowadays, resulting in high power consumption, low resource utilization, poor transmission efficiency, and a lack of the ability to adaptively adjust according to the actual needs of the system in multi-chip optoelectronic hybrid interconnection systems. Summary of the Invention

[0005] Embodiments of this application provide an optimization method and system for multi-chip optoelectronic hybrid interconnection, which solve the problem that the advantages of dynamic power management, flexible resource allocation, and global optimization strategies have not been fully utilized in multi-chip optoelectronic hybrid interconnection nowadays, resulting in high power consumption, low resource utilization, poor transmission efficiency, and a lack of the ability to adaptively adjust according to the actual needs of the system in multi-chip optoelectronic hybrid interconnection systems.

[0006] In a first aspect, embodiments of this application provide an optimization method for multi-chip optoelectronic hybrid interconnection, and the method includes:

[0007] Obtain the first power consumption state of the optical interconnection module of each chip, and determine the optical interconnection power consumption data of each chip according to the first power consumption state;

[0008] Obtain the second power consumption state of the electrical interconnection module of each chip, and determine the electrical interconnection power consumption data of each chip according to the second power consumption state;

[0009] Obtain the chip configuration and optical interconnection working mode of each chip, and determine the optical wavelength multiplexing factor of each chip according to the chip configuration and optical interconnection working mode;

[0010] Obtain the maximum bandwidth data of each wavelength of each chip, and determine the optical channel capacity of each chip according to the optical wavelength multiplexing factor and the maximum bandwidth data;

[0011] Obtain the chip quantity data, and calculate the overall optical - electrical interconnection transmission energy efficiency ratio according to the chip quantity data, optical interconnection power consumption data, electrical interconnection power consumption data, optical wavelength multiplexing factor, optical channel capacity, and a preset transmission energy efficiency calculation formula.

[0012] If the overall optical - electrical interconnection transmission energy efficiency ratio is higher than a preset energy efficiency threshold, obtain the chip static parameters of each chip, the chip load data of each chip, and the network topology status data, input the optical interconnection power consumption data, electrical interconnection power consumption data, optical wavelength multiplexing factor, optical channel capacity, chip static parameters, chip load data, and network topology status data into a preset optimization model, determine the optical - electrical interconnection optimization scheme, and optimize each chip according to the optical - electrical interconnection optimization scheme.

[0013] Further, the preset transmission energy efficiency calculation formula is:

[0014]

[0015] where, T opt is the overall optical - electrical interconnection transmission energy efficiency ratio; N is the chip quantity data; γ opt，i is the optical wavelength multiplexing factor of the i - th chip; C opt，i is the optical channel capacity of the i - th chip; P opt，i is the optical interconnection power consumption data of the i - th chip; P elec，i is the electrical interconnection power consumption data of the i - th chip.

[0016] Further, after optimizing each chip according to the optical - electrical interconnection optimization scheme, the method further includes:

[0017] If a data exchange request is recognized, determine the target exchange chips corresponding to the data exchange request; where the number of target exchange chips is at least two;

[0018] Obtain the load data of each target exchange chip, and calculate the load imbalance data between each target exchange chip according to the load data;

[0019] Obtain the bandwidth demand data between each target exchange chip, the latency data between each target exchange chip, the preset maximum transmission bandwidth between each target exchange chip, calculate the bandwidth allocation data between each target exchange chip according to the load imbalance data, bandwidth demand data, latency data, load data, preset maximum transmission bandwidth, and a preset bandwidth allocation formula, and implement bandwidth adjustment for each target exchange chip according to the bandwidth allocation data.

[0020] Further, the preset bandwidth allocation formula is:

[0021]

[0022] Among them, B i，j is the bandwidth allocation data; L i is the load data of chip i; L j is the load data of chip j; D ij is the delay data; C ij is the preset maximum transmission bandwidth; N i，j is the bandwidth requirement data; Load imbalance is the load imbalance data; α is the preset bandwidth requirement adjustment coefficient; β is the preset load imbalance adjustment coefficient.

[0023] Further, after implementing the bandwidth adjustment of each target switching chip according to the bandwidth allocation data, the method further includes:

[0024] If the preset update interval is reached, re-obtain the load data of each target switching chip, and re-calculate the load imbalance data between each target switching chip according to the load data;

[0025] Re-obtain the bandwidth requirement data between each target switching chip and the delay data between each target switching chip, and re-calculate the bandwidth allocation data between each target switching chip according to the re-calculated load imbalance data, the re-obtained bandwidth requirement data, the re-obtained delay data, the re-obtained load data, the preset maximum transmission bandwidth, and the preset bandwidth allocation formula, and implement the bandwidth adjustment of each target switching chip according to the re-calculated bandwidth allocation data. Re-calculate the bandwidth allocation data between each target switching chip every time the preset update interval is reached, and implement the bandwidth adjustment of each target switching chip according to the re-calculated bandwidth allocation data until the data exchange of each target switching chip is completed.

[0026] Further, after implementing the bandwidth adjustment of each target switching chip according to the bandwidth allocation data, the method further includes:

[0027] Calculate the power consumption data between each target switching chip according to the load data, the bandwidth allocation data, the delay data, and the preset power consumption calculation formula;

[0028] If there is power consumption data greater than the preset power consumption threshold, determine the target switching chip group corresponding to the power consumption data greater than the preset power consumption threshold, determine the data exchange request, the bandwidth requirement data, the bandwidth allocation data, the delay data, and the preset maximum transmission bandwidth of the target switching chip group, and, determine the load data of each chip of the target switching chip group;

[0029] Obtain the maximum load limit data of each chip in the target switch chip group, input the power consumption data, data exchange request, bandwidth allocation data, latency data, preset maximum transmission bandwidth, load data, bandwidth demand data, and maximum load limit data of the target switch chip group into a preset power consumption adjustment model, determine the power consumption adjustment plan for the target switch chip group, and perform power consumption adjustment on the target switch chip group according to the power consumption adjustment plan.

[0030] Further, the preset power consumption calculation formula is:

[0031]

[0032] Wherein, P i，j is the power consumption data; δ is the preset power consumption coefficient; B i，j is the bandwidth allocation data; L i is the load data of chip i; L j is the load data of chip j; D ij is the latency data.

[0033] In a second aspect, an embodiment of the present application provides an optimization system for multi-chip optoelectronic hybrid interconnection, and the system includes:

[0034] An optoelectronic interconnection power consumption data determination module, configured to obtain the first power consumption state of the optoelectronic interconnection module of each chip, and determine the optoelectronic interconnection power consumption data of each chip according to the first power consumption state;

[0035] An electrical interconnection power consumption data determination module, configured to obtain the second power consumption state of the electrical interconnection module of each chip, and determine the electrical interconnection power consumption data of each chip according to the second power consumption state;

[0036] An optical wavelength multiplexing factor determination module, configured to obtain the chip configuration and optoelectronic interconnection working mode of each chip, and determine the optical wavelength multiplexing factor of each chip according to the chip configuration and optoelectronic interconnection working mode;

[0037] An optical channel capacity determination module, configured to obtain the maximum bandwidth data of each wavelength of each chip, and determine the optical channel capacity of each chip according to the optical wavelength multiplexing factor and the maximum bandwidth data;

[0038] An optoelectronic interconnection transmission energy efficiency ratio calculation module, configured to obtain the chip quantity data, and calculate the overall optoelectronic interconnection transmission energy efficiency ratio according to the chip quantity data, optoelectronic interconnection power consumption data, electrical interconnection power consumption data, optical wavelength multiplexing factor, optical channel capacity, and a preset transmission energy efficiency calculation formula;

[0039] An optoelectronic interconnection optimization module, which is used to obtain the chip static parameters of each chip, the chip load data of each chip, and the network topology status data if the overall optoelectronic interconnection transmission energy efficiency ratio is higher than a preset energy efficiency threshold, input the optical interconnection power consumption data, the electrical interconnection power consumption data, the optical wavelength multiplexing factor, the optical channel capacity, the chip static parameters, the chip load data, and the network topology status data into a preset optimization model, determine an optoelectronic interconnection optimization solution, and optimize each chip according to the optoelectronic interconnection optimization solution.

[0040] In a third aspect, an embodiment of the present application provides an electronic device, which includes a processor, a memory, and a program or instruction stored on the memory and executable on the processor. When the program or instruction is executed by the processor, the steps of the method described in the first aspect are implemented.

[0041] In a fourth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of the method described in the first aspect are implemented.

[0042] In the embodiment of the present application, obtain the first power consumption state of the optical interconnection module of each chip, and determine the optical interconnection power consumption data of each chip according to the first power consumption state; obtain the second power consumption state of the electrical interconnection module of each chip, and determine the electrical interconnection power consumption data of each chip according to the second power consumption state; obtain the chip configuration of each chip and the optical interconnection working mode, and determine the optical wavelength multiplexing factor of each chip according to the chip configuration and the optical interconnection working mode; obtain the maximum bandwidth data of each wavelength of each chip, and determine the optical channel capacity of each chip according to the optical wavelength multiplexing factor and the maximum bandwidth data; obtain the chip quantity data, and calculate the overall optoelectronic interconnection transmission energy efficiency ratio according to the chip quantity data, the optical interconnection power consumption data, the electrical interconnection power consumption data, the optical wavelength multiplexing factor, the optical channel capacity, and a preset transmission energy efficiency calculation formula; if the overall optoelectronic interconnection transmission energy efficiency ratio is higher than a preset energy efficiency threshold, obtain the chip static parameters of each chip, the chip load data of each chip, and the network topology status data, input the optical interconnection power consumption data, the electrical interconnection power consumption data, the optical wavelength multiplexing factor, the optical channel capacity, the chip static parameters, the chip load data, and the network topology status data into a preset optimization model, determine an optoelectronic interconnection optimization solution, and optimize each chip according to the optoelectronic interconnection optimization solution. Through the above-mentioned optimization method for multi-chip optoelectronic hybrid interconnection, optimization is carried out based on the energy efficiency threshold to ensure that the system operates in a high energy efficiency state, reduce unnecessary power consumption, and lower the operating cost. Through intelligent optimization, the computing and communication loads of different chips can be adjusted to improve the throughput of the entire system. At the same time, manual intervention is reduced, and the system's adaptive ability is improved. Description of the Drawings

[0043] Figure 1 It is a schematic flowchart of an optimization method for multi-chip optoelectronic hybrid interconnection provided in the first embodiment of the present application;

[0044] Figure 2 It is a schematic flowchart of an optimization method for multi-chip optoelectronic hybrid interconnection provided in the second embodiment of the present application;

[0045] Figure 3 It is a schematic structural diagram of an optimization system for multi-chip optoelectronic hybrid interconnection provided in the third embodiment of the present application;

[0046] Figure 4 It is a schematic structural diagram of an electronic device provided in the fourth embodiment of the present application. Detailed implementation manners

[0047] In order to make the objectives, technical solutions and advantages of the present application clearer, the following further describes the specific embodiments of the present application in detail with reference to the accompanying drawings. It can be understood that the specific embodiments described herein are only used to explain the present application, rather than limiting the present application. Additionally, it should be noted that for the sake of description, only parts related to the present application are shown in the drawings rather than all the content. Before discussing the exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the operations (or steps) as sequential processes, many of the operations can be implemented in parallel, concurrently or simultaneously. In addition, the order of the operations can be rearranged. When the operations are completed, the process can be terminated, but there may also be additional steps not included in the drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0048] The following will clearly describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application belong to the scope of protection of the present application.

[0049] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. generally belong to the same category, and the number of objects is not limited. For example, the first object can be one or multiple. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally represents an "or" relationship between the associated objects before and after.

[0050] The following will, in conjunction with the accompanying drawings, through specific embodiments and their application scenarios, elaborate in detail on a kind of RSMC chip, a multi-stage chip startup method, and a Beidou communication navigation device provided by the embodiments of the present application.

[0051] Embodiment 1

[0052] Figure 1 is a schematic flowchart of an optimization method for multi-chip optoelectronic hybrid interconnection provided by Embodiment 1 of the present application. As Figure 1 shown, it specifically includes the following steps:

[0053] S101, obtain the first power consumption state of the optical interconnection module of each chip, and determine the optical interconnection power consumption data of each chip according to the first power consumption state.

[0054] First, the application scenario of this solution can be to accurately obtain the power consumption states of the optical interconnection and electrical interconnection modules, and combine chip configuration, optical interconnection working mode, and bandwidth support data to calculate the overall transmission energy efficiency. When the energy efficiency is lower than the preset threshold, use the chip static parameters, load data, and network topology status, input them into the optimization model, and determine the scenario of the optoelectronic interconnection optimization solution.

[0055] Based on the above application scenario, it can be understood that the execution entity of the present application can be an optimization system for multi-chip optoelectronic hybrid interconnection, and no excessive limitation is made here.

[0056] In this solution, in a multi-chip optoelectronic hybrid interconnection architecture, a chip can include: computing chips (such as CPU, GPU, TPU, etc.), switching chips (such as optical switching chips, electrical switching chips), and network chips (such as on-chip network NoC supporting optoelectronic interconnection). These chips can transmit data through optical interconnection and electrical interconnection.

[0057] The optical interconnection module can be an optical communication unit inside or outside the chip, responsible for converting electrical signals into optical signals for transmission and converting optical signals back into electrical signals at the receiving end. Its main components include: optical transceiver: including lasers, modulators, detectors. Optical waveguide: used to transmit optical signals between chips. Multiplexer / demultiplexer: used to support multiple optical wavelength channels. Optical switching unit: can adjust the optical transmission path. The power consumption of the optical interconnection module mainly comes from links such as optical emission, optical reception, optical modulation, and optical amplification.

[0058] The first power consumption state can be the current power consumption characteristics of the optical interconnection module, generally including: static power consumption: the power consumption of the optical interconnection module when there is no data transmission, such as the maintenance power consumption of the laser. Dynamic power consumption: the power consumption generated during processes such as optical signal modulation, transmission, and detection.

[0059] The optical interconnection power consumption data can be a power consumption metric calculated based on the first power consumption state. Specifically, it is the power consumption characteristic of the optical interconnection module under the current working conditions.

[0060] The power consumption of the optical interconnection module without data transmission, i.e., the static power consumption, can be measured by a power monitoring unit or a current sensor. Specifically, it can be obtained through the following formula:

[0061] P static = V × I idle

[0062] where P static is the static power consumption; V is the supply voltage of the optical interconnection module; I idle is the current of the optical interconnection module in the standby state.

[0063] The current of the optical interconnection module during data transmission, i.e., the dynamic power consumption, is measured by a current sensor or a PMU. Specifically, it can be obtained through the following formula:

[0064] P dynamic = V × (I active - I idle )

[0065] where P dynamic is the dynamic power consumption; V is the supply voltage of the optical interconnection module; I active is the current of the optical interconnection module during data transmission; I idle is the current of the optical interconnection module in the standby state. The static power consumption and the dynamic power consumption constitute the first power consumption state. Then, the static power consumption and the dynamic power consumption are added together to obtain the optical interconnection power consumption data of each chip.

[0066] S102. Obtain the second power consumption state of the electrical interconnection module of each chip, and determine the electrical interconnection power consumption data of each chip according to the second power consumption state.

[0067] The electrical interconnection module can be a communication component for data transmission between chips through electrical signals, mainly used for short-distance and high-speed data exchange.

[0068] The second power consumption state can be the power consumption state of the electrical interconnection module under different working conditions, mainly including: Static power consumption: The standby power consumption of the chip electrical interconnection module without data transmission. Dynamic power consumption: The power consumption of the electrical interconnection module during data exchange, including the power consumption of the driving signal, the equalization circuit, and the amplifier.

[0069] The electrical interconnection power consumption data can be a power consumption metric calculated based on the second power consumption state. Specifically, it is the power consumption characteristic of the electrical interconnection module under the current working conditions.

[0070] The power consumption of the electrical interconnection module without data transmission, i.e., the static power consumption, can be measured by a power monitoring unit or a current sensor. Specifically, the static power consumption of the electrical interconnection module can also be obtained using the formula for measuring the static power consumption of the optical interconnection module. The current during data transmission of the electrical interconnection module is measured by a current sensor or a PMU, i.e., the dynamic power consumption. Specifically, the dynamic power consumption of the electrical interconnection module can also be obtained using the formula for measuring the dynamic power consumption of the optical interconnection module. Similarly, the static power consumption and the dynamic power consumption of the electrical interconnection module constitute the second power consumption state, and then the static power consumption and the dynamic power consumption are added together to obtain the electrical interconnection power consumption data.

[0071] S103, obtain the chip configurations and optical interconnection working modes of each chip, and determine the optical wavelength multiplexing factor of each chip according to the chip configurations and optical interconnection working modes.

[0072] The chip configuration can refer to the hardware and communication parameters at the chip level, including but not limited to: the type of optical transceiver module (such as silicon photonics, VCSEL, DFB laser), optical modulation format (NRZ, PAM-4, QPSK), number of wavelength channels (single wavelength vs. multi-wavelength), data rate (such as 25Gbps, 100Gbps, 400Gbps), signal processing capabilities (FEC error correction, DSP digital signal processing). These configurations determine how the chip uses optical signals for data transmission.

[0073] The optical interconnection working mode can determine the transmission mode of optical signals. Specifically, it can include: single wavelength: only one wavelength is used for transmission on each optical link. Wavelength division multiplexing: multiple wavelengths are transmitted simultaneously in the same optical fiber, which is divided into: CWDM (Coarse WDM): the wavelength interval is relatively large (such as 20nm), and the number of channels is small. DWDM (Dense WDM): the wavelength interval is relatively small (such as 0.8nm), and the number of channels is large, up to 40 / 80 / 96 wavelengths. Space division multiplexing: multi-core optical fiber is used, and each optical fiber core transmits signals independently. Polarization multiplexing: different signals are transmitted using the polarization direction of light (horizontal / vertical). Different working modes determine how data is transmitted between chips and affect the calculation of the optical wavelength multiplexing factor.

[0074] The optical wavelength multiplexing factor can refer to the number of wavelengths that can be multiplexed on a single optical link.

[0075] A standard or look-up table can be predefined, which contains the corresponding optical wavelength multiplexing factors under different chip configurations and optical interconnection working modes. For example: different modulation methods (such as NRZ, PAM-4), different optical interconnection modes (such as CWDM, DWDM), supported bandwidth ranges and transmission rates, and then look up according to the chip configuration and optical interconnection working mode: according to the current chip configuration and optical interconnection working mode (such as using CWDM or DWDM, how many wavelengths are supported, etc.), look up the corresponding optical wavelength multiplexing factor in the standard. For example: NRZ modulation format + CWDM mode → the multiplexing factor is found to be 4, PAM-4 modulation format + DWDM mode → the multiplexing factor is found to be 40. Once the corresponding optical wavelength multiplexing factor is found, it can be directly applied.

[0076] S104, obtain the maximum bandwidth data of each wavelength of each chip, and determine the optical channel capacity of each chip according to the optical wavelength multiplexing factor and the maximum bandwidth data.

[0077] The optical channel capacity can refer to the maximum data volume that can be carried through the optical fiber transmission channel (or optical interconnection link).

[0078] The maximum bandwidth data can be the maximum data transmission rate supported by each chip at different wavelengths, usually in Gbps (gigabits per second) or Tbps (terabits per second). These data can be used to calculate the optical channel capacity of the chip.

[0079] The maximum bandwidth data of the chip can be obtained through the following methods: Chip data manual or specification: The manufacturer usually provides detailed technical documents, including the supported wavelength range and maximum bandwidth. Protocol standard: According to the optical communication standard supported by the chip (such as CWDM, DWDM, PON), consult the relevant standard documents to determine the maximum bandwidth of each wavelength. Hardware test measurement: Use a bandwidth tester or optical communication test equipment to measure the actual maximum bandwidth of the chip at different wavelengths. System monitoring data: If the chip has been deployed in the optical network, the actual bandwidth data of each wavelength can be obtained from the network management system (NMS) or real-time monitoring system. After obtaining the maximum bandwidth data, the optical channel capacity of each chip can be calculated through the following formula:

[0080] Optical channel capacity = Optical wavelength multiplexing factor × Maximum bandwidth data of each wavelength

[0081] Suppose a chip supports the CWDM mode, multiplexes 8 wavelengths, and the maximum bandwidth of each wavelength is 10 Gbps, then the optical channel capacity is calculated as follows:

[0082] Optical channel capacity = 8 × 10 Gbps = 80 Gbps

[0083] S105. Obtain the chip quantity data, and calculate the overall optical and electrical interconnection transmission energy efficiency ratio according to the chip quantity data, optical interconnection power consumption data, electrical interconnection power consumption data, optical wavelength multiplexing factor, optical channel capacity, and a preset transmission energy efficiency calculation formula.

[0084] The chip quantity data may refer to the total number of chips participating in optical and electrical interconnection communication in the system, and is used to evaluate the overall transmission energy efficiency.

[0085] The overall optical and electrical interconnection transmission energy efficiency ratio may be the total power consumption per unit transmission capacity (bandwidth), that is, the energy consumption efficiency of the system when transmitting a certain amount of data. The smaller the overall optical and electrical interconnection transmission energy efficiency ratio, the higher the overall transmission energy efficiency (less power consumption per unit bandwidth), the system is in a better state and does not require optimization.

[0086] The chip quantity in each module of the device can be counted through the system architecture information. Then, substitute the chip quantity data, optical interconnection power consumption data, electrical interconnection power consumption data, optical wavelength multiplexing factor, and optical channel capacity into the preset transmission energy efficiency calculation formula to obtain the overall optical and electrical interconnection transmission energy efficiency ratio.

[0087] Based on the above technical solution, optionally, the preset transmission energy efficiency calculation formula is:

[0088]

[0089] Among them, T opt is the overall optical and electrical interconnection transmission energy efficiency ratio; N is the chip quantity data; γ opt，i is the optical wavelength multiplexing factor of the i-th chip; C opt，i is the optical channel capacity of the i-th chip; P opt，i is the optical interconnection power consumption data of the i-th chip; P elec，i is the electrical interconnection power consumption data of the i-th chip.

[0090] In this solution, the relationship between each parameter and the overall optical and electrical interconnection transmission energy efficiency ratio is as follows:

[0091] Optical interconnection power consumption and electrical interconnection power consumption: Both directly affect the total power consumption. The greater the power consumption, the lower the overall transmission energy efficiency.

[0092] Optical wavelength multiplexing factor and optical channel capacity: Both determine the total transmission capacity. Improving these parameters can improve the data transmission efficiency, and thus improve the overall transmission energy efficiency.

[0093] Chip quantity: More chips can increase the parallel transmission capacity, but if the power consumption increases too much, the overall transmission energy efficiency may decrease. Therefore, the optimization solution needs to balance performance and power consumption.

[0094] This formula takes into account the power consumption of both optical and electrical interconnections simultaneously, and can comprehensively reflect the energy consumption of the entire interconnection system. The optical wavelength multiplexing factor and optical channel capacity in the formula reflect the bandwidth utilization rate and data transmission capacity of the optical communication system, enabling the calculation results to accurately evaluate the system performance. The calculated T opt The smaller the value, the less energy is consumed per unit bandwidth, that is, the higher the transmission energy efficiency. Therefore, this formula can be used to evaluate and optimize the energy efficiency level of the optical and electrical interconnection system.

[0095] S106, if the overall optical and electrical interconnection transmission energy efficiency ratio is higher than the preset energy efficiency threshold, obtain the chip static parameters of each chip, the chip load data of each chip, and the network topology status data, input the optical interconnection power consumption data, electrical interconnection power consumption data, optical wavelength multiplexing factor, optical channel capacity, chip static parameters, chip load data, and network topology status data into the preset optimization model, determine the optical and electrical interconnection optimization plan, and optimize each chip according to the optical and electrical interconnection optimization plan.

[0096] The preset energy efficiency threshold can refer to a reference value used to measure whether the energy efficiency of the overall optical and electrical interconnection system reaches the optimization standard. It is usually an empirically set value or a value obtained through experimental statistics, and is used to determine whether the transmission energy efficiency of the current system needs to be optimized.

[0097] The chip static parameters can be the inherent attributes of the chip, parameters that remain unchanged under different loads and network topologies. Specifically, they can include: Chip manufacturing process (nm): such as 5nm, 7nm, 14nm, which affects power consumption and performance. Operating voltage (V): determines the power consumption level, such as 0.8V, 1.2V. Peak computing power (TOPS / FLOPS): the upper limit of the chip's theoretical computing ability. Bandwidth upper limit (Gbps): the maximum data throughput supported. On-chip cache size (MB / GB): affects data storage and access efficiency. Interface type: optical interface: such as Silicon Photonics (SiPh), VCSEL, DFB, electrical interface: such as PCIe5.0, CXL, SerDes.

[0098] The chip load data can be the current actual computing and communication load conditions of the chip. Specifically, it can include current computing load (%): the utilization rate of the chip's computing cores, such as 30%, 70%. I / O load (Gbps): the current traffic of the optical and electrical interconnection interface. Cache utilization rate (%): the usage of the on-chip cache. Dynamic power consumption (W): the power consumption that changes with the load, such as 50W at full load and 10W at low load. Transmission rate (Gbps): the data exchange rate between chips. Data transmission error rate (BER): bit error rate, which affects data retransmission and energy consumption.

[0099] The network topology status data can be the current network interconnection structure of the system, including information such as the data flow path between chips, bandwidth allocation, and traffic bottlenecks. Specifically, it can include chip interconnection topologies: fully connected, ring, tree, Mesh, FatTree. Link utilization rate (%): the occupancy of each link, such as 80%, 40%. Congestion situation (%): Links with high congestion levels will increase latency and energy consumption. Data flow direction: traffic from computing to storage, traffic from computing to computing, traffic from computing to I / O devices. Key node load: which nodes are transmission bottlenecks.

[0100] The preset optimization model can be a mathematical model or an AI prediction model that performs optimization calculations based on multi-variable inputs (optoelectronic interconnection parameters, chip load, network topology). Specifically, the core of the optimization model is to adjust the optoelectronic interconnection structure according to the input data to improve energy efficiency. Possible optimization methods include: Optimization models based on machine learning / reinforcement learning: Using historical data to train the model and dynamically predict the optimal optoelectronic interconnection strategy. Mathematical optimization models (such as mixed integer programming MIP, dynamic programming DP): Optimizing the resource allocation of optoelectronic channels under given constraints. Heuristic algorithms (such as genetic algorithm GA, simulated annealing SA): Finding approximate optimal solutions in large-scale chip networks.

[0101] The optoelectronic interconnection optimization scheme can be an adjustment scheme calculated based on the optimization model to improve the overall optoelectronic interconnection transmission energy efficiency ratio. Specifically, the optimization measures in the optimization scheme can include: Adjusting the optoelectronic interconnection structure (optimizing the optical wavelength allocation, dynamically adjusting the switching strategy between electrical and optical interconnections). Optimizing traffic scheduling (optimizing the data transmission path based on load balancing and traffic prediction). Dynamically adjusting the optical wavelength multiplexing factor (improving the utilization rate of optical channels). Reducing the power consumption of electrical interconnections (reducing unnecessary data transmission, optimizing routing selection). Intelligent load balancing (balancing the computing and communication loads between chips).

[0102] If the overall optoelectronic interconnection transmission energy efficiency ratio is higher than the preset energy efficiency threshold, it indicates that the power consumption per unit bandwidth is relatively high and the energy efficiency is low, suggesting that there may be problems such as inefficient transmission paths and unreasonable power consumption allocation in the current optoelectronic interconnection solution. At this time, optimization is required. Chip manufacturers usually provide detailed manuals that contain the static parameters of the chips. The chip static parameters can be determined by querying the manual, and third-party performance monitoring tools can be used to obtain more detailed chip load data. For example, HWMonitor: Function: A real-time hardware monitoring tool that can monitor CPU temperature, usage rate, fan speed, etc. Features: Intuitive interface, easy to use, and capable of displaying the real-time usage and temperature of each core of the CPU. Network topology discovery tools can automatically scan the network and generate a network topology diagram. These tools usually support multiple protocols and operating systems and can discover information such as devices, connections, and paths in the network. For example, nmap can be used for host discovery and port scanning to infer the network topology; Wireshark can capture and analyze network packets and infer the network topology by parsing the packets. Then, the optoelectronic interconnection power consumption data, electrical interconnection power consumption data, optical wavelength multiplexing factor, optical channel capacity, chip static parameters, chip load data, and network topology status data are input into a preset optimization model, and then the preprocessed data is input into a trained optimization model. The model can be: Deep learning models (such as DNN, LSTM) - directly predict the optimal interconnection strategy. Reinforcement learning models (DQN, PPO) - select optimization actions based on the current state. Mathematical optimization models (linear programming, MIP) - calculate the optimal parameter configuration. The model performs inference and outputs an optoelectronic interconnection optimization plan. According to the optimization plan, corresponding optimization measures can be implemented for each chip to improve the overall transmission energy efficiency. Specifically, the adjustment of the optoelectronic interconnection structure can include:

[0103] (1) Optimize the optical wavelength allocation: Optimization objective: Maximize the utilization rate of the optical channel bandwidth and reduce optical channel contention and bottlenecks.

[0104] Implementation method: Calculate the communication requirements of each chip (based on chip load data and network topology status data). Dynamically allocate wavelength resources to ensure that chips with high communication requirements obtain more wavelengths. Give priority to ensuring high-priority services. For example, the data stream of real-time computing tasks is preferentially allocated more stable optical wavelength channels. For example: Before optimization: The wavelength resources are fixedly allocated, and the optical communication bandwidth of some chips is insufficient, resulting in a fallback to electrical interconnection. After optimization: High-load chips automatically obtain more wavelength resources, increasing the optical transmission ratio and reducing the electrical interconnection power consumption.

[0105] (2) Dynamically adjust the switching strategy between electrical interconnection and optical interconnection: Optimization objective: Ensure high-energy efficiency communication and avoid waste of optoelectronic interconnection resources.

[0106] Implementation method: Monitor the optical channel utilization rate in real time. If the load of the optical communication link is insufficient, part of the electrical interconnection tasks are migrated to the optical channel. Establish a switching threshold. For example, when the load of the optical channel is lower than 60%, give priority to using optical interconnection; when it exceeds 90%, introduce electrical interconnection as a supplement. Low-priority data flows give priority to using electrical interconnection, and high-priority traffic gives priority to using optical interconnection. For example: Before optimization: By default, data goes through electrical interconnection, and the utilization rate of the optical channel is low, and it switches to optical interconnection only under high load. After optimization: Dynamically adjust according to the load, optimize the utilization rate of optical and electrical interconnections, and improve the overall bandwidth efficiency.

[0107] Optimize traffic scheduling

[0108] (1) Optimize the data transmission path based on load balancing: Optimization goal: Prevent some links from being overloaded and improve the network throughput at the same time.

[0109] Implementation method: Calculate the load of each link, dynamically adjust the data flow path, and avoid congestion on hot links. Shunt part of the data on high-load paths and use low-load links to improve communication efficiency. For example: Before optimization: All data goes through the shortest path, resulting in overloading of some links. After optimization: Part of the data is changed to go through alternative paths, enabling multiple links to be evenly utilized.

[0110] (2) Optimize data transmission based on traffic prediction Optimization goal: By predicting future traffic demands, adjust the path in advance to improve the transmission efficiency.

[0111] Implementation method: Combine historical data and machine learning to predict future traffic changes, and adjust routing and resource allocation in advance. Perform pre-scheduling on periodic data flows to avoid congestion caused by burst traffic. For example: Before optimization: The data path adjustment is based on the current state without considering future load trends. After optimization: Predict high-traffic periods, adjust link resources in advance, and improve the overall throughput.

[0112] Dynamically adjust the optical wavelength multiplexing factor: Optimization goal: Improve the utilization rate of the optical channel and enable more data to be transmitted on the same optical channel.

[0113] Implementation method: Monitor the idle rate of the optical channel. If the idle rate is high, increase the wavelength multiplexing factor to increase the throughput. Set an adaptive adjustment rule. For example, when the utilization rate of the optical channel is lower than 50%, increase the multiplexing factor so that a single wavelength can carry more data flows. Combine the bandwidth requirements of different data types and provide a higher multiplexing rate for low-speed data flows to save resources. For example: Before optimization: The wavelength multiplexing factor is fixed, resulting in insufficient utilization of the bandwidth of some wavelengths. After optimization: Dynamically adjust the multiplexing factor, enabling data with low bandwidth requirements to share a single wavelength and improving resource utilization.

[0114] Reduce the power consumption of electrical interconnection

[0115] (1) Reduce unnecessary data transmission: Optimization objective: Reduce invalid data transmission and lower communication power consumption.

[0116] Implementation method: Adopt data compression algorithms to reduce the amount of data transmitted. Intelligently cache hot data to reduce repeated data requests. For example: Before optimization: The same data is transmitted multiple times, resulting in unnecessary power consumption. After optimization: Repeated transmissions are reduced through caching, lowering energy consumption.

[0117] (2) Optimize routing selection: Optimization objective: Select a low-power path for data transmission.

[0118] Implementation method: Calculate the energy consumption of different paths and select the most energy-efficient communication path. Prioritize the use of optical interconnections rather than long-distance electrical interconnections.

[0119] For example: Before optimization: The shortest path is selected by default, but the energy consumption is high. After optimization: Switch to a low-power path, reducing the overall energy consumption by 20%.

[0120] Intelligent load balancing

[0121] (1) Balance the computing load between chips: Optimization objective: Prevent a single chip from being overloaded and improve the overall computing efficiency.

[0122] Implementation method: Real-time monitor the computing load of each chip and dynamically adjust the distribution of computing tasks. When the load of a certain chip approaches the threshold, migrate some tasks to other chips.

[0123] For example: Before optimization: The computing load of chip A is 90%, while that of chip B is only 40%. After optimization: Some tasks are migrated to chip B, balancing both at 65%.

[0124] (2) Balance the communication load between chips

[0125] Optimization objective: Avoid overloading the communication volume of individual chips and ensure stable data transmission.

[0126] Implementation method: Identify communication hot-spot chips and disperse some data streams to other chips. Reduce the communication pressure on hot-spot chips through topology adjustment. For example: Before optimization: More than 80% of the data traffic of a certain chip passes through a high-load channel. After optimization: Some data streams are redirected to other low-load paths, improving the overall stability.

[0127] The training process of the preset optimization model includes:

[0128] Collect historical data, including: optical interconnection power consumption data (unit: W), electrical interconnection power consumption data (unit: W), optical wavelength multiplexing factor (unit: dimensionless), optical channel capacity (unit: Gbps), chip static parameters (including computing power, communication interfaces, etc.), chip load data (unit: percentage or data throughput), network topology status data (unit: link utilization rate, connection relationship, etc.). The collection of historical data can be based on a long-term running monitoring system to record the optoelectronic interconnection behavior of different chips under different load conditions. Then perform normalization processing (such as Min-Max normalization): to avoid the influence of data with different dimensions on model training. Data cleaning (removing outliers and filling missing values): to improve data quality. Feature engineering (such as time window processing): to extract trend features, such as the average power consumption in the past 10 seconds, etc. Then perform label setting, and the label is the corresponding historical optoelectronic interconnection optimization scheme, that is, under the same input conditions, the optimization measures adopted historically, including: adjusting the optoelectronic interconnection structure (optimizing optical wavelength allocation, dynamically switching optical / electrical interconnection), optimizing traffic scheduling (load balancing, traffic prediction), adjusting the optical wavelength multiplexing factor (improving optical channel utilization rate), reducing electrical interconnection power consumption (reducing data transmission, optimizing routing), intelligent load balancing (balancing computing load and communication load). This means that the model learns the mapping relationship from historical data to optimization schemes and can recommend the best optimization strategy when encountering similar situations in the future. The following machine learning / deep learning methods can be used: Supervised learning (training a classification model based on historical data optimization schemes): such as decision trees, XGBoost, random forests, deep neural networks (DNN). Reinforcement learning (dynamically adjusting optimization strategies): such as deep reinforcement learning (DQN, PPO), which is optimized after continuously simulating the execution effect of optimization strategies. Reinforcement + supervised hybrid (initially trained based on historical data and then optimized using reinforcement learning). Then verify the accuracy of the model's optimization suggestions through historical data (such as Top-1 / Top-3 prediction accuracy). Use a simulation environment to test the adaptability of the model to new situations and adjust hyperparameters. And run it in a real system and continuously improve the model performance through online learning.

[0129] Among them, the relationships between the optical interconnection power consumption data, electrical interconnection power consumption data, optical wavelength multiplexing factor, optical channel capacity, chip static parameters, chip load data, and network topology status data and the optoelectronic interconnection optimization scheme are as follows:

[0130] Optical interconnection power consumption data: It is affected by adjusting the optoelectronic interconnection structure and reducing the electrical interconnection power consumption in the optimization scheme. Specifically, it can reflect the energy efficiency of optical communication and help judge whether it is necessary to adjust the optoelectronic interconnection switching strategy to reduce the usage ratio of optical interconnection under high energy consumption conditions.

[0131] Electrical interconnection power consumption data: It has an impact on adjusting the optoelectronic interconnection structure and reducing the electrical interconnection power consumption in the optimization scheme. Specifically, if the electrical interconnection power consumption is too high, it may be necessary to increase the proportion of optical interconnection or optimize the data transmission path to reduce the burden of electrical interconnection.

[0132] Optical wavelength multiplexing factor: It has an impact on adjusting the optical wavelength multiplexing factor and optimizing traffic scheduling in the optimization scheme. Specifically, it will affect the utilization rate of optical channels. Increasing the multiplexing factor can increase the carrying capacity of optical channels, but it may affect signal interference and needs to be weighed.

[0133] Optical channel capacity: It has an impact on optimizing traffic scheduling and adjusting the optical wavelength multiplexing factor in the optimization scheme. Specifically, it will affect the maximum bandwidth of data transmission. If the capacity is insufficient, it may be necessary to increase the multiplexing factor or reallocate wavelength resources.

[0134] Chip static parameters: It has an impact on intelligent load balancing and optimizing traffic scheduling in the optimization scheme. Specifically, it determines the computing and communication capabilities of the chip and affects the load balancing strategy. A chip with high computing power can undertake more tasks, while a chip with low computing power needs to reduce communication pressure.

[0135] Chip load data: It has an impact on intelligent load balancing and optimizing traffic scheduling in the optimization scheme. Specifically, it can reflect the current computing and communication load of the chip and determine whether it is necessary to migrate tasks or adjust the communication path.

[0136] Network topology status data: It has an impact on optimizing traffic scheduling and adjusting the optoelectronic interconnection structure in the optimization scheme. Specifically, it will affect the routing selection of data streams, help optimize the data transmission path, avoid hot spot congestion, and improve the overall throughput.

[0137] This scheme can recalculate the overall optoelectronic interconnection transmission energy efficiency ratio at regular intervals and re-determine the optoelectronic interconnection optimization scheme when the overall optoelectronic interconnection transmission energy efficiency ratio is higher than the preset energy efficiency threshold to achieve dynamic optimization of the optoelectronic interconnection.

[0138] In the embodiments of the present application, the first power consumption state of the optical interconnection module of each chip is obtained, and the optical interconnection power consumption data of each chip is determined according to the first power consumption state; the second power consumption state of the electrical interconnection module of each chip is obtained, and the electrical interconnection power consumption data of each chip is determined according to the second power consumption state; the chip configuration of each chip and the optical interconnection working mode are obtained, and the optical wavelength multiplexing factor of each chip is determined according to the chip configuration and the optical interconnection working mode; the maximum bandwidth data of each wavelength of each chip is obtained, and the optical channel capacity of each chip is determined according to the optical wavelength multiplexing factor and the maximum bandwidth data; the chip quantity data is obtained, and the overall optoelectronic interconnection transmission energy efficiency ratio is calculated according to the chip quantity data, the optical interconnection power consumption data, the electrical interconnection power consumption data, the optical wavelength multiplexing factor, the optical channel capacity, and a preset transmission energy efficiency calculation formula; if the overall optoelectronic interconnection transmission energy efficiency ratio is higher than a preset energy efficiency threshold, the chip static parameters of each chip, the chip load data of each chip, and the network topology state data are obtained, the optical interconnection power consumption data, the electrical interconnection power consumption data, the optical wavelength multiplexing factor, the optical channel capacity, the chip static parameters, the chip load data, and the network topology state data are input into a preset optimization model, an optoelectronic interconnection optimization scheme is determined, and each chip is optimized according to the optoelectronic interconnection optimization scheme. Through the above optimization method for multi-chip optoelectronic hybrid interconnection, optimization is performed based on the energy efficiency threshold to ensure that the system operates in a high energy efficiency state, reduce unnecessary power consumption, and lower the operating cost. Through intelligent optimization, the computing and communication loads of different chips can be adjusted to improve the throughput of the entire system. At the same time, manual intervention is reduced, and the system's adaptability is improved.

[0139] Embodiment 2

[0140] Figure 2 is a schematic flowchart of the optimization method for multi-chip optoelectronic hybrid interconnection provided by Embodiment 2 of the present application. As Figure 2 shown, it specifically includes the following steps:

[0141] S201, if a data exchange request is recognized, determine the target exchange chips corresponding to the data exchange request; wherein, the number of target exchange chips is at least two.

[0142] The data exchange request may refer to the data transmission requirement initiated by the system in the optoelectronic interconnection network, usually triggered by computing tasks, storage access, or communication protocols, indicating that data needs to be exchanged between some chips. Specifically, it may be triggered by internal chip tasks, such as the intermediate data transmission of cross-chip computing tasks. It may be triggered by external instructions, such as data transmission requests initiated by network devices, storage controllers, etc. It may be based on system scheduling, such as actively adjusting the data transmission path according to strategies such as load balancing and power consumption optimization.

[0143] The target switching chips can be chips that need to participate in data exchange, namely the source chip that sends data and the destination chip that receives data. Among them, the source chip is responsible for sending data to the destination chip. The destination chip is responsible for receiving the data transmitted from the source chip. The number of target switching chips is at least two or more, which means that the data exchange may be point-to-point (single chip to single chip) or multi-to-multi (data exchange among multiple chips).

[0144] It can monitor the data bus and the chip - to - chip communication protocol to detect whether there is a data exchange request. Once a data exchange request is identified, the system determines the target switching chips that need to participate in the data exchange according to the request content. The number of target switching chips is at least two, and all chips participating in the data exchange are regarded as target switching chips, including the source chip and the destination chips (which can be multiple destination chips). Specifically, the system can automatically select target switching chips through network topology analysis. First, the system selects the optimal data transmission path according to the network structure. For multicast or broadcast requests, the target switching chips will include all chips that receive the requests. The target chips include the source chip and all its connected destination chips (receiving chips), and these chips will participate in the data exchange. Then, obtain the source chip ID and destination chip ID of the data exchange to confirm the direction of data transmission. Analyze parameters such as the bandwidth requirement, priority, and time constraint of the data exchange.

[0145] S202, obtain the load data of each target switching chip, and calculate the load imbalance data between each target switching chip according to the load data.

[0146] The load data can be the resource consumption or utilization related to the calculation, processing, communication, or task execution of each chip. These data reflect the workload of the chip during operation.

[0147] The load imbalance data can be used to indicate whether the load distribution among multiple target switching chips is uniform. If the load differences among chips are large, it will lead to load imbalance, affecting the efficiency and performance of the system. The load imbalance data reflects the degree of these differences.

[0148] Load data can be collected from each target switching chip, and these data can be collected in real time through hardware monitoring tools, operating systems, or sensors. For each target switching chip, relevant data including computing load, communication load, storage load, and power consumption load are collected. Specifically, computing load: generally refers to the processing power occupied when the chip executes computing tasks, such as the usage rate of the CPU or GPU, or the complexity of a specific computing task. Communication load: refers to the amount of data exchanged between the chip and other chips or systems, including the data traffic sent and received, communication latency, etc. Storage load: reflects the usage of the chip's storage resources, such as disk I / O operations, storage bandwidth, storage access frequency, etc. Power consumption load: the power consumption when the chip is running, which is usually related to the activity level of the chip. The higher the power consumption, the greater the load. These load data come from different types of resources, and their units, magnitudes, and influencing factors may be different, so different weights usually need to be assigned according to the actual situation. The weighted composite load data can be obtained in the following way: Direct weighting: Assign a weight factor to each load item (computing load, communication load, storage load, power consumption load, etc.). The distribution of weights reflects the impact of each load on system performance. For example, the computing load may be more important than the storage load, so a larger weight can be assigned to the computing load. Then calculate the load data through the following formula:

[0149] Total load data = w 1 Computing load + w 2 Communication load + w 3 Storage load + w 4 Power consumption load

[0150] where w 1 , w 2 , w 3 , w 4 are the weight factors corresponding to the load types.

[0151] Then calculate the average value of the loads of all target switching chips, and then calculate the difference between each chip and this average value to obtain the load imbalance data. Specifically, it can be calculated through the following formula:

[0152]

[0153] where M is the number of target switching chips, and the load data i is the load data of the i-th target chip, and the average load is the average value of the load data of all chips. For example, if there are three target switching chips, chip a exchanges data with chip b, and chip b exchanges data with chip c, then one calculation is performed between chip a and chip b, and one calculation is performed between chip b and chip c.

[0154] S203. Obtain the bandwidth requirement data, latency data, and preset maximum transmission bandwidth between each target switching chip. Calculate the bandwidth allocation data between each target switching chip according to the load imbalance data, bandwidth requirement data, latency data, load data, preset maximum transmission bandwidth, and a preset bandwidth allocation formula. Adjust the bandwidth of each target switching chip according to the bandwidth allocation data.

[0155] The bandwidth requirement data can be the size of the bandwidth required by each target switching chip during data exchange.

[0156] The latency data can be the data transmission latency between each target switching chip, usually measured in milliseconds (ms) or microseconds (μs). The influencing factors include the length of the data transmission path, the degree of network congestion, and the processing latency inside the switching chip, etc.

[0157] The preset maximum transmission bandwidth can be the maximum available transmission bandwidth between each target switching chip. This value is limited by factors such as the chip hardware capabilities, the configuration of the optical - electrical interconnection system, and the network topology structure, etc.

[0158] The bandwidth allocation data can be the actual bandwidth allocation result calculated according to the bandwidth requirement data, load imbalance data, latency data, and preset maximum transmission bandwidth. This data is used to guide the bandwidth adjustment of each target switching chip to optimize the data transmission efficiency and reduce bottlenecks.

[0159] It is possible to count the total amount of data sent from chip i to chip j within a certain time window and calculate the bandwidth requirement. The calculation formula can be:

[0160]

[0161] where D i is the bandwidth requirement data of the target switching chip i; R i (t) is the traffic rate at the sampling moment of time t; T is the sampling window size (such as 1 second).

[0162] The latency data represents the data transmission latency between chips. Usually, it can be obtained in the following ways: Network clock synchronization measurement: After chip A sends a data packet, record the arrival time at chip B and calculate the round - trip time (RTT). Active probing: Send small probing data packets and record the return time to calculate the one - way latency (the processing latency can be subtracted). Hardware topology information: Based on the connection path of the switching architecture, query the preset link latency parameters. The calculation formula can be:

[0163]

[0164] where L i，jis the latency data between chip i and chip j; RTT i，j is the round-trip time.

[0165] The preset maximum transmission bandwidth between each target switching chip can be obtained in the following ways: Hardware specification query: Determine the maximum bandwidth according to the physical interface rate of the switching chip (such as 10Gbps, 25Gbps). Network topology configuration: Query the current link allocation situation between chips to ensure that the bandwidth does not exceed the allocated upper limit. QoS restriction: If there is a bandwidth sharing mechanism, query the priority rules and calculate the available maximum bandwidth.

[0166] Then, substitute the load imbalance data, bandwidth demand data, latency data, load data, and preset maximum transmission bandwidth into the preset bandwidth allocation formula to obtain the bandwidth allocation data between each target switching chip, and then perform bandwidth adjustment: Traffic regulation: Dynamically adjust the data transmission rate to match the calculated bandwidth allocation. Priority scheduling: Prioritize bandwidth allocation to high-priority tasks and reduce low-priority traffic. Path optimization: If the bandwidth of a certain path is insufficient, switch to an alternative path.

[0167] In this embodiment, by dynamically calculating the bandwidth allocation, the bandwidth resources between chips can be utilized more reasonably, data transmission bottlenecks can be reduced, and the data exchange speed can be improved. Bandwidth is allocated on demand to avoid resource waste, enabling high-load chips to obtain higher bandwidth.

[0168] Based on the above technical solution, optionally, the preset bandwidth allocation formula is:

[0169]

[0170] where B i，j is the bandwidth allocation data; L i is the load data of chip i; L j is the load data of chip j; D ij is the latency data; C ij is the preset maximum transmission bandwidth; N i，j is the bandwidth demand data; Load imbalance is the load imbalance data; α is the preset bandwidth demand adjustment coefficient; β is the preset load imbalance adjustment coefficient.

[0171] In this solution, the relationship between the parameters in the formula and the formula is:

[0172] L i ·L j represents the current computing load of chip i and chip j. The higher the load, the more bandwidth the chip needs to process tasks. Therefore, the bandwidth allocation should be positively correlated.

[0173] D ijRepresents the communication delay from chip i to chip j. Chips with high delays may be more sensitive to bandwidth requirements because high delays affect data transmission efficiency.

[0174] C ij Represents the theoretical maximum transmission bandwidth between chip i and chip j. This value serves as a physical constraint on the bandwidth and determines the upper limit of bandwidth allocation between chips.

[0175] N i，j Represents the real-time bandwidth requirement between chip i and chip j. The higher the requirement, the more the bandwidth allocation should tend to increase, but it is limited by C ij and the load balancing strategy.

[0176] Load imbalance can measure the load balancing situation of the entire chip network. When the load is unbalanced, the system needs to dynamically adjust the bandwidth to reduce local overload or bandwidth waste.

[0177] α and β can determine appropriate weights by analyzing historical data and observing the impact of bandwidth requirements and load imbalance on system performance. For example, if historical data indicates that bandwidth requirements have a greater impact on performance, then increase the value of α. Conduct experiments with different α and β, analyze their impact on bandwidth allocation and system load balancing, and select the optimal parameters. Or preset an initial value (such as α = 0.5, β = 0.5), and then dynamically adjust it through an adaptive optimization algorithm (such as gradient descent or reinforcement learning) to ensure long-term optimization of the system.

[0178] Based on the above technical solution, optionally, after adjusting the bandwidth of each target switching chip according to the bandwidth allocation data, the method further includes:

[0179] If a preset update interval is reached, re-obtain the load data of each target switching chip, and recalculate the load imbalance data between each target switching chip according to the load data;

[0180] Re-obtain the bandwidth requirement data between each target switching chip and the delay data between each target switching chip. According to the recalculated load imbalance data, the re-obtained bandwidth requirement data, the re-obtained delay data, the re-obtained load data, the preset maximum transmission bandwidth, and the preset bandwidth allocation formula, recalculate the bandwidth allocation data between each target switching chip, and adjust the bandwidth of each target switching chip according to the recalculated bandwidth allocation data. Recalculate the bandwidth allocation data between each target switching chip every time a preset update interval is reached, and adjust the bandwidth of each target switching chip according to the recalculated bandwidth allocation data until the data exchange of each target switching chip is completed.

[0181] In this solution, the preset update interval can refer to the time period when the system periodically triggers the recalculation and adjustment of bandwidth allocation.

[0182] Each time the preset update interval is reached, the system can re-obtain the load data of each target switching chip and calculate the load imbalance between them; at the same time, re-obtain the bandwidth requirements and latency data of each target switching chip. Based on the latest load imbalance data, bandwidth requirement data, latency data, current load data, preset maximum transmission bandwidth, and bandwidth allocation formula, calculate the new bandwidth allocation data and adjust the bandwidth allocation of each target switching chip accordingly. This process is continuously repeated within each update interval cycle to ensure dynamic optimization of bandwidth allocation until all target switching chips complete data exchange.

[0183] In this solution, dynamically adjusting the bandwidth according to the bandwidth requirements and load status of each chip can reduce the waiting time for data transmission, thereby reducing latency and improving the system response speed. The system can sense and respond to load changes in real time and adjust the bandwidth allocation according to actual needs, rather than relying on static configuration, which enables the system to adapt to changing workloads.

[0184] Based on the above technical solution, optionally, after implementing the bandwidth adjustment of each target switching chip according to the bandwidth allocation data, the method further includes:

[0185] Calculate the power consumption data between each target switching chip according to the load data, bandwidth allocation data, latency data, and preset power consumption calculation formula;

[0186] If there is power consumption data greater than the preset power consumption threshold, determine the target switching chip group corresponding to the power consumption data greater than the preset power consumption threshold, determine the data exchange request, bandwidth requirement data, bandwidth allocation data, latency data, and preset maximum transmission bandwidth of the target switching chip group, and determine the load data of each chip in the target switching chip group;

[0187] Obtain the maximum load limit data of each chip in the target switching chip group, input the power consumption data, data exchange request, bandwidth allocation data, latency data, preset maximum transmission bandwidth, load data, bandwidth requirement data, and maximum load limit data of the target switching chip group into the preset power consumption adjustment model, determine the power consumption adjustment plan for the target switching chip group, and perform power consumption adjustment on the target switching chip group according to the power consumption adjustment plan.

[0188] In this solution, the power consumption data can be the power consumed by each target switching chip during the data exchange process.

[0189] The preset power consumption threshold can be a pre-set upper limit of power consumption. When the power consumption data of the switching chip exceeds this threshold, measures need to be taken for power consumption optimization. This threshold is usually set according to the power management design of the system and the maximum power consumption bearing capacity of the chip, aiming to prevent the chip from overheating or the power supply resources from being overloaded.

[0190] The target switching chip group can be a group of switching chips participating in the data exchange process. Usually, there will be data exchange tasks among these chips. Their power consumption, load, bandwidth requirements, etc. need to be comprehensively considered during the calculation.

[0191] The maximum load limit data can represent the maximum working load that each switching chip can bear.

[0192] The preset power consumption adjustment model can be a mathematical or algorithmic model established through previous research or experience, used to calculate the power consumption adjustment plan according to factors such as the power consumption data, load, and bandwidth requirements of each chip. This model usually needs to input information including load, bandwidth allocation, delay, etc. to evaluate the power consumption situation and propose optimization strategies.

[0193] The power consumption adjustment plan can be an optimization measure generated by the power consumption adjustment model, aiming to reduce the power consumption of the target switching chip group that exceeds the power consumption threshold and ensure their stable operation within the preset power consumption range. The power consumption adjustment plan may include reducing the frequency of data exchange, lowering the workload, adjusting the bandwidth allocation, etc.

[0194] The load data, bandwidth allocation data, and latency data can be substituted into a preset power consumption calculation formula to calculate the power consumption data between each target switching chip. If the power consumption of a certain target switching chip group exceeds the threshold, it indicates that the chips in this group may face problems such as overheating and insufficient power, and adjustment is required. For example, if chip a and chip b exchange data, and chip b and chip c exchange data, then these are two exchange groups. If the power consumption data between chip a and chip b is greater than the preset power consumption threshold, the target switching chip group is the switching chip group between chip a and chip b. When the power consumption of a certain target switching chip group exceeds the preset threshold, relevant data of this chip group needs to be obtained for adjustment: Data exchange request: Understand the amount of data exchange requests sent by this target switching chip group. Bandwidth requirement data: The bandwidth required for data transmission between chips. Bandwidth allocation data: The bandwidth currently allocated between the target switching chip groups. Latency data: The latency value between the target switching chip groups, indicating the delay of data transmission. Preset maximum transmission bandwidth: The maximum allowable data transmission bandwidth between each pair of chips. Each switching chip usually has a maximum load limit, and exceeding this limit will cause the chip performance to degrade or become overloaded. The maximum load limit data of each chip can be found according to the chip hardware characteristics or configuration file. Once all the necessary data (power consumption data, bandwidth requirement data, bandwidth allocation data, latency data, maximum load limit data, etc.) is ready, these data can be input into a preset power consumption adjustment model. This model takes into account multiple factors, such as load, bandwidth, latency, maximum load limit, etc., to determine how to adjust bandwidth allocation, load, and other factors to reduce power consumption. In the power consumption adjustment model, through the processing and calculation of the above data, the model will output a power consumption adjustment plan. This plan usually includes the following aspects: Adjust bandwidth allocation: To reduce power consumption, the model may suggest reducing the bandwidth allocation of certain links, or reallocating the bandwidth to chips with lighter loads, thereby reducing the power consumption of high-load chips. Adjust load allocation: The model can reallocate load tasks according to the maximum load limit of the chips, avoid overloading certain chips, and thus reduce power consumption. Optimize latency: Adjust the data flow path or bandwidth allocation to optimize latency and reduce the power consumption caused by long waiting times. Power consumption limit: If the power consumption of some chips exceeds the standard, the model will propose adjustment strategies to ensure that the power consumption is within the threshold. Once the power consumption adjustment plan is generated, the model will implement the adjustment according to this plan. These adjustments can include: Bandwidth adjustment: Adjust the bandwidth configuration of the network link. Load adjustment: Reallocate processing tasks or data streams. Latency optimization: Adjust the network routing or select a low-latency path.

[0195] The training process of the preset power consumption adjustment model includes:

[0196] First, a large amount of historical data needs to be collected, which usually comes from the actual operation of switching chips in the network. The main data collected includes: power consumption data of the historical target switching chipset, historical data exchange requests, historical bandwidth allocation data, historical latency data, historical preset maximum transmission bandwidth, historical load data, historical bandwidth demand data, and historical maximum load limit data. Based on these historical data, they are integrated into a dataset, and each data record (sample) contains the above-mentioned multiple features, describing the working state of the network at a specific moment. For each sample (data record), a label, that is, the target output, needs to be defined. This label is usually the historical power consumption adjustment plan, which is used to guide how to adjust the power consumption according to the current state. The label usually comes from two ways: Manual annotation: Experienced engineers manually annotate the power consumption adjustment plan according to the historical state of the network. This method usually requires professional knowledge. Rule generation: Based on certain rules (such as adjusting when the power consumption exceeds the threshold), the system automatically generates the power consumption adjustment plan. Once the dataset is ready, the input features and labels can be organized into training data. Each record (sample) will consist of the following two parts: Input features: That is, the dataset integrated based on these historical data. Label: That is, the power consumption adjustment plan. Train the model on the prepared dataset. Common machine learning methods can be used for this process: Regression model: If the task is to predict the power consumption value, a regression model (such as linear regression, decision tree regression, support vector machine regression, etc.) can be used. Classification model: If the task is to predict the adjustment strategy (such as "increase bandwidth allocation" or "decrease bandwidth allocation"), then a classification model (such as random forest, support vector machine, neural network, etc.) can be used. Deep learning: If the dataset is large and the feature relationships are complex, deep learning models (such as neural network, convolutional neural network, long short-term memory network, etc.) can be considered. The goal of model training is to learn how to optimize power consumption based on the input features. During the training process, a part of the data (validation set) is used to evaluate the effect of the model. By calculating metrics such as error and accuracy, check whether the model can predict a reasonable power consumption adjustment plan on new data. When the trained model is deployed to the actual environment, it will predict the power consumption according to the real-time network state and provide corresponding adjustment suggestions. The model will continuously feedback and adjust according to new data to optimize the power consumption allocation.

[0197] There is a close correlation between multiple key parameters of the target switching chipset (such as power consumption data, data exchange requests, bandwidth allocation data, latency data, preset maximum transmission bandwidth, load data, bandwidth demand data, and maximum load limit data) and the power consumption adjustment plan. This is because these parameters directly or indirectly affect the working state of the switching chip, and thus determine its power consumption performance. The correlation between the parameters input to the model and the power consumption adjustment plan is as follows:

[0198] The power consumption data reflects the power consumption level of the target switching chipset under the current network load and bandwidth allocation. Power consumption is usually a direct manifestation of the working intensity of the device. When the power consumption data exceeds the preset threshold, power consumption adjustment is required. The power consumption adjustment scheme will reduce power consumption by optimizing bandwidth allocation, load scheduling, etc., and maintain the stable operation of the system. The power consumption data is directly used as one of the inputs for adjustment, determining whether adjustment is needed and the extent of adjustment.

[0199] The data exchange request refers to the amount of data that needs to be transmitted between switching chips within a certain period of time. The data exchange request volume usually determines the workload of the chip. The data exchange request volume affects the bandwidth demand and indirectly affects the load of the chip. When the data exchange request volume is large, it may lead to an increase in bandwidth demand, thereby increasing power consumption. Therefore, adjusting the bandwidth allocation according to the data exchange request volume is the key to optimizing power consumption.

[0200] The bandwidth allocation data determines the way of network bandwidth allocation among different switching chips. Reasonable bandwidth allocation can effectively avoid bandwidth bottlenecks, thereby reducing power consumption. The optimization of bandwidth allocation is crucial for power consumption control. Excessive bandwidth allocation may cause overload of some chips and increase power consumption; on the contrary, too little bandwidth allocation may affect data transmission efficiency and increase latency. Therefore, as an input parameter, the bandwidth allocation data will affect the design of the final power consumption adjustment scheme.

[0201] The latency data reflects the time experienced during data transmission. An increase in latency may mean unreasonable bandwidth allocation or overloading, thus affecting the working state of the switching chip. An increase in latency usually means a heavy network load or unbalanced bandwidth allocation, which may lead to an increase in power consumption. Therefore, the power consumption adjustment scheme must consider the latency data to ensure that transmission latency is not increased while reducing power consumption.

[0202] The preset maximum transmission bandwidth is the maximum bandwidth limit of the network link, avoiding congestion or overload caused by excessive bandwidth allocation. When the actual bandwidth demand approaches or exceeds the preset maximum transmission bandwidth, the system needs to adjust the bandwidth allocation strategy to avoid excessive power consumption increase. In the power consumption adjustment scheme, considering the maximum bandwidth limit can prevent excessive power consumption increase.

[0203] The load data refers to the processing capacity of the switching chip, reflecting the workload borne by the chip when processing data transmission. When the chip load is too high, its power consumption will increase. Therefore, the change in load data can directly affect power consumption. If the load of a certain chip is too high, it may be necessary to readjust the load allocation to reduce the power consumption of the chip and ensure the stability of the system.

[0204] The bandwidth demand data describes the network bandwidth demand of each switching chip at a certain moment. This is a key factor affecting bandwidth allocation and power consumption. Excessive bandwidth demand may lead to an increase in power consumption. When adjusting the bandwidth allocation, it is necessary to determine whether to reallocate the bandwidth according to the bandwidth demand data of each switching chip to reduce the overall power consumption.

[0205] The maximum load limit data refers to the maximum workload that each switching chip can bear. Exceeding this load limit may lead to a decline in chip performance or even failure. The maximum load limit is an important constraint condition. To avoid chip overload, the power consumption adjustment scheme needs to ensure that the load does not exceed this limit. By reasonable bandwidth and load allocation, it is possible to avoid exceeding the maximum load limit, thereby avoiding unnecessary increase in power consumption.

[0206] In this scheme, by monitoring the power consumption of the switching chip group in real time and adjusting the part that exceeds the preset threshold, it is possible to significantly reduce unnecessary power consumption waste and improve the energy efficiency of the system. According to the dynamic bandwidth demand and load changes, the power consumption adjustment model can respond in a timely manner to different workloads, ensuring that the system is always in the best working state.

[0207] On the basis of the above technical scheme, optionally, the preset power consumption calculation formula is:

[0208]

[0209] Among them, P i，j is the power consumption data; δ is the preset power consumption coefficient; B i，j is the bandwidth allocation data; L i is the load data of chip i; L j is the load data of chip j; D ij is the delay data.

[0210] In this scheme, the relationship between the parameters in the formula and the power consumption data is:

[0211] The preset power consumption coefficient is used to adjust the influence weights of various factors in the formula. It is preset to balance the influence of different factors (such as bandwidth, load, and delay) on power consumption, making the formula calculation more in line with the actual power consumption characteristics. In practical applications, this coefficient can be determined through experimental data or prior knowledge.

[0212] The bandwidth demand data directly affects the communication volume and power consumption between switching chips, because the larger the bandwidth, the more energy is consumed for data transmission between chips. For example, more data transmission requires more power to support the sending and receiving of data packets.

[0213] The load data represents the computing load of the target switching chip i, which usually refers to the amount of data processed on the chip or the processing tasks in progress. The higher the load, the greater the working intensity of the chip, and thus more power is required to maintain normal operation. Therefore, there is a direct positive correlation between the load and power consumption.

[0214] The relationship between the latency data and power consumption is relatively complex. Generally speaking, the higher the latency, the lower the data transmission efficiency, which may lead to more power consumption in the system to compensate for the performance loss caused by the latency. For example, to make up for the latency, it may be necessary to increase redundant transmissions or adopt additional scheduling strategies, which will increase the power consumption.

[0215] Embodiment III

[0216] Figure 3 is a schematic structural diagram of an optimized system for multi-chip optoelectronic hybrid interconnection provided by Embodiment III of the present application. As Figure 3 shown, it specifically includes:

[0217] An optical interconnection power consumption data determination module 301, configured to obtain the first power consumption state of the optical interconnection module of each chip, and determine the optical interconnection power consumption data of each chip according to the first power consumption state;

[0218] An electrical interconnection power consumption data determination module 302, configured to obtain the second power consumption state of the electrical interconnection module of each chip, and determine the electrical interconnection power consumption data of each chip according to the second power consumption state;

[0219] An optical wavelength multiplexing factor determination module 303, configured to obtain the chip configuration and optical interconnection working mode of each chip, and determine the optical wavelength multiplexing factor of each chip according to the chip configuration and optical interconnection working mode;

[0220] An optical channel capacity determination module 304, configured to obtain the maximum bandwidth data of each wavelength of each chip, and determine the optical channel capacity of each chip according to the optical wavelength multiplexing factor and the maximum bandwidth data;

[0221] An optoelectronic interconnection transmission energy efficiency ratio calculation module 305, configured to obtain the chip number data, and calculate the overall optoelectronic interconnection transmission energy efficiency ratio according to the chip number data, optical interconnection power consumption data, electrical interconnection power consumption data, optical wavelength multiplexing factor, optical channel capacity, and a preset transmission energy efficiency calculation formula;

[0222] The optoelectronic interconnection optimization module 306 is configured to, if the overall optoelectronic interconnection transmission energy efficiency ratio is higher than a preset energy efficiency threshold, obtain the chip static parameters of each chip, the chip load data of each chip, and the network topology status data, input the optical interconnection power consumption data, the electrical interconnection power consumption data, the optical wavelength multiplexing factor, the optical channel capacity, the chip static parameters, the chip load data, and the network topology status data into a preset optimization model, determine an optoelectronic interconnection optimization solution, and optimize each chip according to the optoelectronic interconnection optimization solution.

[0223] The optimization system for multi-chip optoelectronic hybrid interconnection provided by the embodiments of the present application can implement Figure 1 each process implemented by the method embodiments. To avoid repetition, details are not described herein again.

[0224] Embodiment 4

[0225] As Figure 4 shown, the embodiments of the present application further provide an electronic device 400, including a processor 401, a memory 402, and a program or instruction stored on the memory 402 and executable on the processor 401. When the program or instruction is executed by the processor 401, it implements each process of the method embodiment of the above-mentioned optimization method for multi-chip optoelectronic hybrid interconnection and can achieve the same technical effect. To avoid repetition, details are not described herein again.

[0226] It should be noted that the electronic device in the embodiments of the present application includes the above-mentioned mobile electronic device and non-mobile electronic device.

[0227] Embodiment 5

[0228] The embodiments of the present application further provide a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, it implements each process of the embodiment of the above-mentioned cable installation process-based adaptive control system and can achieve the same technical effect. To avoid repetition, details are not described herein again.

[0229] Wherein, the processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disc, etc.

[0230] It should be noted that in this document, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article or system comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or system. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the existence of additional identical elements in the process, method, article or system comprising that element. In addition, it should be pointed out that the scope of the methods and systems in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in a reverse order according to the functions involved. For example, the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, the features described with reference to certain examples may be combined in other examples.

[0231] Through the description of the above embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. The computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disc) and includes several instructions for causing a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present application.

[0232] The embodiments of the present application have been described above in conjunction with the accompanying drawings. However, the present application is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present application, those of ordinary skill in the art can also make many forms without departing from the purpose of the present application and the scope protected by the claims, and all of them fall within the protection scope of the present application.

[0233] The above is only the preferred embodiment of the present application and the technical principles applied. The present application is not limited to the specific embodiments described herein. Various obvious changes, re-adjustments and substitutions that can be made by those skilled in the art will not depart from the protection scope of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments. Without departing from the concept of the present application, more other equivalent embodiments may be included, and the scope of the present application is determined by the scope of the claims.

Claims

1. A method for optimizing multi-chip optoelectronic hybrid interconnection, characterized in that: The method comprises: Acquire a first power consumption state of an optical interconnect module of each chip, and determine optical interconnect power consumption data of each chip according to the first power consumption state; Acquire a second power consumption state of the electrical interconnection module of each chip, and determine the electrical interconnection power consumption data of each chip according to the second power consumption state; Obtaining chip configuration and optical interconnection working mode of each chip, and determining the optical wavelength multiplexing factor of each chip according to the chip configuration and optical interconnection working mode; Acquire the maximum bandwidth data of each wavelength of each chip, and determine the optical channel capacity of each chip according to the optical wavelength multiplexing factor and the maximum bandwidth data; Obtain chip quantity data, and calculate the overall optoelectronic interconnection transmission energy efficiency ratio according to the chip quantity data, optical interconnection power consumption data, electrical interconnection power consumption data, optical wavelength multiplexing factor, optical channel capacity, and a preset transmission energy efficiency calculation formula; If the overall optoelectronic interconnection transmission energy efficiency ratio is higher than the preset energy efficiency threshold, the chip static parameters of each chip, the chip load data of each chip and the network topology status data are obtained, and the optical interconnection power consumption data, the electrical interconnection power consumption data, the optical wavelength multiplexing factor, the optical channel capacity, the chip static parameters, the chip load data and the network topology status data are input into the preset optimization model to determine the optoelectronic interconnection optimization plan, and optimize each chip according to the optoelectronic interconnection optimization plan.

2. The optimization method for multi-chip optoelectronic hybrid interconnection according to claim 1, characterized in that: The preset transmission energy efficiency calculation formula is: Among them, T opt is the overall optoelectronic interconnection transmission energy efficiency ratio; N is the number of chips; γ opt，i is the optical wavelength multiplexing factor of the ith chip; C opt，i is the optical channel capacity of the ith chip; P opt，i is the optical interconnection power consumption data of the i-th chip; P elec，i is the electrical interconnection power consumption data of the i-th chip.

3. The optimization method for multi-chip optoelectronic hybrid interconnection according to claim 1, characterized in that: After optimizing each chip according to the optoelectronic interconnection optimization solution, the method further includes: If a data exchange request is identified, determining a target switching chip corresponding to the data exchange request; wherein the number of the target switching chips is at least two; Obtaining load data of each target switching chip, and calculating load imbalance data between the target switching chips according to the load data; Obtain bandwidth demand data between target switching chips, delay data between target switching chips, and preset maximum transmission bandwidth between target switching chips; calculate bandwidth allocation data between target switching chips based on the load imbalance data, bandwidth demand data, delay data, load data, preset maximum transmission bandwidth, and preset bandwidth allocation formula; and implement bandwidth adjustment of target switching chips based on the bandwidth allocation data.

4. The optimization method for multi-chip optoelectronic hybrid interconnection according to claim 3, characterized in that: The default bandwidth allocation formula is: Among them, B i，j Allocate data for bandwidth; L i is the load data of chip i; L j is the load data of chip j; D ij is the delayed data; C ij is the preset maximum transmission bandwidth; N i，j is bandwidth demand data; Load imbalance is load imbalance data; α is a preset bandwidth demand adjustment coefficient; β is a preset load imbalance adjustment coefficient.

5. The optimization method for multi-chip optoelectronic hybrid interconnection according to claim 3, characterized in that: After adjusting the bandwidth of each target switching chip according to the bandwidth allocation data, the method further includes: If the preset update interval is reached, reacquire the load data of each target switch chip, and recalculate the load imbalance data between the target switch chips according to the load data; Reacquire the bandwidth demand data between each target switching chip and the delay data between each target switching chip, recalculate the bandwidth allocation data between each target switching chip according to the recalculated load imbalance data, the reacquired bandwidth demand data, the reacquired delay data, the reacquired load data, the preset maximum transmission bandwidth and the preset bandwidth allocation formula, implement bandwidth adjustment of each target switching chip according to the recalculated bandwidth allocation data, recalculate the bandwidth allocation data between each target switching chip after each preset update interval is reached, and implement bandwidth adjustment of each target switching chip according to the recalculated bandwidth allocation data, until each target switching chip completes data exchange.

6. The optimization method for multi-chip optoelectronic hybrid interconnection according to claim 3, characterized in that: After adjusting the bandwidth of each target switching chip according to the bandwidth allocation data, the method further includes: Calculating the power consumption data between each target switching chip according to the load data, bandwidth allocation data, delay data and a preset power consumption calculation formula; If there is power consumption data greater than a preset power consumption threshold, determine the target switching chipset corresponding to the power consumption data greater than the preset power consumption threshold, determine the data exchange request, bandwidth demand data, bandwidth allocation data, delay data and preset maximum transmission bandwidth of the target switching chipset, and determine the load data of each chip of the target switching chipset; The maximum load limit data of each chip of the target switching chipset is obtained, and the power consumption data, data exchange request, bandwidth allocation data, delay data, preset maximum transmission bandwidth, load data, bandwidth demand data, and maximum load limit data of the target switching chipset are input into a preset power consumption adjustment model, a power consumption adjustment scheme of the target switching chipset is determined, and the power consumption of the target switching chipset is adjusted according to the power consumption adjustment scheme.

7. The optimization method for multi-chip optoelectronic hybrid interconnection according to claim 6, characterized in that: The preset power consumption calculation formula is: Among them, P i，j is the power consumption data; δ is the preset power consumption coefficient; B i，j Allocate data for bandwidth; L i is the load data of chip i; L j is the load data of chip j; D ij Delayed data.

8. An optimization system for multi-chip optoelectronic hybrid interconnection, characterized in that: The system comprises: An optical interconnection power consumption data determination module, used to obtain a first power consumption state of the optical interconnection module of each chip, and determine the optical interconnection power consumption data of each chip according to the first power consumption state; An electrical interconnection power consumption data determination module, used to obtain a second power consumption state of the electrical interconnection module of each chip, and determine the electrical interconnection power consumption data of each chip according to the second power consumption state; An optical wavelength multiplexing factor determination module is used to obtain the chip configuration and the optical interconnection working mode of each chip, and determine the optical wavelength multiplexing factor of each chip according to the chip configuration and the optical interconnection working mode; An optical channel capacity determination module, used to obtain the maximum bandwidth data of each wavelength of each chip, and determine the optical channel capacity of each chip according to the optical wavelength multiplexing factor and the maximum bandwidth data; The optoelectronic interconnection transmission energy efficiency ratio calculation module is used to obtain chip quantity data, and calculate the overall optoelectronic interconnection transmission energy efficiency ratio according to the chip quantity data, optical interconnection power consumption data, electrical interconnection power consumption data, optical wavelength multiplexing factor, optical channel capacity and a preset transmission energy efficiency calculation formula; The optoelectronic interconnection optimization module is used to obtain the chip static parameters of each chip, the chip load data of each chip and the network topology status data if the overall optoelectronic interconnection transmission energy efficiency ratio is higher than a preset energy efficiency threshold, input the optical interconnection power consumption data, the electrical interconnection power consumption data, the optical wavelength multiplexing factor, the optical channel capacity, the chip static parameters, the chip load data and the network topology status data into a preset optimization model, determine the optoelectronic interconnection optimization plan, and optimize each chip according to the optoelectronic interconnection optimization plan.

9. An electronic device, characterized in that: The invention comprises a processor, a memory and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction, when executed by the processor, implements the steps of the optimization method for multi-chip optoelectronic hybrid interconnection as described in any one of claims 1 to 7.

10. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by the processor, the steps of the optimization method for multi-chip optoelectronic hybrid interconnection according to any one of claims 1 to 7 are implemented.

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