Received signal quality monitor

Abstract

A phase adjustment circuit (11) of a received signal quality monitor is capable of performing phase scanning of a sampling clock signal (phi e) of a reference sampler in a phase range that is several times the unit interval (UI) of a serial data signal. A first synchronization circuit (13A) receives a first output signal of one sampler included in the plurality of data receiving samplers and a second output signal of the reference sampler (SMe). A first output signal and a second output signal synchronously output from the first synchronization circuit (13A) are input to a comparison logic circuit (15), and the comparison logic circuit (15) outputs a comparison result relating to the quality of the received signal.

Description

Technical Field

[0001] The present invention relates to a received signal quality monitor. Background Art

[0002] Patent Document 1, Patent Document 2, Patent Document 3, Non-Patent Document 1, and Non-Patent Document 2 disclose receiving apparatuses. When a received signal quality monitor capable of outputting data for eye diagram generation (quality monitoring signal of the received signal) is assembled inside the receiving apparatus, the quality of the received signal can be evaluated by evaluating the data.

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2018-152731

[0006] Patent Document 2: US Patent No. 10720910 Specification

[0007] Patent Document 3: US Patent No. 10735116 Specification

[0008] Non-Patent Documents

[0009] Non-Patent Document 1: Yu-Chuan Lin, H. Tsao, "A 10-Gb / s Eye-Opening Monitor Circuit for Receiver Equalizer Adaptations in 65-nm CMOS", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1 January 2020

[0010] Non-Patent Document 2: Hyosup Won, Joon-Yeong Lee, et.al., "A 28-Gb / s Receiver With Self-contained Adaptive Equalization and Sampling Point Control Using Stochastic Sigma-Tracking Eye-Opening Monitor", IEEE Transactions on Circuits and Systems I, Regular Papers, Volume 64, Issue 3, March 2017 Summary of the Invention

[0011] Problems to be Solved by the Invention

[0012] A received signal quality monitor that can accurately monitor the quality of a received signal while reducing circuit area and power consumption.

[0013] Means for solving the problem

[0014] The received signal quality monitor includes: a plurality of data reception samplers that receive a serial data signal and are connected in parallel, with multi-phase sampling clock signals respectively input thereto; a reference sampler that receives the serial data signal; a phase adjustment circuit that can perform phase scanning of the sampling clock signal input to the reference sampler within a phase range that is N times the unit interval of the serial data signal, where the unit interval is UI and 2 ≤ N; a first synchronization circuit that receives the output signal of one of the plurality of data reception samplers and the output signal of the reference sampler; and a comparison logic circuit that receives two output signals synchronously output from the first synchronization circuit.

[0015] In the case where the phase scanning range of the phase adjustment circuit is narrow, in order to handle errors, a delay adjustment circuit is sometimes arranged in front of the plurality of data reception samplers. In this device, since the phase scanning range is wide, the error generation area can be sufficiently separated from the eye diagram formation area, and this circuit can also be omitted, enabling accurate monitoring of the received signal quality while reducing circuit area and power consumption.

[0016] In the received signal quality monitor, it is preferable that the phase range adjusted by the phase adjustment circuit is more than one cycle of the sampling clock signal input to the reference sampler. By expanding the phase range, it is easier to obtain even if the position of the eye aperture moves.

[0017] Preferably, the received signal quality monitor further includes a counter that counts the output result of the comparison logic circuit.

[0018] Preferably, the reference sampler includes: a first input terminal that receives the serial data signal; and a second input terminal that receives a variable reference threshold voltage, and the reference sampler samples the comparison result between the serial data signal and the reference threshold voltage synchronously with the sampling clock signal that can be phase scanned.

[0019] Preferably, each sampler included in the plurality of data receiving samplers has: a first input terminal for receiving the serial data signal; and a second input terminal for inputting a threshold voltage. Each sampler included in the plurality of data receiving samplers samples the comparison result between the serial data signal and the threshold voltage synchronously with the sampling clock signal included in the multi-phase sampling clock signal and corresponding to the sampler.

[0020] Preferably, the received signal quality monitor has: a second synchronization circuit for inputting a plurality of output signals output from the plurality of data receiving samplers; and a CDR (Clock and Data Recovery) circuit for inputting the plurality of output signals output from the second synchronization circuit and generating the multi-phase sampling clock signal.

[0021] In the received signal quality monitor, preferably, the serial data signal is a multi-valued pulse amplitude modulation signal having k levels, where 3 ≤ k and k is an integer. Pulse amplitude modulation refers to PAM. Each of the plurality of data receiving samplers has k - 1 samplers, and threshold voltages with different levels are input to each of the k - 1 samplers together with the serial data signal, and k - 1 comparison results are output from each of the k - 1 samplers.

[0022] In the received signal quality monitor, preferably, the k - 1 comparison results are output from one sampler included in the plurality of data receiving samplers, the k - 1 comparison results and the output signal of the reference sampler are input to the first synchronization circuit, the comparison logic circuit has k - 1 sub-comparison logic circuits, and the output signals synchronously output from the first synchronization circuit are input to the k - 1 sub-comparison logic circuits respectively. At least two output signals synchronously output from the first synchronization circuit are input.

[0023] Preferably, the phase adjustment circuit has: a selection circuit for inputting the multi-phase sampling clock signal output from the CDR circuit; and a phase interpolation circuit for inputting the output signal of the selection circuit.

[0024] Advantages of the Invention

[0025] According to the received signal quality monitor, it is possible to accurately monitor the quality of the received signal while reducing the circuit area and power consumption. Brief Description of the Drawings

[0026] Figure 1 It is a block diagram showing a transceiver system and an external device 300.

[0027] Figure 2 It is a block diagram of a receiving device RX.

[0028] Figure 3 It is a block diagram of the reference sampler SMe.

[0029] Figure 4 It is a block diagram of the phase adjustment circuit 11.

[0030] Figure 5 It is a block diagram of the phase interpolation circuit 11B.

[0031] Figure 6 It is a block diagram showing the structure of the first synchronization circuit 13A.

[0032] Figure 7 It is a diagram showing the truth table of the comparison logic circuit (XOR circuit).

[0033] Figure 8 It is a diagram depicting the output of the error counter in a two-dimensional manner.

[0034] Figure 9 It is a timing diagram for explaining the setup time ST and the hold time HD.

[0035] Figure 10 It is a block diagram of a general CDR circuit.

[0036] Figure 11 It is for explaining Figure 10 The operation of the CDR circuit shown.

[0037] Figure 12 It is a block diagram of the CDR circuit 17.

[0038] Figure 13 It is for explaining Figure 12 The phase difference of the data in the CDR circuit shown.

[0039] Figure 14 It is a block diagram showing the structure of the second synchronization circuit 13B.

[0040] Figure 15 (A) of [] is a timing diagram of the serial data signal DATA-S, Figure 15 and (B) of [] is a timing diagram showing the reference sampling clock signal φe.

[0041] Figure 16 It is a timing diagram showing the serial data signal, the polyphase clock signals φ1 to φ10, and the clock signal φe.

[0042] Figure 17 It is a timing diagram of the serial data signal and the signals output from the synchronization circuits 13A and 13B.

[0043] Figure 18 It is a block diagram of another receiving device RX.

[0044] Figure 19 is Figure 18 a block diagram of the phase adjustment circuit 11 shown in the figure.

[0045] Figure 20 is a block diagram showing the configuration of the multi-value sampler.

[0046] Figure 21 is a graph showing the change of the input voltage (V) input to the multi-value sampler with respect to time (Time).

[0047] Figure 22 is a block diagram showing the circuit configuration of the multi-value sampler and the subsequent stage.

[0048] Figure 23 is a graph showing the change of the input voltage (V) input to the first data reception sampler SM1high and the reference sampler Sme with respect to time (Time).

[0049] Figure 24 is a block diagram showing the circuit configuration of the multi-value sampler and the subsequent stage.

[0050] Figure 25 is a block diagram showing the circuit configuration of the multi-value sampler and the subsequent stage.

[0051] Figure 26 (A) of Figure 26 (B) of is an exemplary timing diagram of the serial data signal. Detailed implementation mode

[0052] Hereinafter, with reference to the accompanying drawings, the mode for implementing the present invention will be described in detail. In addition, in the description of the drawings, the same reference numerals are assigned to the same elements, and repeated descriptions are omitted. The present invention is not limited to these examples, which are shown in the claims, and is intended to include all changes within the meaning equivalent to the claims and the scope.

[0053] Figure 1 is a block diagram showing the transceiver system and the external device 300.

[0054] The transceiver system includes a receiving device RX and a transmitting device TX. The receiving device RX can be connected to the external device 300 for signal quality inspection.

[0055] The transmitting device TX has an input terminal for inputting a parallel data signal DATA-PI and an output terminal for outputting a serial data signal DATA-S. The serial data signal DATA-S transmitted from the transmitting device TX is transmitted via a communication cable CB and received by the receiving device RX. For example, in the case of transmitting an 8-bit parallel data signal, the parallel data signal is serially converted, and by performing encryption in the 8b / 10b format on it, a clock is embedded in the serial data, and a 10-bit serial data signal DATA-S is transmitted.

[0056] The receiving device RX has a digital implementer for parallel-converting the received serial data signal DATA-S, an output terminal for outputting a parallel data signal DATA-PO, and a received signal quality monitor (eye monitor). The received signal quality monitor in the receiving device RX has an output terminal for a quality monitoring signal OUTPUT, an input terminal for an external input threshold control signal CNT-TH, and an input terminal for an external input phase control signal CNT-PH. The quality monitoring signal OUTPUT is a signal indicating the state of the received signal such as an eye diagram and contains information related to the quality of the signal.

[0057] The external device 300 is a computer and has a memory 301, a central processing unit (CPU) 302, an interface 303, a bus 304, a display 305, an output terminal for an external input threshold control signal CNT-TH, and an output terminal for an external input phase control signal CNT-PH.

[0058] The central processing unit 302 performs arithmetic processing according to a control signal generation program stored in the memory 301 and generates an external input phase control signal CNT-PH and an external input threshold control signal CNT-TH. The external input phase control signal CNT-PH is a signal for controlling the phase of the sampling clock signal φe at the moment (tφe) corresponding to the depicted horizontal axis by the phase adjustment circuit 11 (see Figure 2 ). The external input threshold control signal CNT-TH is a signal for controlling the reference threshold voltage Ve at the moment (tVe) corresponding to the depicted vertical axis by the voltage generator 12 (see Figure 2 ). When these moments (tφe, tVe) reach the maximum values of the depicted horizontal and vertical axes, they are periodically reset to 0. Additionally, instead of directly controlling the target parameters (phase, voltage), these control signals can be used as triggers to control the target parameters within the receiving device RX.

[0059] The external device 300 can receive the quality monitoring signal OUTPUT output from the receiving device RX, and the central processing unit 302 performs arithmetic processing according to the eye diagram drawing program stored in the memory 301, and displays the received signal status such as the eye diagram on the display 305. After storing the quality monitoring signal OUTPUT output in time series in the memory 301, the eye diagram drawing program draws the eye diagram. The quality monitoring signal OUTPUT corresponds to the timing at the time of reception, and has the moment information (tφe) of the phase of the reference sampling clock signal φe (reference Figure 2 ) as the information of the X-axis coordinate of the eye diagram, and has the moment information (tVe) of the reference threshold voltage Ve (reference Figure 2 ) to be scanned as the Y-axis coordinate information. At the position defined by the two-dimensional coordinates at the time of drawing, the number of errors counted in the error counter (counter) 16 (reference Figure 2 ) is recorded, and the eye diagram information is stored in the two-dimensional memory space. Then, the program sends the obtained eye diagram image information to the display 305. Of course, by storing the data included in the quality monitoring signal in the memory 301 of the computer and inputting the data into spreadsheet software (spreadsheet), an eye diagram can also be obtained.

[0060] In addition, the external device 300 can be implemented by a dedicated device or a portable information terminal that performs the same signal processing as these computers in addition to a general personal computer and a single-board computer.

[0061] Figure 2 is a block diagram of the receiving device RX.

[0062] The receiving device RX has an input terminal for the serial data signal DATA-S, and the serial data signal DATA-S is input to the amplifier 101. The amplifier 101 in this example is a simple buffer amplifier, but it may also include an equalizer and a filter. The serial data signal DATA-S output from the amplifier 101 is input to the received signal quality monitor, and the received signal quality monitor outputs the quality monitoring signal OUTPUT from the output terminal. The serial data signal DATA-S output from the amplifier 101 is also input to a deserializing circuit having a plurality of data receiving samplers SM1 to SMm (example: m = 10). The digital implementer converts the received serial data signal DATA-S into an output parallel data signal DATA-PO and outputs it from a plurality of output terminals. The sampling timing of the received signal is adjusted by the CDR (Clock and Data Recovery) circuit 17, and the voltage and phase at the time of sampling are controlled by the control circuit 18. As described above, the receiving device RX includes a received signal quality monitor and a digital implementer.

[0063] (Received Signal Quality Monitor)

[0064] The received signal quality monitor utilizes the output signals of multiple samplers SM1 to SMm for data reception. The digital implementer includes m samplers, and the nth sampler among them is set as sampler SMn. 1 ≤ n ≤ m, where m and n are integers. The multiple samplers SM1 to SMm for data reception respectively receive the serial data signal DATA-S and are connected in parallel. Each clock signal included in the polyphase sampling clock signals (φ1 to φm) is input to the input terminal of the sampling clock signal φn of each of the multiple samplers SM1 to SMm for data reception. In this figure, as a specific example, m = 10 is illustrated, but m can be greater than 10 or less than 10.

[0065] The received signal quality monitor has multiple samplers SM1 to SMm for data reception, a reference sampler SMe for receiving the serial data signal DATA-S, a phase adjustment circuit 11, a voltage generator 12, a first synchronization circuit 13A, a comparison logic circuit 15, an error counter 16, and a CDR circuit 17. Details are described below.

[0066] (Reference Sampler)

[0067] Figure 3 It is a block diagram of the reference sampler SMe.

[0068] The reference sampler SMe receives the serial data signal DATA-S. The received serial data signal DATA-S is compared with the reference threshold voltage Ve by the comparator COMP, and this comparison result is sampled at the reference sampling timing (the rising edge of the sampling clock signal), and the comparison result is output. As an example, a D flip-flop FF1 is used in the sampling. In the D flip-flop FF1, when the rising edge of the clock signal is input to the C terminal in the state where the true value to be stored in the D terminal is input, the D flip-flop stores the true value of the D terminal and outputs the stored true value from the Q terminal. The output of the Q terminal (comparison result) is held until the next rising edge of the input sampling clock signal φe.

[0069] Regarding the comparison result (the second output signal (reference signal Se)) output from the reference sampler SMe, when the serial data signal DATA-S is greater than the reference threshold voltage Ve, this comparison result shows "1", and when it is less than the reference threshold voltage Ve, this comparison result shows "0". The sampling clock signal φe is output from the phase adjustment circuit 11, and the reference threshold voltage Ve is output from the voltage generator 12.

[0070] In this manner, in the reception signal quality monitor, the reference sampler SMe has a first input terminal SMe1 for receiving the serial data signal DATA-S, a second input terminal SMe2 for inputting the reference threshold voltage Ve, and an input terminal SMe3 for the sampling clock signal φe, and samples the comparison result (reference signal Se) between the serial data signal DATA-S and the reference threshold voltage Ve synchronously with the sampling clock signal φe.

[0071] (Multiple data reception samplers)

[0072] In addition, the structures of the multiple data reception samplers SM1 to SMm are the same as that of the reference sampler SMe. In the Figure 3 explanation, the reference threshold voltage Ve is expressed as the threshold voltage Vn (n = 1 to m), the sampling clock signal φe is expressed as the sampling clock signal φn (n = 1 to m), and the reference signal Se is expressed as the output signal Sn (n = 1 to m) to explain the operations of the respective samplers SMn (n = 1 to m).

[0073] (Phase adjustment circuit)

[0074] Figure 4 is a block diagram of the phase adjustment circuit 11.

[0075] The phase adjustment circuit 11 has one or two or more input terminals and an output terminal for the sampling clock signal φe. The number of input terminals of the phase adjustment circuit 11 in this example is two or more. Two or more sampling clock signals (φ1 to φm) included in the multi-phase clock signal (φ1 to φm) are input to these input terminals. The sampling clock signal φe is output from the output terminal of the phase adjustment circuit 11. The output terminal of the phase adjustment circuit 11 is connected to the input terminal for the sampling clock signal φe of the reference sampler SMe (reference Figure 2 , Figure 3 ). The phase adjustment circuit 11 can perform phase scanning of the sampling clock signal φe. In this example, the phase adjustment circuit 11 receives the phase control signal PH-SEL and adjusts the phase of the sampling clock signal φe according to the received phase control signal PH-SEL. The phase control signal PH-SEL is output from the control circuit 18 (reference Figure 2 ). The control circuit 18 can generate the phase control signal PH-SEL based on the externally input external input phase control signal CNT-PH. The external input phase control signal CNT-PH and the phase control signal PH-SEL can be the same signal, and in this case, the control circuit 18 can be omitted (see Figure 2 ).

[0076] As the configuration of the phase adjustment circuit 11, multiple methods can be considered. The phase adjustment circuit shown in the figure includes a multiplexer 11A (selection circuit) and a phase interpolation circuit 11B (Phase Interpolator). The multiplexer 11A selects two clock signals φA and φB (the values of A and B are indicated by the clock selection signal PH-SEL) from the multi-phase clock signals φ1 to φm according to the indication of the clock selection signal SEL0 in the phase control signal PH-SEL. The phase interpolation circuit 11B generates a clock signal φe having a phase between the two input clock signals φA and φB and outputs it. The time tE of the rising edge Eφe of the clock signal φe is set to the time when a predetermined time ΔT has elapsed from the time tA of the rising edge EφA of the clock signal φA. Let the time of the rising edge EφB of the clock signal φB be the time tB. The predetermined time ΔT has a value obtained by multiplying the time difference (tB - tA) by a coefficient of 1 or less, and this coefficient is given by the interpolation position selection signal SEL1 in the phase control signal PH-SEL.

[0077] As described above, the phase adjustment circuit 11 includes a multiplexer 11A and a phase interpolation circuit 11B. The multiplexer 11A receives the multi-phase clock signals φ1 to φm output from the CDR circuit, and the phase interpolation circuit 11B receives the output signal of the multiplexer 11A. The multiplexer is a selection circuit that selects and outputs a required signal from the input signals. The multi-phase clock signals have multiple phases, and the phase interpolation circuit 11B can output a reference clock signal φe having a required phase according to the phases of the two input signals and the phase control signal.

[0078] (Phase interpolation circuit)

[0079] Figure 5 is a block diagram of the phase interpolation circuit 11B.

[0080] The phase interpolation circuit 11B includes a first inverter 11BA for inputting the clock signal φA, a second inverter 11BB for inputting the clock signal φB, and a third inverter 11BC connected to the output terminals of these inverters. The first inverter 11BA and the second inverter 11BB respectively connect multiple gated inverters in parallel, and gates (switches of transistors) are connected in series to the inverters, and the number of gates to be turned on can be controlled by the interpolation position selection signal SEL1. When α gates are turned on in the first inverter 11BA and (1 - α) gates are turned on in the second inverter 11BB, the time tE of the rising edge of the output signal φE can be changed according to the interpolation parameter α (0 < α < 1).

[0081] (Voltage generator)

[0082] Figure 2The voltage generator 12 shown generates a plurality of threshold voltages V1 to Vm (e.g., m = 10) input to a plurality of data receiving samplers SM1 to SMm, and a reference threshold voltage Ve input to the reference sampler Sme. In this example, the voltage generator 12 receives a threshold selection signal or a threshold control signal TH-SEL, and changes the reference threshold voltage Ve according to the received threshold control signal TH-SEL. In order to obtain an eye diagram, the reference threshold voltage Ve is scanned. The reference threshold voltage Ve can be implemented by a structure in which the voltage generator 12 itself scans it, but in this example, the threshold control signal TH-SEL is used. The threshold control signal TH-SEL in this example is output from the control circuit 18. The control circuit 18 can generate the threshold control signal TH-SEL according to an externally input external input threshold control signal CNT-TH. The external input threshold control signal CNT-TH and the threshold control signal TH-SEL can be the same signal, and in this case, the control circuit 18 can also be omitted. There are countless known configurations for changing the threshold voltage according to the threshold control signal. For example, as long as a plurality of resistors are connected in parallel downstream of the node providing the threshold voltage, each switch is connected in series with each resistor, and the on / off of these switches is controlled by the threshold control signal, the threshold voltage can be changed.

[0083] The plurality of threshold voltages V1 to Vm input to the plurality of data receiving samplers SM1 to SMm can be fixed values, or can be set to the amplitude center voltage of the serial data signal DATA-S received by the sampler. For the plurality of threshold voltages V1 to Vm, their values can also be changed as needed using feedback control or the like. For example, a threshold control signal can also be input to the voltage generator 12 such that: when the cumulative value obtained by cumulatively adding the digital values of the respective output signals from the deserializers during the reference period exceeds the first cumulative threshold, it is determined that the current threshold voltage is low, and the input threshold voltage input to the corresponding sampler is increased; if it is lower than the second cumulative threshold, it is determined that the current threshold voltage is high, and the input threshold voltage is decreased.

[0084] Thus, in the received signal quality monitor, each sampler SMn (n is an arbitrary number selected from 1 to m) included in the plurality of data receiving samplers SM1 to SMm has: a first input terminal that receives the serial data signal DATA-S; a second input terminal to which the threshold voltage Vn is input; and an input terminal for the sampling clock signal φn. Synchronously with the sampling clock signal φn (φ1 to φm) included in the multi-phase sampling clock signal and corresponding to the sampler SMn (SM1 to SMm), the comparison result Sn (S1 to Sm) between the serial data signal DATA-S and the threshold voltage Vn is sampled and output.

[0085] (First Synchronization Circuit)

[0086] Figure 6 It is a block diagram showing the configuration of the first synchronization circuit 13A.

[0087] An evaluation target signal Sx (first output signal (e.g., S2)) and a reference signal Se (second output signal) are input to the first synchronization circuit 13A. The evaluation target signal Sx (e.g., S2) is an output signal of one sampler among the plurality of data reception samplers SM1 to SMm. The reference signal Se is an output signal of the reference sampler SMe. The first synchronization circuit 13A synchronizes the evaluation target signal Sx and the reference signal Se. The first synchronization circuit 13A outputs a synchronized evaluation target signal SxOUT and a synchronized reference signal SeOUT. The timing of the rising edge of the evaluation target signal SxOUT coincides with the timing of the rising edge of the reference signal SeOUT.

[0088] As an example, the first synchronization circuit 13A includes: a flip-flop 13A1, whose D terminal is input with the evaluation target signal Sx; and a flip-flop 13A2, whose D terminal is input with the output signal Sx' of the flip-flop 13A1. The first synchronization circuit 13A includes: a flip-flop 13A3, whose D terminal is input with the reference signal Se; and a flip-flop 13A4, whose D terminal is input with the reference signal Se' output from the flip-flop 13A3. Each flip-flop is a D flip-flop, and a sampling clock signal φK (e.g., φ7) for synchronization is input to the clock input terminal (C terminal) of each flip-flop.

[0089] In addition, the first synchronization circuit 13A may include a frequency divider 13DIV. The frequency divider 13DIV is not essential, but it can reduce the frequency of the sampling clock signal. If the frequency divider 13DIV divides the sampling clock signal φK (e.g., φ7) input to the first synchronization circuit 13A into two equal parts, the frequency of the sampling clock signal becomes one-half and the period becomes twice as long.

[0090] (Comparison logic circuit)

[0091] Figure 7 It is a diagram showing the truth table of the comparison logic circuit (XOR circuit).

[0092] The evaluation object signal SxOUT and the reference signal SeOUT synchronously output from the first synchronization circuit 13A are input to the comparison logic circuit 15. The comparison logic circuit 15 is a circuit that compares the logic of the input digital signals. In this example, it is an XOR circuit (exclusive OR circuit). In an XOR circuit, "0" is output when the logic of the input data is the same, and "1" is output when the logic is different. The XOR circuit can also be replaced by four NAND circuits. Depending on the signal processing method of the subsequent stage, a structure that outputs other logical structures can also be used. For example, a circuit that flips the output of the XOR circuit through a NOT circuit can also be used. Therefore, the comparison logic circuit 15 only needs to be a logic circuit that compares the logic of the input data, and is not limited to the XOR circuit.

[0093] (Error counter)

[0094] Figure 8 Is a diagram that depicts the output of the error counter in a two-dimensional manner.

[0095] The error counter 16 (refer to Figure 2 ) is a counter that counts the output result (digital data) of the comparison logic circuit 15. The error counter 16 performs an increment count when the input data (evaluation object signal Sx, reference signal Se) input to the comparison logic circuit 15 is inconsistent. The comparison results are counted and accumulated within a fixed period (set as E-COUNT), and the count value is output. The phase of the reference rising edge (for example, Eφ8) is set to 0°. The reference signal Se is a signal sampled at a rising edge Eφe that is separated from the reference rising edge by a phase of Pφe (degrees). The count value represents the degree of inconsistency between the evaluation object signal Sx and the reference signal Se at the coordinates (Pφe, Ve) (pixels). When depicting a two-dimensional graph with the phase Pφe as the horizontal axis and the reference threshold voltage Ve as the vertical axis, the count value of the error counter 16 depicts an eye diagram at the position of the coordinates (Pφe, Ve). Pixels with a low count value represent the area within the opening of the eye diagram, and within the opening of the eye diagram, the count value is substantially zero.

[0096] The phase range of the eye diagram formation region R(EYE) depicted in a two-dimensional manner is at least 1 / 2 or less, preferably 1 / 3 or less, and more preferably 1 / 4 or less of the maximum value (N×UI, 360°) of the phase Pφe in this example. Here, N is a natural number, and UI represents the unit interval of the serial data signal DATA-S. That is, the maximum value of the phase Pφe is larger than the phase range of the eye diagram formation region R(EYE) required to obtain data. The center of the error tolerance region R(VIO) is set at a position where the phase is approximately (N×UI×1 / 2, 180°) away from the center of the eye diagram formation region R(EYE). The phase range of the error tolerance region R(VIO) is at least 1 / 2 or less, preferably 1 / 3 or less, and more preferably 1 / 4 or less of the maximum value of the phase Pφe. In the error tolerance region R(VIO), in the first synchronization circuit 13A, a setup time violation and / or a hold time violation may occur between the reference signal Se and the sampling clock signal φ7. In short, an error occurs in the error tolerance region R(VIO). In this example, there is an advantage that the error tolerance region R(VIO) is separated from the eye diagram formation region R(EYE), and the eye diagram formation region R(EYE) is not affected by the error.

[0097] In addition, the positions of the eye diagram formation region R(EYE) and the error tolerance region R(VIO) on the horizontal axis may shift along the horizontal axis from the reference position due to an unexpected inherent delay amount caused by the operating temperature of the phase adjustment circuit or manufacturing deviation, etc. In addition, the position of the phase Pφe = 360° and the position of the phase Pφe = 0° are the same position, and there are cases where the left end and the right end of the graph are continuously connected. If the inherent delay amount increases, there are cases where a part of the eye diagram appears near the left end of the graph and the remaining part appears near the right end of the graph. In this device, even if the inherent delay amount of the phase adjustment circuit changes, the eye diagram formation region R(EYE) is far from the error tolerance region R(VIO), having the advantage of not being affected by the error.

[0098] Figure 9 It is a timing diagram for explaining the setup time ST and the hold time HD.

[0099] Refer to Figure 2 , the sampling clock signal φ7 as a synchronization signal is input to the first synchronization circuit 13A, and the evaluation target signal Sx and the reference signal Se are set as the input signals to be synchronized. In this example, the evaluation target signal Sx (example: S2) is sampled by the sampling clock signal φ2 in the sampler SM2.

[0100] An example is shown in which the phase Pφe varies within a range R(Pφe) corresponding to the UI of 5 serial data signals DATA-S.

[0101] In the first case (Case 1), the rising edge Eφe of the sampling clock signal φe coincides with the positions of data D1 and data D6. In the reference signal Se, the true value of data D6 is output after the true value of data D1. In this case, within the range (setup time ST and hold time HD) near the rising edge Eφ7 of the sampling clock signal φ7, there is no inter-data boundary position of the reference signal Se, so no setup time violation or hold time violation occurs.

[0102] In the second case (Case 2), the rising edge Eφe of the sampling clock signal φe coincides with the positions of data D3 and data D8. In the reference signal Se, the true value of data D8 is output after the true value of data D3. In this case, within the range (setup time ST) near the rising edge Eφ7 of the sampling clock signal φ7, there is an inter-data boundary position of the reference signal Se, so a setup time violation exists.

[0103] In the third case (Case 3), the rising edge Eφe of the sampling clock signal φe coincides with the positions of data D4 and data D9. In the reference signal Se, the true value of data D9 is output after the true value of data D4. In this case, within the range (hold time HD) near the rising edge Eφ7 of the sampling clock signal φ7, there is an inter-data boundary position of the reference signal Se, so a hold time violation occurs.

[0104] In this example, to keep these error-occurring regions sufficiently away from the eye diagram formation region, the time from the rising edge Eφ2 of the sampling clock signal φ2 of the signal under evaluation Sx (e.g., S2) to the rising edge Eφ7 of the sampling clock signal φ7 is set to R(Pφe) / 2 (2.5UI). For this purpose, for example, it can be set that 2 ≤ (R(Pφe) / 2) ≤ 8.

[0105] (CDR circuit)

[0106] Figure 10 is a block diagram of a general CDR circuit.

[0107] This CDR circuit includes a phase difference detector 72, a filter 73, and a voltage controlled oscillator 74. A serial data signal Data and a clock signal Clock are input to the phase difference detector 72. The CDR circuit generates a clock signal based on the edge information of the input data.

[0108] Figure 11 is for explaining Figure 10 the operation of the CDR circuit shown

[0109] The phase difference detector 72 detects the phase difference between the position of the switching edge of the serial data signal Data and the rising edge of the clock signal Clock. When the position on the serial data signal Data side is advanced, it outputs a positive pulse signal UP with a width corresponding to this phase difference. When the position on the serial data signal Data side is delayed, it outputs a negative pulse signal DOWN with a width corresponding to this phase difference. The (low-pass) filter 73 accumulates and smoothes the positive pulse signal UP and the negative pulse signal DOWN, and outputs a voltage corresponding to the phase difference. If the phase is advanced compared to the reference (the cumulative value of the width of the positive pulse signal is large and the input voltage is positive), the voltage controlled oscillator 74 reduces the repetition frequency of the clock signal Clock. If the phase is delayed compared to the reference (the cumulative value of the width of the negative pulse signal is large and the input voltage is negative), the voltage controlled oscillator 74 increases the repetition frequency of the clock signal Clock.

[0110] In addition, Figure 2 The CDR circuit 17 shown is arranged at the subsequent stage of the second synchronization circuit 13B, so it is input with a parallel data signal, which is different from the Figure 10 CDR circuit with the structure shown. When applying the Figure 10 CDR circuit with the structure shown to the Figure 2 receiver shown, for example, the following structure can be adopted: The serial data signal DATA-S and each sampling clock signal φn (φ1 to φm) are respectively input to the CDR circuit, and based on these input signals, the sampling clock signal φn (φ1 to φm) is generated.

[0111] Figure 12 is a block diagram of the CDR circuit 17.

[0112] The CDR circuit 17 is arranged at the subsequent stage of the second synchronization circuit 13B and has a phase difference detector 172, a filter 173, a voltage controlled oscillator 174, and a polyphase clock signal generator 175. The CDR circuit 17 is input with the parallel data signal (digital signals S1OUT to SmOUT) output from the second synchronization circuit 13B.

[0113] Each of the digital signals S1OUT to SmOUT has information of "1" or "0". The arrangement of these "1"s and "0"s has phase difference information as a whole arrangement. That is, this phase difference information is the phase difference information between the phase of the serial data signal DATA-S in the data reception samplers SM1 to SMm and the phase of the sampling clock signal. This phase difference information indicates whether it is in a state (FAST) where the phase of each sampling clock signal is advanced compared to the phase of the serial data signal DATA-S or in a state (SLOW) where the phase of each sampling clock signal is delayed compared to the phase of the serial data signal DATA-S.

[0114] Figure 13 It is for explaining Figure 12 The timing chart of the phase difference of the data in the CDR circuit shown.

[0115] Figure 12 Among the digital signals S1OUT to SmOUT shown, the odd-numbered signals (S1OUT, S3OUT, S5OUT, S7OUT, S9OUT) have: data sampled at the position of the edge of the serial data signal DATA-S in the Figure 2 odd-numbered samplers (SM1, SM3, SM5, SM7, SM9). In addition, the even-numbered signals (S2OUT, S4OUT, S6OUT, S8OUT, S10OUT) are sampled at the central position of the pulse width in the serial data signal DATA-S.

[0116] In this case, when the arrangement of the data of the digital signals S2OUT, S3OUT, S4OUT sampled with the sampling clock signals φ2, φ3, φ4 is, for example, "0, 0, 1" or "1, 1, 0", it is in a state (FAST) where the rising edge of the sampling clock signal φ3 is advanced compared to the edge of the serial data signal DATA-S.

[0117] On the contrary, when the arrangement of the data of the digital signals S4OUT, S5OUT, S6OUT sampled with the sampling clock signals φ4, φ5, φ6 is "0, 1, 1" or "1, 0, 0", it is in a state (SLOW) where the rising edge of the sampling clock signal φ5 is delayed compared to the edge of the serial data signal DATA-S.

[0118] In the case of data arrangements other than these, for example, in the case of "1, 0, 1" or "1, 1, 1", etc., they are ignored as exceptions.

[0119] Refer to again Figure 12, the phase difference detector 172 detects whether the rising edge position of the odd-numbered sampling clock signals (φ1, φ3, φ5, φ7, φ9) is in a leading state or a lagging state with respect to the data boundary position of the serial data signal according to the data arrangement of the input digital signals S1OUT to SmOUT, such as 10-bit digital data. The phase difference detector 172 pre-stores the decision tables for the data arrangements in the leading case (FAST) and the lagging case (SLOW). When it is consistent with the former, it outputs "1", and when it is consistent with the latter, it outputs "0". In this way, the FAST / SLOW state determination can be made based on the input data. In addition, the logic circuit for determining the consistency of three data can be configured, for example, by arranging three AND circuits in parallel and inputting the outputs of these three into a three-input AND circuit.

[0120] When the phase difference information signal is output from the phase difference detector 172 (for example, when there are 4 for FAST and 1 for SLOW, arranged as "1, 1, 1, 1, 0"), the (low-pass) filter 173 outputs, for example, the DC voltage obtained by integrating and smoothing these pulse signals. In this case, as a whole, it can be determined that the phase of the sampling clock signal is in the leading state. Therefore, the voltage-controlled oscillator 174 reduces the repetition frequency of the clock signal. This operation is the same as that of Figure 10 the general CDR circuit shown. When it is determined as a whole to be in the lagging state, the opposite operation is performed. In addition, as a control method for the repetition frequency of the clock signal in the CDR circuit, other methods are also known, and such methods can also be used.

[0121] As described above, in the CDR circuit 17, if the number of FAST is large, the clock frequency of the voltage-controlled oscillator is reduced, and if the number of SLOW is large, the clock frequency of the voltage-controlled oscillator is increased. By repeating this process, the rising edge of the odd-numbered ones among the sampling clock signals φ1 to φm is aligned with the edge of the serial data signal DATA-S, and a sampling clock signal matching the serial data signal is obtained.

[0122] In addition, the clock signal output from the voltage-controlled oscillator 174 is input to the multi-phase clock signal generator 175. The multi-phase clock signal generator 175 generates a plurality of sampling clock signals φ1 to φm with different phases based on the input one clock signal. The multi-phase clock signal generator 175 can be configured, for example, using one or more frequency dividers. It is also possible to connect a plurality of delay circuits in series after one frequency divider and output each sampling clock signal from the output terminals of each delay circuit. A structure in which a plurality of frequency dividers are connected in parallel and the reset timing of each frequency divider is different is also considered. In the past, various types of multi-phase clock signal generators have been known, so a known circuit can be adopted.

[0123] As described above, the received signal quality monitor has: a second synchronization circuit 13B to which a plurality of output signals S1 to Sm output from a plurality of data reception samplers SM1 to SMm are input; and a CDR circuit 17 to which a plurality of output signals S1OUT to SmOUT output from the second synchronization circuit 13B are input, and which generates a multi-phase clock signal (φ1 to φm). Further, instead of inputting all of the output signals S1OUT to SmOUT to the CDR circuit 17, a part of the output signals selected from them may be input.

[0124] (Control circuit)

[0125] The control circuit 18 generates and outputs a phase control signal PH-SEL input to the phase adjustment circuit 11 and a threshold control signal TH-SEL for the voltage generator 12. The control circuit 18 outputs a reset control signal CNT-RESET and a stop control signal CNT-STOP input to the error counter 16. As described above, in the case where the eye diagram is depicted two-dimensionally in the error counter 16, the number of errors corresponding to each pixel of the eye diagram is counted during a fixed period (E-COUNT). This fixed period (E-COUNT) is provided by the period from the input timing of the reset control signal CNT-RESET to the input timing of the stop control signal CNT-STOP. The former input resets the error counter 16, and the latter input ends the counting and outputs the count value.

[0126] (Digital implementer)

[0127] The digital implementer includes a plurality of data reception samplers SM1 to SMm and a second synchronization circuit 13B.

[0128] The structure of each sampler SMn (SM1 to SMm) is the same as that of the reference sampler SMe shown Figure 3 The serial data signals DATA-S received by the plurality of data reception samplers SM1 to SMm are sampled in synchronization with the multi-phase sampling clock signals φ1 to φm, respectively. The plurality of data reception samplers receive the serial data signals and are connected in parallel, and are respectively input with the multi-phase sampling clock signals φ1 to φm.

[0129] (Second synchronization circuit)

[0130] Figure 14 is a block diagram showing the configuration of the second synchronization circuit 13B.

[0131] The output signals S1 to Sm (e.g., m = 10) output from a plurality of data reception samplers SM1 to SMm are input to a second synchronization circuit 13B. The second synchronization circuit 13B synchronizes the timings of the received output signals S1 to Sm and outputs them as a parallel data output signal DATA-PO (S1OUT to SmOUT). Each output signal Sn (S1 to Sm) is input to a flip-flop group formed by connecting two flip-flops in series. Each flip-flop is a D flip-flop.

[0132] The first output signal Sn (1 ≤ n ≤ m) is input to the D terminal of the flip-flop at the front stage of the n-th flip-flop group. The sampling clock signal φK for synchronization (e.g., φ7) is input to the clock input terminal (C terminal) of the flip-flop at the front stage of the flip-flop group when n = 1, 2, 3, 4, 10. The sampling clock signal φL for synchronization (e.g., φ2) is input to the clock input terminal (C terminal) of the flip-flop at the front stage of the flip-flop group when n = 5, n = 6, n = 7, n = 8, n = 9.

[0133] The D terminal of the flip-flop at the rear stage of the n-th flip-flop group is input with the first output signal Sn' (1 ≤ n ≤ m) sampled by the flip-flop at the front stage. The sampling clock signal φK for synchronization (e.g., φ7) is input to the clock input terminal (C terminal) of the flip-flop at the rear stage of the n-th flip-flop group.

[0134] That is, the second synchronization circuit 13B performs final synchronization using the sampling clock signal φK (e.g., φ7). The data when n is even (2, 4, 6, 8, 10) are the data sampled at the median value of the pulse width of the serial data signal DATA-S. The output data can be arranged in the order of n = 10, 2, 4, 6, 9.

[0135] Next, a supplementary explanation of the data sampling is given.

[0136] Figure 15 (A) of is a timing diagram of the serial data signal DATA-S, Figure 15 and (B) of is a timing diagram showing the reference sampling clock signal φe.

[0137] The serial data signal DATA-S and the scannable reference threshold voltage Ve are input to the reference sampler SMe. The serial data signal DATA-S is, for example, "1, 0, 1, 0, 0, 1". The position of the rising edge Eφe of the sampling clock signal φe can be adjusted by the phase adjustment circuit 11 (refer to Figure 2) It scans by moving in the time axis direction. In this figure, the threshold voltage V2 input to the sampler SMn (e.g., SM2) used in the deserialization and the rising edge Eφn (e.g., Eφ2) of its sampling clock signal φn are also shown. The sampler SM2 samples the serial data signal at the rising edge Eφ2 and outputs "1". The width of one data of the serial data signal DATA-S is UI (unit interval).

[0138] For example, the reference position (0°) of the rising edge Eφe that can be scanned is set to the position of the first eighth rising edge Eφ8. The phase Pφe of the rising edge Eφe can be scanned to the position of the next eighth rising edge Eφ8. If converted to UI, the phase Pφe can change in the range of 0 to N×UI (e.g., N = 5), and the phase change range R(Pφe) = N×UI. When expressed in terms of the angle of the phase, the phase Pφe can change between 0° and 360° (0° ≤ Pφe ≤ 360°), and the phase change range R(Pφe) = 360°. The period Tφe of the sampling clock signal φe can be set to Tφe = N×UI, but since the position of the rising edge Eφe is required, it can also be a different period. Also, for the same reason, the duty cycle of the sampling clock signal φe can also be not 50%.

[0139] Regarding the period of the sampling clock signal φe (Tφe = N×UI), in order to reduce the sampling frequency, it is preferable that 2 ≤ N. Also, as described above, in order to suppress the influence of setup time violation or hold time violation on the eye diagram, it is preferable that 3 ≤ N, and more preferably 4 ≤ N. Also, if the duty cycle of the sampling clock signal is 50% and N is odd, then by the flip of the signal, the phase of the rising edge will increase to 2 times, so it is preferable to set the parallel data signal to X = 2×N bits (e.g., 10 bits). Therefore, it is preferable that N = 5, N = 7, but in the cases of N = 2, 3, 4, N = 6, the same effect can also be expected.

[0140] Also, when the clock frequency f of the sampling clock signal φe (or the sampling clock signals φ1 to φ10) is given by the reciprocal of the time T of one unit of the data (f = 1 / T), it is called full-rate transmission. When the clock frequency f is 1 / 4T, it is called quarter-rate transmission. When the frequency f of the clock is 1 / (N×T), it can be called (1 / N)-rate transmission. For example, in the above, 1 / N-rate (e.g., N = 5) transmission is performed using an m-phase clock (m = 10) (m, N are integers, 2 ≤ m, 2 ≤ N, N ≤ m). In addition, although the number of clock signal lines required for the transmission of the clock signal is determined by the number of phases of the required clock signal, in most cases it is N lines or 2×N lines.

[0141] In addition, as described above, the reference threshold voltage Ve is varied by the voltage generator 12 and scanned. In this way, the received signal quality monitor has a voltage generator 12 that generates a variable reference threshold voltage Ve, and the reference threshold voltage Ve gives the coordinates of the vertical axis when the eye diagram is depicted. By varying the reference threshold voltage Ve, the coordinates (Pφe, Ve) in the case of depicting a two-dimensional eye diagram can be varied along the vertical axis direction. By varying the value of the phase Pφe using the phase adjustment circuit 11, the coordinates (Pφe, Ve) in the case of depicting a two-dimensional eye diagram can be varied along the horizontal axis direction.

[0142] In addition, the threshold voltage Vn (e.g., V2) of any sampler can also be varied by the voltage generator 12. As described above, the received signal quality monitor has a voltage generator 12 that generates variable threshold voltages Vn (V1 to Vm). Furthermore, feedback control can be performed such that the threshold voltages Vn (V1 to Vm) input to the multiple data reception samplers become the amplitude centers of the serial data signals input to the respective samplers SMn (SM1 to SMm). For example, in the case where the serial data signal DATA-S is a signal encoded in 8b10b format, the number of "1"s and "0"s output from each sampler is counted within a specified period. If the number of "1"s is greater than the number of "0"s, it is determined that the threshold voltage Vn is lower than the amplitude center voltage of the serial data signal DATA-S, and the reference threshold voltage Ve is increased. If the number of "1"s is less than the number of "0"s, the reference threshold voltage Ve can be decreased.

[0143] The threshold voltage Vn input to the multiple data reception samplers is preferably set such that the input signal levels can be clearly distinguished. For example, when the level of data "1" is 1V and the level of "0" is -1V, the threshold voltage is set to 0V. Additionally, for example, when the level of data "1" is 2V and the level of "0" is 0V, the threshold voltage is set to 1V.

[0144] Figure 16 It is a timing chart showing the serial data signal, the multi-phase clock signals φ1 to φ10, and the clock signal φe.

[0145] Two signals are input to the first synchronization circuit 13A (refer to Figure 2 ). One signal is a signal obtained by sampling the serial data signal DATA-S at the rising edge Eφ2 of the sampling clock signal φ2. The other signal is a signal obtained by sampling the serial data signal DATA-S at the rising edge Eφe of the sampling clock signal φe. Two signals are input to the second synchronization circuit 13B (refer to Figure 2)The input is a signal sampled by a sampling clock signal φn (e.g., φ1 to φ10). These synchronization circuits output the sampled data at the timing of the sampling clock signal φ7 for synchronization.

[0146] The phase Pφe of the rising edge Eφe moves within the phase change range R(Pφe). When a signal input to the first synchronization circuit 13A is sampled at the rising edge Eφn (e.g., Eφ2), it is preferable to set the phase interval from Eφ2 to Eφ7 to R(Pφe) / 2 (= 2.5UI). In other words, when the parallel data signal converted from the serial data signal is X bits, the phase interval (time) from the first rising edge Eφn to the second rising edge Eφ(n + X / 2) is set to (X / 4)×UI. As described above, the phase change range R(Pφe) is preferably set to 5×UI (= (X / 2)×UI).

[0147] Figure 17 It is a timing chart of the serial data signal and the signals output from the synchronization circuits 13A and 13B.

[0148] The data of the digital signals S2, S4, S6, S8 sampled by the sampler SMn (n is even) where n is the even-numbered sampler are converted into the data of the digital signals S2’, S4’, S6’, S8’ by the flip-flops in the front stage in the second synchronization circuit 13B (refer to Figure 14 ), and then are converted into the data of the digital signals S2OUT, S4OUT, S6OUT, S8OUT by the flip-flops in the rear stage, and are output from the second synchronization circuit 13B in a state where the phases of the data edges are consistent.

[0149] Figure 18 It is a block diagram of another receiving device RX.

[0150] Figure 18 In the receiving device RX of Figure 2 , only the structures of the phase adjustment circuit 11 and the input unit 110 are different from those of the receiving device RX of

[0151] Figure 19 is Figure 18 The block diagram of the phase adjustment circuit 11 shown.

[0152] A single sampling clock signal φ1 is input to the phase adjustment circuit 11. A plurality of inverter circuits (NOT circuits 11a, 11b, 11c, 11d ··· 11s, 11t) are connected in series, and every two inverter circuits, the output terminal inputs to the multiplexer 11C (selection circuit). A pair of inverter circuits constitutes a delay circuit, which gives a delay to the input sampling clock signal and outputs it. The multiplexer 11C receives a plurality of sampling clock signals with different rising edge times. The phase control signal PH-SEL (phase or clock selection signal SEL0) selects one sampling clock signal from the m sampling clock signals input to the multiplexer 11C and outputs a sampling clock signal φe with a specific phase. By switching the signal selected by the phase control signal PH-SEL (phase or clock selection signal SEL0), the phase of the sampling clock signal φe can be adjusted for scanning.

[0153] In addition, the transmission mode of the above serial data signal is, for example, an NRZ (Non Return to Zero) signal, and the serial data signal has two voltage levels. Therefore, the threshold voltage input to each sampler is 1, and the determination of 2 levels can be performed. PAM4 (Pulse Amplitude Modulation 4: 4-level pulse amplitude modulation) is a signal transmission mode using 4 voltage levels. In the signal transmission mode using PAMk (3 ≤ k), when the voltage level is 3 or more, a multi-value sampler capable of discriminating these levels is used. In the above, a plurality of data reception samplers SM1 to SMm are shown, but they have the same structure. Therefore, hereinafter, as a representative of these samplers, the structure after changing one data reception sampler SM1 to a multi-value sampler will be described.

[0154] Figure 20 It is a block diagram showing the structure of the multi-value sampler.

[0155] When receiving a serial data signal (PAM4) with 4 voltage levels, in order to discriminate them, 3 threshold voltages are required, and an eye diagram with 3 eye holes is obtained. Generally, when receiving a serial data signal with k levels, in order to discriminate them, k - 1 threshold voltages are required, and an eye diagram with k - 1 eye holes is obtained. In this figure, the case of receiving a serial data signal of PAM4 is shown, and the data reception sampler SM1 has a first data reception sampler SM1high, a second data reception sampler SM1mid, and a third data reception sampler SM1low, and the structure of each sampler is the same as Figure 3The structures shown are the same. A high-level threshold voltage V1high (first threshold voltage), a mid-level threshold voltage V1mid (second threshold voltage), and a low-level threshold voltage V1low (third threshold voltage) are input to each sampler. A first sampling clock signal φ1 is input to each sampler, and a first output signal S1high, a second output signal S1mid, and a third output signal S1low are output.

[0156] Figure 21 It is a graph showing the change of the input voltage (V) with respect to time (Time) input to the multi-value sampler.

[0157] When the data included in the serial data signal is the first data DATA1 and it is input to the first data reception sampler SM1high, the second data reception sampler SM1mid, and the third data reception sampler SM1low, at the sampling timing of the sampling clock signal φ1, the input voltage is higher than all the threshold voltages. Therefore, the outputs (S1high, S1mid, S1low) of the first, second, and third samplers = (1, 1, 1). If a data conversion table is used, (1, 1, 1) can be converted to "111".

[0158] Similarly, when the data included in the serial data signal is the second data DATA2 and it is input to the first data reception sampler SM1high, the second data reception sampler SM1mid, and the third data reception sampler SM1low, at the sampling timing of the sampling clock signal φ1, the outputs (S1high, S1mid, S1low) of the first, second, and third samplers = (0, 1, 1). If a data conversion table is used, (0, 1, 1) can be converted to "10".

[0159] Similarly, when the data included in the serial data signal is the third data DATA3 and it is input to the first data reception sampler SM1high, the second data reception sampler SM1mid, and the third data reception sampler SM1low, at the sampling timing of the sampling clock signal φ1, the outputs (S1high, S1mid, S1low) of the first, second, and third samplers = (0, 0, 1). If a data conversion table is used, (0, 0, 1) can be converted to "01".

[0160] Similarly, when the data included in the serial data signal is the fourth data DATA4 and it is input to the first data reception sampler SM1high, the second data reception sampler SM1mid, and the third data reception sampler SM1low, at the sampling timing of the sampling clock signal φ1, the outputs of the first, second, and third samplers (S1high, S1mid, S1low) = (0, 0, 0). If a data conversion table is used, (0, 0, 0) can be converted to "00".

[0161] As described above, when using a multi-value sampler, the signal levels of PAM4 can be separated and discriminated, and deserialization can be performed. A synchronization circuit can be provided in the same manner as described above at the subsequent stage of multiple multi-value samplers. In addition, for obtaining an eye diagram, it is not necessary to use all the output signals of the samplers.

[0162] Figure 22 It is a block diagram showing the circuit configuration of the multi-value sampler and the subsequent stage.

[0163] The configuration of the data reception sampler SM1 is as Figure 20 shown. The output signal S1high of the first data reception sampler SM1high and the reference signal Se of the reference sampler SMe are input to the first synchronization circuit 13A. The configuration of the reference sampler SMe is the same as the Figure 3 configuration shown, and the subsequent stage circuit and the remaining circuits can be the same as the above circuit. That is, the receiving device has a comparison logic circuit 15 and an error counter 16. A serial data signal and a reference threshold voltage Ve are input to the reference sampler SMe, and sampling is performed by the sampling clock signal φe. The reference threshold voltage Ve is variable and can be one. In this example, an eye diagram can be obtained in the same manner as described above.

[0164] In the case where the signal transmission method is PAM4, although a precise signal quality measurement can be performed using a method that utilizes all the outputs of a sampler with three-level thresholds, the signal quality can also be evaluated in the case of using only the output of one-level threshold determination. In this case, there is an advantage that the circuit structure becomes simple. In this figure, an example of using the high-level threshold voltage V1high as the threshold of one level is illustrated, but an example of using the middle-level threshold voltage V1mid or the low-level threshold voltage V1low is also possible.

[0165] Figure 23 It is a graph showing the change of the input voltage (V) input to the first data reception sampler SM1high and the reference sampler Sme with respect to time (Time).

[0166] When the data included in the serial data signal is the first data DATA1 and it is input to the sampler SM1high for receiving the first data, at the timing of the sampling clock signal φ1, the output signal S1high of the sampler SM1high for receiving the first data becomes "1". When the first data DATA1 is input to the reference sampler SMe, at the sampling timing of the sampling clock signal φe, the reference signal Se output from the reference sampler SMe becomes "1".

[0167] Similarly, when the data included in the serial data signal is the second data DATA2 and it is input to the sampler SM1high for receiving the first data, at the timing of the sampling clock signal φ1, the output signal S1high of the sampler SM1high for receiving the first data becomes "0". When the second data DATA2 is input to the reference sampler SMe, at the sampling timing of the sampling clock signal φe, the output signal Se of the reference sampler SMe becomes "1".

[0168] Similarly, when the data included in the serial data signal is the third data DATA3 or the fourth data DATA4 and it is input to the sampler SM1high for receiving the first data, at the timing of the sampling clock signal φ1, the output signal S1high of the sampler SM1high for receiving the first data becomes "0". When the third data DATA3 or the fourth data DATA4 is input to the reference sampler SMe, at the sampling timing of the sampling clock signal φe, the output signal Se of the reference sampler SMe becomes "0".

[0169] Figure 24 It is a block diagram showing the circuit configuration of the multi-value sampler and the subsequent stage.

[0170] Figure 24 The circuit shown is the same as Figure 22Compared with the circuit shown, the difference is that a multiplexer 131 (selection circuit) is arranged on the input side of the first synchronization circuit 13A, and the other structures are the same. The multiplexer 131 is input with a plurality of output signals from the first data reception sampler SM1high. These output signals are the first output signal S1high obtained by performing a high-level threshold determination, the second output signal S1mid obtained by performing a medium-level threshold determination, and the third output signal S1low obtained by performing a low-level threshold determination. These output signals (S1high, S1mid, S1low) are input to the multiplexer 131, and one of them is selected and output. The output signal selected by the multiplexer 131 is input to the first synchronization circuit 13A. By switching the selected signal by the multiplexer 131, three eye diagrams obtained by three threshold level determinations can be obtained. In addition, a selection signal for instructing the switching of the output signals (S1high, S1mid, S1low) can be input to the multiplexer 131 from the control circuit or an external device. In the circuit of this example, since the input signal input from the sampler to the first synchronization circuit 13A is switched, the size of the circuit can be made smaller. The remaining circuit structure is the same as that of Figure 22 the structure shown.

[0171] Figure 25 It is a block diagram showing the circuit configuration of a multi-value sampler and the subsequent stage.

[0172] Figure 25 The multiplexer shown in Figure 24 is omitted, and it has a circuit structure that processes all the output signals (S1high, S1mid, S1low) of the first sampler in parallel without switching based on the multiplexer. All the output signals (the first output signal S1high, the second output signal S1mid, the third output signal S1low) from the first sampler are input to the first synchronization circuit 13A.

[0173] The first output signal S1high, the second output signal S1mid, the third output signal S1low, and the reference signal Se output from the reference sampler SMe are input to the first synchronization circuit 13A. The first synchronization circuit 13A synchronizes the input signals and outputs them. The above-mentioned comparison logic circuit 15 is composed of a plurality of sub-comparison logic circuits.

[0174] A first output signal S1high is input to an input terminal of a first comparison logic circuit 15high. A second output signal S1mid is input to an input terminal of a second comparison logic circuit 15mid. A third output signal S1low is input to an input terminal of a third comparison logic circuit 15low. A reference signal Se is input to the other input terminal of each comparison logic circuit. Each comparison logic circuit is the same as the comparison logic circuit 15 shown in Figure 2 and is preferably an XOR circuit, which outputs "0" if the logic of the input data is the same and outputs "1" if they are different.

[0175] An output terminal of the first comparison logic circuit 15high is connected to an input terminal of a first error counter 16high. An output terminal of the second comparison logic circuit 15mid is connected to an input terminal of a second error counter 16mid. An output terminal of the third comparison logic circuit 15low is connected to an input terminal of a third error counter 16low. The processing in each error counter is the same as that of the error counter shown in Figure 2 . According to this circuit, the outputs of the three samplers are processed in parallel, so that a multi-value eye diagram can be obtained in a short time.

[0176] As described above, in the Figures 20 - 25 reception signal quality monitor, the serial data signal is a pulse amplitude modulation (PAM) signal having multiple values of k levels (3 ≤ k, k is an integer), and each of the multiple data reception samplers includes k - 1 samplers. Threshold voltages (V1high, V1mid, V1low) with different levels are input to the k - 1 samplers together with the serial data signal. k - 1 comparison results (S1high, S1mid, and S1low) are output from each of the k - 1 samplers. According to this structure, processing of a multi-value serial data signal can also be performed.

[0177] In addition, in the Figure 25 reception signal quality monitor, k - 1 comparison results (S1high, S1mid, S1low) are output as a first output signal from one sampler included in the multiple data reception samplers, and the k - 1 comparison results and a second output signal (reference signal Se) of a reference sampler are input to a first synchronization circuit 13A. The comparison logic circuit 15 includes k - 1 sub-comparison logic circuits (15high, 15mid, 15low), and the k - 1 comparison results (S1high, S1mid, S1low) synchronously output from the first synchronization circuit 13A and the second output signal (reference signal Se) are input to the k - 1 sub-comparison logic circuits respectively.

[0178] Figure 26 of (A), Figure 26(B) is a timing diagram of an exemplary serial data signal.

[0179] Figure 26 The serial data signal of (A) is a periodic signal. Figure 26 The serial data signal of (B) is a signal having a random pattern or a pseudo-random pattern. In the case of performing data sampling for an eye diagram at a 1 / 5 rate, data sampling is performed every 5 data, and they are overlapped and displayed in the center of the eye diagram. That is, for any signal, data of D6 is sampled after data of D1 is sampled.

[0180] From the serial data signal having periodicity ( Figure 26 (A)), the size of the aperture of the eye diagram obtained is generally larger than the size of the aperture of the eye diagram obtained from the serial data signal having a random pattern ( Figure 26 (B)). Since the transmission line characteristics are preferably assumed for all inputs, in the case of accurately evaluating the quality of the received signal, the received serial data signal is preferably a random pattern or a pseudo-random pattern.

[0181] As described above, the above-described received signal quality monitor includes: a plurality of data reception samplers SM1 to SMm, which respectively receive the serial data signal DATA-S and are connected in parallel, and each of their sampling clock signals φn (1 ≤ n ≤ m, m and n are integers) is input with each clock signal included in the polyphase clock signal at their input terminals; a reference sampler Sme, which receives the serial data signal; a phase adjustment circuit 11, which has one or more input terminals for inputting one or more clock signals included in the polyphase clock signal, and an output terminal connected to the input terminal of the sampling clock signal φe of the reference sampler, and can perform phase scanning of the sampling clock signal φe within a phase range (N × UI) that is N times (2 ≤ N) the unit interval (UI) of the serial data signal; a first synchronization circuit 13A, which is input with a first output signal of one sampler included in the plurality of data reception samplers and a second output signal of the reference sampler (SMe), and synchronously outputs the first and second output signals; and a comparison logic circuit (15), which is input with the first and second output signals synchronously output from the first synchronization circuit 13A. The first and second output signals synchronously output from the first synchronization circuit 13A are input to the comparison logic circuit 15, and the comparison logic circuit 15 outputs a comparison result related to the quality of the received signal.

[0182] In the above receiving device, the frequency of the sampling clock signal φn is preferably 1 / N (2 ≤ N) of the frequency of the serial data signal DATA-S. The received signal quality monitor has a phase adjustment circuit 11, and the phase adjustment circuit 11 can perform phase scanning of the output sampling clock signal φe within a phase range (N × UI) (several times the phase range) that is N times (2 ≤ N) the unit interval (UI) of the serial data signal. It is possible to perform phase scanning of the sampling clock signal φe within several times the UI phase range. Preferably, when the frequency of the received sampling clock signal φn is 1 / N (e.g., N = 5) of the frequency given by the reciprocal of the time width of one data of the input serial data signal, the phase range that can be scanned is N × UI (e.g., N = 5 (phase scanning range 360°)). When this phase range is, for example, (N / 2) × UI or more (e.g., 2.5UI), it also has the effect of reducing the influence of setup time violation and hold time violation. In addition, the phase range (phase change range R(Pφe)) adjusted by the phase adjustment circuit 11 is preferably set to be one cycle (in the case of Figure 15 N × UI in the example) or more of the sampling clock signal φe input to the reference sampler. By expanding the phase range, it is easy to obtain even if the position of the eye diagram moves.

[0183] In the above receiving device, the phase adjustment circuit 11 is arranged in the front stage of the reference sampler SMe, but no phase adjustment circuit for delay adjustment is arranged in the front stage of other samplers. Compared with a receiving device that requires such a phase adjustment circuit for delay adjustment, the above receiving device can reduce the circuit area and power consumption. In addition, by setting the phase scanning range as described above, the influence of the inherent delay of such a delay adjustment circuit can be suppressed without arranging the delay adjustment circuit in the front stage of each sampler. In addition, in the phase adjustment circuit 11, even if an unexpected inherent delay occurs due to changes in the operating environment or the like, since the phase scanning range is wide as described above, an eye diagram can still be obtained.

[0184] As described above, a phase adjustment circuit technology for an eye monitor in a data receiving device using a multi-phase clock signal is disclosed. In this technology, it is preferable to set the input data to a random pattern. The phase adjustment range of the phase adjustment circuit is set wide. In addition, in the comparison logic circuit, synchronization is obtained in such a way that no synchronization error occurs in the part related to the aperture of the eye diagram. Thus, there is no need to add a dummy circuit or a phase compensation circuit of the phase adjustment circuit in the path of the multi-phase clock signal to cancel the inherent delay of the phase adjustment circuit, and power consumption and area can be reduced.

[0185] Supplement the evaluation of signal quality. The signals received via the transmission line are deteriorated due to their respective loads and the like. The quality of the transmitted signal can be judged by observing the eye opening of the eye diagram. The eye diagram is a diagram in which signals are overlapped with two minimum unit amounts of transmitted data as one cycle, and the eye opening refers to the size of the hole at the center of the eye diagram. The larger the height and width of the hole, the better the signal quality is evaluated. Note that the signal quality can be evaluated not by evaluating the entire eye hole, but by evaluating a part of the quality monitoring signal. The opening size in the longitudinal axis direction passing through the center of the eye hole can be evaluated. The opening size in the horizontal axis direction passing through the center of the eye hole can be evaluated. The opening size at an appropriate position passing through the eye hole can be evaluated. The opening size in the tilt direction of the eye hole can be evaluated. In this way, various evaluation methods can be considered.

[0186] In recent years, with the popularization of communication devices, paperless work, and the popularization of working from home, etc., the data rate of the required communication data has increased. The above-mentioned receiving device performs data transmission using a polyphase clock (m-phase clock), and thus can cope with high data rate communication. The power consumption of the above-mentioned receiving device is small, and the area is also small. The larger the N in the 1 / N rate transmission, the greater this effect, but in the above-mentioned device, proper synchronization can still be performed.

[0187] Description of reference numerals

[0188] 11: Phase adjustment circuit, 11A: Multiplexer, 11B: Phase interpolation circuit, 11C: Multiplexer, 12: Voltage generator, 13A: First synchronization circuit, 13B: Second synchronization circuit, 13DIV: Divider, 15: Comparison logic circuit, 16: Error counter, 17: CDR circuit, 18: Control circuit, 72: Phase difference detector, 73: Filter, 74: Voltage controlled oscillator, 101: Amplifier, 110: Input section, 131: Multiplexer, 172: Phase difference detector, 173: Filter, 174: Voltage controlled oscillator, 175: Polyphase clock signal generator, 300: External device, 301: Memory, 303: Interface, 304: Bus, 305: Display, CB: Communication cable, COMP: Comparator, OUTPUT: Quality monitoring signal, SM1~SMm: Data reception sampler, SMe: Reference sampler.

Claims

1. A received signal quality monitor, comprising: A plurality of samplers for data reception, which receive serial data signals and are connected in parallel, and to which sampling clock signals of multiple phases are respectively input; A reference sampler, which receives the serial data signal; A phase adjustment circuit, which can perform phase scanning of the sampling clock signal input to the reference sampler within a phase range of N times the unit interval UI of the serial data signal, wherein, 2≤N； A first synchronization circuit, which receives the output signal of one of the plurality of samplers for data reception and the output signal of the reference sampler; and A comparison logic circuit, which receives two output signals synchronously output from the first synchronization circuit.

2. The received signal quality monitor according to claim 1, characterized in that The phase range adjusted by the phase adjustment circuit is more than one cycle of the sampling clock signal input to the reference sampler.

3. The received signal quality monitor according to claim 1, characterized in that The received signal quality monitor further includes a counter, which counts the output result of the comparison logic circuit.

4. The received signal quality monitor according to claim 1, characterized in that The reference sampler includes: A first input terminal, which receives the serial data signal; and A second input terminal, to which a variable reference threshold voltage is input, The reference sampler samples the comparison result between the serial data signal and the reference threshold voltage synchronously with the sampling clock signal capable of phase scanning.

5. The received signal quality monitor according to claim 4, characterized in that Each sampler included in the plurality of samplers for data reception includes: A first input terminal, which receives the serial data signal; and A second input terminal, to which a threshold voltage is input, Each sampler included in the plurality of samplers for data reception samples the comparison result between the serial data signal and the threshold voltage synchronously with the sampling clock signal included in the multiple-phase sampling clock signals and corresponding to the sampler.

6. The received signal quality monitor according to claim 1, characterized in that The received signal quality monitor includes: A second synchronization circuit, which receives a plurality of output signals output from the plurality of samplers for data reception; and A CDR circuit, which receives the plurality of output signals output from the second synchronization circuit and generates the multiple-phase sampling clock signals.

7. The received signal quality monitor according to claim 1, characterized in that The serial data signal is a multi-valued pulse amplitude modulation signal with k levels, where 3 ≤ k and k is an integer, and pulse amplitude modulation refers to PAM, Each of the plurality of samplers for data reception has k - 1 samplers, and threshold voltages with different levels are input to each of the k - 1 samplers together with the serial data signal, and k - 1 comparison results are output from each of the k - 1 samplers.

8. The received signal quality monitor according to claim 7, characterized in that Output the k-1 comparison results from one sampler included in the plurality of data reception samplers. Input the k-1 comparison results and the output signal of the reference sampler to the first synchronization circuit. The comparison logic circuit has k-1 sub-comparison logic circuits. Input the output signals synchronously output from the first synchronization circuit to the k-1 sub-comparison logic circuits respectively.

9. The received signal quality monitor according to claim 6. Characterized in that The phase adjustment circuit has: A selection circuit for inputting the multi-phase sampling clock signal output from the CDR circuit; and A phase interpolation circuit for inputting the output signal of the selection circuit.

Images