A vehicle-mounted video image stitching method and system based on FPGA

Abstract

The present invention discloses an FPGA-based vehicle-mounted video image stitching method and system. The system utilizes a cross-temporal processing module, an input frame storage module, a storage controller, an output frame storage module, an output buffer unit, a video stitching module, an output timing generation module, and a windowing processing module. The output buffer unit is used to buffer image data retrieved by the output frame storage module to obtain a first image and a second image to be stitched together; the output timing generation module is used to generate a corresponding timing signal based on the resolution parameters of a third image; the windowing processing module is used to generate effective window signals for the corresponding images based on the resolution parameters of the first image, the resolution parameters of the second image, and the timing signal; and the video stitching module is used to stitch the first image and the second image together based on the effective window signal to form a third image, and output the third image to a display screen. The present invention provides efficient, convenient, and real-time video processing and intuitive preview functions.

Description

Technical Field

[0001] The present invention relates to the technical field of video image transmission, and in particular discloses a vehicle-mounted video image splicing method and system based on FPGA. Background Art

[0002] In recent years, with the rapid development of information technology, video technology has gradually become one of the important application technologies in various fields. In the field of visual interaction, video splicing technology has been widely used. However, in the field of automotive display, existing video interaction technology cannot meet the needs of the majority of car users for real-time observation of car images.

[0003] Therefore, in the field of automotive display, the existing video interaction technology cannot meet the needs of the majority of car users to observe car images in real time, which is a technical problem that needs to be solved urgently. Summary of the Invention

[0004] The present invention provides an FPGA-based vehicle-mounted video image splicing method and system, aiming to solve the technical problem in the field of vehicle display that existing video interaction technology cannot meet the needs of the majority of vehicle users for real-time observation of vehicle images.

[0005] One aspect of the present invention relates to an FPGA-based vehicle-mounted video image splicing system, comprising a cross-time domain processing module, an input frame storage module, a storage controller, an output frame storage module, an output buffer unit, a video splicing module, an output timing generation module, and a windowing processing module, wherein:

[0006] Cross-time domain processing module, used to synchronize image data from the image clock to the FPGA internal logic processing clock;

[0007] A storage controller is connected to the input frame storage module and the output frame storage module respectively, and is used to control the input frame storage module to write the image data processed by the cross-time domain processing module into the memory; and control the output frame storage module to retrieve the image data stored in the memory;

[0008] An output buffer unit, connected to the output frame storage module, for buffering the image data retrieved by the output frame storage module to obtain the first image and the second image to be spliced;

[0009] An output timing generation module, connected to the video splicing module, is used to generate a corresponding timing signal according to the resolution parameter of the third image; wherein the third image is used to splice the first image and the second image;

[0010] a window processing module connected to the output buffer unit and the output timing generation module, and configured to generate effective window signals for corresponding images according to the resolution parameters of the first image, the resolution parameters of the second image, and the timing signal;

[0011] The video splicing module is connected to the window processing module and is used to splice the first image and the second image according to the effective window signal to form a third image, and output the third image to the display screen.

[0012] Furthermore, the output timing generation module includes:

[0013] The first definition unit is used to define variables V and H; V is the variable for calculating the number of rows in Graph3, and H is the variable for calculating the number of columns in Graph3;

[0014] The calculation unit is used to clear the value to 0 and re-accumulate if H = (X1 + X2) is recognized; if H = (X1 + X2) is recognized, the V count is increased by 1; if V = Y is recognized, the value is cleared to 0 and re-accumulated; wherein X1 is the width of Graph1, X2 is the width of Graph2; Y is the height of Graph3;

[0015] The first generating unit is configured to flip the field synchronization signal, the line synchronization signal and the data valid signal of the output image to generate a timing diagram if it is recognized that the accumulated value of the variables V and H is equal to a preset parameter value.

[0016] Furthermore, the effective window signal includes a first effective window signal and a second effective window signal. In the window processing module, the first effective window signal and the second effective window signal are generated according to the resolution parameters of the first image, the resolution parameters of the second image and the timing signal.

[0017] Furthermore, the window processing module includes:

[0018] The second definition unit is used to define variables row and col; row is the row count and col is the column count;

[0019] The second generating unit is used to identify DE=1, and When , DE1 is determined to be valid; where DE is the valid signal of Graph3 data, X1 is the width of Graph1, Y is the height of Graph3, DE1 is the valid signal of Graph1 data, and X1 is the width of Graph1;

[0020] The third generating unit is used to identify DE=1, and When DE2 is valid, X2 is the width of Graph2, and DE2 is the valid signal of Graph2 data.

[0021] Furthermore, the video splicing module includes:

[0022] The acquisition unit is used to read the data in the output buffer using DE1 and DE2 respectively to obtain data data1 and data2; wherein data1 is the data of Graph1 and data2 is the data of Graph2;

[0023] The splicing unit is used to synchronize data1 and data2 with the DE signal, and output data1 and data2 in sequence under the premise that DE is valid to complete data splicing; wherein the DE signal is a valid window signal.

[0024] Another aspect of the present invention relates to an FPGA-based vehicle-mounted video image stitching method, which is applied to the above-mentioned FPGA-based vehicle-mounted video image stitching system. The FPGA-based vehicle-mounted video image stitching method includes the following steps:

[0025] The cross-time domain processing module synchronizes the image data from the image clock to the FPGA internal logic processing clock;

[0026] The storage controller controls the input frame storage module to write the image data processed by the cross-time domain processing module into the memory; and controls the output frame storage module to retrieve the image data stored in the memory;

[0027] The output buffer unit buffers the image data retrieved by the frame storage module to obtain the first image and the second image to be spliced;

[0028] The output timing generation module is connected to the video splicing module and generates a corresponding timing signal according to the resolution parameter of the third image;

[0029] The window processing module generates effective window signals of corresponding images according to the resolution parameters of the first image, the resolution parameters of the second image and the timing signal;

[0030] The video splicing module splices the first image and the second image according to the effective window signal to form a third image, and outputs the third image to the display screen.

[0031] Furthermore, the window processing module generates effective window signals of corresponding images according to the resolution parameters of the first image, the resolution parameters of the second image, and the timing signal, respectively, including the following steps:

[0032] Define variables V and H;

[0033] If H = (X1 + X2) is recognized, the value is cleared to 0 and the value is accumulated again. If H = (X1 + X2) is recognized, the value V is counted up by 1. If V = Y is recognized, the value is cleared to 0 and the value is accumulated again.

[0034] If it is recognized that the accumulated value of the variables V and H is equal to the preset parameter value, the field synchronization signal, the line synchronization signal and the data valid signal of the output image are flipped to generate a timing diagram.

[0035] Furthermore, in the step in which the window processing module generates effective window signals for corresponding images according to the resolution parameters of the first image, the resolution parameters of the second image and the timing signal, the first effective window signal and the second effective window signal are generated according to the resolution parameters of the first image, the resolution parameters of the second image and the timing signal.

[0036] Furthermore, the window processing module generates effective window signals of corresponding images according to the resolution parameters of the first image, the resolution parameters of the second image, and the timing signal, respectively, including the following steps:

[0037] Define variables row and col;

[0038] If DE=1 is recognized, and When , DE1 is determined to be valid;

[0039] If DE=1 is recognized, and , DE2 is determined to be valid.

[0040] Furthermore, the video splicing module splices the first image and the second image according to the valid window signal to form a third image, and outputs the third image to the display screen, including the following steps:

[0041] Use DE1 and DE2 to read the data in the output buffer to obtain data data1 and data2;

[0042] Data1 and data2 are processed synchronously with the DE signal. Under the premise that DE is valid, data1 and data2 are output in sequence to complete data splicing.

[0043] The beneficial effects achieved by the present invention are:

[0044] The present invention provides an FPGA-based vehicle-mounted video image splicing method and system. The system adopts a cross-time domain processing module, an input frame storage module, a storage controller, an output frame storage module, an output buffer unit, a video splicing module, an output timing generation module and a window processing module. The cross-time domain processing module is used to synchronize image data from an image clock to an internal logic processing clock of the FPGA; the storage controller is used to control the input frame storage module to write the image data processed by the cross-time domain processing module into a memory; and control the output frame storage module to retrieve the image data stored in the memory; the output buffer unit is used to cache the image data retrieved by the output frame storage module to obtain a first image and a second image to be spliced; the output timing generation module is used to generate a corresponding timing signal according to a resolution parameter of a third image; the window processing module is used to generate an effective window signal of a corresponding image according to the resolution parameter of the first image, the resolution parameter of the second image and the timing signal; the video splicing module is used to splice the first image and the second image according to the effective window signal to form a third image, and output the third image to a display screen. The FPGA-based vehicle-mounted video image stitching method and system provided by the present invention are mainly used in the field of automobile display. In order to meet the needs of a large number of automobile users for real-time observation of automobile images, it provides efficient, convenient, real-time video processing and intuitive preview functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 This is a functional block diagram of an embodiment of an FPGA-based vehicle-mounted video image splicing system of the present invention;

[0046] Figure 2 This is a schematic diagram of image stitching in an FPGA-based vehicle-mounted video image stitching system of the present invention;

[0047] Figure 3 Graph3 is a timing diagram of the output image in an FPGA-based vehicle-mounted video image splicing system of the present invention;

[0048] Figure 4 This is a schematic diagram of effective window signals in an FPGA-based vehicle-mounted video image splicing system of the present invention. DETAILED DESCRIPTION

[0049] In order to better understand the above technical solution, the above technical solution will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0050] like Figures 1 to 4As shown, the first embodiment of the present invention proposes an FPGA-based vehicle-mounted video image stitching system, including a cross-time domain processing module, an input frame storage module, a storage controller, an output frame storage module, an output buffer unit, a video stitching module, an output timing generation module and a window processing module, wherein the cross-time domain processing module is used to synchronize image data from an image clock to an internal logic processing clock of the FPGA; the storage controller is respectively connected to the input frame storage module and the output frame storage module, and is used to control the input frame storage module to write the image data processed by the cross-time domain processing module into the memory; and control the output frame storage module to take out the image data stored in the memory; the output buffer unit is connected to the output frame storage module, and is used to cache the output data. The frame storage module takes out the image data to obtain the first image and the second image to be spliced; the output timing generation module is connected to the video splicing module, and is used to generate a corresponding timing signal according to the resolution parameter of the third image; wherein the third image is used to splice the first image and the second image; the window processing module is connected to the output buffer unit and the output timing generation module, and is used to generate effective window signals of corresponding images according to the resolution parameters of the first image, the resolution parameters of the second image and the timing signal; the video splicing module is connected to the window processing module, and is used to splice the first image and the second image according to the effective window signal to form a third image, and output the third image to the display screen.

[0051] The cross-temporal processing module synchronizes image data from the image clock to the internal logic processing clock of the FPGA (Field Programmable Gate Array). This function is implemented using an asynchronous FIFO (First Input First Output) queue. Data is written to the FIFO (First In, First Out) queue based on the image clock and read out based on the logic clock.

[0052] Frame memory module: controls data writing into memory.

[0053] Frame output storage module: takes data out of the memory.

[0054] Storage controller: implements storage interface functions.

[0055] Output buffer unit: stores image data read from the memory.

[0056] Output timing generation module: generates the timing signal of the output image.

[0057] Windowing module: Generates an image valid window signal, which is used to read data from the output buffer module. Generating a valid window signal is a crucial step in this method. Failure to obtain a valid window signal, or the obtained valid window signal exhibits timing deviations, prevents complete input image data acquisition, impacts the timing of subsequent image stitching, and results in an incorrect output image.

[0058] Video stitching module: stitches the first image and the second image to form a third image, outputs the data to the display screen, and the final display screen can be observed.

[0059] The inbound frame memory module operates in three phases: preparation, data writing, and termination. 1. Preparation: Configures the write frame memory base address, write frame number, and data burst length. 2. Data Writing: The inbound frame memory module initiates a write request and begins writing data after receiving a response from the storage controller. 3. Termination: Data writing is complete after the inbound frame memory module receives a completion signal from the storage controller.

[0060] The outbound frame storage module operates in three phases: preparation, data read, and termination. 1. Preparation: Configures the frame storage base address, read frame number, and data burst length. 2. Data read: The outbound frame storage module initiates a read request and begins reading data after receiving a response from the storage controller. 3. Termination: Data read is complete after the inbound frame storage module receives a completion signal from the storage controller.

[0061] Further, see Figures 1 to 4 , the FPGA-based vehicle-mounted video image splicing system provided in this embodiment, Figure 3 Note: frontporch: front porch blanking. backporch: back porch blanking. sync time: horizontal (or vertical) synchronization. blanking: data blanking period. active video: data valid period. VS (vert sync): vertical sync signal. HS (horizsync): horizontal sync signal; DE (data enable): data valid signal. Figure 3 The timing parameters marked in the middle are the field synchronization (VS) and the timing parameters of the horizontal synchronization (HS) are the same as above. The timing signals mentioned in this embodiment collectively refer to the horizontal field synchronization and DE (valid data) signals. Figure 3The timing parameters are determined by the video standards established by the Video Electronics Standards Association. The output timing generation module includes a first definition unit, a calculation unit, and a first generation unit. The first definition unit is used to define variables V and H. V is a variable for calculating the number of rows in Graph3, and H is a variable for calculating the number of columns in Graph3. The calculation unit is used to reset the value to 0 and restart the accumulation if H = (X1 + X2). If H = (X1 + X2), the V count is incremented by 1. If V = Y, the value is reset to 0 and restart the accumulation. X1 is the width of Graph1, X2 is the width of Graph2, and Y is the height of Graph3. The first generation unit is used to flip the field synchronization signal, line synchronization signal, and data valid signal of the output image to generate the timing diagram if the accumulated value of variables V and H equals the preset parameter value.

[0062] Timing generation process:

[0063] 1) Define variables V and H.

[0064] 2) H accumulates with the clock. When H = (X1 + X2), it is cleared to 0 and accumulated again. When H = (X1 + X2), V counts up by 1. When V = Y, it is cleared to 0 and accumulated again.

[0065] 3) V, H cumulative value = Figure 3 When the parameter value is medium, the VS, HS, and DE signals are flipped to generate Figure 3 The timing diagram shown in .

[0066] Preferably, see Figures 1 to 4 In the FPGA-based vehicle-mounted video image stitching system provided in this embodiment, the valid window signal includes a first valid window signal and a second valid window signal. In the window processing module, the first valid window signal and the second valid window signal are generated according to the resolution parameter of the first image, the resolution parameter of the second image, and the timing signal. The window processing module includes a second definition unit, a second generation unit, and a third generation unit, wherein the second definition unit is used to define variables row and col; wherein row is the row count and col is the column count; the second generation unit is used to, if DE=1 is recognized, and row , then DE1 is determined to be valid; wherein DE is a valid signal for Graph3 data, X1 is the width of Graph1, Y is the height of Graph3, DE1 is a valid signal for Graph1 data, X1 is the width of Graph1; the third generating unit is used to identify DE=1, and When DE2 is valid, X2 is the width of Graph2, and DE2 is the valid signal of Graph2 data.

[0067] Windowing module: Generates an image valid window signal, which is used to read data from the output buffer module. Generating a valid window signal is a crucial step in this method. Failure to obtain a valid window signal, or the obtained valid window signal exhibits timing deviations, prevents complete input image data acquisition, impacts the timing of subsequent image stitching, and results in an incorrect output image.

[0068] The window processing module generates the effective window signals DE1 (first effective window signal) and DE2 (second effective window signal) of the corresponding images according to the timing of the image Graph3 (third image), the resolution of the image Graph1 (first image) and the resolution of the image Graph2 (second image), as shown in FIG. Figure 4 shown.

[0069] Window opening process:

[0070] 1) Define variables row and col; row is the row count and col is the column count.

[0071] 2) When DE=1; and DE1 is valid.

[0072] 3) When DE=1; and DE2 is effective.

[0073] Generate DE1 and DE2 signals in the above manner to prepare for subsequent splicing.

[0074] Further, see Figures 1 to 4 The FPGA-based vehicle-mounted video image stitching system provided in this embodiment has a video stitching module including an acquisition unit and a stitching unit, wherein the acquisition unit is used to read data in the output buffer using DE1 and DE2 respectively to obtain data data1 and data2; wherein data1 is Graph1 data, and data2 is Graph2 data; the stitching unit is used to synchronize data1 and data2 with the DE signal, and output data1 and data2 in sequence under the premise that DE is valid to complete data stitching; wherein the DE signal is a valid window signal.

[0075] Video stitching module: stitches two images together.

[0076] Splicing process:

[0077] Use DE1 and DE2 to read the data in the output buffer respectively to obtain data data1 and data2.

[0078] Synchronize data1 and data2 with the DE signal. When DE is valid, output data1 and data2 in sequence to complete data splicing.

[0079] The above process completes image stitching to form the final image sequence and data.

[0080] The present invention also relates to an FPGA-based vehicle-mounted video image stitching method, which is applied to the above-mentioned FPGA-based vehicle-mounted video image stitching system. The FPGA-based vehicle-mounted video image stitching method includes the following steps:

[0081] Step S100: The cross-time domain processing module synchronizes the image data from the image clock to the FPGA internal logic processing clock.

[0082] Cross-time processing: Synchronizes image data from the image clock to the FPGA's internal logic processing clock (hereafter referred to as the logic clock). This function is implemented using an asynchronous FIFO. Data is written to the FIFO based on the image clock and read out based on the logic clock.

[0083] Step S200: The storage controller controls the input frame storage module to write the image data processed by the cross-temporal processing module into the memory; and controls the output frame storage module to retrieve the image data stored in the memory.

[0084] Frame memory module: controls data writing into memory.

[0085] Frame output storage module: takes data out of the memory.

[0086] Storage controller: implements storage interface functions.

[0087] Step S300: The output buffer unit buffers the image data retrieved from the frame storage module to obtain the first image and the second image to be spliced.

[0088] Output buffer unit: stores image data read from the memory.

[0089] Step S400: The output timing generation module is connected to the video splicing module to generate a corresponding timing signal according to the resolution parameter of the third image.

[0090] Output timing generation module: generates the timing signal of the output image.

[0091] Step S500: The window processing module generates effective window signals of corresponding images according to the resolution parameters of the first image, the resolution parameters of the second image and the timing signal.

[0092] Windowing module: Generates an image valid window signal, which is used to read data from the output buffer module. Generating a valid window signal is a crucial step in this method. Failure to obtain a valid window signal, or the obtained valid window signal exhibits timing deviations, prevents complete input image data acquisition, impacts the timing of subsequent image stitching, and results in an incorrect output image.

[0093] Step S600: The video splicing module splices the first image and the second image according to the valid window signal to form a third image, and outputs the third image to the display screen.

[0094] Video stitching module: stitches the first image and the second image to form a third image, outputs the data to the display screen, and the final display screen can be observed.

[0095] Furthermore, the FPGA-based vehicle-mounted video image stitching method provided in this embodiment includes step S400:

[0096] Step S410: Define variables V and H.

[0097] Step S420: If H=(X1+X2) is recognized, the value is cleared to 0 and the accumulation is restarted; if H=(X1+X2) is recognized, the V count is increased by 1; if V=Y is recognized, the value is cleared to 0 and the accumulation is restarted.

[0098] Step S430: If it is identified that the accumulated value of the variables V and H is equal to the preset parameter value, the field synchronization signal, the horizontal synchronization signal and the data valid signal of the output image are flipped to generate a timing diagram.

[0099] Preferably, the FPGA-based vehicle-mounted video image stitching method provided in this embodiment includes step S500:

[0100] Step S510: Define variables row and col.

[0101] Step S520: If DE=1 is identified, and , DE1 is determined to be valid.

[0102] Step S530: If DE=1 is identified, and , DE2 is determined to be valid.

[0103] Furthermore, the FPGA-based vehicle-mounted video image stitching method provided in this embodiment includes step S600:

[0104] Step S610: Use DE1 and DE2 to read the data in the output buffer to obtain data data1 and data2.

[0105] Step S620: synchronize data1 and data2 with the DE signal. Under the premise that DE is valid, output data1 and data2 in sequence to complete data splicing.

[0106] This embodiment provides an FPGA-based vehicle-mounted video image stitching method and system. Compared with the existing technology, the system adopts a cross-time domain processing module, an input frame storage module, a storage controller, an output frame storage module, an output buffer unit, a video stitching module, an output timing generation module and a windowing processing module. The cross-time domain processing module is used to synchronize image data from the image clock to the FPGA internal logic processing clock; the storage controller is used to control the input frame storage module to write the image data processed by the cross-time domain processing module into the memory; and control the output frame storage module to retrieve the image data stored in the memory; the output buffer unit is used to cache the image data retrieved by the output frame storage module to obtain the first image and the second image to be stitched; the output timing generation module is used to generate a corresponding timing signal according to the resolution parameter of the third image; the windowing processing module is used to generate an effective window signal for the corresponding image according to the resolution parameter of the first image, the resolution parameter of the second image and the timing signal; the video stitching module is used to stitch the first image and the second image according to the effective window signal to form a third image, and output the third image to the display screen. The FPGA-based vehicle-mounted video image stitching method and system provided in this embodiment are mainly used in the field of automobile display to meet the needs of a large number of automobile users for real-time observation of automobile images, thereby providing efficient, convenient, real-time video processing and intuitive preview functions.

[0107] Although preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic inventive concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the invention. Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the invention. Thus, the present invention is intended to include such changes and modifications as fall within the scope of the claims and their equivalents.

Claims

1. An FPGA-based vehicle-mounted video image stitching system, characterized in that: It includes a cross-time domain processing module, an input frame storage module, a storage controller, an output frame storage module, an output buffer unit, a video splicing module, an output timing generation module and a window processing module, wherein: The cross-time domain processing module is used to synchronize the image data from the image clock to the FPGA internal logic processing clock; The storage controller is connected to the input frame storage module and the output frame storage module respectively, and is used to control the input frame storage module to write the image data processed by the cross-time domain processing module into the memory; and control the output frame storage module to retrieve the image data stored in the memory; The output buffer unit is connected to the output frame storage module and is used to buffer the image data retrieved by the output frame storage module to obtain the first image and the second image to be spliced; The output timing generation module is connected to the video splicing module and is used to generate a corresponding timing signal according to the resolution parameter of the third image; wherein the third image is used to splice the first image and the second image; The windowing processing module is connected to the output buffer unit and the output timing generation module, and is used to generate a valid window signal of the corresponding image according to the resolution parameter of the first image, the resolution parameter of the second image and the timing signal; The video splicing module is connected to the window processing module, and is used to splice the first image and the second image according to the effective window signal to form a third image, and output the third image to the display screen.

2. The FPGA-based vehicle-mounted video image stitching system according to claim 1, characterized in that: The output timing generation module includes: The first definition unit is used to define variables V and H; V is the variable for calculating the number of rows in Graph3, and H is the variable for calculating the number of columns in Graph3; The calculation unit is used to clear the value to 0 and re-accumulate if H = (X1 + X2) is recognized; if H = (X1 + X2) is recognized, the V count is increased by 1; if V = Y is recognized, the value is cleared to 0 and re-accumulate; wherein X1 is the width of Graph1, X2 is the width of Graph2; Y is the height of Graph3; Graph1 is the first image, Graph2 is the second image, and Graph3 is the third image; The first generating unit is configured to flip the field synchronization signal, the line synchronization signal and the data valid signal of the output image to generate a timing diagram if it is recognized that the accumulated value of the variables V and H is equal to a preset parameter value.

3. The FPGA-based vehicle-mounted video image stitching system according to claim 2, wherein: The valid window signal includes a first valid window signal and a second valid window signal. In the window processing module, the first valid window signal and the second valid window signal are generated according to the resolution parameter of the first image, the resolution parameter of the second image and the timing signal.

4. The FPGA-based vehicle-mounted video image stitching system according to claim 3, wherein: The window processing module includes: The second definition unit is used to define variables row and col; row is the row count and col is the column count; The second generating unit is used to identify DE=1, and When , DE1 is determined to be valid; where DE is the valid signal of Graph3 data, X1 is the width of Graph1, Y is the height of Graph3, DE1 is the valid signal of Graph1 data, and X1 is the width of Graph1; The third generating unit is used to identify DE=1, and When DE2 is valid, X2 is the width of Graph2, and DE2 is the valid signal of Graph2 data.

5. The FPGA-based vehicle-mounted video image stitching system according to claim 4, characterized in that: The video splicing module includes: The acquisition unit is used to read the data in the output buffer using DE1 and DE2 respectively to obtain data data1 and data2; wherein data1 is the data of Graph1 and data2 is the data of Graph2; The splicing unit is used to synchronize data1 and data2 with the DE signal, and output data1 and data2 in sequence under the premise that DE is valid to complete data splicing; wherein the DE signal is a valid window signal.

6. A vehicle-mounted video image stitching method based on FPGA, applied to the vehicle-mounted video image stitching system based on FPGA according to any one of claims 1 to 5, characterized in that: The FPGA-based vehicle-mounted video image stitching method comprises the following steps: The cross-time domain processing module synchronizes the image data from the image clock to the FPGA internal logic processing clock; The storage controller controls the input frame storage module to write the image data processed by the cross-time domain processing module into the memory; and controls the output frame storage module to retrieve the image data stored in the memory; The output buffer unit buffers the image data retrieved by the frame storage module to obtain the first image and the second image to be spliced; The output timing generation module is connected to the video splicing module and generates a corresponding timing signal according to the resolution parameter of the third image; The window processing module generates effective window signals of corresponding images according to the resolution parameters of the first image, the resolution parameters of the second image and the timing signal; The video splicing module splices the first image and the second image according to the effective window signal to form a third image, and outputs the third image to a display screen.

7. The FPGA-based vehicle-mounted video image stitching method according to claim 6, wherein: The step of the windowing processing module generating effective window signals of corresponding images respectively according to the resolution parameter of the first image, the resolution parameter of the second image and the timing signal comprises: Define variables V and H; If H = (X1 + X2) is recognized, the value is cleared to 0 and the value is accumulated again. If H = (X1 + X2) is recognized, the value V is counted up by 1. If V = Y is recognized, the value is cleared to 0 and the value is accumulated again. If it is recognized that the accumulated value of the variables V and H is equal to the preset parameter value, the field synchronization signal, the line synchronization signal and the data valid signal of the output image are flipped to generate a timing diagram.

8. The FPGA-based vehicle-mounted video image stitching method according to claim 7, wherein: In the step in which the windowing processing module generates effective window signals for corresponding images according to the resolution parameters of the first image, the resolution parameters of the second image and the timing signal, a first effective window signal and a second effective window signal are generated according to the resolution parameters of the first image, the resolution parameters of the second image and the timing signal.

9. The FPGA-based vehicle-mounted video image stitching method according to claim 8, wherein: The step of the windowing processing module generating effective window signals of corresponding images respectively according to the resolution parameter of the first image, the resolution parameter of the second image and the timing signal comprises: Define variables row and col; If DE=1 is recognized, and When , DE1 is determined to be valid; If DE=1 is recognized, and , DE2 is determined to be valid.

10. The FPGA-based vehicle-mounted video image stitching method according to claim 9, wherein: The video splicing module splices the first image and the second image according to the valid window signal to form a third image, and outputs the third image to the display screen, comprising: Use DE1 and DE2 to read the data in the output buffer to obtain data data1 and data2; Data1 and data2 are processed synchronously with the DE signal. Under the premise that DE is valid, data1 and data2 are output in sequence to complete data splicing.

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