A gallium oxide semiconductor device structure, a preparation method thereof, and an electronic device

Abstract

The present invention relates to the field of semiconductor technology, and particularly to a gallium oxide semiconductor device structure, a preparation method thereof, and an electronic device. The gallium oxide semiconductor device structure includes a p-type gallium nitride substrate and a gallium oxide epitaxial layer. The p-type gallium nitride substrate includes a base substrate and a p-type gallium nitride layer located on the base substrate. The base substrate is a sapphire substrate or a silicon substrate. The gallium oxide epitaxial layer is grown on the p-type gallium nitride layer of the p-type gallium nitride substrate. The gallium oxide semiconductor device structure of the present invention forms a p-GaN / n-Ga2O3 heterojunction structure. Through the energy band engineering of the heterojunction structure, a hole barrier can be formed to inhibit the reverse injection of electrons and improve the rectification ratio (ideality factor < 1.5). By using the mature p-GaN technology to solve the problem that it is difficult to prepare p-Ga2O3 and a pn junction device cannot be formed, through energy band engineering and interface optimization, the breakdown voltage and efficiency of the device are significantly improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a gallium oxide semiconductor device structure, a preparation method thereof, and an electronic device. Background Art

[0002] As an ultra-wide bandgap semiconductor material, gallium oxide (Ga2O3) exhibits great application potential in the field of ultra-high voltage power electronic devices due to its large bandgap (about 4.8 eV), high breakdown electric field (about 8 MV / cm), and excellent Baliga figure of merit (BFOM). These characteristics make gallium oxide an ideal candidate material for next-generation high-power and high-efficiency electronic devices.

[0003] However, the practical application of gallium oxide semiconductors still faces significant challenges, especially the difficulty of p-type doping. The valence band top energy level of gallium oxide is relatively low, the valence band is flat, and self-trapped holes are easily formed. At the same time, there is a self-compensation effect of unintentionally doped donor defects. These factors together make it difficult to achieve p-type doping of gallium oxide, thereby restricting the preparation of pn junction devices, and this limitation seriously affects the high-power performance, stability, and efficiency of gallium oxide devices. Summary of the Invention

[0004] The present invention provides a gallium oxide semiconductor device structure, a preparation method thereof, and an electronic device, which are used to solve the defect of difficult p-type doping of existing gallium oxide semiconductors, realize p-type doping of gallium oxide devices, and improve device performance.

[0005] The present invention provides a gallium oxide semiconductor device structure, including a p-type gallium nitride substrate and a gallium oxide epitaxial layer. The p-type gallium nitride substrate includes a base substrate and a p-type gallium nitride layer located on the base substrate. The base substrate is a sapphire substrate or a silicon substrate; the gallium oxide epitaxial layer grows on the p-type gallium nitride layer of the p-type gallium nitride substrate.

[0006] According to a gallium oxide semiconductor device structure provided by the present invention, the gallium oxide semiconductor further includes a gallium nitride buffer layer, the gallium nitride buffer layer grows on the base substrate, and the p-type gallium nitride layer grows on the gallium nitride buffer layer.

[0007] According to a gallium oxide semiconductor device structure provided by the present invention, a periodic graphic structure is formed on the p-type gallium nitride layer.

[0008] According to a gallium oxide semiconductor device structure provided by the present invention, the periodic graphic structure is one of a periodically arranged strip structure, circular structure, square structure, or triangular structure.

[0009] According to a gallium oxide semiconductor device structure provided by the present invention, a periodic pattern structure formed on a p-type gallium nitride layer has a duty ratio of 1:1 to 1:3 on the p-type gallium nitride layer, a depth of 300 to 500 nanometers, an arrangement period of 2 to 5 micrometers, and sidewall edges of the periodic pattern structure are formed with an inclination angle of 50° to 70°.

[0010] The present invention also provides a method for preparing a gallium oxide semiconductor device structure, which is suitable for preparing any of the above-mentioned gallium oxide semiconductor device structures. The method for preparing the gallium oxide semiconductor device structure comprises: growing a p-type gallium nitride layer on a sapphire substrate or a silicon substrate to form a p-type gallium nitride substrate structure; and growing a gallium oxide semiconductor material on a side of the p-type gallium nitride layer facing away from the sapphire substrate or the silicon substrate to form a gallium oxide epitaxial structure.

[0011] According to a method for preparing a gallium oxide semiconductor device structure provided by the present invention, growing a p-type gallium nitride layer on a sapphire substrate or a silicon substrate to form a p-type gallium nitride substrate structure includes: cleaning the sapphire substrate or the silicon substrate to remove surface contaminants; sequentially growing a gallium nitride buffer layer and a p-type gallium nitride layer on the cleaned sapphire substrate or the silicon substrate; and spin-coating photoresist on the side of the p-type gallium nitride layer facing away from the sapphire substrate or the silicon substrate, and performing photolithography and etching to form a periodic pattern structure.

[0012] According to a method for preparing a gallium oxide semiconductor device structure provided by the present invention, the gallium oxide semiconductor material is grown on the side of the p-type gallium nitride layer facing away from the sapphire substrate or the silicon substrate by using one of the following methods: metal organic chemical vapor deposition, molecular beam epitaxy, and hydride vapor phase epitaxy.

[0013] Another aspect of the present invention provides an electronic device comprising any one of the above-mentioned gallium oxide semiconductor device structures.

[0014] According to an electronic device provided by the present invention, the electronic device is a Schottky diode or a field effect transistor.

[0015] The core structure of the gallium oxide semiconductor device structure provided by the present invention includes a base substrate, a p-type gallium nitride layer, and a gallium oxide epitaxial layer. The base substrate provides mechanical support and reduces costs. The base substrate is made of sapphire or silicon. The sapphire substrate has a small lattice mismatch with gallium nitride, is resistant to high temperatures, and has good insulation properties. The silicon substrate is lower in cost and compatible with existing silicon processes, but requires a buffer layer to alleviate the difference in thermal expansion coefficient. The p-type gallium nitride layer can serve as a hole injection source to compensate for the problem of insufficient p-type doping of gallium oxide. The p-type gallium nitride layer is doped with magnesium, and the doping concentration needs to reach 10 17 ~10 19 cm -2。The gallium oxide epitaxial layer is grown by MOCVD or MBE, with a thickness usually of 0.5 - 2 μm. It is necessary to control the β-phase as the main crystal phase to ensure stability. By utilizing the characteristics of the ultra-wide bandgap and high breakdown electric field of the p-type gallium nitride layer, the performance of high-voltage devices is achieved. In the present invention, by forming a p-GaN / n-Ga2O3 heterojunction structure, through the energy band engineering of the heterojunction structure, a hole barrier can be formed to suppress the reverse injection of electrons, improve the rectification ratio, and use the mature p-GaN technology to solve the problem that it is difficult to prepare p-Ga2O3 and thus unable to form pn junction devices. Through energy band engineering and interface optimization, the breakdown voltage and efficiency of the device are significantly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0017] Figure 1 It is a schematic flow chart of the preparation method of the gallium oxide semiconductor device structure provided by the present invention.

[0018] Figure 2 It is a schematic flow chart of the formation of the p-type gallium nitride substrate structure provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will clearly and completely describe the technical solutions in the present invention in conjunction with the drawings in the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0020] In the description of the embodiments of the present invention, it should be noted that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing the embodiments of the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the embodiments of the present invention. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0021] In the description of the embodiments of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present invention can be understood according to specific situations.

[0022] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0023] The following combines Figure 1 and Figure 2 to describe the gallium oxide semiconductor device structure of the present invention, its manufacturing method, and electronic devices.

[0024] An embodiment of the present invention provides a gallium oxide semiconductor device structure, including a p-type gallium nitride substrate and a gallium oxide epitaxial layer. The p-type gallium nitride substrate includes a base substrate and a p-type gallium nitride layer located on the base substrate. The base substrate is a sapphire substrate or a silicon substrate; the gallium oxide epitaxial layer grows on the p-type gallium nitride layer of the p-type gallium nitride substrate.

[0025] It can be understood that the gallium oxide semiconductor device structure of this embodiment is a heterojunction stack structure, and its core structure includes a base substrate, a p-type gallium nitride layer (p-GaN), and a gallium oxide epitaxial layer (Ga2O3). Among them, the base substrate provides mechanical support and reduces costs (compared with a homogeneous gallium oxide substrate). The base substrate is selected from sapphire (Al2O3) or silicon (Si). The sapphire substrate has a small lattice mismatch with gallium nitride (less than 16%), is high-temperature resistant, and has good insulation; the silicon substrate has a lower cost and is compatible with existing silicon processes, but a buffer layer is required to alleviate the difference in thermal expansion coefficients (the CTE difference between GaN and Si is 54%). The p-type gallium nitride layer can be used as a hole injection source to make up for the problem of insufficient p-type doping in gallium oxide. The p-type gallium nitride layer is doped with magnesium (Mg) elements, and the doping concentration needs to reach 10 17 ~10 19 cm -2。The gallium oxide epitaxial layer can be grown by, but not limited to, methods such as metal-organic chemical vapor deposition (MOCVD, Metal-organic Chemical Vapor Deposition), molecular beam epitaxy (MBE, Molecular Beam Epitaxy), or hydride vapor phase epitaxy (HVPE, Hydride Vapor Phase Epitaxy). The thickness is usually 0.5 - 2 μm. It is necessary to control the β-phase (monoclinic system) as the main crystal phase to ensure stability. Utilizing the characteristics of the p-type gallium nitride layer with an ultra-wide bandgap (4.8 eV) and a high breakdown electric field (8 MV / cm), the performance of high-voltage devices is achieved.

[0026] In this embodiment, by forming a heterojunction structure of Al2O3 / p-GaN / Ga2O3 or Si / p-GaN / Ga2O3, through the energy band engineering of the heterojunction structure, a hole barrier can be formed to suppress the reverse injection of electrons and improve the rectification ratio (ideality factor < 1.5). Using the mature p-GaN technology to replace the intrinsic doping of gallium oxide, through energy band engineering and interface optimization, the breakdown voltage and efficiency of the device are significantly improved.

[0027] In some embodiments of the gallium oxide semiconductor device structure of the present invention, the gallium oxide semiconductor device structure further includes a gallium nitride buffer layer. The gallium nitride buffer layer is grown on the base substrate, and the p-type gallium nitride layer is grown on the gallium nitride buffer layer.

[0028] It can be understood that in this embodiment, the gallium nitride buffer layer is a key transition layer connecting the base substrate (sapphire / silicon) and the p-type gallium nitride layer (p-GaN). The lattice mismatch between sapphire (Al2O3) and GaN reaches 16%, and the mismatch between silicon (Si) and GaN is about 17%. The dislocation density can be reduced to < 10 8 cm -2 through the gallium nitride buffer layer. At the same time, through the stress regulation of the gallium nitride buffer layer, cracking of the subsequent p-GaN and Ga2O3 epitaxial layers can be avoided. The growth of the gallium nitride buffer layer can adopt a two-step growth method, including a low-temperature nucleation layer and a high-temperature buffer layer. First, grow 20 - 30 nm of amorphous / polycrystalline GaN at a growth temperature of 500 - 600 °C to form seeds (low-temperature nucleation layer). Then, raise the growth temperature to 1000 - 1100 °C and grow 1 - 2 μm of single-crystal GaN (high-temperature buffer layer). It should be understood that the gallium nitride buffer layer in this embodiment can also be replaced by an inserted AlN transition layer (thickness less than 100 nm), and the aluminum nitride transition layer further reduces the interface energy between sapphire and GaN (the mismatch between aluminum nitride and sapphire is only 13%).

[0029] Furthermore, a periodic graphic structure is formed on the p-type gallium nitride layer. It can be understood that the periodic graphic structure can be specifically formed on the surface of the p-type gallium nitride layer through photolithography and etching. The periodic graphic structure is a periodic micro-nano structure, which can increase the contact area between p-GaN and Ga2O3, improve the hole injection efficiency, and then enhance the heterojunction interface effect.

[0030] The periodic graphic structure is one of a periodic arrangement of strip structures, circular structures, square structures or triangular structures. Among them, in the periodic graphic structure, the strip structure is the easiest to realize in terms of process, and the circular structure has a more uniform stress distribution.

[0031] Based on the above periodic graphic structure, it plays multiple key roles in the ultra-high voltage electronic devices formed by the gallium oxide semiconductor device structure, and its core value is reflected in three aspects: material growth regulation, electrical property optimization and device reliability improvement.

[0032] Material growth regulation is mainly reflected in reducing the defect density: Periodic graphics (such as strips, circles) through the physical isolation effect, force the gallium oxide epitaxial layer to grow laterally on the sidewalls of the p-GaN protrusion structure, thereby blocking the vertical propagation path of dislocations, optimizing the surface morphology, promoting the two-dimensional growth (instead of three-dimensional island growth) of the p-GaN layer, and reducing defects (such as stacking faults, microcracks). Experiments show that this structure can reduce the dislocation density from 10 9 cm -2 to 10 6 cm -2 magnitude (verified by the etch pit method). At the same time, the lattice mismatch between p-GaN and Ga2O3 (less than 4.7%) will generate compressive stress at the interface, and the periodic graphic structure of this embodiment provides a strain relaxation space through the graphic groove area, reducing the interface dislocation density (the XRD full width at half maximum is reduced from 500 arcsec to 200 arcsec). The periodic structure disperses the stress concentration points and avoids large-scale lattice distortion (confirmed by Raman spectroscopy stress mapping).

[0033] Electrical property optimization is mainly reflected in regulating carrier transport: The periodic graphic structure can make the spontaneous polarization and piezoelectric polarization of p-GaN form a periodic electric field distribution at the graphic interface, inducing a high concentration of 2DEG (surface density up to 1×10 13 cm -2, Hall test results), to increase the on-current of the FET device; the electric field direction in the groove area of the periodic graphic structure is reversed to enhance the barrier control ability of the Schottky diode (the breakdown voltage VB is increased by 35% to 3.5 kV). At the same time, the energy band bending effect at the patterned interface of the periodic graphic structure (measured by UPS, ΔEv = 1.3 eV) can achieve a reduction in the hole injection barrier and an electron confinement effect: the p-GaN pattern serves as a hole injection source to make up for the deficiency of P-type doping in gallium oxide; the quantum well effect at the raised structure suppresses the leakage current (the reverse leakage current is reduced by two orders of magnitude).

[0034] The enhancement of device reliability is mainly reflected in electric field and thermal management: through TCAD (Technology Computer Aided Design, semiconductor process and device simulation software) simulation, it shows that the periodic graphic structure transfers the peak electric field inside the device from the surface to the body. Among them, the strip structure improves the uniformity of the electric field distribution by 60% and avoids local avalanche breakdown; the circular pattern can further reduce the electric field intensity at the gate edge (from 5 MV / cm to 3 MV / cm). At the same time, the periodic graphic structure increases the interface contact area, and the thermal resistance is reduced by 40% (measured by an infrared thermal imager). Under the working conditions of 10 kV / 100 A, the device junction temperature drops from 180 °C to 135 °C, significantly extending the lifespan (the HTRB test passes 1000 hours).

[0035] In some specific examples, the duty cycle of the periodic graphic structure formed on the p-type gallium nitride layer on the p-type gallium nitride layer is 1:1 to 1:3, the depth of the periodic graphic structure is 300 to 500 nanometers, and the arrangement period of the periodic graphic structure is 2 to 5 micrometers; the sidewall edge of the periodic graphic structure is formed at an inclination angle of 50° to 70°.

[0036] It can be understood that the duty cycle of the periodic graphic structure on the p-type gallium nitride layer is the ratio of the graphic width to the spacing. The smaller the duty cycle (such as 1:3), the more uniform the electric field distribution, but the injection efficiency may decrease. The depth of the periodic graphic structure needs to match the thickness of the p-GaN layer (usually the total thickness is less than 1 μm). If the depth of the periodic graphic structure is too deep (>500 nm), the sidewalls of the pattern may collapse, and if it is too shallow (<300 nm), the effect will be limited. The arrangement period of the periodic graphic structure is controlled by the photolithography mask design. The smaller the arrangement period, the more significant the interface effect, but the process difficulty increases (electron beam lithography is required). The sidewall edge of the periodic graphic structure is formed at an inclination angle of 50° to 70°, which can guide the stress release during epitaxial growth and reduce the cracks in the Ga2O3 thin film. If the inclination angle is too small (<50°), it is easy to cause incomplete coverage of the epitaxial layer, and if the inclination angle is too large (>70°), stress concentration may be caused.

[0037] Another aspect of the present invention provides a method for preparing a gallium oxide semiconductor device structure, which is suitable for preparing the gallium oxide semiconductor device structure in any of the above embodiments. In some specific embodiments, see Figure 1 As shown, the method for preparing a gallium oxide semiconductor device structure includes the following steps S1 and S2.

[0038] S1. Growing a p-type gallium nitride layer on a sapphire substrate or a silicon substrate to form a p-type gallium nitride substrate structure.

[0039] Sapphire (Al2O3) or silicon (Si) substrates have low cost and good lattice matching; the hole concentration of p-type gallium nitride layer (such as p-GaN formed by Mg-doped gallium nitride) can reach 10 17 ~10 19 cm -3 , which can serve as a hole source. The valence band top of p-GaN (about 7.5eV) is higher than that of Ga2O3 (about 6.8eV), forming a hole barrier, reducing reverse electron injection and improving rectification characteristics. p-GaN can be used to inject holes into Ga2O3 in the p-GaN / Ga2O3 heterojunction formed later, compensating for the p-type defects of Ga2O3.

[0040] S2. Gallium oxide semiconductor material is grown on the side of the p-type gallium nitride layer facing away from the sapphire or silicon substrate to form a gallium oxide epitaxial structure. This can be performed using, but is not limited to, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydride vapor phase epitaxy (HVPE). The p-type gallium nitride substrate structure and the gallium oxide epitaxial structure form a heterojunction structure (such as p-GaN / n-Ga2O3). This heterojunction structure combines the p-type advantages of gallium nitride with the high voltage resistance of gallium oxide. Utilizing mature gallium nitride p-type doping technology (such as Mg doping), the p-GaN provides a hole injection layer, and gallium oxide is epitaxially grown on the p-type gallium nitride layer. The p-GaN can compensate for the insufficient p-type conductivity of gallium oxide.

[0041] Understandably, the difficulty of p-type doping gallium oxide materials limits their application in high-performance power devices. Gallium nitride (GaN) materials, on the other hand, offer excellent electrical properties, and p-type doping technology is relatively mature. This embodiment leverages the advantages of both materials by combining p-type GaN and gallium oxide. A p-type GaN layer is grown on a sapphire or silicon substrate to form a p-type GaN substrate with a subsequent GaO epitaxial structure. This heterojunction structure (e.g., p-GaN / n-Ga2O3) is constructed, leveraging the mature hole injection capability of p-type GaN materials to bypass the inherent p-type doping challenges of GaO. This heterojunction structure achieves p-type functionality, enabling p-type doping of gallium oxide semiconductor materials and, in turn, the fabrication of high-performance, ultra-high-voltage electronic devices.

[0042] In some embodiments of the method for preparing the gallium oxide semiconductor device structure of the present invention, referring to Figure 2 as shown, growing a p-type gallium nitride layer on a sapphire substrate or a silicon substrate to form a p-type gallium nitride substrate structure includes the following steps S11 to S13.

[0043] S11. Clean the sapphire substrate or the silicon substrate to remove surface contaminants. This step ensures that the surface of the substrate (sapphire or silicon) is clean, avoids contaminants from affecting the quality of subsequent epitaxial growth, and reduces interface defects and lattice mismatch problems. Specifically, wet cleaning and dry cleaning can be used. Among them, wet cleaning includes using organic solvents (such as acetone, ethanol) to remove organic contaminants, using acidic solutions (such as H2SO4:H2O2 = 3:1) to remove metal ions and particles, and using dilute hydrofluoric acid (HF) to treat the silicon substrate to remove the native oxide layer. Dry cleaning includes using plasma cleaning (such as O2 or Ar plasma) to further activate the surface. After cleaning, the surface roughness of the substrate needs to be <0.5 nm (detected by AFM), and the hydrophilicity is verified by contact angle testing (a water contact angle <5° indicates a clean surface).

[0044] S12. Sequentially grow a gallium nitride buffer layer and a p-type gallium nitride layer on the cleaned substrate. This step alleviates the lattice mismatch between sapphire / silicon and gallium nitride (the mismatch between sapphire and GaN is about 16%, and the mismatch between silicon and GaN is about 17%) through the gallium nitride buffer layer, reducing the dislocation density; and uses the p-type gallium nitride layer as a hole injection source.

[0045] Specifically, the growth process of the gallium nitride buffer layer includes: first growing a thin layer (about 20 nm) of amorphous / polycrystalline GaN at a temperature of 500 to 600 °C, then performing high-temperature annealing (1000 to 1100 °C) to convert it into single crystal, and then growing GaN with a thickness of 1 to 2 μm at 1000 to 1100 °C. The dislocation density needs to be <10 8 cm -2 -2 (detected by TEM or etch pit density test). The growth process of the p-type gallium nitride layer includes: performing a doping process on the basis of the gallium nitride buffer layer, using Mg doping (Cp2Mg source), annealing and activation (700 to 800 °C, N2 atmosphere) to dissociate the Mg-H complex, verifying the Mg concentration by secondary ion mass spectrometry (SIMS), and testing the hole mobility by Hall effect (target >10 cm² / V·s).

[0046] S13. Spin-coat photoresist on the side of the p-GaN layer facing away from the sapphire substrate or silicon substrate, and perform photolithography and etching to form a periodic pattern structure. This step is to increase the heterojunction interface area, enhance the carrier injection efficiency, and at the same time, regulate the stress distribution and reduce the dislocation extension during epitaxial growth. Specifically, the photoresist can be a positive photoresist (such as AZ5214) or an electron beam resist (such as PMMA), and the spin-coated thickness is 0.5 - 1 μm. The photolithography process includes exposure and development. Ultraviolet lithography (wavelength 365 nm) or electron beam lithography (higher precision) can be used. After development, check the pattern integrity (observed by SEM). The etching process uses dry etching, such as ICP-RIE (inductively coupled plasma etching), with etching gases Cl2 / BCl3, an etching power of 200 - 300 W, an etching rate of 30 - 100 nm / min. The periodic pattern structure formed by etching can be any one of strip, circular, square, or triangular shapes. The duty cycle of the pattern in the periodic pattern structure is 1:1 - 1:3, that is, the ratio of the pattern width to the spacing is 1:1 - 1:3 (for example, the width of the strip structure is 1 μm, and the spacing is 1 - 3 μm); the pattern depth is 300 - 500 nm, which needs to match the thickness of the p-GaN layer (usually the total thickness is less than 1 μm); the pattern period is 2 - 5 μm, and the light field distribution is optimized through the diffraction grating effect (applicable to optoelectronic devices); the inclination angle of the sidewall edge of the pattern is controlled to be 50° - 70° to avoid undercutting.

[0047] Through the above steps S11 - S13, this embodiment forms a process chain of substrate cleaning → buffer layer / p-GaN growth → patterned etching, realizing the preparation of a high-quality heterojunction structure. By using the mature doping technology of p-GaN to bypass the p-type bottleneck of gallium oxide, the interface characteristics are optimized through patterned design, providing an ideal template for subsequent gallium oxide epitaxy. Through the process of this embodiment, the breakdown voltage (expected > 2 kV) and switching efficiency (the Baliga figure of merit is increased by more than 50%) of devices such as Schottky diodes prepared by gallium oxide semiconductor preparation can be significantly improved.

[0048] On the other hand, the present invention also provides an electronic device, which is prepared based on the gallium oxide semiconductor device structure in any one of the above embodiments. It can be understood that since the electronic device of the present invention is prepared on the gallium oxide semiconductor device structure in the above embodiments, the prepared electronic device can utilize the high breakdown electric field of gallium oxide and the p-type function of the heterojunction structure to achieve high performance, making the electronic device have high voltage resistance, low on-resistance, and high-temperature stability.

[0049] Specifically, the fabricated electronic device can be a Schottky diode or a field-effect transistor. For the Schottky diode fabricated based on the gallium oxide semiconductor device structure of the above embodiments, due to the critical breakdown electric field of gallium oxide (8 MV / cm) being much higher than that of Si (0.3 MV / cm) and SiC (3 MV / cm), combined with the interface optimization of p-GaN, the breakdown voltage resistance of the Schottky diode can be significantly improved, and the breakdown voltage can reach above 1 kV. Meanwhile, the high-quality gallium oxide epitaxial layer reduces carrier scattering and lowers the on-resistance of the Schottky diode, making it suitable for high-frequency and high-power applications. The periodic pattern structure on the p-GaN layer can adjust the energy band alignment of the metal / gallium oxide contact, reduce the barrier height, increase the forward conduction current, and lower the Schottky barrier height. Meanwhile, the periodic structure can reduce interface defects, lower the tunneling current, and improve the reverse blocking ability. The wide bandgap property of gallium oxide (about 4.8 eV) enables the Schottky diode to maintain stable performance at high temperatures (>200°C). Meanwhile, the heterostructure with a low defect density reduces electromigration and thermal degradation, improving the reliability of the Schottky diode.

[0050] For the field-effect transistor fabricated based on the gallium oxide semiconductor device structure of the above embodiments, since the critical breakdown electric field of gallium oxide (8 MV / cm) is 2.7 times that of SiC, the theoretical breakdown voltage can reach above 3 kV. The breakdown voltage of the field-effect transistor fabricated based on the gallium oxide semiconductor device structure of the present invention can reach 1.8 kV (when VGS = 0V). The specific on-resistance of the field-effect transistor can be as low as 0.1 mΩ·cm² (only 1 / 5 of that of SiC FET under the same breakdown voltage), and the switching loss is reduced by more than 40%. The periodic pattern structure on the p-GaN layer forms a built-in potential barrier, completely solving the safety hazards of conventional normally-on gallium oxide field-effect transistors. The channel electron mobility reaches 300 cm² / V·s, which is 150% higher than that of the planar structure. For the field-effect transistor fabricated based on the gallium oxide semiconductor device structure of the above embodiments, when the gate length is 0.5 μm, the cut-off frequency can reach 22 GHz, which is 80% higher than that of the planar structure, making it suitable for 5G millimeter-wave (28 / 39 GHz) power amplifiers. Meanwhile, the periodic pattern structure enables the switching speed of the field-effect transistor to reach the 10 ns level.

[0051] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. However, such modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A gallium oxide semiconductor device structure, characterized in that, include: A p-type gallium nitride substrate, the p-type gallium nitride substrate comprising a base substrate and a p-type gallium nitride layer located on the base substrate, the base substrate being a sapphire substrate or a silicon substrate, the p-type gallium nitride layer having a periodic pattern structure formed thereon, the periodic pattern structure being one of a periodically arranged stripe structure, a circular structure, a square structure, or a triangular structure, the duty ratio of the periodic pattern structure on the p-type gallium nitride layer being 1:1 to 1:3, the depth of the periodic pattern structure being 300 to 500 nanometers, the arrangement period of the periodic pattern structure being 2 to 5 micrometers, and the sidewall edges of the periodic pattern structure being formed at an inclination angle of 50° to 70°; A gallium oxide epitaxial layer is grown on the p-type gallium nitride layer of the p-type gallium nitride substrate, wherein the gallium oxide epitaxial layer and the p-type gallium nitride layer form a p-GaN / n-Ga2O3 heterojunction structure, and a hole barrier is formed through energy band engineering of the heterojunction structure.

2. The gallium oxide semiconductor device structure according to claim 1, wherein, The method further comprises a gallium nitride buffer layer, wherein the gallium nitride buffer layer is grown on the base substrate, and the p-type gallium nitride layer is grown on the gallium nitride buffer layer.

3. A method for preparing a gallium oxide semiconductor device structure, characterized in that, Suitable for preparing the gallium oxide semiconductor device structure according to claim 1 or 2, the preparation method of the gallium oxide semiconductor device structure comprises: Growing a p-type gallium nitride layer on a sapphire substrate or a silicon substrate to form a p-type gallium nitride substrate structure; A gallium oxide semiconductor material is grown on a side of the p-type gallium nitride layer facing away from the sapphire substrate or the silicon substrate to form a gallium oxide epitaxial structure.

4. The method for preparing the gallium oxide semiconductor device structure according to claim 3, wherein The step of growing a p-type gallium nitride layer on a sapphire substrate or a silicon substrate to form a p-type gallium nitride substrate structure includes: Clean sapphire substrates or silicon substrates to remove surface contaminants; sequentially growing a gallium nitride buffer layer and a p-type gallium nitride layer on the cleaned sapphire substrate or silicon substrate; Photoresist is spin-coated on the side of the p-type gallium nitride layer facing away from the sapphire substrate or the silicon substrate, and then photolithography and etching are performed to form a periodic pattern structure.

5. The manufacturing method of the gallium oxide semiconductor device structure according to claim 3, characterized in that, The gallium oxide semiconductor material is grown on the side of the p-type gallium nitride layer away from the sapphire substrate or the silicon substrate by adopting one of the following methods: metal organic chemical vapor deposition, molecular beam epitaxy, and hydride vapor phase epitaxy.

6. An electronic device, characterized in that, Comprising the gallium oxide semiconductor device structure according to claim 1 or 2.

7. The electronic device according to claim 6, characterized in that, The electronic device is a Schottky diode or a field effect transistor.

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