Wafer manufacturing system scheduling method, device and equipment

Abstract

The invention provides a scheduling method, device and equipment of a wafer manufacturing system. The method comprises the following steps: constructing a time Petri net model by adopting a Petri net model according to a wafer processing route and constraint conditions; the constraint condition is the time delay added on the transition or library; an incidence matrix of the time Petri net model is calculated, and the incidence matrix is used for calculation to obtain the number of times of emission; the emission times are emission times corresponding to each transition from the initial identifier to the target identifier under the time Petri network model; operating the time Petri net model by using the launching times in combination with the shortest process time priority strategy, and processing the deadlock problem by adopting multi-step rollback in the operation process of the time Petri net model to obtain a scheduling result of the wafer manufacturing system; wherein the shortest process time priority strategy only reserves a preset number of enabling transitions under each identifier. And the generation efficiency of the scheduling result is improved on the basis of stable operation of the wafer manufacturing system.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor wafer manufacturing system scheduling optimization, and in particular to a scheduling method, device and equipment for a wafer manufacturing system. Background Art

[0002] As the core of modern science and technology, semiconductor manufacturing supports a wide range of applications from home appliances to cutting-edge communication technologies. Especially in the wafer manufacturing process, efficient scheduling strategies are essential to ensure high yield, high quality and on-time delivery. As the market demand for high-performance, low-power semiconductor devices continues to grow, how to optimize the scheduling process of wafer manufacturing systems has become a common challenge for academia and industry. In actual production, wafer manufacturing systems are highly complex due to the involvement of multiple processes, equipment, materials and strict time constraints. In particular, the reasonable allocation of robotic arm resources is directly related to the efficiency and cost of the entire manufacturing process.

[0003] In order to address the above challenges, researchers have developed a variety of algorithms to optimize the scheduling process of wafer manufacturing systems. For example, the A* algorithm uses a heuristic search method to find the optimal path from the initial state to the target state; the ant colony algorithm simulates the foraging behavior of ants and uses the pheromone mechanism to explore the solution space. These algorithms have improved scheduling efficiency to a certain extent and reduced unnecessary waiting time and resource waste. In addition, the method of combining Petri net model for modeling and analysis has also been widely used to describe the characteristics of deadlock, concurrency and conflict in manufacturing systems, thus providing an effective solution framework.

[0004] However, although the above methods have achieved certain results, they still face some significant technical limitations. For example, when the ant colony algorithm is applied on a large scale, it needs to iteratively update the pheromone values ​​of all edges, which leads to huge computational complexity and long running time. In addition, improper selection of the initial pheromone distribution may seriously affect the quality of the final solution. On the other hand, although the A* algorithm can find the shortest path, due to its wide search space, it often consumes a lot of memory and time when processing complex tasks, which limits its practicality. These problems not only increase production costs, but may also lead to slower response speeds and fail to meet the requirements of real-time scheduling, thereby affecting the efficiency and competitiveness of the entire wafer manufacturing system. Therefore, there is an urgent need for a new method to overcome these challenges and improve scheduling performance. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a scheduling method, device and equipment for a wafer manufacturing system.

[0006] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0007] In a first aspect, the present invention provides a scheduling method for a wafer manufacturing system, comprising:

[0008] According to the wafer processing route and constraints, the Petri net model is used to construct the time Petri net model; the constraints are the delays added to the transitions or places;

[0009] Calculate the association matrix of the time Petri net model, and use the association matrix to calculate the number of emissions; the number of emissions is the number of emissions corresponding to each transition from the initial identifier to the target identifier under the time Petri net model;

[0010] The time Petri net model is run by combining the number of emission times with the shortest process time priority strategy. Multi-step backoff is used to deal with the deadlock problem during the running of the time Petri net model to obtain the scheduling result of the wafer manufacturing system. Among them, the shortest process time priority strategy only retains a preset number of enabled transitions under each identifier.

[0011] Optionally, according to the wafer processing route and constraints, a time Petri net model is constructed using a Petri net model, including:

[0012] Determine the locations and transitions existing in the wafer processing system according to the wafer processing route;

[0013] Determine constraints according to wafer processing steps;

[0014] Places, transitions and constraints are added to the Petri net model to construct a time Petri net model.

[0015] Optionally, the association matrix of the time Petri net model is calculated, and the number of transmissions is calculated using the association matrix, including:

[0016] Compute the incidence matrix of the temporal Petri net model;

[0017] Construct the state equation corresponding to the time Petri net model according to the association matrix;

[0018] The number of firings is calculated based on the state equation.

[0019] Alternatively, the state equation is expressed as:

[0020]

[0021] Among them, M 2 Indicates the target identifier, M 1 represents the initial identification, [N] represents the association matrix, Indicates that from the initial mark M 1 Transition to target ID M 2 The corresponding number of launches.

[0022] Optionally, the time Petri net model is run by using the launch number combined with the shortest process time priority strategy, and a multi-step backoff is used to handle the deadlock problem during the operation of the time Petri net model to obtain the scheduling results of the wafer manufacturing system, including:

[0023] S201, using the emission times and process time function, calculate the process time of the corresponding identifier when all enabling transitions are emitted under the current identifier in the time Petri net model; the current identifier is generated after the previous identifier is emitted through the enabling transition t; the current identifier is represented by all the libraries in the time Petri net model;

[0024] S202, sorting the enabling transitions in ascending order according to the process time to obtain the first enabling transition;

[0025] S203, taking the first N sorted enabling transitions to form a second enabling transition, and selecting the second enabling transition with the shortest process time for emission;

[0026] S204, determining whether the transmission flag corresponding to the second enabling transition transmission is a dead flag;

[0027] S205. If not, the transmitting identifier is used as the current identifier and returns to S201, and S201-S204 are repeatedly executed until the current identifier is the target identifier, and finally the scheduling result is obtained.

[0028] Optionally, the scheduling result includes: processing sequence, completion time, extension identification number and program running time;

[0029] The processing sequence is all the processing sequences corresponding to the initial identification and the target identification.

[0030] Optionally, after S204, the scheduling method of the wafer manufacturing system further includes:

[0031] S301: If the transmitting identifier corresponding to the second enabling transition when transmitting is a dead identifier, then back off the transmitting identifier by a preset step length, and use the identifier after backing off as the current identifier;

[0032] S302, take the current enabling transition in the second enabling transition corresponding to the current identifier and transmit it, and return to step S204; the current enabling transition is the enabling transition with the shortest process time among the second enabling transitions except the second enabling transitions that have been transmitted in all previous iterations.

[0033] Optionally, the process time function is expressed as:

[0034] T(M)=lt(M)+∑ p ω(M,p);

[0035] Among them, T(M) represents the process time under the current mark M, lt(M) represents the global time under the current mark M, and ω(M,p) represents the processing time required for the p library under the current mark M.

[0036] In a second aspect, the present invention provides a scheduling device for a wafer manufacturing system, the scheduling device for the wafer manufacturing system comprising: a model building unit, a calculation unit, and a model running unit;

[0037] The model building unit is used to: build a time Petri net model using a Petri net model according to the wafer processing route and constraint conditions; the constraint condition is the delay added to the transition or library;

[0038] The calculation unit is used to: calculate the association matrix of the time Petri net model, and use the association matrix to calculate the emission number; the emission number is the emission number corresponding to each transition from the initial identifier to the target identifier under the time Petri net model;

[0039] The model running unit is used to: use the number of launches combined with the shortest process time priority strategy to run the time Petri net model, and use multi-step backoff to handle deadlock problems during the running of the time Petri net model to obtain the scheduling result of the wafer manufacturing system; among them, the shortest process time priority strategy only retains a preset number of enabled changes under each identifier.

[0040] In a third aspect, the present invention provides a scheduling device for a wafer manufacturing system, comprising: a processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor. When the scheduling device of the wafer manufacturing system is running, the processor and the storage medium communicate through the bus, and the processor executes the machine-readable instructions to perform the steps of the scheduling method of the wafer manufacturing system as described in the first aspect above.

[0041] The present invention provides a scheduling method, device and equipment for a wafer manufacturing system. A scheduling method for a wafer manufacturing system includes: constructing a time Petri net model using a Petri net model according to a wafer processing route and a constraint condition; the constraint condition is a delay added to a transition or a place; calculating the association matrix of the time Petri net model, and obtaining the number of launches using the association matrix; the number of launches is the number of launches corresponding to each transition from an initial identifier to a target identifier under the time Petri net model; running the time Petri net model using the number of launches combined with a shortest process time priority strategy, and using multi-step backoff to handle deadlock problems during the operation of the time Petri net model to obtain a scheduling result for the wafer manufacturing system; wherein the shortest process time priority strategy only retains a preset number of enabling transitions under each identifier. In the present invention, on the one hand, the shortest process time priority strategy is used to quickly obtain the scheduling result, thereby improving the search efficiency; on the other hand, the shortest process time priority strategy adopted by the present invention only retains a fixed number of enabled transitions under each identifier. Based on this setting, not only the scale of the search tree can be limited, but also the exponential increase in the number of nodes with the increase in the search level can be avoided. Combined with multi-step backoff, the number of backoffs in the search process can be reduced, thereby reducing the number of extended identifiers; and using the above strategy, the transition emission sequence from the initial identifier to the target identifier can be quickly obtained, and the robot resources are reasonably utilized, that is, the efficiency of generating scheduling results is improved on the basis of stable operation of the wafer manufacturing system.

[0042] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A schematic flow chart of a scheduling method for a wafer manufacturing system provided by an embodiment of the present invention;

[0044] Figure 2 The following is a logic diagram showing the execution process of the shortest process time priority strategy by way of example;

[0045] Figure 3 A schematic diagram of the structure of a scheduling device for a wafer manufacturing system provided by an embodiment of the present invention;

[0046] Figure 4 A schematic diagram of the structure of a scheduling device for a wafer manufacturing system provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0047] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0048] In order to improve the efficiency of generating scheduling results on the basis of stable operation of a wafer manufacturing system, an embodiment of the present invention provides a scheduling method for a wafer manufacturing system. Figure 1 A schematic diagram of a scheduling method for a wafer manufacturing system provided by an embodiment of the present invention. Figure 1 As shown, including:

[0049] S101. According to the wafer processing route and constraint conditions, a time Petri net model is constructed using a Petri net model.

[0050] It should be noted that, in the present invention, the constraint condition is the delay added to the transition or place.

[0051] The wafer processing route refers to the entire processing flow of wafers from raw materials to final products in semiconductor production. This process includes multiple steps, such as cleaning, lithography, etching, ion implantation, deposition, etc., each of which is a processing or transformation of the wafer. In wafer processing, constraints may involve multiple aspects, such as equipment utilization, material processing time, temperature control, process sequence, etc. In this specific scenario, constraints are defined as delays added to transitions (i.e., processing steps) or places (i.e., states or resources of processing steps). Delay represents the time required to complete a step or state transition.

[0052] Petri net is a mathematical model used to describe dynamic behaviors such as concurrency, synchronization, and conflict in discrete event systems. It consists of two types). Places and transitions are connected by directed edges, indicating that resources or states in places can trigger transitions, and the occurrence of transitions may change resources or states in places.

[0053] The time Petri net is an extension of the Petri net, which adds time constraints on transitions or places. These time constraints can be fixed delays (such as the constraints mentioned in this embodiment) or dynamic delays that depend on other events or conditions. Therefore, the time Petri net can more accurately describe dynamic systems that need to consider time factors.

[0054] Optionally, S101 may specifically include:

[0055] Determine the locations and transitions existing in the wafer processing system according to the wafer processing route;

[0056] Determine constraints according to wafer processing steps;

[0057] Places, transitions and constraints are added to the Petri net model to construct a time Petri net model.

[0058] Exemplarily, the execution process of constructing a temporal Petri net model may include:

[0059] 1. Define places: Define each important state or resource in the wafer processing route as a place. For example, the wafer state before cleaning, the wafer state after cleaning, etc.

[0060] 2. Define transitions: Define each step in the wafer processing route as a transition, for example, cleaning step, photolithography step, etc.

[0061] 3. Add directed edges: According to the actual process of wafer processing, the places and transitions are connected through directed edges. This represents the state transition and the execution order of the steps.

[0062] 4. Add delays: Add delays to transitions or places based on constraints. These delays represent the time required to complete each step or state transition.

[0063] S102, calculating the association matrix of the time Petri net model, and using the association matrix to calculate the number of transmissions.

[0064] Optionally, S102 may specifically include:

[0065] Compute the incidence matrix of the temporal Petri net model;

[0066] Construct the state equation corresponding to the time Petri net model according to the association matrix;

[0067] The number of firings is calculated based on the state equation.

[0068] The state equation is an algebraic description of the change of the identifier in the time Petri net model. In other words, it is a concise expression of the relationship between the identifier and the number of occurrences of the transition in the transition sequence. Any reachable state satisfies the state equation, but not vice versa.

[0069] Alternatively, the state equation is expressed as:

[0070]

[0071] Among them, M 2 Indicates the target identifier, M 1 represents the initial identification, [N] represents the association matrix, Indicates that from the initial mark M 1 Transition to target ID M 2 The corresponding number of launches.

[0072] [N] is an integer matrix of |P|×|T|, P represents the set of places, T represents the set of transitions, and [N](p,t)=W(t,p)-W(p,t). [N](p,t) represents the elements of the association matrix [N] under p places and t transitions, W(t,p) represents the weight of the t-th transition in T to place p, and W(p,t) represents the weight of place p to transition t. W(t,p) and W(p,t) can be directly determined based on the time Petri net model. Place p represents the p-th place in P.

[0073] The number of emissions is the number of emissions corresponding to each transition from the initial identifier to the target identifier in the time Petri net model.

[0074] S103, using the launch number combined with the shortest process time priority strategy to run the time Petri net model, and using multi-step backoff to handle deadlock problems during the operation of the time Petri net model to obtain a scheduling result for the wafer manufacturing system.

[0075] Among them, the shortest process time priority strategy only retains a preset number of enabling transitions under each identifier. The core idea of ​​the shortest process time priority strategy is to calculate the process time of the corresponding identifier after all enabling transitions under the current identifier are emitted through the defined process time function, sort these enabling transitions according to the process time, and only retain a fixed number of enabling transitions, add the retained enabling transitions to the queue, and select the transition with the shortest process time in the queue for emission. When encountering a dead identifier and falling back later, only the remaining transitions can be selected from the queue for emission.

[0076] It should be noted that multi-step backoff means that when a dead mark is encountered during the algorithm search process, a backoff process needs to be performed. The multi-step backoff proposed in the present invention can directly backoff two, three or even more steps when a dead mark is encountered, and the mark backoff is used as the current mark, and the remaining transitions are selected and launched according to the shortest process time priority strategy until the path from the initial mark to the target mark, i.e., the transition sequence, is found. The size of the backoff step can be flexibly set according to the actual scenario.

[0077] Optionally, S103 may specifically include:

[0078] S201, using the emission times and process time function, calculate the process time of the corresponding identifier when all enabling transitions are emitted under the current identifier in the time Petri net model; the current identifier is generated after the previous identifier is emitted through the enabling transition t; the current identifier is represented by all the libraries in the time Petri net model;

[0079] S202, sorting the enabling transitions in ascending order according to the process time to obtain the first enabling transition;

[0080] S203, taking the first N sorted enabling transitions to form a second enabling transition, and selecting the second enabling transition with the shortest process time for emission;

[0081] S204, determining whether the transmission flag corresponding to the second enabling transition transmission is a dead flag;

[0082] S205. If not, the transmitting identifier is used as the current identifier and returns to S201, and S201-S204 are repeatedly executed until the current identifier is the target identifier, and finally the scheduling result is obtained.

[0083] Optionally, the process time function is expressed as:

[0084] T(M)=lt(M)+∑ p ω(M,p);

[0085] Among them, T(M) represents the process time under the current mark M, lt(M) represents the global time under the current mark M, and ω(M,p) represents the processing time required for the p library under the current mark M. The global time is the system time when running to the current mark M.

[0086] Optionally, the scheduling result includes: processing sequence, completion time, extension identification number and program running time;

[0087] The processing sequence is all the processing sequences corresponding to the initial identification and the target identification.

[0088] Optionally, after S204, the scheduling method of the wafer manufacturing system further includes:

[0089] S301: If the transmitting identifier corresponding to the second enabling transition when transmitting is a dead identifier, then back off the transmitting identifier by a preset step length, and use the identifier after backing off as the current identifier;

[0090] S302, take the current enabling transition in the second enabling transition corresponding to the current identifier and transmit it, and return to step S204; the current enabling transition is the enabling transition with the shortest process time among the second enabling transitions except the second enabling transitions that have been transmitted in all previous iterations.

[0091] In addition, in order to clearly illustrate the execution process of the shortest process time priority strategy provided by the embodiment of the present invention, Figure 2 The following is an example of a logic diagram of the execution process of the shortest process time priority strategy. Figure 2 As shown, two enabling transitions are reserved under each identifier. 0 is the initial identifier, M 7 、M 8 M is the death mark. 11is the target identifier. According to the above process time function, the process time f of the corresponding identifier is calculated after the transition is launched. The number of times each transition is launched is calculated according to the state equation and recorded in the arr array. Under each identifier, a node is expanded according to the f value (with the smallest f), and two nodes (with the smallest f) are retained for dead identifier fallback processing. 0 At the beginning, there are two enabling transitions. According to the above description, two nodes M 1 and M 2 All are retained, f 1 <f 2 , and the corresponding arr[t 1 -1]>0, so emit t 1 , we get M 1 ,arr[t 1 -1]-1;M 1 There are three enabling transitions below, f 3 <f 4 <f 5 , and the values ​​in the arr array corresponding to these three transitions are all greater than 0, so t is emitted 3 , we get M 3 ,arr[t 3 -1]-1, keep M 3 and M 4 Similarly, due to f 7 <f 8 <f 9 <f 6 , M 3 Keep M 7 and M 8 , determine the corresponding value of arr[t 7 -1]<0, arr[t 8 -1]>0, although t 7 The corresponding f value is small, and only the transition t can be emitted. 8 Get M 8 is a dead mark, arr[t 8 -1]-1, at this time, you need to roll back. Take the example of rolling back two steps and directly roll back to M 1 , and arr[t 8 -1]+1,arr[t 3 -1]+1, traverse M 1 The remaining nodes that are retained and not emitted are sent down until the target node is reached.

[0092] The complete optimization logic of the shortest process time priority strategy is as follows:

[0093] 1. Determine whether the current mark is the target mark. If so, output the calculated extended mark number and the processing sequence from the initial mark to the target mark, completion time, extended mark number, and program running time;

[0094] 2. If it is not the target identifier, the process time of generating the corresponding identifier after each transition in the enabling transition is calculated according to the process time function, and the transition emission sequence, that is, the number of transition emissions, is calculated according to the state equation and the correlation matrix, and stored in the arr array;

[0095] 3. Arrange all transitions in the transition sequence in ascending order according to process time, select the transition t with the lowest ranking in the sorted transition sequence, and check arr[t-1] corresponding to the transition;

[0096] 4. Determine whether arr[t-1] is greater than 0. If not, select the lowest-ranked transition among the remaining transitions that have not been selected, check the value of the corresponding transition in the arr array, and then determine whether the value is greater than 0;

[0097] 5. If yes, take the transition as the transmitting transition and expand it to get the new identifier, and arr[t-1]-1;

[0098] 6. Determine whether the current identifier is a dead identifier. If not, return to step 1;

[0099] 7. If yes, perform the operation according to the number of steps back. For example, if two steps are backed up, the current mark is returned to the previous mark, and the arr[t-1]+1 operation is performed on the corresponding transition.

[0100] 8. Take the previous identifier as the new current identifier, and determine whether the traversal of the sorted transition sequence corresponding to the current identifier is complete. If all traversals are completed, return false and return to the previous loop;

[0101] 9. If the traversal is not completed, select the lowest-ranked transition in the remaining transitions that have not been selected in the sequence of transitions corresponding to the current identifier, and the transition corresponds to a value in the arr array that is greater than 0. Use the lowest-ranked transition as the emitted transition and expand it to obtain the new current identifier, and return to step 1.

[0102] A scheduling method for a wafer manufacturing system provided by an embodiment of the present invention can, on the one hand, quickly obtain scheduling results by utilizing the shortest process time priority strategy, thereby improving search efficiency; on the other hand, the shortest process time priority strategy adopted only retains a fixed number of enabled transitions under each identifier, and based on this setting, not only the scale of the search tree can be limited, but also the exponential increase in the number of nodes with the increase in the search level can be avoided, and combined with multi-step backoff, the number of backoffs in the search process can be reduced, thereby reducing the number of extended identifiers; and using the above strategy, the transition emission sequence from the initial identifier to the target identifier can be quickly obtained, and the robot resources are reasonably utilized, that is, the efficiency of generating scheduling results is improved on the basis of stable operation of the wafer manufacturing system.

[0103] The method provided in the embodiment of the present invention can be applied to an electronic device. Specifically, the electronic device can be: a desktop computer, a portable computer, an intelligent mobile terminal, a server, etc., which is not limited in the embodiment of the present invention.

[0104] Based on the same inventive concept, an embodiment of the present invention also provides a scheduling device for a wafer manufacturing system. Figure 3 A schematic diagram of the structure of a scheduling device for a wafer manufacturing system provided by an embodiment of the present invention. Figure 3 As shown, it includes: a model building unit 301, a calculation unit 302 and a model running unit 303;

[0105] The model building unit 301 is used to: build a time Petri net model using a Petri net model according to the wafer processing route and constraint conditions; the constraint condition is the delay added to the transition or library;

[0106] The calculation unit 302 is used to calculate the association matrix of the time Petri net model, and use the association matrix to calculate the emission number; the emission number is the emission number corresponding to each transition from the initial identifier to the target identifier under the time Petri net model;

[0107] The model operation unit 303 is used to: use the number of launches combined with the shortest process time priority strategy to run the time Petri net model, and use multi-step backoff to handle deadlock problems during the operation of the time Petri net model to obtain the scheduling result of the wafer manufacturing system; wherein, the shortest process time priority strategy only retains a preset number of enabled changes under each identifier.

[0108] Figure 4A schematic diagram of the structure of a scheduling device for a wafer manufacturing system provided by an embodiment of the present invention includes: a processor 410, a storage medium 420 and a bus 430, wherein the storage medium 420 stores machine-readable instructions executable by the processor 410, and when the scheduling device for the wafer manufacturing system is running, the processor 410 communicates with the storage medium 420 via the bus 430, and the processor 410 executes the machine-readable instructions to execute the steps of the above method embodiment. The specific implementation method and technical effect are similar and will not be repeated here.

[0109] The storage medium may include a random access memory (RAM) or a non-volatile memory (NVM), such as at least one disk storage. Optionally, the storage medium may also be at least one storage device located away from the aforementioned processor.

[0110] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0111] It should be noted that the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention.

[0112] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0113] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other changes of the above disclosed embodiments by viewing the drawings and the disclosed content. In the description of the present invention, the term "comprising" does not exclude other components or steps, "one" or "an" does not exclude multiple situations, and the meaning of "multiple" is two or more, unless otherwise clearly and specifically limited. In addition, certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0114] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A scheduling method for a wafer manufacturing system, characterized in that: include: According to the wafer processing route and constraints, the Petri net model is used to construct the time Petri net model; The constraint condition is a delay added to a transition or a place; Calculating the association matrix of the time Petri net model, and using the association matrix to calculate the number of emissions; the number of emissions is the number of emissions corresponding to each transition from the initial identifier to the target identifier under the time Petri net model; The time Petri net model is run by utilizing the number of transmissions in combination with the shortest process time priority strategy, and a multi-step backoff is used to handle the deadlock problem during the running of the time Petri net model to obtain the scheduling result of the wafer manufacturing system; wherein the shortest process time priority strategy only retains a preset number of enabling transitions under each identifier.

2. The wafer manufacturing system scheduling method according to claim 1, characterized in that: The Petri net model is used to construct a time Petri net model according to the wafer processing route and constraint conditions, including: Determine the locations and transitions existing in the wafer processing system according to the wafer processing route; Determining the constraint conditions according to the wafer processing procedure; The places, the transitions and the constraints are added to the Petri net model to construct the time Petri net model.

3. The wafer manufacturing system scheduling method according to claim 1, characterized in that: The step of calculating the association matrix of the time Petri net model and obtaining the number of transmissions by using the association matrix comprises: Calculating the association matrix of the temporal Petri net model; Constructing a state equation corresponding to the time Petri net model according to the association matrix; The number of transmissions is calculated based on the state equation.

4. The scheduling method for a wafer manufacturing system according to claim 3, characterized in that: The state equation is expressed as: Wherein, M2 represents the target identifier, M1 represents the initial identifier, [N] represents the association matrix, Indicates the number of transmissions corresponding to the transition from the initial identifier M1 to the target identifier M2.

5. The wafer manufacturing system scheduling method according to claim 3, characterized in that: The method of running the time Petri net model by using the number of launches combined with the shortest process time priority strategy, and using multi-step backoff to handle deadlock problems during the running of the time Petri net model to obtain the scheduling result of the wafer manufacturing system includes: S201, using the emission times and process time function, calculate the process time of the corresponding identifier when all enabling transitions are emitted under the current identifier in the time Petri net model; the current identifier is generated after the previous identifier is emitted through the enabling transition t; the current identifier is represented by all the libraries in the time Petri net model; S202, sorting the enabling transitions in ascending order according to process time to obtain a first enabling transition; S203, taking the first N enabling transitions in the order to form a second enabling transition, and selecting the second enabling transition with the shortest process time for emission; S204, determining whether a transmission flag corresponding to the second enabling transition transmission is a dead flag; S205. If not, take the transmitting identifier as the current identifier and return to S201, and repeat S201-S204 until the current identifier is the target identifier, and finally obtain the scheduling result.

6. The scheduling method for a wafer manufacturing system according to claim 5, characterized in that: The scheduling results include: processing sequence, completion time, extension identification number and program running time; The processing sequence is all processing sequences corresponding to the initial identification and the target identification.

7. The wafer manufacturing system scheduling method according to claim 5, characterized in that: After S204, the scheduling method of the wafer manufacturing system further includes: S301: If the transmitting identifier corresponding to the transmitting of the second enabling transition is a dead identifier, then regress a preset step length on the transmitting identifier, and use the identifier after regressing as the current identifier; S302, taking the current enabling transition in the second enabling transition corresponding to the current identifier and transmitting it, and returning to step S204; the current enabling transition is the enabling transition with the shortest process time among the second enabling transitions except the second enabling transitions transmitted in all previous iterations.

8. The scheduling method for a wafer manufacturing system according to claim 5, characterized in that: The process time function is expressed as: T(M)=lt(M)+∑ p ω(M,p); Among them, T(M) represents the process time under the current mark M, lt(M) represents the global time under the current mark M, and ω(M,p) represents the processing time required for the p library under the current mark M.

9. A scheduling device for a wafer manufacturing system, characterized in that: The scheduling device of the wafer manufacturing system includes: a model building unit, a calculation unit and a model running unit; The model building unit is used to: build a time Petri net model using a Petri net model according to the wafer processing route and constraint conditions; the constraint conditions are delays added to transitions or places; The calculation unit is used to calculate the association matrix of the time Petri net model, and use the association matrix to calculate the number of emission; the number of emission is the number of emission corresponding to each transition from the initial identifier to the target identifier under the time Petri net model; The model running unit is used to: use the number of transmissions combined with the shortest process time priority strategy to run the time Petri net model, and use multi-step backoff to handle deadlock problems during the running of the time Petri net model to obtain the scheduling result of the wafer manufacturing system; wherein the shortest process time priority strategy only retains a preset number of enabled transitions under each identifier.

10. A scheduling device for a wafer manufacturing system, characterized in that: include: A processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, and when the scheduling device of the wafer manufacturing system is running, the processor communicates with the storage medium through the bus, and the processor executes the machine-readable instructions to perform the steps of the scheduling method of the wafer manufacturing system as described in any one of claims 1-8.

Images