Artificial synapse transistor based on multilayer ITZO thin film and preparation method and application thereof

Abstract

The invention belongs to the technical field of electronic devices, and particularly relates to an artificial synapse transistor based on multiple layers of ITZO thin films and a preparation method and application thereof. The invention discloses an artificial synapse transistor based on a multilayer ITZO film. The artificial synapse transistor structurally comprises a substrate, an active layer, a source-drain electrode layer, a passivation layer and a gate dielectric layer which are stacked in sequence. Wherein the active layer is composed of multiple layers of ITZO thin films, and the thickness of the active layer is regulated to be 28-36 nm, so that the surface defects of the thin films are greatly reduced, and the interface quality of the active layer of the transistor is remarkably optimized. Not only is the mobility of the device greatly improved, but also the operation stability and the synaptic plasticity of the device are remarkably enhanced. Benefited from the ingenious combination of the materials, the synaptic transistor shows excellent electrical properties, opens up a new application prospect for a plurality of fields such as bionic sensing devices, neuromorphic memories and brain-like computing chips, and shows huge potential and value.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic devices. More specifically, it relates to an artificial synaptic transistor based on a multi-layer ITZO thin film, its preparation method and application. Background Art

[0002] In the process of exploring efficient and stable neuromorphic simulation devices, researchers have been continuously committed to developing new materials and structures to optimize the overall performance of the devices. Among them, artificial synaptic devices with a transistor structure are particularly remarkable because they can simulate the functions and behaviors of neural synapses. These devices provide a solid hardware foundation for the field of neuromorphic computing by mimicking the signal reception, integration, and transmission mechanisms of neural synapses.

[0003] However, although certain progress has been made in the technology of artificial synaptic devices, many problems still need to be solved. Currently, researchers mainly focus on optimizing the thickness of the gate dielectric layer in order to improve the electrical performance and stability of the devices. The research by Zhang (Zhang X, Cho SW. Solution Process-Based Thickness Engineering of InZnO Semiconductors for Oxide Thin-Film Transistors with High Performance and Stability. Micromachines (Basel). 2024 Jan 27;15(2):193. doi: 10.3390 / mi15020193. PMID: 38398922; PMCID: PMC10890482.) et al. shows that the channel thickness has a significant impact on the mobility and conductivity. Specifically, in thinner semiconductor thin films, the interaction between free carriers and the interface and surface is enhanced, which may lead to a decrease in the device performance and stability; while too thick a film increases the difficulty of controlling the number of free electrons in the channel region through the gate voltage. Therefore, they achieved nanoscale thickness control of the oxide semiconductor thin film through a fine repetitive coating and annealing process. However, this single-dimensional optimization strategy has limitations because it ignores that the quality change of the gate dielectric layer is also crucial for the device performance. Defects, impurities, or microstructural variations in the gate dielectric layer may cause electrical performance fluctuations, thereby affecting the stability and reliability of the device. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to solve the defects and deficiencies in the prior art that the synaptic transistor ignores quality maintenance when optimizing the thickness of the active layer, and to provide an artificial synaptic transistor based on a multi-layer ITZO thin film.

[0005] Another object of the present invention is to provide a method for fabricating the above artificial synaptic transistor based on a multi-layer ITZO thin film.

[0006] Another object of the present invention is to provide the application of the above artificial synaptic transistor based on a multi-layer ITZO thin film in fabricating bionic sensing devices, neuromorphic memories or brain-inspired computing chips.

[0007] The above objects of the present invention are achieved by the following technical solutions:

[0008] The present invention protects an artificial synaptic transistor based on a multi-layer ITZO thin film, which is characterized by comprising a substrate, an active layer, a source-drain electrode layer, a passivation layer and a gate dielectric layer stacked in sequence;

[0009] Wherein, the active layer is composed of a multi-layer ITZO thin film;

[0010] The thickness of the active layer is 28-36 nm.

[0011] The artificial synaptic transistor based on a multi-layer ITZO thin film of the present invention has a structure including a substrate, an active layer, a source-drain electrode layer, a passivation layer and a gate dielectric layer stacked in sequence. The substrate serves as the core support structure, which bears the active layer, electrodes, passivation layer and gate dielectric layer, ensuring the stability and reliability of the entire device; by precisely controlling and coating the ITZO thin film in batches, the total thickness is 28-36 nm, which is more conducive to fully exerting the performance potential of each layer of ITZO thin film. Compared with coating to the same total thickness at one time, this method shows significant advantages. Spin-coating to the same thickness at one time is extremely challenging technically because the precise control of the thin film thickness in the spin-coating process highly depends on the fine adjustment of the rotation speed and solution concentration. In a laboratory environment, it is often difficult to stably reach this thickness at one time, which not only increases the complexity of the experiment but also may require multiple repetitions of the experiment due to improper parameter control, thus increasing the working cost. In contrast, the batch coating strategy not only reduces the difficulty of regulating the number of free electrons in the channel region through the gate voltage but also significantly optimizes the interface quality of the transistor, greatly reducing surface defects, thereby improving the mobility of the device and enhancing its operating stability and synaptic plasticity; the synergistic effect of the source-drain electrodes enables precise signal transmission. Through the ingenious combination of the above materials, the synaptic transistor exhibits excellent electrical properties.

[0012] Specifically, in the artificial synaptic transistor based on a multi-layer ITZO thin film of the present application, the passivation layer not only covers the region between the source electrode and the drain electrode in the source-drain electrode layer, but also extends to cover the upper surfaces of the source electrode and the drain electrode respectively, while the gate dielectric layer is covered on the passivation layer. This design not only significantly enhances the isolation and protection effect of the device, effectively suppressing the current collapse effect caused by surface states or interface states, but also improves the voltage withstand capacity of the device by optimizing the electric field distribution. In addition, the combination of the gate dielectric layer and the passivation layer further optimizes the control performance of the gate over the active layer, enabling the device to have higher stability and response speed during switching operations.

[0013] Further, the substrate includes any one of silicon dioxide, polyethylene terephthalate, and a glass substrate.

[0014] Preferably, the thickness of the substrate is 280 - 320 nm. The substrate within this range has good mechanical stability and processing feasibility, thus ensuring that it can reliably carry the device without directly affecting the device performance.

[0015] More preferably, the thickness of the substrate is 290 - 310 nm. Within this range, the substrate can maximize the improvement of the above-mentioned performance.

[0016] Preferably, the multi-layer ITZO thin film is a four-layer ITZO thin film.

[0017] Preferably, the thickness of each layer of the ITZO thin film is 7 - 8 nm. Within this thickness range, due to its relatively thin characteristics, the thin film exhibits excellent electron transport performance, and also has significant advantages such as excellent optical transparency and low energy consumption. This design of the thin film thickness not only ensures that the synaptic transistor maintains high performance, but also promotes the improvement of its energy utilization efficiency and more sensitive signal response.

[0018] Further, the multi-layer ITZO thin film is prepared by a spin coating process.

[0019] Even further, the specific preparation method of the multi-layer ITZO thin film includes the following steps:

[0020] Mix indium salt, zinc salt, and stannous salt in a solvent to obtain an ITZO solution, spin coat the obtained ITZO solution evenly on the substrate, and perform annealing treatment at 280 - 320 °C to form a layer of ITZO thin film; repeat the operation several times on this basis to form a multi-layer ITZO thin film.

[0021] Further, the indium salt includes indium nitrate, indium trichloride, indium sulfate, or a hydrate of any of the above indium salts.

[0022] Further, the zinc salt includes zinc nitrate, zinc acetate, zinc sulfate, or a hydrate of any of the above zinc salts.

[0023] Further, the stannous salt includes stannous chloride, stannous sulfate, stannous bromide, or a hydrate of any of the above stannous salts.

[0024] Further, the molar ratio of the indium salt, zinc salt, and stannous salt is 1:(1 - 2):(1 - 2).

[0025] Further, the solvent includes one or more of ethylene glycol monomethyl ether, ethylene glycol monobutyl ether, and ethylene glycol dimethyl ether.

[0026] Preferably, the mixing time is 12 - 36 h.

[0027] Preferably, the total concentration of metal ions in the ITZO solution is 0.08 - 0.12 mol / L.

[0028] Preferably, the rotation speed of spin coating is 1000 - 3000 rpm.

[0029] Preferably, the spin coating time is 20 - 60 s.

[0030] Preferably, the annealing treatment time is 1 - 2 h.

[0031] Further, the source-drain electrode layer includes a source electrode and a drain electrode.

[0032] Further, the source electrode and the drain electrode of the source-drain electrode layer are made of the same material; the source electrode and the drain electrode are silver, copper, or gold.

[0033] Preferably, the source electrode and the drain electrode are silver. The silver electrode has a small contact resistance, so it can significantly improve the overall performance and reliability of the synaptic transistor.

[0034] Preferably, the thickness of the source electrode and the drain electrode is 40 - 80 nm. The source electrode and the drain electrode within this thickness range can firmly adhere to the substrate, thus significantly reducing the risk of detachment.

[0035] More preferably, the thickness of the source electrode and the drain electrode is 50 - 70 nm.

[0036] Further, the passivation layer is a thin film formed of any one of polymethyl methacrylate (PMMA), polystyrene (PS), and polycarbonate (PC). The main function of this passivation layer is to reduce the intrusion of the active layer and the source-drain electrodes by the external environment (such as moisture, oxygen, and pollutants), provide effective protection for the active layer and the electrodes, and thereby enhance the stability and reliability of the device.

[0037] Preferably, the thickness of the passivation layer is 5 - 20 nm. The passivation layer within this thickness range can effectively isolate the adverse effects of the external environment on the device performance, improve the interface characteristics, and significantly reduce the leakage current, thereby enhancing the overall performance and stability of the device.

[0038] More preferably, the thickness of the passivation layer is 8 - 15 nm.

[0039] Furthermore, the gate dielectric layer is an ionic gel film.

[0040] Even further, the ionic gel film includes any one of polyethylene oxide - sodium (PEO - Na + ) ionic gel film, polyethylene oxide - potassium (PEO - K + ) ionic gel film, and polyethylene oxide - lithium (PEO - Li + ) ionic gel film.

[0041] Preferably, the thickness of the gate dielectric layer is 4 - 15 μm. The gate dielectric layer within this thickness range can effectively improve the ion migration efficiency, shorten the ion migration path, and thus significantly accelerate the device response speed. In addition, it can also reduce the driving voltage and energy consumption of the device, while enhancing the gate's control ability over the channel, thereby achieving better synaptic plasticity.

[0042] More preferably, the thickness of the gate dielectric layer is 5 - 10 μm. The gate dielectric layer within this thickness range can not only maximize the above - mentioned all performances, but also ensure the stability and reliability of the device during long - term operation while achieving high - speed response and low energy consumption of the device, providing an ideal choice for the design of high - performance synaptic transistors.

[0043] The present invention protects the preparation method of the above - mentioned artificial synaptic transistor based on a multi - layer ITZO film, which includes the following steps:

[0044] S1. Prepare a multi - layer ITZO film on a substrate as the active layer;

[0045] S2. Attach a mask plate to the surface of the active layer obtained in step S1, and then evaporate the source electrode and the drain electrode;

[0046] S3. Remove the mask plate in step S2, then evenly apply the passivation layer solution and perform an annealing treatment at 100 - 120 °C to obtain a substrate coated with a passivation layer;

[0047] S4. Prepare a gate dielectric layer solution, evenly apply it on the substrate coated with the passivation layer obtained in step S3 as the gate dielectric layer, and the resulting device is an artificial synaptic transistor based on a multi - layer ITZO film.

[0048] In the preparation method of the artificial synaptic transistor of the present invention, first, by precisely controlling the coating and annealing treatment of the ITZO solution, a high-quality multi-layer ITZO thin film is constructed layer by layer, effectively reducing defects and improving the overall electrical performance; subsequently, the source electrode and the drain electrode are precisely evaporated using a mask template technology to ensure accurate positioning and good contact, further enhancing the conductive stability of the device; then, a passivation layer is coated to provide a flat substrate for the gate dielectric layer and enhance the mechanical strength of the device; finally, the gate dielectric layer is prepared to obtain an artificial synaptic transistor based on the multi-layer ITZO thin film. Thanks to the optimization of the multi-layer ITZO thin film, the passivation effect of the passivation layer, and the excellent performance of the gate dielectric layer, the prepared synaptic transistor exhibits excellent electrical characteristics and fast response speed, is very suitable for large-scale production, and can be widely applied to high-performance and low-power electronic systems, especially in the fields of bionic sensing devices, neuromorphic memories, or brain-like computing chips, providing solid technical support and reliable application routes for the development of these fields.

[0049] Further, in step S1, the use of the substrate includes pretreatment.

[0050] Furthermore, as a preferred method, the pretreatment includes the following steps:

[0051] The substrate is ultrasonically cleaned with water, acetone, and isopropyl alcohol solution in sequence for 30 - 40 min, then dried with nitrogen, and treated with oxygen plasma for 10 - 15 min; the purpose of the oxygen plasma treatment is to hydroxylate the substrate surface and enhance wettability.

[0052] Further, as a preferred method, in step S1, the multi-layer ITZO thin film is a four-layer ITZO thin film.

[0053] Further, in step S2, the evaporation is carried out under the condition of an evaporation rate of.

[0054] Preferably, in step S3, the rotation speed of the coating is 1500 - 2000 rpm.

[0055] Preferably, in step S3, the coating time is 30 - 40 s.

[0056] Further, as a preferred method, in step S3, the preparation method of the passivation layer solution includes the following steps:

[0057] The PMMA powder is fully dissolved in a solvent to prepare a PMMA solution with a concentration of 0.3% - 1%.

[0058] Further, the solvent includes one or more of chlorobenzene, acetone, and methanol.

[0059] Preferably, the dissolution time is 12 to 36 h.

[0060] Further, in step S3, the annealing time is 15 to 20 min.

[0061] Further, as a preferred embodiment, in step S4, the gate dielectric layer solution is a PEO-Na + ionic gel solution.

[0062] Even further, the preparation method of the PEO-Na + ionic gel solution includes the following steps:

[0063] Mix PEO and sodium salt in a solvent to obtain a PEO-Na + ionic gel solution.

[0064] Further, the sodium salt includes one or more of sodium bis(trifluoromethylsulfonyl)imide, sodium hexafluorophosphate, and sodium difluoromethanesulfonimide.

[0065] Even further, the mass ratio of PEO to sodium salt is (8 - 10):1.

[0066] Further, the solvent includes one or more of acetonitrile, methanol, and tetrahydrofuran.

[0067] Preferably, the mixing time is 48 to 50 h.

[0068] Further, as a preferred embodiment, in step S4, the gate dielectric layer solution is a PEO-Li + ionic gel solution.

[0069] Even further, the preparation method of the PEO-Li + ionic gel solution includes the following steps:

[0070] Mix PEO and lithium salt in a solvent to obtain a PEO-Li + ionic gel solution.

[0071] Further, the lithium salt includes one or more of lithium bis(trifluoromethylsulfonyl)imide, lithium hexafluorophosphate, and lithium difluoromethanesulfonimide.

[0072] Even further, the mass ratio of PEO to lithium salt is (8 - 10):1.

[0073] Further, the solvent includes one or more of acetonitrile, methanol, and tetrahydrofuran.

[0074] Preferably, the mixing time is 48 to 50 h.

[0075] Further, as a preferred method, in step S4, the gate dielectric layer solution is a PEO-K + ionic gel solution.

[0076] Furthermore, the preparation method of the PEO-K + ionic gel solution includes the following steps:

[0077] Mix PEO and potassium salt in a solvent to obtain a PEO-K + ionic gel solution.

[0078] Further, the potassium salt includes one or more of potassium bis(trifluoromethylsulfonyl)imide, potassium hexafluorophosphate, and potassium bis(fluorosulfonyl)imide.

[0079] Furthermore, the mass ratio of PEO to potassium salt is (8-10):1.

[0080] Further, the solvent includes one or more of acetonitrile, methanol, and tetrahydrofuran.

[0081] Preferably, the mixing time is 48-50 h.

[0082] Further, as a preferred method, in step S4, the gate dielectric layer solution is uniformly coated by using a pipette to pipette the PEO-Na + ionic gel solution and uniformly dropping it onto the substrate coated with the passivation layer obtained in step S3, and spin-coating for 30-40 s at a rotation speed of 1500-2500 rpm.

[0083] The present invention protects the application of the above artificial synaptic transistor based on a multi-layer ITZO film in the preparation of bionic sensing devices, neuromorphic memories, or brain-like computing chips.

[0084] Compared with the prior art, the present invention has the following beneficial effects:

[0085] The present invention prepares an artificial synaptic transistor based on a multi-layer ITZO film, and its structure includes a substrate, an active layer, a source-drain electrode layer, a passivation layer, and a gate dielectric layer stacked in sequence. Among them, the active layer is composed of multi-layer ITZO films. By controlling its thickness to be 28-36 nm, the surface defects of the film are greatly reduced, and the interface quality of the active layer of the transistor is significantly optimized. It not only greatly improves the mobility of the device, but also significantly enhances its operating stability and synaptic plasticity. Thanks to the ingenious combination of the above materials, the synaptic transistor exhibits excellent electrical properties, opening up new application prospects for multiple fields such as bionic sensing devices, neuromorphic memories, or brain-like computing chips, and showing great potential and value. Description of the Drawings

[0086] Figure 1Schematic diagrams of the artificial synaptic transistors in Example 1(a) and Comparative Examples 1-4(b-e); the schematic diagrams mainly focus on expressing the structural relationships rather than accurately reflecting the actual thickness of each layer.

[0087] Figure 2 Atomic force microscopy (AFM) images of different numbers of ITZO thin film layers in Example 1(d) and Comparative Examples 1-4(a-c, e).

[0088] Figure 3 Graph of the change in postsynaptic current gain of the artificial synaptic transistors in Example 1 and Comparative Examples 1-4 under single-pulse stimulation.

[0089] Figure 4 Excitatory postsynaptic current graphs of the artificial synaptic transistors in Example 1 and Comparative Examples 1-4 under 100-pulse stimulation.

[0090] Figure 5 Excitatory postsynaptic current graphs of the artificial synaptic transistor in Example 1 under pulsed stimulation at different frequencies.

[0091] Figure 6 Excitatory postsynaptic current graphs of the artificial synaptic transistor in Comparative Example 1 under pulsed stimulation at different frequencies.

[0092] Figure 7 Excitatory postsynaptic current graphs of the artificial synaptic transistor in Comparative Example 2 under pulsed stimulation at different frequencies.

[0093] Figure 8 Excitatory postsynaptic current graphs of the artificial synaptic transistor in Comparative Example 3 under pulsed stimulation at different frequencies.

[0094] Figure 9 Excitatory postsynaptic current graphs of the artificial synaptic transistor in Comparative Example 4 under pulsed stimulation at different frequencies. Detailed implementation manners

[0095] The present invention will be further described below in conjunction with the accompanying drawings of the specification and specific embodiments, but the embodiments do not limit the present invention in any form. Unless otherwise specified, the reagents, methods, and equipment used in the present invention are conventional reagents, methods, and equipment in the technical field.

[0096] Unless otherwise specified, the reagents and materials used in the following examples are all commercially available.

[0097] Figure 1 (a) represents Figure 1 Figure (a) in Figure 1 (b) represents Figure 1 Figure (b) in, and so on for the order of the other figures.

[0098] Example 1 An artificial synaptic transistor based on a four-layer ITZO thin film and its preparation method

[0099] 1. An artificial synaptic transistor based on a four-layer ITZO thin film (the structural schematic diagram is as shown in Figure 1 (a)), including a substrate - SiO 2 , an active layer - a four-layer ITZO thin film, a source-drain electrode layer (source electrode - Ag and drain electrode - Ag), a passivation layer - PMMA thin film, and a gate dielectric layer - PEO-Na + ion gel.

[0100] 2. The preparation method of the above artificial synaptic transistor based on a four-layer ITZO thin film includes the following steps:

[0101] S1. Pretreatment of the substrate:

[0102] Put the SiO 2 substrate into deionized water, acetone solution, and isopropanol in sequence, ultrasonically clean for 30 minutes respectively, then dry with nitrogen, and put it into a plasma cleaner for oxygen plasma treatment for 10 minutes to obtain the pretreated SiO 2 substrate, and the thickness of the substrate is 300 nm.

[0103] S2. Preparation of the active layer:

[0104] S2-1. Take indium nitrate, zinc nitrate, and stannous chloride powders as solutes, dissolve them in ethylene glycol monomethyl ether according to a molar ratio of 1:1:1, and control the total metal ion concentration to be 0.1 mol / L. Then place the blended solution on a magnetic stirrer and stir at a speed of 800 rpm at room temperature for 24 hours to obtain an ITZO solution;

[0105] S2-2. Use a pipette to transfer the ITZO solution obtained in step S2-1 and evenly drop it on the pretreated SiO 2 thin film substrate obtained in step S1, spin-coat at a speed of 2000 rpm / s for 40 s, and then place it on a hot plate for annealing at 300 °C for 1.5 h to obtain a substrate covered with a layer of ITZO thin film, and the thickness of a layer of ITZO thin film is 8 nm;

[0106] S2-3. Repeat step S2-2 three times for the substrate covered with a layer of ITZO thin film obtained in step S2-2 to obtain a substrate covered with a four-layer ITZO thin film, and the thickness of the active layer (four-layer ITZO thin film) is 32 nm.

[0107] S3. Evaporation of electrodes:

[0108] Attach the mask plate to the surface of the substrate covered with the active layer prepared in step S2, and then place it in a coating machine. First, Deposit 30 nm at the evaporation rate, and then increase the evaporation rate to Deposit 30 nm, and finally obtain Ag with an evaporation thickness of 60 nm as the source electrode and the drain electrode;

[0109] S4. Preparation of the passivation layer:

[0110] S4-1. Use PMMA powder as the solute and chlorobenzene as the solvent to prepare a PMMA solution with a concentration of 0.5%. Then place the solution on a magnetic stirrer and stir at a speed of 800 rpm at room temperature for 24 h to obtain a uniformly mixed PMMA solution;

[0111] S4-2. Remove the mask plate in step S3, and use a pipette to uniformly drop the PMMA solution obtained in step S4-1 onto the substrate of the evaporated electrode obtained in step S3. Spin-coat for 30 s at a speed of 2000 rpm, and then anneal on a hot plate at 120 °C for 15 min to obtain a substrate covered with a passivation layer, and the thickness of the passivation layer is 10 nm.

[0112] S5. Preparation of the gate dielectric layer:

[0113] Disperse 0.1 g of sodium bis(trifluoromethylsulfonyl)imide powder and 0.8 g of PEO powder in 10 mL of acetonitrile solution, and magnetically stir for 48 h to obtain a PEO-Na + ionic gel solution. Use a pipette to transfer the above PEO-Na + ionic gel solution and uniformly drop it onto the substrate covered with the passivation layer obtained in step S4. Spin-coat for 30 s at a speed of 1700 rpm to obtain a gate dielectric layer with a thickness of 7 μm, and the obtained device is an artificial synaptic transistor based on a four-layer ITZO thin film.

[0114] Example 2 An artificial synaptic transistor based on a four-layer ITZO thin film and a preparation method thereof

[0115] The difference from Example 1 is that in step S2-1 of the preparation method of the artificial synaptic transistor based on a four-layer ITZO thin film, the molar ratio of indium nitrate, zinc nitrate, and stannous chloride powders is changed from 1:1:1 to 1:2:2.

[0116] Other steps and conditions are the same as those in Example 1.

[0117] Example 3 An artificial synaptic transistor based on a four-layer ITZO thin film and a preparation method thereof

[0118] The difference from Example 1 is that in step S5 of the preparation method of the artificial synaptic transistor based on a four-layer ITZO thin film, the mass of PEO is changed from 0.8 g to 1 g, that is, the mass ratio of PEO to the sodium salt is 10:1.

[0119] Other steps and conditions are the same as those in Example 1.

[0120] Comparative Example 1: An artificial synaptic transistor based on a single-layer ITZO film and a preparation method thereof

[0121] The difference from Example 1 is that the steps of S2-2 in step S2-3 of the preparation method of the artificial synaptic transistor based on the four-layer ITZO film are not repeated three times. That is, the active layer is a single-layer ITZO film with a thickness of 8 nm, and the structural schematic diagram is as Figure 1 shown in (b).

[0122] Other steps and conditions are the same as those in Example 1.

[0123] Comparative Example 2: An artificial synaptic transistor based on a double-layer ITZO film and a preparation method thereof

[0124] The difference from Example 1 is that in step S2-3 of the preparation method of the artificial synaptic transistor based on the four-layer ITZO film, the step of repeating S2-2 three times is changed to repeating S2-2 once. That is, the active layer is a double-layer ITZO film with a thickness of 16 nm, and the structural schematic diagram is as Figure 1 shown in (c).

[0125] Other steps and conditions are the same as those in Example 1.

[0126] Comparative Example 3: An artificial synaptic transistor based on a triple-layer ITZO film and a preparation method thereof

[0127] The difference from Example 1 is that in step S2-3 of the preparation method of the artificial synaptic transistor based on the four-layer ITZO film, the step of repeating S2-2 three times is changed to repeating S2-2 twice. That is, the active layer is a triple-layer ITZO film with a thickness of 24 nm, and the structural schematic diagram is as Figure 1 shown in (d).

[0128] Other steps and conditions are the same as those in Example 1.

[0129] Comparative Example 4: An artificial synaptic transistor based on a five-layer ITZO film and a preparation method thereof

[0130] The difference from Example 1 is that in step S2-3 of the preparation method of the artificial synaptic transistor based on the four-layer ITZO film, the step of repeating S2-2 three times is changed to repeating S2-2 four times. That is, the active layer is a five-layer ITZO film with a thickness of 40 nm, and the structural schematic diagram is as Figure 1 shown in (e).

[0131] Other steps and conditions are the same as those in Example 1.

[0132] Experimental Example 1 Atomic Force Microscopy Characterization Based on Multilayer ITZO Thin Films

[0133] 1. Experimental Methods

[0134] The five ITZO films with different numbers of layers prepared in Example 1 and Comparative Examples 1 to 4 were used as test samples, and the Dimension FastScan atomic force microscope was used for AFM characterization analysis. Before the test, the sample was fixed on the sample stage to ensure that the sample position remained stable during the test. During the test, the tapping mode was selected to scan in a non-contact manner, the scanning rate was set to 1Hz, and a 20×20μm area scan was performed on the sample surface to obtain detailed information on the surface morphology of each sample. Subsequently, the collected high-resolution images were analyzed using AFM software to intuitively and clearly display the microstructure and characteristics of the sample surface.

[0135] 2. Experimental results

[0136] The innovation of the present invention is that by precisely controlling the number of layers of the ITZO film, the interface quality of the active layer is significantly optimized. During the spin coating process, the inventors observed that ITZO films with different numbers of layers exhibited completely different surface defect characteristics. Specifically, the raised defects (highlighted areas) and recessed defects (dark areas) in the AFM image directly reflect the high non-uniformity of the film surface, which is not conducive to the electrical performance of the device. After comparing ITZO films with different numbers of layers, the inventors found that: when spin coating a layer of ITZO film ( Figure 2 (a)) and two-layer ITZO film ( Figure 2 (b)), three-layer ITZO film ( Figure 2 (c)) and five-layer ITZO film ( Figure 2 (e)) samples have many bright and dark areas on their surfaces, indicating that there are a large number of surface defects on the surface of these films. These defects not only increase the surface roughness, but also significantly increase the trap density, which seriously restricts the electrical performance of the device. However, when spin-coated onto four-layer ITZO films ( Figure 2 (d)), the situation changes significantly. At this point, the number of bright and dark areas in the film reaches a minimum, and the surface roughness and trap density are reduced to the lowest level. This finding means that the four-layer ITZO film has shown excellent performance in optimizing surface quality, laying a solid foundation and providing strong guarantee for the full play of the device's electrical performance.

[0137] Experimental Example 2 Postsynaptic current gain performance test of artificial synaptic transistor based on multilayer ITZO film under single pulse stimulation

[0138] 1. Experimental Methods

[0139] The artificial synaptic transistors prepared in Example 1 and Comparative Examples 1-4 were used as test samples and tested with a Keithley 4200-SCS semiconductor characterization analyzer. Test procedure: Connect the probe of electrode SUM1 to the source electrode, connect the probe of electrode SUM2 to the drain electrode, and connect the probe of electrode SUM3 to the PEO-Na + ionic gel conductor as the top electrode; then continuously apply a reading voltage of 0.2 V to electrode SUM2, and apply a single synaptic pre-spike with an amplitude of 5 V and a duration of 0.05 s to electrode SUM3, and test the postsynaptic current gain (PSC) graph of the artificial synaptic transistor under a single positive pulse stimulation of 0.05 s.

[0140] 2. Experimental results

[0141] It can be seen from Figure 3 that when the synaptic transistor receives a spike stimulus, a significant postsynaptic current will be generated, and its PSC gain performance is excellent. Specifically, the maximum PSC gain of Example 1 is as high as 0.0257 μA. In contrast, the PSC gains of Comparative Examples 1-4 are 0.0021 μA, 0.0200 μA, 0.0134 μA, and 0.0090 μA, respectively, all lower than that of Example 1. When the stimulus pulse is removed, the PSC gains of the artificial synaptic transistors in both Example 1 and Comparative Examples 1-4 will gradually decline over time and finally return to the initial level. The change in postsynaptic current is one of the important indicators for evaluating the strength of synaptic plasticity. In the facilitatory synaptic plasticity (such as short-term potentiation) concerned in this application, the greater the increase in postsynaptic current, the stronger the synaptic plasticity usually indicates. In the test of Example 1, the artificial synaptic transistor prepared with a four-layer ITZO thin film exhibited significant characteristics of postsynaptic current change, which strongly indicates that this device shows more excellent performance in synaptic plasticity.

[0142] Experimental Example 3 Excitatory Postsynaptic Current Performance Test of Artificial Synaptic Transistor Based on Multilayer ITZO Thin Film under 100 Pulse Stimulations

[0143] 1. Experimental method

[0144] The artificial synaptic transistor based on a four-layer ITZO thin film prepared in Example 1 was used as a test sample and tested with a Keithley 4200-SCS semiconductor characterization analyzer. Test procedure: Connect the probe of electrode SUM1 to Ag as the source electrode, connect the probe of electrode SUM2 to Ag as the drain electrode, and connect the probe of electrode SUM3 to the PEO-Na +The ionic gel conductor is connected as the top electrode; then a reading voltage of 0.2 V is continuously applied to the electrode SUM2, and a signal with a duration of 0.05 s and an amplitude of 5 V is applied to the electrode SUM3 for 100 times as the presynaptic spike. The excitatory postsynaptic current diagram of the artificial synaptic transistor based on the four-layer ITZO film is obtained by testing under 100 consecutive positive pulse stimulations.

[0145] 2. Experimental results

[0146] As Figure 4 shown, when 100 presynaptic spikes with an amplitude of 5 V and a duration of 0.05 s are continuously applied to the source electrode of the artificial synaptic transistor prepared in Example 1, and a reading voltage of 0.2 V is simultaneously applied to the drain electrode, the output excitatory postsynaptic current gain is significantly increased to 65.063 μA, and this gain value is 2531.63 times the amplitude of the current triggered by a single stimulation under the same conditions. In contrast, the postsynaptic current gains of Comparative Examples 1, 2, 3, and 4 are 0.007 μA, 0.7145 μA, 2.651 μA, and 0.047 μA, respectively, which are 3.33 times, 35.73 times, 197.84 times, and 5.22 times the amplitude of the current triggered by a single stimulation. It can be seen that as the number of input presynaptic spikes increases, the response degree of the postsynaptic current of the synaptic transistor based on the four-layer ITZO film in Example 1 also increases significantly. This characteristic not only reveals the high dependence of the device on the number of presynaptic spikes, but also further reflects the enhanced plasticity characteristic.

[0147] Experimental Example 4 Performance test of excitatory postsynaptic current of artificial synaptic transistor based on multi-layer ITZO film under different frequency pulse stimulations

[0148] 1. Experimental method

[0149] The artificial synaptic transistors prepared in Example 1 and Comparative Examples 1-4 are used as test samples and tested with a Keithley 4200-SCS semiconductor characteristic analyzer. Test process: The probe of electrode SUM1 is connected to Ag as the source electrode, the probe of electrode SUM2 is connected to Ag as the drain electrode, and the probe of electrode SUM3 is connected to PEO-Na + ionic gel conductor as the top electrode; then a reading voltage of 0.2 V is continuously applied to SUM2, and a series of pulse sequences with different frequencies are applied to SUM3 as the main presynaptic spikes. Among them, each sequence contains 10 pulse spikes, with an amplitude of 5 V and a single pulse duration of 0.05 s, and the frequencies of the pulse sequences are 0.625 Hz, 1.25 Hz, 2.5 Hz, and 5 Hz respectively. The excitatory postsynaptic current diagrams of the artificial synaptic transistors under positive pulse stimulations with different frequencies are obtained by testing.

[0150] 2. Experimental results

[0151] As can be seen from Figure 5 , in Example 1, when the frequency of the stimulating spike increased from 0.625 Hz to 5 Hz, the postsynaptic current of the artificial synaptic transistor increased significantly from 1.0859 μA to 7.8807 μA, and its regulation range reached 6.7948 μA. This result indicates that the device exhibits excellent current regulation ability and spike frequency-dependent plasticity under different frequency stimulation drives. In contrast, Comparative Example 1 ( Figure 6 ), Comparative Example 2 ( Figure 7 ), Comparative Example 3 ( Figure 8 ) and Comparative Example 4 ( Figure 9 ) have regulation ranges of only 0.01 μA, 0.0066 μA, 0.0593 μA and 0.0061 μA, respectively. Specifically, the regulation range of the postsynaptic current generated by the synaptic transistor in Example 1 is 679.48 times that of Comparative Example 1, 1029.52 times that of Comparative Example 2, 114.58 times that of Comparative Example 3, and 1113.9 times that of Comparative Example 4. Thus, it can be seen that the artificial synaptic transistor prepared based on the four-layer ITZO film in Example 1 exhibits the strongest performance in terms of stimulus frequency-dependent synaptic plasticity.

[0152] In Example 2 and Example 3, by only changing the feeding ratio, it was experimentally verified that the performance of the prepared synaptic transistors is basically the same as that of Example 1, and both are superior to Comparative Examples 1-4, so they will not be elaborated here.

[0153] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principle of the present invention shall be equivalent replacement methods and are all included in the protection scope of the present invention.

Claims

1. An artificial synaptic transistor based on a multilayer ITZO film, characterized in that: It includes a substrate, an active layer, a source-drain electrode layer, a passivation layer and a gate dielectric layer stacked in sequence; Wherein, the active layer is composed of multiple layers of ITZO thin film; The thickness of the active layer is 28-36 nm.

2. The artificial synaptic transistor based on multilayer ITZO thin film according to claim 1, characterized in that: The thickness of each layer of the ITZO film is 7-9 nm.

3. The artificial synaptic transistor based on multilayer ITZO thin film according to claim 1, characterized in that: The multilayer ITZO film is prepared by a spin coating process.

4. The artificial synaptic transistor based on multi-layer ITZO thin film according to claim 1, characterized in that: The specific preparation method of the multilayer ITZO film comprises the following steps: Indium salt, zinc salt and stannous salt are mixed in a solvent to prepare an ITZO solution, the obtained ITZO solution is evenly spin-coated on a substrate, and annealing treatment is performed at 280-320°C to form a layer of ITZO film; on this basis, the operation is repeated several times to form a multi-layer ITZO film.

5. The artificial synaptic transistor based on multi-layer ITZO thin film according to claim 1, characterized in that: The gate dielectric layer is an ion gel film.

6. The artificial synaptic transistor based on multi-layer ITZO thin film according to claim 5, characterized in that: The ion glue film includes any one of a polyethylene oxide-sodium ion glue film, a polyethylene oxide-potassium ion glue film, and a polyethylene oxide-lithium ion glue film.

7. The artificial synaptic transistor based on multi-layer ITZO thin film according to claim 1, characterized in that: The passivation layer includes a film formed of any one of polymethyl methacrylate, polystyrene and polycarbonate.

8. The artificial synaptic transistor based on multi-layer ITZO thin film according to claim 1, characterized in that: The source electrode and the drain electrode of the source-drain electrode layer are made of the same material; the source electrode and the drain electrode are made of silver, copper or gold.

9. The method for preparing an artificial synaptic transistor based on a multilayer ITZO thin film according to any one of claims 1 to 8, characterized in that: The following steps are involved: S1. Preparing a multilayer ITZO film as an active layer on a substrate; S2. Laminating the mask on the surface of the active layer obtained in step S1, and then evaporating the source electrode and the drain electrode; S3. removing the mask in step S2, and then evenly applying the passivation layer solution, and annealing at 100 to 120°C to obtain a substrate coated with a passivation layer; S4. Prepare a gate dielectric layer solution and evenly apply it on the substrate coated with the passivation layer obtained in step S3 as a gate dielectric layer. The resulting device is an artificial synaptic transistor based on a multilayer ITZO film.

10. Use of the artificial synaptic transistor based on the multilayer ITZO film according to any one of claims 1 to 8 in the preparation of bionic sensor devices, neuromorphic memory or brain-like computing chips.

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