Time synchronization method of system-on-chip, system-on-chip and vehicle

Abstract

The invention discloses a time synchronization method of a system-on-chip, the system-on-chip and a vehicle. The time synchronization method of the system on chip comprises the following steps: determining daisy chain data transmission delay between a first hardware domain and a second hardware domain; determining a system clock difference between the second hardware domain and the first hardware domain according to the daisy chain data transmission delay; calibrating the clock of the second daisy chain counter according to the system clock difference, so that the clock of the second daisy chain counter is synchronized with the clock of the first daisy chain counter; determining a timestamp of the second subsystem based on first subsystem time information sent from the first hardware domain; wherein the first subsystem time information comprises a timestamp of the first subsystem and clock information of a first daisy chain counter; updating the system time of the second subsystem according to the timestamp of the second subsystem, so that the system time of the second subsystem is synchronized with the system time of the first subsystem; by adopting the method and the device, the time synchronization between the subsystems of the system on chip can be realized.

Description

Technical Field

[0001] The present application relates to the field of electronic technologies, and particularly relates to a method for time synchronization of a system on chip, a system on chip, and a vehicle. Background Art

[0002] In related technologies, methods for implementing time synchronization between subsystems of a multi-core heterogeneous SoC (System on chip) mainly include: (1) Each subsystem of the multi-core heterogeneous SoC is connected to the same external device, such as a switching device, etc., and the external device uniformly completes time synchronization. (2) Time synchronization is achieved between subsystems of the multi-core heterogeneous SoC through a virtual network interface based on the ptp (Precision Time Protocol) tool.

[0003] However, the above method of uniformly completing time synchronization through an external device requires additional physical connections, increasing costs. And the above method of time synchronization through a pure software method such as a virtual network interface has a large network jitter, thereby resulting in a low accuracy of time synchronization. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide a method for time synchronization of a system on chip, a system on chip, and a vehicle.

[0005] In a first aspect, the embodiments of the present application provide a method for time synchronization of a system on chip. The system on chip includes a first subsystem and at least one second subsystem. Both the first subsystem and the second subsystem include multiple hardware domains. One hardware domain in the first subsystem is a first hardware domain, and one hardware domain in the second subsystem is a second hardware domain. The first hardware domain is a root node, and the second hardware domain is a leaf node. The root node is electrically connected to at least one leaf node in a daisy-chain manner; the first hardware domain includes a first daisy-chain counter, and the second hardware domain includes a second daisy-chain counter. The method includes:

[0006] Synchronize the time of each hardware domain of the first subsystem through the first real-time clock module of the first subsystem;

[0007] Determine the daisy-chain data transmission delay between the first hardware domain and the second hardware domain;

[0008] Determine the system clock difference between the second hardware domain and the first hardware domain according to the daisy-chain data transmission delay;

[0009] Calibrate the clock of the second daisy-chain counter according to the system clock difference so that the clock of the second daisy-chain counter is synchronized with the clock of the first daisy-chain counter;

[0010] Determine the timestamp of the second subsystem based on the first subsystem time information sent from the first hardware domain; wherein, the first subsystem time information includes the timestamp of the first subsystem and the clock information of the first daisy chain counter;

[0011] Update the system time of the second subsystem according to the timestamp of the second subsystem, so that the system time of the second subsystem is synchronized with the system time of the first subsystem;

[0012] Synchronize the time of each hardware domain of the second subsystem through the second real-time clock module of the second subsystem.

[0013] In a second aspect, an embodiment of the present application provides a system on a chip, which includes a first subsystem and at least one second subsystem. Both the first subsystem and the second subsystem include multiple hardware domains. One hardware domain in the first subsystem is the first hardware domain, and one hardware domain in the second subsystem is the second hardware domain. The first hardware domain is the root node, and the second hardware domain is the leaf node. The root node is electrically connected to at least one leaf node in a daisy chain manner; the first hardware domain includes a first daisy chain counter, and the second hardware domain includes a second daisy chain counter; the first subsystem includes a first real-time clock module, and the second subsystem includes a second real-time clock module;

[0014] The first real-time clock module is configured to synchronize the time of each hardware domain of the first subsystem;

[0015] The second hardware domain is configured to determine the daisy chain data transmission delay between the first hardware domain and the second hardware domain;

[0016] The second hardware domain is configured to determine the system clock difference between the second hardware domain and the first hardware domain according to the daisy chain data transmission delay;

[0017] The second hardware domain is configured to calibrate the clock of the second daisy chain counter according to the system clock difference, so that the clock of the second daisy chain counter is synchronized with the clock of the first daisy chain counter;

[0018] The second hardware domain is configured to determine the timestamp of the second subsystem based on the first subsystem time information sent from the first hardware domain; wherein, the first subsystem time information includes the timestamp of the first subsystem and the clock information of the first daisy chain counter;

[0019] The second hardware domain is configured to update the system time of the second subsystem according to the timestamp of the second subsystem, so that the system time of the second subsystem is synchronized with the system time of the first subsystem;

[0020] The second real-time clock module is configured to synchronize the time of each hardware domain of the second subsystem.

[0021] In a third aspect, an embodiment of the present application provides a vehicle, including the on-chip system provided in the above embodiment.

[0022] In a fourth aspect, an embodiment of the present application provides a computer program product, including a computer program / instructions, and when the computer program / instructions are executed by a processor, the steps of the method for time synchronization of the on-chip system provided in any of the above embodiments are implemented.

[0023] For the method for time synchronization of the on-chip system provided in the embodiment of the present application, first, time synchronization is performed on each hardware domain of the first subsystem, then the clock of the first daisy-chain counter of the first subsystem is synchronized with the second daisy-chain counter of the second subsystem, and then, by using the clock synchronization of the two daisy-chain counters, the system time synchronization between the first subsystem and the second subsystem is achieved. Finally, time synchronization is performed on each hardware domain of the second subsystem, thereby realizing the time synchronization between the first subsystem and the second subsystem of the on-chip system, and the time synchronization of each hardware domain within the first subsystem and the second subsystem. By means of the daisy-chain counter, the present application realizes the time synchronization between the first subsystem and the second subsystem of the on-chip system, which can not only reduce the influence of time delay, jitter, etc. of the communication path between subsystems on the time synchronization accuracy, thereby improving the time synchronization accuracy of the on-chip system, but also does not require additional hardware costs. Description of the Drawings

[0024] Figure 1 It is a schematic flow chart of a method for time synchronization of an on-chip system provided in an embodiment of the present application;

[0025] Figure 2 It is a schematic flow chart of step S10 in an embodiment of the present application;

[0026] Figure 3 It is a schematic flow chart of step S20 in an embodiment of the present application;

[0027] Figure 4 It is a schematic flow chart of step S30 in an embodiment of the present application;

[0028] Figure 5 It is a schematic flow chart of step S50 in an embodiment of the present application;

[0029] Figure 6 It is a schematic flow chart of step S70 in an embodiment of the present application;

[0030] Figure 7 It is a schematic structural diagram of an on-chip system provided in an embodiment of the present application;

[0031] Figure 8 It is another schematic structural diagram of an on-chip system provided in an embodiment of the present application. Detailed Embodiments

[0032] The various solutions and features of the present application are described herein with reference to the accompanying drawings.

[0033] It should be understood that various modifications can be made to the embodiments applied herein. Therefore, the above description should not be regarded as a limitation, but only as an example of the embodiments. Those skilled in the art will think of other modifications within the scope and spirit of the present application.

[0034] In an embedded system, time synchronization has a wide range of practical requirements. Specifically, in a multi-core heterogeneous SoC system, time synchronization with a certain accuracy is also required between each subsystem and each domain to meet the time requirements of some time-sensitive applications.

[0035] Before describing the embodiments of the present application in detail, first, the technical names and terms involved in the embodiments of the present application are described.

[0036] DCI (Daisy Chain Interface) is usually referred to as the "daisy chain interface" and is a serial or parallel communication interface technology for connecting multiple devices.

[0037] Based on the DCI (Daisy Chain Interface) technology, the present application realizes time synchronization between each subsystem, which can not only reduce the influence of time delay, jitter, etc. of the communication path between subsystems on the time synchronization accuracy, thereby improving the time synchronization accuracy of the on-chip system, but also does not require additional hardware costs.

[0038] The following describes in detail a method for time synchronization of an on-chip system provided by the embodiments of the present application with reference to the accompanying drawings. The embodiments of the present application provide a method for time synchronization of an on-chip system, see Figure 7 As shown, the on-chip system includes a first subsystem and at least one second subsystem. Both the first subsystem and the second subsystem include multiple hardware domains. One hardware domain in the first subsystem is the first hardware domain, and one hardware domain in the second subsystem is the second hardware domain. The first hardware domain is the root node, and the second hardware domain is the leaf node. The root node is electrically connected to at least one leaf node in a daisy chain manner; the first hardware domain includes a first daisy chain counter, and the second hardware domain includes a second daisy chain counter. Figure 7 In, the second subsystem 1 represents the first second subsystem, the second subsystem 2 represents the second second subsystem, and the second subsystem n represents the nth second subsystem, where n is an integer greater than or equal to 1.

[0039] Figure 1It is a schematic flowchart of a method for time synchronization of a system-on-chip provided by an embodiment of the present application. For the method of time synchronization of the system-on-chip, first, the time of each hardware domain of the first subsystem is synchronized, and then, the system time of the first subsystem and any second subsystem on the daisy chain is synchronized. For example, the system time of the first subsystem and the 5th second subsystem on the daisy chain is synchronized. Finally, the time of each hardware domain of the 5th second subsystem is synchronized, thereby realizing the time synchronization between the first subsystem and the second subsystem of the system-on-chip, and the time synchronization between each hardware domain within the first subsystem and the second subsystem. That is, the method for time synchronization of the system-on-chip provided by the embodiment of the present application is a method for synchronizing the time between the first subsystem of the system-on-chip and one of the second subsystems on the daisy chain. The second hardware domain in the following steps S10 to S70 refers to the second hardware domain of the same second subsystem.

[0040] Specifically, referring to Figure 1 shown, the method for time synchronization of the system-on-chip includes:

[0041] S10, synchronize the time of each hardware domain of the first subsystem through the first real-time clock module of the first subsystem;

[0042] Referring to Figure 7 , the first subsystem further includes a first real-time clock module (RTC, Real_Time Clock). The first real-time clock module is used to provide a time reference for the first subsystem. By using the first real-time clock module, the time of each hardware domain of the first subsystem where the first real-time clock module is located can be synchronized.

[0043] S20, determine the daisy chain data transmission delay between the first hardware domain and the second hardware domain;

[0044] Exemplarily, the daisy chain data transmission delay between the first hardware domain and the second hardware domain can be determined by the second hardware domain, or can be determined by the first hardware domain. The present application does not make a special limitation.

[0045] In this example, determining the daisy chain data transmission delay between the first hardware domain and the second hardware domain can refer to determining the daisy chain data transmission delay between the first hardware domain and the second hardware domain of any second subsystem.

[0046] For example, determine the daisy chain data transmission delay between the first hardware domain and the second hardware domain of the 1st second subsystem, or determine the daisy chain data transmission delay between the first hardware domain and the second hardware domain of the 5th second subsystem, etc.

[0047] S30, determine the system clock difference between the second hardware domain and the first hardware domain according to the daisy chain data transmission delay;

[0048] Exemplarily, the second hardware domain may determine the system clock difference between the second hardware domain and the first hardware domain according to the daisy chain data transmission delay, or the first hardware domain may determine the system clock difference between the second hardware domain and the first hardware domain according to the daisy chain data transmission delay. This application does not make special limitations.

[0049] S40. Calibrate the clock of the second daisy chain counter according to the system clock difference, so that the clock of the second daisy chain counter is synchronized with the clock of the first daisy chain counter.

[0050] Exemplarily, the second hardware domain may calibrate the clock of the second daisy chain counter in the second hardware domain according to the system clock difference, so that the clock of the second daisy chain counter in the second hardware domain is synchronized with the clock of the first daisy chain counter in the first hardware domain.

[0051] S50. Determine the time stamp of the second subsystem based on the first subsystem time information sent from the first hardware domain; wherein, the first subsystem time information includes the time stamp of the first subsystem and the clock information of the first daisy chain counter.

[0052] Exemplarily, the first hardware domain sends the first subsystem time information to the second hardware domain, wherein the first subsystem time information includes the time stamp of the first subsystem and the clock information of the first daisy chain counter. The second hardware domain receives the first subsystem time information and determines the time stamp of the second subsystem where the second hardware domain is located according to the first subsystem time information.

[0053] The time stamp refers to the data generated using digital signature technology for subsequent synchronization of the system time of the second subsystem and the first subsystem.

[0054] S60. Update the system time of the second subsystem according to the time stamp of the second subsystem, so that the system time of the second subsystem is synchronized with the system time of the first subsystem.

[0055] Exemplarily, the second hardware domain may update the system time of the second subsystem where the second hardware domain is located according to the time stamp of the second subsystem where the second hardware domain is located, so that the system time of the second subsystem where the second hardware domain is located is synchronized with the system time of the first subsystem.

[0056] S70. Synchronize the time of each hardware domain of the second subsystem through the second real-time clock module of the second subsystem.

[0057] See Figure 7, the second subsystem further includes a second Real-Time Clock module (RTC), and the second Real-Time Clock module is used to provide a time reference for the second subsystem. By using the second Real-Time Clock module, each hardware domain of the second subsystem where the second Real-Time Clock module is located can be time-synchronized.

[0058] The method for time synchronization of the system-on-chip provided by the embodiments of the present application first time-synchronizes each hardware domain of the first subsystem, then synchronizes the clock of the first daisy-chain counter of the first subsystem with the second daisy-chain counter of the second subsystem, and then uses the clock synchronization of the two daisy-chain counters to achieve the system time synchronization between the first subsystem and the second subsystem. Finally, each hardware domain of the second subsystem is time-synchronized, thereby realizing the time synchronization between the first subsystem and the second subsystem of the system-on-chip, and the time synchronization of each hardware domain within the first subsystem and the second subsystem. The present application realizes the time synchronization between the first subsystem and the second subsystem of the system-on-chip by means of a daisy-chain counter, which can not only reduce the influence of time delay, jitter, etc. of the communication path between subsystems on the time synchronization accuracy, thereby improving the time synchronization accuracy of the system-on-chip, but also does not require additional hardware costs.

[0059] It should be noted that the above method steps for time synchronization of the system-on-chip are the method steps for time-synchronizing the first subsystem with one of all the second subsystems on the daisy-chain.

[0060] If you want to time-synchronize the first subsystem with all the second subsystems, you can time-synchronize the first subsystem with all the second subsystems in sequence according to a preset time synchronization order. The preset time synchronization order can be: the first subsystem synchronizes with the 1st second subsystem, the 2nd second subsystem,..., the nth second subsystem in sequence, and finally completes the time synchronization between the first subsystem and all the second subsystems. The preset time synchronization order can also be: the first subsystem synchronizes with the nth second subsystem,..., the 2nd second subsystem, the 1st second subsystem in sequence, and finally completes the time synchronization between the first subsystem and all the second subsystems. The preset time synchronization order can also be: the first subsystem synchronizes with the 3rd second subsystem, the 2nd second subsystem, the nth second subsystem,..., and finally completes the time synchronization between the first subsystem and all the second subsystems.

[0061] The hardware domains in the embodiments of the present application can be protection domains, application domains, multi-functional domains, security domains, etc. Optionally, the first hardware domain can be one of the protection domain, application domain, multi-functional domain, and security domain, and the second hardware domain can be one of the protection domain, application domain, multi-functional domain, and security domain. Figure 8In the illustrated embodiment, both the first hardware domain and the second hardware domain are application domains. Of course, it is also possible that both the first hardware domain and the second hardware domain are protection domains, or the first hardware domain is an application domain and the second hardware domain is a multi-functional domain, etc. The present application does not make special limitations.

[0062] In some embodiments, referring to Figure 8 as shown, the first subsystem includes at least an application domain, a multi-functional domain, a protection domain, and a security domain; the first real-time clock module includes a first real-time clock chip and a second real-time clock chip;

[0063] Referring to Figure 2 , through the first real-time clock module of the first subsystem, time synchronization of each hardware domain of the first subsystem is performed, including:

[0064] S101, the application domain, the multi-functional domain, and the security domain perform clock synchronization through the first real-time clock chip, and the security domain performs clock synchronization through the second real-time clock chip;

[0065] S102, obtain the timestamp of the first real-time clock chip through one of the application domain, the multi-functional domain, and the protection domain, and transfer the timestamp of the first real-time clock chip to the security domain through an inter-domain communication method;

[0066] S103, the security domain writes the timestamp of the first real-time clock chip into the second real-time clock chip, so that the first real-time clock chip and the second real-time clock chip are clock-synchronized, so that the application domain, the multi-functional domain, the protection domain, and the security domain are time-synchronized.

[0067] In this embodiment, the inter-domain communication method may include asynchronous message passing through the mailbox mechanism and data sharing across hardware domains through the shared memory mechanism.

[0068] In this embodiment, the application domain, the multi-functional domain, and the protection domain share the first real-time clock chip, and the security domain uses the second real-time clock chip. Any one of the application domain, the multi-functional domain, and the protection domain obtains the timestamp of the first real-time clock chip and transfers the timestamp of the first real-time clock chip to the security domain through the mailbox. The security domain writes the timestamp of the first real-time clock chip into the second real-time clock chip, so that the first real-time clock chip and the second real-time clock chip are clock-synchronized, so that the application domain, the multi-functional domain, the protection domain, and the security domain are time-synchronized, thereby making the time of each hardware domain of the first subsystem synchronized.

[0069] Optionally, before performing time synchronization of each hardware domain of the first subsystem through the first real-time clock module of the first subsystem, it includes: the first subsystem obtains standard time from the outside. The standard time is the reference time for time synchronization of each hardware domain of the first subsystem.

[0070] For example, the first subsystem can obtain the standard time from the outside through Ethernet, or use PTP (Precision Time Protocol) to synchronize the time of the local area network to the first subsystem, so that the first subsystem obtains the standard time.

[0071] Using the standard time and the first real-time clock module, synchronize the time of each hardware domain of the first subsystem.

[0072] In some embodiments, referring to Figure 3 as shown, determining the daisy-chain data transmission delay between the first hardware domain and the second hardware domain includes:

[0073] S202, based on the timing instruction obtained from the first hardware domain, control the second daisy-chain counter to time; wherein, when the first hardware domain sends the timing instruction, control the first daisy-chain counter to time;

[0074] S203, send a stop timing instruction from the second hardware domain to the first hardware domain and synchronously control the second daisy-chain counter to stop timing, so that the first hardware domain controls the first daisy-chain counter to stop timing according to the stop timing instruction;

[0075] S204, based on the read instruction obtained from the first hardware domain, read the clock value of the second daisy-chain counter and use it as the second clock value; wherein, when the first hardware domain sends the read instruction, read the clock value of the first daisy-chain counter and use it as the first clock value;

[0076] S205, based on the first clock value and the second clock value obtained from the first hardware domain, determine the daisy-chain data transmission delay between the first hardware domain and the second hardware domain.

[0077] In some embodiments, continuing to refer to Figure 3 , before controlling the second daisy-chain counter to time based on the timing instruction obtained from the first hardware domain, includes:

[0078] S201, based on the initialization instruction obtained from the first hardware domain, control the second daisy-chain counter to initialize; wherein, when the first hardware domain sends the initialization instruction, control the first daisy-chain counter to initialize.

[0079] Exemplarily, when n = 1, the system-on-chip includes a first subsystem and 1 second subsystem on the daisy-chain. The process of determining the daisy-chain data transmission delay between the first hardware domain and the second hardware domain is described in detail below. Set t as the daisy-chain data transmission delay between the first hardware domain and the second hardware domain, t1 as the daisy-chain data transmission delay from the first hardware domain to the second hardware domain, and t2 as the daisy-chain data transmission delay from the second hardware domain to the first hardware domain.

[0080] Specifically, when determining the daisy-chain data transmission delay, all other communications on the daisy-chain bus are temporarily turned off. Therefore, t1 and t2 can be considered approximately equal. Thus, the average daisy-chain data transmission delay, that is, the daisy-chain data transmission delay t between the first hardware domain and the second hardware domain, is t = (t1 + t2) / 2.

[0081] First, the first hardware domain sends an initialization instruction to the second hardware domain and synchronously controls the initialization of the first daisy-chain counter; based on the initialization instruction obtained from the first hardware domain, the second hardware domain controls the initialization of the second daisy-chain counter; at this time, both the first daisy-chain counter and the second daisy-chain counter are set to zero.

[0082] Next, the first hardware domain sends a timing instruction to the second hardware domain and synchronously controls the first daisy-chain counter to start timing, and the first daisy-chain counter immediately starts timing; based on the timing instruction obtained from the first hardware domain, the second hardware domain controls the second daisy-chain counter to start timing, and the second daisy-chain counter starts timing after a delay of t.

[0083] Next, the second hardware domain sends a stop-timing instruction to the first hardware domain and synchronously controls the second daisy-chain counter to stop timing, and the second daisy-chain counter immediately stops timing; the first hardware domain controls the first daisy-chain counter to stop timing according to the stop-timing instruction, and the first daisy-chain counter starts to stop timing after a delay of t.

[0084] Next, the first hardware domain sends a read instruction to the second hardware domain and synchronously reads the clock value of the first daisy-chain counter as the first clock value C0; based on the read instruction obtained from the first hardware domain, the second hardware domain reads the clock value of the second daisy-chain counter as the second clock value C1.

[0085] Finally, based on the first clock value C0 and the second clock value C1 obtained from the first hardware domain, the second hardware domain calculates the daisy-chain data transmission delay t between the first hardware domain and the second hardware domain according to the formula t = (C0 - C1) / 2.

[0086] Exemplarily, when n = 3, the system-on-chip includes a first subsystem and 3 second sub-systems on the daisy-chain. It should be noted that the lengths of the daisy-chain buses connecting any two adjacent hardware domains are equal, and it can be understood that the daisy-chain data transmission delays between adjacent hardware domains are equal. The process of determining the daisy-chain data transmission delay between the first hardware domain and the second hardware domain of the 3rd second sub-system is described in detail below. Let t be the daisy-chain data transmission delay between adjacent hardware domains, and t3 be the daisy-chain data transmission delay from the first hardware domain of the first subsystem to the second hardware domain of the 3rd second sub-system, and t3 = 3t.

[0087] Specifically, when determining the daisy-chain data transmission delay, all other communications on the daisy-chain bus are temporarily turned off.

[0088] First, the first hardware domain sends an initialization instruction to the second hardware domain of the 3rd second subsystem and synchronously controls the initialization of the first daisy-chain counter; the second hardware domain of the 3rd second subsystem controls the initialization of the second daisy-chain counter based on the initialization instruction obtained from the first hardware domain; at this time, both the first daisy-chain counter and the second daisy-chain counter are set to zero.

[0089] Next, the first hardware domain sends a timing instruction to the second hardware domain of the 3rd second subsystem and synchronously controls the timing of the first daisy-chain counter, and the first daisy-chain counter immediately starts timing; the second hardware domain of the 3rd second subsystem controls the timing of the second daisy-chain counter based on the timing instruction obtained from the first hardware domain, and the second daisy-chain counter starts timing after a delay of 3t.

[0090] Next, the second hardware domain of the 3rd second subsystem sends a stop-timing instruction to the first hardware domain and synchronously controls the stop-timing of the second daisy-chain counter, and the second daisy-chain counter immediately stops timing; the first hardware domain controls the stop-timing of the first daisy-chain counter according to the stop-timing instruction, and the first daisy-chain counter starts to stop timing after a delay of t.

[0091] Next, the first hardware domain sends a read instruction to the second hardware domain of the 3rd second subsystem and synchronously reads the clock value of the first daisy-chain counter as the first clock value C0; the second hardware domain of the 3rd second subsystem reads the clock value of the second daisy-chain counter as the second clock value C1 based on the read instruction obtained from the first hardware domain.

[0092] Finally, the second hardware domain of the 3rd second subsystem obtains the daisy-chain data transmission delay t between two adjacent hardware domains according to the formula t = (C0 - C1) / 4 based on the first clock value C0 and the second clock value C1 obtained from the first hardware domain, and obtains the daisy-chain data transmission delay t3 between the first hardware domain and the second hardware domain of the 3rd second subsystem according to the formula t3 = 3t.

[0093] Since there is no other data on the daisy-chain bus during the above signal transmission process, for each communication between the first hardware domain and the second hardware domain, there is only the transmission delay on the daisy-chain physical link, and this transmission delay is stable.

[0094] In some embodiments, as shown in Figure 4 Determining the system clock difference between the second hardware domain and the first hardware domain according to the daisy-chain data transmission delay includes:

[0095] S301, sample the clock of the second daisy-chain counter based on the first sampling instruction obtained from the first hardware domain, and obtain a second sampling value; wherein, when the first hardware domain sends the first sampling instruction, it samples the clock of the first daisy-chain counter and obtains a first sampling value;

[0096] S302, sample the clock of the second daisy-chain counter based on the second sampling instruction obtained from the first hardware domain, and obtain a fourth sampling value; wherein, when the first hardware domain sends the second sampling instruction, it samples the clock of the first daisy-chain counter and obtains a third sampling value;

[0097] S303, determine the system clock difference between the second hardware domain and the first hardware domain based on the first sampling value and the third sampling value obtained from the first hardware domain, as well as the second sampling value, the fourth sampling value, and the daisy-chain data transmission delay.

[0098] Exemplarily, when n = 1, the system-on-chip includes a first subsystem and 1 second subsystem on the daisy chain. The process of determining the system clock difference between the second hardware domain of the second subsystem and the first hardware domain of the first subsystem is described in detail below. Set t as the daisy-chain data transmission delay between the first hardware domain and the second hardware domain.

[0099] First, the first hardware domain sends a first sampling instruction to the second hardware domain, and simultaneously samples the clock of the first daisy-chain counter and obtains a first sampling value C01; after a delay of t, the second hardware domain samples the clock of the second daisy-chain counter based on the first sampling instruction obtained from the first hardware domain, and obtains a second sampling value C11;

[0100] Next, after a preset duration, the first hardware domain sends a second sampling instruction to the second hardware domain, and simultaneously samples the clock of the first daisy-chain counter and obtains a third sampling value C02; after a delay of t, the second hardware domain samples the clock of the second daisy-chain counter based on the second sampling instruction obtained from the first hardware domain, and obtains a fourth sampling value C12;

[0101] Finally, the second hardware domain determines the system clock difference d between the second hardware domain and the first hardware domain based on the first sampling value C01 and the third sampling value C02 obtained from the first hardware domain, as well as the second sampling value C11, the fourth sampling value C12, and the daisy-chain data transmission delay t.

[0102] Specifically, the system clock difference d can be calculated according to the following formula;

[0103]

[0104] After calculation, d = ((C11 + C12) - (C01 + C02)) / 2 + t.

[0105] Exemplarily, when n = 3, the system - on - chip includes a first subsystem and three second subsystems on the daisy chain. The process of determining the system clock difference between the second hardware domain of the third second subsystem and the first hardware domain of the first subsystem is described in detail below. Set t as the daisy - chain data transfer delay between two adjacent hardware domains, and t3 as the daisy - chain data transfer delay from the first hardware domain of the first subsystem to the second hardware domain of the third second subsystem, t3 = 3t.

[0106] First, the first hardware domain sends a first sampling instruction to the second hardware domain, and synchronously samples the clock of the first daisy - chain counter to obtain a first sampling value C01; after a delay of 3t duration, the second hardware domain of the third second subsystem samples the clock of the second daisy - chain counter based on the first sampling instruction obtained from the first hardware domain to obtain a second sampling value C11;

[0107] Next, after a preset duration, the first hardware domain sends a second sampling instruction to the second hardware domain, and synchronously samples the clock of the first daisy - chain counter to obtain a third sampling value C02; after a delay of 3t duration, the second hardware domain of the third second subsystem samples the clock of the second daisy - chain counter based on the second sampling instruction obtained from the first hardware domain to obtain a fourth sampling value C12;

[0108] Finally, the second hardware domain determines the system clock difference d between the second hardware domain of the third second subsystem and the first hardware domain based on the first sampling value C01 and the third sampling value C02 obtained from the first hardware domain, as well as the second sampling value C11, the fourth sampling value C12, and the daisy - chain data transfer delay 3t between the first hardware domain and the second hardware domain of the third second subsystem.

[0109] Specifically, the system clock difference d can be calculated according to the following formula;

[0110]

[0111] After calculation, d = ((C11 + C12) - (C01 + C02)) / 2 + 3t.

[0112] The above - mentioned processes of determining the daisy - chain data transfer delay and the system clock difference between the first hardware domain and the second hardware domains of the first and third second subsystems are described in detail respectively. The processes of determining the daisy - chain transfer delay and the system clock difference between the first hardware domain and the second hardware domains of the second, fourth... second subsystems are similar to the above - mentioned processes and will not be elaborated here.

[0113] After determining the system clock difference d between the second hardware domain and the first hardware domain, the second hardware domain calibrates the clock of the second daisy chain counter in the second hardware domain according to the system clock difference d, so that the clock of the second daisy chain counter in the second hardware domain is synchronized with the clock of the first daisy chain counter in the first hardware domain.

[0114] By using the daisy chain counter as described above to achieve time synchronization between two subsystems, the time delay, jitter, etc. of the communication path between the subsystems can be reduced, and the influence on the time synchronization accuracy can be minimized. The time synchronization accuracy can reach the microsecond level. The clock synchronization accuracy of the two daisy chain counters in this embodiment can be less than 1 microsecond. Therefore, in practical applications, the first hardware domain can send the first subsystem time information to the second hardware domain of the second subsystem through various communication link methods. For example, the first subsystem time information can be sent to the second hardware domain of the second subsystem through a virtual network card, SPI, I2C, etc., so as to be able to more flexibly handle various actual scenarios.

[0115] In some embodiments, the first subsystem further includes a first virtual network card, and the second subsystem further includes a second virtual network card;

[0116] The first hardware domain sends the first subsystem time information to the second hardware domain through the first virtual network card, the daisy chain bus, and the second virtual network card.

[0117] Optionally, the first virtual network card and the second virtual network card can be ulink virtual network cards based on DCI technology.

[0118] Optionally, the first hardware domain and the second hardware domain are connected through a TCP network. Specifically, the first hardware domain sends the first subsystem time information to the second hardware domain through the first TCP / IP protocol stack, the first virtual network card, the daisy chain bus, the second virtual network card, and the second TCP / IP protocol stack in sequence; where the first subsystem time information includes the time stamp of the first subsystem and the clock information of the first daisy chain counter.

[0119] In some embodiments, refer to Figure 5 , determining the time stamp of the second subsystem based on the first subsystem time information sent from the first hardware domain includes:

[0120] S501, obtaining the clock information of the second daisy chain counter;

[0121] S502, determining the network data transmission delay according to the clock information of the first daisy chain counter and the clock information of the second daisy chain counter;

[0122] S503, determining the time stamp of the second subsystem according to the network data transmission delay and the time stamp of the first subsystem.

[0123] Exemplarily, based on the DCI-based virtual network card technology, a TCP network connection is established between the first hardware domain of the first subsystem and the second hardware domain of the second subsystem. That is, the first hardware domain (root node) sends the time information of the first subsystem to the second hardware domain (leaf node) through the first TCP / IP protocol stack, the first virtual network card, the daisy-chain bus, the second virtual network card, and the second TCP / IP protocol stack in sequence. The time information of the first subsystem includes the timestamp of the first subsystem and the clock information of the first daisy-chain counter.

[0124] Specifically, the first hardware domain packs and sends the DCI_CA of the time information of the first subsystem to the second hardware domain through the TCP network. The DCI_CA of the time information of the first subsystem includes the timestamp Timestamp_A of the first subsystem and the clock information root DCI counter of the first daisy-chain counter.

[0125] The second hardware domain obtains the clock information leaf DCI counter of the second daisy-chain counter;

[0126] The second hardware domain determines the network data transmission delay delta_DCI according to the clock information root DCI counter of the first daisy-chain counter and the clock information leaf DCI counter of the second daisy-chain counter; that is, delta_DCI = leaf DCI counter - root DCI counter.

[0127] The second hardware domain obtains the timestamp Timestamp_B of the second subsystem according to the network data transmission delay delta_DCI and the timestamp Timestamp_A of the first subsystem according to the formula Timestamp_B = Timestamp_A + delta_DCI.

[0128] The second hardware domain updates the system time of the second subsystem according to the timestamp Timestamp_B of the second subsystem, so that the system time of the second subsystem is synchronized with the system time of the first subsystem.

[0129] In some embodiments, as shown in Figure 8 the second subsystem at least includes an application domain, a multi-functional domain, a protection domain, and a security domain; the second real-time clock module includes a third real-time clock chip and a fourth real-time clock chip;

[0130] As shown in Figure 6 the time synchronization of each hardware domain of the second subsystem is performed through the second real-time clock module of the second subsystem, including:

[0131] S701, the application domain, the multi-functional domain, and the security domain are synchronized in clock by a third real-time clock chip, and the security domain is synchronized in clock by a fourth real-time clock chip;

[0132] S702, obtain the timestamp of the third real-time clock chip through one of the application domain, the multi-functional domain, and the protection domain, and transmit the timestamp of the third real-time clock chip to the security domain through inter-domain communication;

[0133] S703, the security domain writes the timestamp of the third real-time clock chip into the fourth real-time clock chip, so that the third real-time clock chip and the fourth real-time clock chip are synchronized in clock, so as to synchronize the time of the application domain, the multi-functional domain, the protection domain, and the security domain.

[0134] In this embodiment, the inter-domain communication method may include asynchronous message passing through the mailbox mechanism and data sharing across hardware domains through the shared memory mechanism.

[0135] In this embodiment, the application domain, the multi-functional domain, and the protection domain share the third real-time clock chip, and the security domain uses the fourth real-time clock chip. Any one of the application domain, the multi-functional domain, and the protection domain obtains the timestamp of the third real-time clock chip and transmits the timestamp of the third real-time clock chip to the security domain through the mailbox. The security domain writes the timestamp of the third real-time clock chip into the fourth real-time clock chip, so that the third real-time clock chip and the fourth real-time clock chip are synchronized in clock, so as to synchronize the time of the application domain, the multi-functional domain, the protection domain, and the security domain, thereby synchronizing the time of each hardware domain of the second subsystem.

[0136] Based on the same inventive concept, an embodiment of the present application provides a system on a chip, as combined with Figure 7 As shown, the system on a chip includes a first subsystem and at least one second subsystem. Both the first subsystem and the second subsystem include multiple hardware domains. One hardware domain in the first subsystem is the first hardware domain, and one hardware domain in the second subsystem is the second hardware domain. The first hardware domain is the root node, and the second hardware domain is the leaf node. The root node is electrically connected to at least one leaf node in a daisy-chain manner; the first hardware domain includes a first daisy-chain counter, and the second hardware domain includes a second daisy-chain counter; the first subsystem includes a first real-time clock module, and the second subsystem includes a second real-time clock module; Figure 7 In, the second subsystem 1 represents the first second subsystem, the second subsystem 2 represents the second second subsystem, and the second subsystem n represents the nth second subsystem, where n is an integer greater than or equal to 1.

[0137] The first real-time clock module is configured to synchronize the time of each hardware domain of the first subsystem;

[0138] A second hardware domain, configured to determine the daisy-chain data transmission delay between the first hardware domain and the second hardware domain;

[0139] A second hardware domain, configured to determine the system clock difference between the second hardware domain and the first hardware domain according to the daisy-chain data transmission delay;

[0140] A second hardware domain, configured to calibrate the clock of the second daisy-chain counter according to the system clock difference, so that the clock of the second daisy-chain counter is synchronized with the clock of the first daisy-chain counter;

[0141] A second hardware domain, configured to determine the timestamp of the second subsystem based on the first subsystem time information sent from the first hardware domain; wherein, the first subsystem time information includes the timestamp of the first subsystem and the clock information of the first daisy-chain counter;

[0142] A second hardware domain, configured to update the system time of the second subsystem according to the timestamp of the second subsystem, so that the system time of the second subsystem is synchronized with the system time of the first subsystem;

[0143] A second real-time clock module, configured to synchronize the time of each hardware domain of the second subsystem.

[0144] The system-on-chip provided by the embodiments of the present application includes a first subsystem and at least one second subsystem. Both the first subsystem and the second subsystem include multiple hardware domains. One hardware domain in the first subsystem is the first hardware domain, and one hardware domain in the second subsystem is the second hardware domain. The first hardware domain is the root node, and the second hardware domain is the leaf node. The root node is electrically connected to at least one leaf node in a daisy-chain manner; the first hardware domain includes a first daisy-chain counter, and the second hardware domain includes a second daisy-chain counter; the first subsystem includes a first real-time clock module, and the second subsystem includes a second real-time clock module; first, the time of each hardware domain of the first subsystem is synchronized, then the clock of the first daisy-chain counter of the first subsystem is synchronized with the clock of the second daisy-chain counter of the second subsystem, and then the system time of the first subsystem and the second subsystem is synchronized by using the clock synchronization of the two daisy-chain counters. Finally, the time of each hardware domain of the second subsystem is synchronized, thereby realizing the time synchronization between the first subsystem and the second subsystem of the system-on-chip, and the time synchronization of each hardware domain within the first subsystem and the second subsystem. By means of the daisy-chain counter, the present application realizes the time synchronization between the first subsystem and the second subsystem of the system-on-chip, which can not only reduce the influence of the time delay and jitter of the communication path between subsystems on the time synchronization accuracy, thereby improving the time synchronization accuracy of the system-on-chip, but also does not require additional hardware costs.

[0145] In some embodiments, refer to Figure 7As shown, the output terminal of the first hardware domain of the first subsystem is electrically connected to the input terminal of the second hardware domain of the first second subsystem through a daisy-chain bus. The output terminal of the second hardware domain of the first second subsystem is electrically connected to the input terminal of the second hardware domain of the next second subsystem through a daisy-chain bus. The output terminal of the second hardware domain of the last second subsystem is electrically connected to the input terminal of the first hardware domain of the first subsystem through a daisy-chain bus.

[0146] Optionally, the lengths of the daisy-chain buses connecting any two adjacent hardware domains are equal.

[0147] In some embodiments, referring to Figure 8 As shown, the first subsystem at least includes an application domain, a multi-functional domain, a protection domain, and a security domain; the first real-time clock module includes a first real-time clock chip and a second real-time clock chip;

[0148] In this embodiment, the application domain, the multi-functional domain, and the protection domain share the first real-time clock chip, and the security domain uses the second real-time clock chip. Any one of the application domain, the multi-functional domain, and the protection domain obtains the time stamp of the first real-time clock chip and transfers the time stamp of the first real-time clock chip to the security domain through the mailbox. The security domain writes the time stamp of the first real-time clock chip into the second real-time clock chip, so that the clocks of the first real-time clock chip and the second real-time clock chip are synchronized, so that the times of the application domain, the multi-functional domain, the protection domain, and the security domain are synchronized, thereby making the times of the various hardware domains of the first subsystem synchronized.

[0149] In some embodiments, referring to Figure 8 As shown, the second subsystem at least includes an application domain, a multi-functional domain, a protection domain, and a security domain; the second real-time clock module includes a third real-time clock chip and a fourth real-time clock chip;

[0150] In this embodiment, the application domain, the multi-functional domain, and the protection domain share the third real-time clock chip, and the security domain uses the fourth real-time clock chip. Any one of the application domain, the multi-functional domain, and the protection domain obtains the time stamp of the third real-time clock chip and transfers the time stamp of the third real-time clock chip to the security domain through the mailbox. The security domain writes the time stamp of the third real-time clock chip into the fourth real-time clock chip, so that the clocks of the third real-time clock chip and the fourth real-time clock chip are synchronized, so that the times of the application domain, the multi-functional domain, the protection domain, and the security domain are synchronized, thereby making the times of the various hardware domains of the second subsystem synchronized.

[0151] Based on the same inventive concept, an embodiment of the present application provides a vehicle, including the system-on-chip provided in the above embodiment. For the vehicle provided in the embodiment of the present application, its implementation manners and effects may refer to the foregoing embodiments and will not be elaborated herein.

[0152] The vehicle in the embodiments of the present application may be an "automobile", a "vehicle", a "complete vehicle", or other similar terms, including general motor vehicles, such as sedans, SUVs, MPVs, buses, trucks, and other cargo or passenger vehicles, watercraft including various ships and boats, and aircraft, etc., including hybrid vehicles, electric vehicles, fuel vehicles, plug-in hybrid vehicles, fuel cell vehicles, and other alternative fuel vehicles. Among them, a hybrid vehicle refers to a vehicle with two or more power sources, and an electric vehicle includes a pure electric vehicle, an extended-range electric vehicle, etc. The present application does not make specific limitations in this regard.

[0153] The embodiments of the present application further provide an electronic device, including a processor and a memory. An executable program is stored in the memory, and the memory executes the executable program to perform the steps of the method as described above. For the electronic device provided by the embodiments of the present application, its implementation manners and effects can refer to the foregoing embodiments and will not be elaborated herein.

[0154] The embodiments of the present application further provide a storage medium that carries one or more computer programs, and when the one or more computer programs are executed by a processor, the steps of the method as described above are implemented.

[0155] The embodiments of the present application further provide a computer program product, including a computer program / instructions, and when the computer program / instructions are executed by a processor, the steps of the method as described above are implemented.

[0156] It should be understood that in the embodiments of the present application, the processor may be a central processing unit (Central Processing Unit, abbreviated as CPU), and the processor may also be other general-purpose processors, digital signal processors (Digital Signal Processing, abbreviated as DSP), application specific integrated circuits (Application Specific Integrated Circuit, abbreviated as ASIC), field-programmable gate arrays (Field-Programmable Gate Array, abbreviated as FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0157] It should also be understood that the memory mentioned in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchlink dynamic random access memory (SLDRAM), and direct rambus random access memory (DR RAM).

[0158] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory (storage module) is integrated in the processor.

[0159] It should be noted that the memory described herein is intended to include, but not be limited to, these and any other suitable types of memory.

[0160] It should also be understood that the first, second, third, fourth, and various numerical numbers involved herein are only for the convenience of description and are not used to limit the scope of the present application.

[0161] It should be understood that the term "and / or" herein is merely an association relationship describing associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " herein generally represents an "or" relationship between the associated objects before and after.

[0162] In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in the processor or the instructions in the form of software. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as being executed and completed by the hardware processor, or executed and completed by the combination of the hardware and software modules in the processor. The software module can be located in a mature storage medium in the art such as random access memory, flash memory, read-only memory, programmable read-only memory, or electrically erasable programmable memory, register, etc. This storage medium is located in the memory, and the processor reads the information in the memory and combines its hardware to complete the steps of the above method. To avoid repetition, it will not be described in detail here.

[0163] In various embodiments of the present application, the magnitude of the serial numbers of the above processes does not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0164] Those of ordinary skill in the art can realize that the various illustrative logical blocks (ILB) and steps described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0165] In several embodiments provided by the present application, it should be understood that the disclosed methods, accelerators, and electronic devices can be implemented in other ways. For example, the accelerator embodiments described above are merely illustrative. For example, the division of the above units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling, direct coupling, or communication connection to each other can be through some interfaces, and the indirect coupling or communication connection of devices or units can be in an electrical, mechanical, or other form.

[0166] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place, or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0167] In addition, in each embodiment of the present application, each functional unit can be integrated in a processing unit, can exist physically separately for each unit, or two or more units can be integrated in one unit.

[0168] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that includes one or more available media integrated. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid-state drive), etc.

[0169] As described above, only the specific embodiments of the present application are provided, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for time synchronization of a system on chip, characterized in that: The system on chip includes a first subsystem and at least one second subsystem, the first subsystem and the second subsystem each include a plurality of hardware domains, one hardware domain in the first subsystem is a first hardware domain, one hardware domain in the second subsystem is a second hardware domain, the first hardware domain is a root node, the second hardware domain is a leaf node, and the root node is electrically connected to at least one of the leaf nodes in a daisy chain manner; The first hardware domain includes a first daisy chain counter, the second hardware domain includes a second daisy chain counter, and the method includes: Performing time synchronization on each hardware domain of the first subsystem through a first real-time clock module of the first subsystem; determining a daisy-chain data transmission delay between the first hardware domain and the second hardware domain; determining a system clock difference between the second hardware domain and the first hardware domain according to the daisy chain data transmission delay; Calibrate the clock of the second daisy chain counter according to the system clock difference so that the clock of the second daisy chain counter is synchronized with the clock of the first daisy chain counter; Determine a timestamp of the second subsystem based on first subsystem time information sent from the first hardware domain; wherein the first subsystem time information includes the timestamp of the first subsystem and clock information of the first daisy chain counter; updating the system time of the second subsystem according to the timestamp of the second subsystem so that the system time of the second subsystem is synchronized with the system time of the first subsystem; The second real-time clock module of the second subsystem is used to synchronize the time of each hardware domain of the second subsystem.

2. The method for time synchronization of a system on chip according to claim 1, characterized in that: The determining of a daisy chain data transmission delay between the first hardware domain and the second hardware domain comprises: Based on the timing instruction obtained from the first hardware domain, controlling the timing of the second daisy chain counter; wherein the first hardware domain controls the timing of the first daisy chain counter while sending the timing instruction; Sending a stop timing instruction to the first hardware domain through the second hardware domain and synchronously controlling the second daisy chain counter to stop timing, so that the first hardware domain controls the first daisy chain counter to stop timing according to the stop timing instruction; Based on the read instruction obtained from the first hardware domain, read the clock value of the second daisy chain counter and use it as the second clock value; wherein, when the first hardware domain sends the read instruction, the clock value of the first daisy chain counter is read and used as the first clock value; A daisy-chain data transmission delay between the first hardware domain and the second hardware domain is determined based on the first clock value and the second clock value obtained from the first hardware domain.

3. The method for time synchronization of a system on chip according to claim 2, characterized in that: Before controlling the timing of the second daisy chain counter based on the timing instruction obtained from the first hardware domain, the method includes: Based on the initialization instruction obtained from the first hardware domain, the second daisy chain counter is controlled to be initialized; wherein, the first hardware domain controls the first daisy chain counter to be initialized while sending the initialization instruction.

4. The method for time synchronization of a system on chip according to claim 1, characterized in that: The determining, according to the daisy chain data transmission delay, a system clock difference between the second hardware domain and the first hardware domain comprises: Based on the first sampling instruction obtained from the first hardware domain, sampling the clock of the second daisy chain counter and obtaining a second sampling value; wherein the first hardware domain samples the clock of the first daisy chain counter and obtains the first sampling value while sending the first sampling instruction; Based on the second sampling instruction obtained from the first hardware domain, sampling the clock of the second daisy chain counter and obtaining a fourth sampling value; wherein, while sending the second sampling instruction, the first hardware domain samples the clock of the first daisy chain counter and obtains a third sampling value; A system clock difference between the second hardware domain and the first hardware domain is determined based on the first sampling value and the third sampling value obtained from the first hardware domain, and the second sampling value, the fourth sampling value, and the daisy chain data transmission delay.

5. The method for time synchronization of a system on chip according to claim 1, characterized in that: The first subsystem further includes a first virtual network card, and the second subsystem further includes a second virtual network card; The first hardware domain sends the first subsystem time information to the second hardware domain through the first virtual network card, the daisy chain bus, and the second virtual network card.

6. The method for time synchronization of a system on chip according to claim 1, characterized in that: The determining the timestamp of the second subsystem based on the first subsystem time information sent from the first hardware domain includes: Obtaining clock information of the second daisy chain counter; determining a network data transmission delay according to the clock information of the first daisy chain counter and the clock information of the second daisy chain counter; The timestamp of the second subsystem is determined according to the network data transmission delay and the timestamp of the first subsystem.

7. The method for time synchronization of a system on chip according to claim 1, characterized in that: The first subsystem includes at least an application domain, a multi-function domain, a protection domain and a security domain; the first real-time clock module includes a first real-time clock chip and a second real-time clock chip; The step of performing time synchronization on each hardware domain of the first subsystem by using the first real-time clock module of the first subsystem includes: The application domain, the multi-function domain and the security domain perform clock synchronization through the first real-time clock chip, and the security domain performs clock synchronization through the second real-time clock chip; Acquire the timestamp of the first real-time clock chip through one of the application domain, the multi-function domain and the protection domain, and transmit the timestamp of the first real-time clock chip to the security domain through inter-domain communication; The security domain writes the timestamp of the first real-time clock chip into the second real-time clock chip, so that the clocks of the first real-time clock chip and the second real-time clock chip are synchronized, so as to synchronize the time of the application domain, the multi-function domain, the protection domain and the security domain.

8. A system on chip, characterized in that: The invention comprises a first subsystem and at least one second subsystem, wherein the first subsystem and the second subsystem both comprise a plurality of hardware domains, wherein one hardware domain in the first subsystem is a first hardware domain, and one hardware domain in the second subsystem is a second hardware domain, wherein the first hardware domain is a root node, and the second hardware domain is a leaf node, wherein the root node is electrically connected to at least one leaf node via a daisy chain; the first hardware domain comprises a first daisy chain counter, and the second hardware domain comprises a second daisy chain counter; the first subsystem comprises a first real-time clock module, and the second subsystem comprises a second real-time clock module; The first real-time clock module is configured to synchronize the time of each hardware domain of the first subsystem; the second hardware domain being configured to determine a daisy-chain data transmission delay between the first hardware domain and the second hardware domain; The second hardware domain is configured to determine a system clock difference between the second hardware domain and the first hardware domain according to the daisy chain data transmission delay; The second hardware domain is configured to calibrate a clock of the second daisy chain counter according to the system clock difference, so that the second daisy chain counter is synchronized with the clock of the first daisy chain counter; The second hardware domain is configured to determine a timestamp of the second subsystem based on first subsystem time information sent from the first hardware domain; wherein the first subsystem time information includes the timestamp of the first subsystem and clock information of the first daisy chain counter; The second hardware domain is configured to update the system time of the second subsystem according to the timestamp of the second subsystem, so that the system time of the second subsystem is synchronized with that of the first subsystem; The second real-time clock module is configured to perform time synchronization on each hardware domain of the second subsystem.

9. A vehicle comprising the system on chip according to claim 8.

10. A computer program product, comprising a computer program / instruction, wherein when the computer program / instruction is executed by a processor, the steps of the method for time synchronization of a system on chip as claimed in any one of claims 1 to 7 are implemented.

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