Memory controller and three-dimensional stacked memory

Abstract

The invention provides a memory controller and a three-dimensional stacked memory, which can be used for accessing the memory cells according to the current configuration mode and the change of the current good and bad information of each memory cell of a to-be-accessed memory area of a memory stack body. The dynamic remapping relation between the address range of the good storage unit of the to-be-accessed storage area of the storage stacking body and the multiple main device interfaces is achieved through the address range of the good storage unit of the to-be-accessed storage area of the storage stacking body, so that the requirement of a user for flexible adjustment of the three-dimensional stacking storage can be met after the three-dimensional stacking storage leaves a factory and is applied, and then the requirement of the user for multiple use scenes is met. For example, a user is supported to decide whether to keep capacity or keep bandwidth in a memory use process, so that the user can adapt to different use scenarios.

Description

Technical Field

[0001] The present invention relates to the technical field of memories, and particularly to a storage controller and a three-dimensional stacked memory. Background Art

[0002] Memories such as Dynamic Random Access Memory (DRAM) are widely used in scenarios such as consumer electronics, data centers, automotive electronics, and industrial applications. Among them, DRAM has the advantages of high bandwidth and large capacity and is widely used in scenarios that require fast reading and writing.

[0003] Currently, how to ensure the data reliability of memories such as DRAM in scenarios with high throughput, and how to perform dynamic adjustment during long-term use to enable memories such as DRAM to flexibly adapt to different usage scenarios are one of the hot topics concerned by those skilled in the art.

[0004] In the prior art, generally, the yield of memories is improved by enhancing the manufacturing process of memories and performing bad point detection through Built-In Self-Test (BIST) before leaving the factory and replacing bad points (error bits) or bad addresses (i.e., redundancy repair). Among them, the method of replacing bad cells (i.e., redundancy repair) through BIST before leaving the factory is generally implemented in the test stage before leaving the factory (such as the CP test of wafers). Memory manufacturers add redundant resources (such as a redundant array composed of redundant word lines redundancy WL and redundant bit lines redundancy BL) in memory chips using redundant resources. When the BIST test discovers bad points (error bits) in the memory, the redundant resources in the memory can replace these bad points (error bits) through methods such as electric fusing or laser repair, thereby increasing the number of effective wafers.

[0005] However, these methods are all carried out by memory manufacturers before leaving the factory and generally cannot be applied to the usage process after the memory leaves the factory, making it difficult to meet the user's demand for flexibly adjusting the memory resources utilized in various usage scenarios. Summary of the Invention

[0006] The purpose of the present invention is to provide a storage controller and a three-dimensional stacked memory, which can improve the flexible configuration ability of the three-dimensional stacked memory after leaving the factory and enable it to meet the user's requirements for various usage scenarios.

[0007] To achieve the above object, the present invention provides a storage controller coupled between a host device and a memory stack. The memory stack includes a plurality of memory dies, each memory die includes a plurality of memory cells, and the storage controller includes: A plurality of host device interfaces for communicating with the host device, wherein each host device interface is a multi-IO parallel interface; A bad cell management module coupled to the plurality of host device interfaces and configured to map the address ranges of the corresponding good memory cells in the memory stack to the corresponding host device interfaces according to the current configuration mode and the current good / bad information of each memory cell in the storage area to be accessed in the memory stack; Wherein, the storage controller provides a plurality of configuration modes for different usage scenarios, the current configuration mode is selected from the plurality of configuration modes, and the mapping relationship between the address ranges of the good memory cells in the storage area to be accessed and the plurality of host device interfaces changes with the change of the current configuration mode.

[0008] Optionally, the number of the plurality of host device interfaces is m, where m is an integer greater than 1, and the configuration modes include at least two of the following (1) to (3): (1) Bandwidth priority mode: m host device interfaces are used simultaneously, and the bad cell management module maps the address ranges of all good memory cells in the storage area to be accessed to each of the host device interfaces in an evenly distributed manner by dividing the address ranges of all good memory cells in the storage area to be accessed by m; (2) Capacity priority mode: each host device interface is used separately, and the bad cell management module maps the address ranges of all good memory cells in the storage area to be accessed to the m host device interfaces correspondingly, so that all good memory cells in the storage area to be accessed can be accessed by the host device; (3) Bandwidth and capacity balance mode: a host device interfaces are used simultaneously, b host device interfaces are used separately, and a + b = m. Wherein, the bad cell management module maps the address ranges of all good memory cells in the storage area to be accessed to the m host device interfaces correspondingly, and the address ranges of the good memory cells mapped to the a host device interfaces are of the same size.

[0009] Optionally, in the capacity priority mode, on the premise of not exceeding the maximum limit of the host device interface, the bad cell management module maps the address ranges of the bad memory cells in the storage area to be accessed to the same host device interface; And / or, in the bandwidth and capacity balance mode, the bad cell management module maps the address ranges of all the bad memory cells in the storage area to be accessed to at least one of the b host device interfaces.

[0010] Optionally, the bad cell management module includes a recording unit for storing the current good / bad information; and / or, the memory die is a DRAM die, and the host device interface is an AXI interface or a CHI interface or an AHB interface.

[0011] Optionally, the current good / bad information includes the number and address range of the current good storage units and the number and address range of the bad storage units in the storage area to be accessed, and the current good / bad information is obtained based on the bad point address information of the memory stack during factory production, or is obtained based on the bad point address information updated on the basis of the bad point address information of the memory stack during factory production; wherein the bad point address information of the memory stack during factory production is obtained by performing a bad point test on the memory stack before factory production.

[0012] Optionally, the method for the bad cell management module to update the bad point address information on the basis of the bad point address information of the memory stack during factory production includes at least one of the following (1) to (2): (1) When the number of error occurrences at a certain storage address or a certain block of storage addresses exceeds the threshold during the use of the memory stack, the certain storage address or the certain block of storage addresses is used as a new bad point address to update the bad point address information on the basis of the bad point address information of the memory stack during factory production; (2) The bad cell management module further includes a built-in self-test unit. After the memory stack leaves the factory, the built-in self-test unit performs a built-in self-test on the memory stack to detect new bad point addresses generated in the memory stack, and then updates the bad point address information on the basis of the bad point address information of the memory stack during factory production.

[0013] Optionally, after updating the bad point address information, the bad cell management module is further configured to determine whether the number of un-repaired bad point addresses included in the storage unit where the new bad point address is located is greater than or equal to the corresponding threshold. If so, the storage unit where the new bad point address is located is marked as a bad storage unit to update the current good / bad information. If not, the storage unit where the new bad point address is located remains a good storage unit; Wherein, when the new bad storage unit is marked, the current good / bad information is updated.

[0014] Optionally, each of the storage units is configured with redundant resources; the bad cell management module is further configured to, after obtaining a new bad point address and determining whether the number of unfixed bad point addresses included in the storage unit where the new bad point address is located is greater than or equal to a corresponding threshold, first determine whether the new bad point address can be redundantly repaired using the corresponding redundant resources. If so, redundantly repair the new bad point address using the corresponding redundant resources.

[0015] Optionally, the storage controller is disposed on the buffer die, the master device is located on the logic die, and the logic die and the buffer die are integrated in the same plane or integrated together in a three-dimensional stacking manner.

[0016] Optionally, the multiple memory dies in the memory stack are stacked together in a three-dimensional stacking manner, and the buffer die is stacked and integrated with the memory stack using through-silicon vias.

[0017] Optionally, the bad cell management module further includes a mode register for configuring the multiple configuration modes and selecting the current configuration mode from the multiple configuration modes.

[0018] Optionally, the memory stack is divided into multiple storage areas. The multiple memory dies in each storage area share row addresses and column addresses. Each storage area serves as a sub-storage system and corresponds to a group of the multiple master device interfaces and a bad cell management module, so as to implement the sub-system management of the memory stack.

[0019] Based on the same inventive concept, the present invention further provides a three-dimensional stacked memory, which includes a stacked memory stack and the storage controller as described in the present invention. The storage controller is disposed on the buffer die, and the stacked memory stack includes multiple three-dimensionally stacked memory dies, wherein the multiple three-dimensionally stacked memory dies and between them and the buffer die are hybrid bonded using through-silicon vias.

[0020] Compared with the prior art, the storage controller and the three-dimensional stacked memory provided by the present invention can implement a dynamic remapping relationship between the address ranges of all good memory cells in the storage area to be accessed of the memory stack (which can be the storage area commonly used by users) and multiple host device interfaces according to the current configuration mode and the change of the good / bad information of each memory cell in the storage area to be accessed of the memory stack. Thus, after the three-dimensional stacked memory is shipped and applied, it can still support the user's flexible adjustment requirements for the three-dimensional stacked memory, and further meet the user's requirements for various usage scenarios. For example, it supports the user to decide whether to preserve capacity or bandwidth during the use of the three-dimensional stacked memory, so that the user can adapt to different usage scenarios; for another example, it supports the usage scenario where the user only accesses one or several storage areas of the three-dimensional stacked memory and does not access other storage areas.

[0021] Furthermore, the storage controller can also support the user to perform built-in self-test on the three-dimensional stacked memory after it is shipped and mark bad memory cells when newly discovered bad memory cells are found, so that the user can have real-time control over the health status of the three-dimensional stacked memory, and then timely change the current configuration method according to needs. Brief Description of the Drawings

[0022] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them: Figure 1 is a schematic diagram of the architecture of the storage controller and the three-dimensional stacked memory according to an embodiment of the present invention.

[0023] Figure 2 is a schematic diagram of an application example of the storage controller and the three-dimensional stacked memory according to an embodiment of the present invention.

[0024] Figure 3 is a schematic diagram of the package structure of the storage controller and the three-dimensional stacked memory according to an embodiment of the present invention.

[0025] Figure 4 is a schematic diagram of the partition management application of the storage controller and the three-dimensional stacked memory according to an embodiment of the present invention.

[0026] Figure 5 is a schematic diagram of the structure of a memory cell unit in the storage controller and the three-dimensional stacked memory according to an embodiment of the present invention. Detailed Description of the Embodiments

[0027] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without one or more of these details. In other instances, well-known features of the art are not described in order to avoid obscuring the present invention. It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Like reference numerals refer to like elements throughout. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0028] Please refer to Figure 1 , this embodiment provides a storage controller 2, which is coupled between a master device (Master, i.e., a device accessing the memory) 1 and a memory stack 3. The storage controller 2 can perform interface conversion to convert commands such as read and write issued by the master device 1 into signals recognizable by the memory stack 3, and complete the conversion of address decoding and data format (such as data bit width) between the master device 1 and the memory stack 3, thereby realizing the necessary control for accessing the memory stack 3 (including the control of address signals, data signals, and various command signals), enabling the master device 1 to access (or "use") the good memory cells in the storage area to be accessed of the memory stack 3 according to the needs of the user. The storage controller 2 can be integrated with the memory stack 3 to form a system-level memory chip, or can be independent of the chip of the memory stack 3 as a separate logic chip, or can be integrated with the master device 1 to form a logic chip, or the memory controller 2, the master device 1, and the memory stack 3 can be integrated together to form a system-level logic chip. The present invention does not make specific limitations on this.

[0029] Among them, the master device 1 may include any type of processor device with computing and processing capabilities, such as a central processing unit (CPU), a digital signal processor (DSP), a network processor, an application processor (AP), a field programmable gate array (FPGA), a dedicated processor, etc. The processor device may be configured to execute instructions or software (including code, an operating system, an application program, etc.), firmware, or a combination thereof that can be executed by one or more computers.

[0030] Please refer to Figures 1 to 5 , the storage controller 2 of this embodiment includes a bad cell management module 21 and m master device interfaces 20_0 to 20_m-1, and the memory stack 3 includes k + 1 memory dies 300 to 30k. Each memory die 300 to 30k includes a plurality of storage units unit. Among them, k≥1, m≥2 and both k and m are integers.

[0031] In the memory stack 3, each storage unit includes a plurality of cells determined by the intersection of a plurality of word lines WL and a plurality of bit lines BL. Each cell corresponds to a storage address. A cell address can be a 1-bit storage address and is determined by a corresponding word line WL and a bit line BL of the memory stack 3. A bad cell is a bad point. Each storage unit unit in the memory stack 3 has a plurality of storage addresses. The storage controller 2 can manage the access to the memory stack 3 from the cell level (a cell address is a 1-bit storage address, and a bad cell is a bad point) to the storage unit (unit) level.

[0032] Among them, the master device interfaces 20_0 to 20_m-1 are used to communicate and connect with the master device 1, implement the interface conversion between the master device 1 and the memory stack 3, receive the commands of the master device 1 and the data to be written into the memory, and return the data read by the master device 1, etc., so as to achieve high bandwidth. The master device interfaces 20_0 to 20_m-1 can be any suitable parallel high-speed communication protocol interface that supports multiple IOs. For example, it is an AXI (Advanced eXtensible Interface) interface or the like. Among them, the AXI interface is an on-chip bus interface for a master-slave architecture oriented to high performance, high bandwidth, and low latency. Its address, instruction, and data phases are separated, support unaligned data transmission. At the same time, in burst transmission, only the first address is required, and the separated read and write data channels support Outstanding (number of outstanding transactions) transmission access and out-of-order access, and it is easier to perform timing convergence, which is suitable for high-speed memory access. It should be noted that although the AXI protocol is shown in the specification drawings, the present invention is not limited thereto. The master device interfaces 20_0 to 20_m-1 can also adopt any other suitable high-bandwidth interface protocols, such as the AHB (Advanced High-performance Bus) protocol or the CHI (Coherent Hub Interface) protocol, etc.

[0033] The bad cell management module 21 is coupled to the m master device interfaces 20_0 to 20_m-1, and is used to allocate the address ranges of all good memory cells in the to-be-accessed storage area of the memory stack 3 in a suitable manner according to the current configuration mode and the current good or bad information (also called "current good and bad cell information") of each memory cell in the to-be-accessed storage area of the memory stack 3, and map them to the m master device interfaces 20_0 to 20_m-1. Thus, when the master device 1 reads or writes to the memory stack 3, the storage controller 2 can implement address decoding between the master device 1 and the to-be-accessed storage area of the memory stack 3. Among them, the current good or bad information of the to-be-accessed storage area includes the number and address range of the current good memory cells in the to-be-accessed storage area and the number and address range of the bad memory cells. The current good or bad information can be visualized to the user through the bad cell management module 21.

[0034] Please refer to Figure 3, in the memory stack 3, k + 1 memory dies 300 to 30k can be stacked three-dimensionally or integrated on the same plane. Each memory die can be a DRAM or any other suitable type of memory die structure. Among them, the DRAM can be any one of, for example, synchronous DRAM (SDRAM), wide I / O DRAM, etc. The memory stack 3 can be implemented as an unbuffered dual in-line memory module (UDIMM), a registered DIMM (RDIMM), a load-reduced DIMM (LRDIMM), a fully buffered DIMM (FBDIMM), a small outline DIMM (SODIMM), etc.

[0035] Optionally, please refer to Figure 4 , and in combination with Figures 2 to 3 , the memory stack 3 is divided into s memory areas, where s is an integer and s ≥ 2. Each memory area serves as a sub-storage system (Subsystem), and each corresponds to a group of master device interfaces (i.e., m master device interfaces) and a bad cell management module 21, thereby realizing the sub-system management of the memory stack 3 by the storage controller 2. Alternatively, the memory stack 3 is divided into s memory areas, where s is an integer and s ≥ 2. Each memory area serves as a sub-storage system, and each is provided with a storage controller 2 of this embodiment as shown in Figure 1 . Each storage controller 2 has a group of master device interfaces (i.e., m master device interfaces) and a bad cell management module 21, thereby realizing the sub-system management of the memory stack 3 (or, realizing the sub-system management of the three-dimensional stacked memory).

[0036] The bad cell management module 21 can perform bad cell management on the memory stack 3 by memory area and map the address range of the storage area to be accessed and the master device interface. The storage area to be accessed currently managed by the bad cell management module 21 is one of the numerous storage areas of the memory stack 3. The capacities of the numerous storage areas of the memory stack 3 can be balanced or personalized configured according to user usage requirements, so that at least one storage area of the numerous storage areas of the memory stack 3 has a different capacity from other storage areas. In one example, the storage area to be accessed currently managed by the bad cell management module 21 can be a certain storage area that the user accesses the memory stack 3 for a long time, and the user does not access other storage areas of the memory stack 3 to meet the needs of some application scenarios.

[0037] In addition, the k + 1 memory dies in the memory stack 3 each have a corresponding memory array, and the memory arrays of these memory dies are of the same size. Each storage unit unit can be any suitable management unit at a level higher than the cell level, such as a block or a sector or a page of the memory stack 3. Each storage area (i.e., subsystem) can be a logical bank (BANK) or a physical bank (RANK) of the memory stack 3. The memory dies of each layer in each storage unit can share row addresses, column addresses, address strobes, write enables, etc. Among them, a page contains multiple bytes (the address range of which can be determined by multiple word lines and multiple bit lines), a sector contains multiple pages, and a storage block contains multiple sectors.

[0038] In one example, please refer to Figure 2 , s = 4, m = 4, k = 7, that is, each layer of memory die has 80 storage units unit, which are distributed in 4 storage areas 30 to 33. Each storage area has 20 storage units unit. Each storage area is coupled to a bad cell management module 21, and the bad cell management module 21 is coupled to 4 main device interfaces. The memory stack 3 and the storage controller 2 are encapsulated in the same package. Adjacent layers of memory dies are connected by through-silicon vias (TSVs). The length of the package is L, and the width is W. The 4 main device interfaces in each storage area are arranged in an area at a distance d1 from the long side of the package, a distance d2 from the wide side of the package, a distance d3 from the adjacent storage area in the transverse direction, and a distance d5 from the adjacent storage area in the longitudinal direction. The transverse pitch between adjacent main device interfaces in the same storage area is d4. d1 to d5 are all greater than 0 and can be any suitable values according to design requirements. The present invention does not make specific limitations on this.

[0039] The storage controller 2 of this embodiment can provide multiple configuration modes (for example, 2 or more) to cope with different usage scenarios, for the user to select one of them according to the current usage scenario requirements as the current configuration mode.

[0040] Optionally, the storage controller 2 of this embodiment can provide configuration modes including at least two of the following (1) to (3): (1) Bandwidth - first mode: m master device interfaces 20_0~20_m - 1 are used simultaneously. The bad cell management module 21 divides the address range of all current good memory cells in the to - be - accessed storage area of the memory stack 3 by m, and then maps the address range of all current good memory cells in the to - be - accessed storage area of the memory stack 3 to each of the master device interfaces 20_0~20_m - 1 in an evenly - distributed manner, achieving the balance of the address ranges of the m master device interfaces 20_0~20_m - 1. In this way, the master device interfaces 20_0~20_m - 1 can receive the same instruction simultaneously and have the same - sized address ranges, ensuring the maximization of bandwidth. Among them, if it can be divided exactly, the master device interfaces 20_0~20_m - 1 evenly distribute the address range of all current good memory cells in the to - be - accessed storage area of the memory stack 3. If it cannot be divided exactly, the addresses of the good memory cells corresponding to the remainder can be left idle (i.e., not allocated), and the memory cells corresponding to the remainder will not be used in this mode.

[0041] (2) Capacity - first mode: Each of the master device interfaces 20_0~20_m - 1 is used separately, and the bad cell management module 21 allocates and maps the address range of all good memory cells in the to - be - accessed storage area of the memory stack 3 to the m master device interfaces 20_0~20_m - 1 accordingly, so that all good memory cells in the to - be - accessed storage area of the memory stack 3 can be accessed by the master device 1. Further optionally, in this capacity - first mode, on the premise of not exceeding the maximum limit of the master device interface, the bad cell management module 21 centrally maps the address range of the bad memory cells in the to - be - accessed storage area of the memory stack 3 to the same master device interface among the master device interfaces 20_0~20_m - 1. For example, please refer to Figure 2 , the storage controller 2 has 4 master device interfaces, namely 20_0~20_3. The address ranges mapped by the master device interfaces 20_0~20_2 are all good memory cells in the to - be - accessed storage area of the memory stack 3. The address range of the bad memory cells in the to - be - accessed storage area of the memory stack 3 is centrally mapped to the master device interface 20_3, so that there are only 2 good memory cells in the master device interface 20_3. However, in this capacity - first mode, all good memory cells in the to - be - accessed storage area of the memory stack 3 will be accessed by the master device 1.

[0042] (3) Bandwidth and capacity balance mode: a master device interfaces (for example, 20_0~20_a-1) are used simultaneously to ensure bandwidth, and b master device interfaces (for example, 20_a~20_m-1) are used separately to ensure capacity, and a+b=m, wherein the bad unit management module 21 allocates the address ranges of all good storage units in the storage area to be accessed of the memory stack 3 accordingly, and maps them to the m master device interfaces, and the address range mapped by the a master device interfaces is the address range of the good storage units and is balanced, so that the a master device interfaces can receive the same instructions at the same time and the address ranges are the same size, thereby ensuring bandwidth. Further optionally, in the bandwidth and capacity balance mode, the bad unit management module 21 also maps the address ranges of all bad storage units in the storage area to be accessed of the memory stack 3 to at least one of the b master device interfaces, and the bad unit management module 21 maps the address ranges of as many bad storage units as possible in the storage area to be accessed of the memory stack 3 to the same master device interface among the b master device interfaces. For example, please refer to Figure 2 The storage controller 2 has four master device interfaces, namely, master device interfaces 20_0 to 20_3. The master device interfaces 20_0 and 20_2 are used to ensure bandwidth, so the address ranges mapped to the master device interfaces 20_0 and 20_2 are all good storage units in the memory stack 3, and the sizes of the address ranges mapped to the master device interfaces 20_0 and 20_2 are the same. The address range mapped to the master device interface 20_1 is half good storage units and half bad storage units, and the address range mapped to the master device interface 20_3 is all bad storage units. This is because the address range of the bad storage units in the storage area to be accessed of the memory stack 3 is first mapped to the master device interface 20_3 to the maximum extent (i.e., "as much as possible"), and after exceeding the maximum limit of the master device interface 20_3, the address range of the remaining bad storage units in the storage area to be accessed is mapped to the master device interface 20_1.

[0043] It should be understood that the above three configuration modes are only illustrative examples of this embodiment, and do not indicate that the technical solution of the present invention is limited to the above examples. The types of configuration modes that the storage controller 2 of the present invention can implement and the performance supported by each configuration mode can be arbitrarily and reasonably configured according to needs. For example, some users may only access one or several storage areas of the memory stack 3 for a long time and do not access other storage areas of the memory stack 3, or the user wants to switch the usage scenario. For these situations, a configuration mode that matches them can be configured. Thus, after selecting the corresponding configuration mode and obtaining the current good or bad information of the storage area to be accessed by the user (which can be the current good or bad information of the storage units of the entire memory stack 3, or the current good or bad unit information of the storage units of the storage area of the memory stack 3 that the user accesses for a long time), the address range of the corresponding good storage units in the memory stack 3 is adaptively allocated and mapped to the corresponding master device interface, so as to flexibly respond to different usage scenarios.

[0044] Optionally, please continue to refer to Figure 1 , the bad unit management module 21 includes a mode register 212, and the mode register 212 can be configured to handle multiple configuration modes for different usage scenarios and allow the user to configure it according to the current usage scenario, so as to select the required current configuration mode from the multiple configuration modes.

[0045] Further optionally, different values of one or more bit (bit) register bits in the mode register 212 can represent different configuration modes. The user sets the register value of the one or more bit register bits equal to the corresponding value to set (or "select") the configuration mode to the required current configuration mode. In one example, there are 2-bit register bits for implementing configuration mode selection in the mode register 212. When the user configures the value of the 2-bit register bits to be equal to 00, the selected configuration mode (i.e., the current configuration mode) is the first mode (for example, the bandwidth priority mode). When the user configures the value of the 2-bit register bits to be equal to 01, the selected configuration mode (i.e., the current configuration mode) is the second mode (for example, the capacity priority mode). When the user configures the value of the 2-bit register bits to be equal to 10, the selected configuration mode (i.e., the current configuration mode) is the third mode (for example, the mode that takes both bandwidth and capacity into account). When the user configures the value of the 2-bit register bits to be equal to 11, the selected configuration mode (i.e., the current configuration mode) is the reserved default mode (reserved mode).

[0046] In this embodiment, the current good / bad information on which the bad cell management module 21 is based may include the number and address range of the current good memory cells and the number and address range of the bad memory cells in the entire memory stack 3. When used for the first time, the bad cell management module 21 obtains the current good / bad information according to the bad point address information of the memory stack 3 at the time of factory shipment. The bad point address information of the memory stack 3 at the time of factory shipment can be obtained through the built-in self-test (BIST) and redundant repair performed by the memory manufacturer on the memory stack 3 in the stage before the memory stack 3 leaves the factory. When the memory stack 3 leaves the factory, the bad point address information of the memory stack 3 will be delivered to the user together (for example, writing these bad point address information into the recording unit 210 in the bad cell management module 21). After the memory stack 3 leaves the factory (i.e., during the user's use process), the bad cell management module 21 obtains the required current good / bad information according to the bad point address information updated on the basis of the bad point address information of the memory stack 3 at the time of factory shipment. Among them, the recording unit 210 is, for example, a register, and the stored bad point address information can be automatically updated through the built-in self-test (BIST) process, or the user is allowed to configure it.

[0047] Among them, the manner in which the bad cell management module 21 updates the bad point address information on the basis of the bad point address information of the memory stack 3 at the time of factory shipment may include any one or both of the following manners: (1) When the number of error occurrences of a certain memory address or a certain piece of memory addresses (i.e., "a piece of address range") exceeds the threshold during the use of the memory stack 3, the erred certain memory address or a certain piece of memory addresses is used as a new bad point address to update the bad point address information on the basis of the bad point address information of the memory stack 3 at the time of factory shipment. This manner supports the user to manually mark as bad the memory cells containing frequently erred addresses.

[0048] (2) Please refer to Figure 1 , the bad cell management module 21 further includes a built-in self-test unit (BIST) 211. After the memory stack 3 leaves the factory, when the chip is powered on or reset or when receiving a test instruction generated by the user through the master device 1, the built-in self-test unit 211 automatically performs a built-in self-test on the memory stack 3 to detect new bad point addresses generated in the memory stack 3, and further updates the bad point address information on the basis of the bad point address information of the memory stack 3 at the time of factory shipment. This manner supports the user to perform a BIST test by himself / herself. After the BIST test ends, the good / bad information of the currently to-be-accessed storage area (i.e., the number of good memory cells and / or the number of bad memory cells, etc.) will be automatically updated.

[0049] Please continue to refer to Figure 1 and Figure 2, optionally, the bad cell management module 21 further includes a recording unit (buffer) 210, and the bad cell management module 21 is further configured to store (or "write") the current good / bad information of the storage area to be accessed into the recording unit 210. Further optionally, the built-in self-test unit 211 can write the address range of the newly discovered bad storage cells in the built-in self-test after the memory stack 3 leaves the factory into the recording unit 210, so that the information such as the number of bad storage cells and the number of good storage cells stored in the recording unit 210 changes accordingly. Thus, the bad cell management module can obtain the updated current good / bad information of each storage cell in the storage area to be accessed of the memory stack 3.

[0050] In one example, the recording unit 210 can store the current good / bad information of all or only the storage cells in the storage area to be accessed of the memory stack 3.

[0051] Furthermore, the recording unit 210 is also used to store the bad point address information of the memory stack 3 (which can be implemented by writing through the bad cell management module 21). At the beginning, the bad point address information stored in the recording unit 210 is the bad point address information when the memory stack 3 leaves the factory. After there is new bad point address information, the bad point address information stored in the recording unit 210 is the updated bad point address information based on the bad point address information when the memory stack 3 leaves the factory, which includes the new bad point address information and the bad point address information that has not been repaired before the new bad point address information is stored.

[0052] In one example, after the bad cell management module 21 obtains a new bad point address (i.e., after updating the bad point address information in the above manner), it can write the new bad point address into the recording unit 210, and does not perform redundant repair on the new bad point address. Instead, it directly determines whether the number of unrepaired bad point addresses in the storage unit unit where the new bad point address is located exceeds the corresponding threshold. If it exceeds, the storage unit unit where the new bad point address is located is marked as a bad storage unit (for example, writing the address range of the storage unit into the recording unit 210). If it does not exceed, the storage unit where the new bad point address is located is not marked as bad and remains a good storage unit. Among them, when a new bad storage unit is generated (i.e., marked), the marking of the new bad storage unit (error unit) will cause the current good / bad information stored in the recording unit 210 to be updated.

[0053] Therefore, when a user discovers that a certain storage address or a certain range of storage addresses is always in error, the bad cell management module 21 supports the user in marking the address as bad. The recording unit 210 can index the storage cells marked as bad in the memory stack 3 this time, so that the user can have real-time control over the health of the memory stack 3. When new bad storage cells are found or the number of newly found bad storage cells exceeds the threshold, during the use of the memory stack 3, based on the current good or bad information of the memory stack 3, it can be timely determined whether it is necessary to change the configuration mode (for example, determining whether to maintain capacity or bandwidth during use), so that the user can adapt to different usage scenarios.

[0054] In another example, each memory cell unit in the memory stack 3 has multiple memory addresses. Among them, each memory address including the bad point address is determined by a corresponding word line WL and a bit line BL of the memory stack 3. Each memory cell unit is configured with redundant resources, which include a certain number of redundant word lines, redundant bit lines, and redundant cells determined by these redundant word lines and redundant bit lines (whose addresses can be regarded as redundant addresses). After the bad cell management module 21 obtains a new bad point address (for example, after writing the new bad point address into the recording unit 210), and before judging whether the number of un-repaired bad point addresses in the memory cell where the new bad point address is located exceeds the corresponding threshold (that is, before judging whether to mark the memory cell where the new bad point address is located as bad), it first judges whether the new bad point address can be redundantly repaired with the corresponding redundant resources. If it can, it means that there are still remaining redundant resources in the current memory cell corresponding to the new bad point address. At this time, the remaining corresponding redundant resources in the current memory cell can be used to redundantly repair the new bad point address (that is, replace the new bad point address with the address of the redundant cell). In this case, before the redundant resources are exhausted, the memory cell remains a good memory cell; if not, it means that the redundant resources of the current memory cell corresponding to the new bad point address have been used up (that is, there is no redundant cell in the current memory cell that can replace the new bad point address). At this time, the new bad point address cannot be redundantly repaired anymore (that is, a new un-repaired bad point address is generated). In this case, the number of un-repaired bad point addresses in the memory cell may exceed the threshold. At this time, the bad cell management module 21 can further judge whether the number of un-repaired bad point addresses included in the current memory cell corresponding to the new bad point address is greater than or equal to the corresponding threshold (the threshold can be any appropriate integer greater than or equal to 0). If so, the bad cell management module 21 marks the current memory cell where the new bad point address is located as a bad memory cell to update the current good / bad information stored in the recording unit 210. If not, the bad cell management module 21 does not mark the current memory cell where the new bad point address is located as bad, and the current memory cell remains a good memory cell. Among them, when a new bad memory cell is generated (that is, marked), the marking of the new bad memory cell will cause the current good / bad information stored in the recording unit 210 to be updated.

[0055] That is to say, in this example, before marking any storage cell as bad, the bad cell management module 21 performs redundant repair on the new bad point address if there is corresponding redundant resource. Moreover, regardless of whether redundant repair is performed, it is ultimately necessary to determine whether the number of bad point addresses that cannot be repaired in the storage cell exceeds the corresponding threshold, and these bad point addresses that cannot be repaired can actually include the bad point addresses at the time of the storage cell's factory production and the new and unrepaired bad point addresses discovered by the BIST test after production. This example can utilize redundant resources to repair the newly added bad point addresses as much as possible after production, which is conducive to ensuring the bandwidth and capacity of the memory.

[0056] In one example, the threshold is equal to 1, and any storage cell in the memory stack 3 will be marked as a bad storage cell as long as there is one bad point address that cannot be repaired.

[0057] For example, please refer to Figure 2, the capacity of one block of the memory stack 3 is 32 Mbit (for example, the area formed by the intersection of 16 kbit word lines WL and 2 kbit bit lines BL). This block is divided into upper 16 Mbit and lower 16 Mbit. The capacity of the minimum management unit of the bad cell management module 21 for the memory stack 3 is 16 Mbit (that is, one memory cell includes 16 Mbit storage addresses). When the memory stack 3 has 8 stacked memory wafers wafer0~wafer7 (i.e., "8-layer memory die"), each layer of memory die has 20 blocks U0~U19. The memory stack 3 has a total of 160 blocks (32 Mbit), that is, 320 memory cells unit (320 * 16 Mbit storage addresses). The built-in self-test unit 211 tests 320 16 Mbit memory cells (DRAM unit). When there are finally 302 16 Mbit good memory cells after testing, the bad cell management module 21 can allocate and map the address ranges of these 302 16 Mbit good memory cells to 4 main device interfaces 20_0~20_3 according to the current configuration mode. For example, it can be allocated and mapped to 4 main device interfaces 20_0~20_3 by allocating 75, 75, 76, 76 16 Mbit good memory cells according to the capacity priority mode, or by allocating 75, 75, 75, 75 16 Mbit good memory cells according to the bandwidth priority mode, or, by allocating 75, 75, 75, 77 16 Mbit good memory cells according to a mode that takes both bandwidth and capacity into account and allocating and mapping them to 4 main device interfaces 20_0~20_3, or by allocating 80, 80, 80, 62 16 Mbit good memory cells according to another mode that takes both bandwidth and capacity into account and allocating and mapping them to 4 main device interfaces 20_0~20_3.

[0058] Further optionally, please refer to Figure 3 , in the embodiment where the memory stack 3 is a multi-layer stacked DRAM die, the memory controller 2 is disposed in Figure 3 the buffer die 200 of Figure 3In the logic die 100, corresponding circuits such as the built-in self-test unit 211, the recording unit 210, and the mode register 212 in the defective unit management module 21 can be formed in the buffer die 200, and the logic die 100 and the buffer die 200 can be integrated in the same plane or integrated in a three-dimensional stacked manner through structures such as through-silicon vias (TSVs). It should be noted that, in some embodiments, the memory controller 2 is only a part of the buffer die 200. In other embodiments, as an interface between the logic die 100 and the memory stack 3, the buffer die 200 may further include input / output (IO) circuits, etc. The buffer die 200 may also be referred to as an interface die or a base die.

[0059] In the memory controller 2 of this embodiment, the defective unit management module 21 can adaptively allocate and map the address range of the good memory units in the memory area to be accessed in the memory stack 3 to the m master device interfaces 20_0~20_m-1 according to the currently selected configuration mode (i.e., the current configuration mode) and the current good / bad information of each memory unit in the memory area to be accessed in the memory stack 3. That is, the mapping relationship between the address range of the good memory units in the memory area to be accessed in the memory stack 3 and the m master device interfaces 20_0~20_m-1 can change with the change of the current configuration mode, so as to realize the dynamic remapping relationship between the address range of the good memory units in the memory area to be accessed in the memory stack 3 and the m master device interfaces 20_0~20_m-1. Thus, after the memory stack 3 is manufactured or delivered to the customer, it can support the flexible adjustment requirements of the user's logic die 100 for the memory stack 3, and further meet the user's requirements for various usage scenarios.

[0060] It should be understood that, in addition to the above-mentioned master device interfaces 20_0~20_m-1 and the defective unit management module 21, the memory controller 2 of this embodiment may also have other control logic modules 22 for implementing other functions. The other control logic modules 22 may include circuits for performing a refresh operation on the memory, circuits for correcting errors in the memory (such as ECC correction), circuits for implementing timing constraint rules (such as a phase-locked loop PLL), circuits for managing power consumption and temperature, first-in-first-out queue registers (fifo), etc., any required circuits. These circuits are not the focus of the present invention, so they will not be described in detail here. Please continue to refer to Figure 3 The other control logic modules 22 and corresponding circuits such as the built-in self-test unit 211 in the defective unit management module 21 are formed in the buffer die 200 together.

[0061] In addition, the division of each module such as the master device interfaces 20_0 to 20_m-1, the bad cell management module 21, and other control logic modules 22 in the storage controller 2 of this embodiment is illustrative and mainly a logical function division. There may be other division methods in actual implementation. Each functional unit in the embodiments of this application may be integrated in a processing module, or each module may exist physically alone, or two or more modules may be integrated in a module. The above-mentioned integrated modules may be implemented in whole or in part through software, hardware, firmware, or any combination thereof. When implemented using software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present invention are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired manner (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more integrated available media. The available medium may be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as an SSD), etc.

[0062] Optionally, please refer to Figures 1 to 3 , the memory stack 3 includes k + 1 layers of memory dies 300 to 30k stacked three-dimensionally, where k is an integer and k≥1, the storage controller 2 is disposed in the buffer die 200, and the master device 1 is disposed in the logic die 100. Any suitable packaging technology such as chip-on-wafer (COW) packaging technology, wafer-on-wafer (WOW) packaging, or chip-on-chip (COC) packaging technology can be used to package the memory stack 3, the buffer die 200, and the logic die 100 together to form a memory product.

[0063] For example, the buffer die 200 and the logic die 100 can be stacked with the k + 1 layers of memory dies 300 to 30k using through-silicon vias (TSVs), thereby expanding the capacity of the memory stack 3 managed by the storage controller 2.

[0064] In one example, the logic die 100 is stacked on the substrate 400, the buffer die 200 is stacked on the logic die 100 by using Through-Silicon Via (TSV) and Hybrid Bonding technologies, the memory die 300 is stacked on the buffer die 200 through TSV, and the remaining upper memory dies are stacked on the lower memory dies through TSV. In the memory stack 3, the k + 1 layers of memory dies 300 to 30k are vertically stacked together, which has great advantages in terms of the wiring, bandwidth, and latency of the memory stack 3. It not only saves space, but also can bring a shorter chip pitch, thereby shortening the signal transmission path and latency. It uses the TSV technology to perforate the edge or specific positions of the memory die, and uses these holes as the path for wiring to complete the vertical interconnection between the memory dies and between them and the buffer die 200, as well as the vertical interconnection between the buffer die 200 and the logic die 100, etc.

[0065] If each layer of memory die (i.e., corresponding to one layer of wafer) has n storage units with the same capacity, then there are a total of n*(k + 1) storage units with the same capacity on the memory stack 3. The bad cell management module 21 can adaptively allocate the address range of the good storage units among the n*(k + 1) storage units with the same capacity according to the current configuration mode, and map them to m master device interfaces 20_0 to 20_m-1. Among them, when the bad cell management module 21 can centrally map the address ranges of the good storage units on the same memory die to the same master device interface, if the master device interfaces 20_0 to 20_m-1 work independently, then the memory dies corresponding to the master device interfaces are also independent of each other.

[0066] Exemplarily, each of the memory dies 300 to 30k is a DRAM die. The bad cell management module 21 can manage each layer of DRAM die from the point (i.e., cell level) to the storage unit level, and can replace the storage address at the bad point level with the address of the internal redundant cell. A storage unit is only determined to be a bad cell when all its redundant cells are used up and there are still excessive bad points.

[0067] Please refer to Figures 1 to 4 , an embodiment of the present invention further provides a three-dimensional stacked memory, which includes a memory stack 3 and a storage controller 2 as described in the present invention. The storage controller 2 is disposed on the buffer die 200. The memory stack 3 includes k + 1 layers of three-dimensionally stacked memory dies 300 to 30k, and the k + 1 layers of memory dies 300 to 30k and between them and the buffer die 200 are hybrid bonded through TSV.

[0068] In summary, the storage controller and the three-dimensional stacked memory provided by the present invention can implement a dynamic remapping relationship between the address ranges of all good memory cells in the storage area to be accessed of the memory stack body and multiple master device interfaces according to the change of the current configuration mode and the good and bad information of each memory cell in the storage area to be accessed of the memory stack body (which can be the storage area commonly used by the user. The storage area commonly used by the user can be a part of the storage space of the memory stack body or all of the storage space). Thus, after the three-dimensional stacked memory is shipped and applied, it can still support the user's flexible adjustment requirements for the three-dimensional stacked memory, and further meet the user's requirements for various usage scenarios. For example, it supports the user to decide whether to maintain capacity or bandwidth during the use of the three-dimensional stacked memory, so that the user can adapt to different usage scenarios and ensure the maximum utilization of the storage resources of the memory; for another example, it supports the usage scenario where the user only accesses a certain area of the three-dimensional stacked memory and does not access other areas.

[0069] Furthermore, the storage controller and the three-dimensional stacked memory can also support the user to perform built-in self-test on the three-dimensional stacked memory after shipment and mark bad memory cells when newly discovered bad memory cells are found, so that the user can have real-time control over the health status of the three-dimensional stacked memory, and then change the current configuration method in a timely manner according to needs.

[0070] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure are within the protection scope of the technical solution of the present invention.

Claims

1. A memory controller coupled between a host device and a memory stack, wherein the memory stack comprises a plurality of memory bare cores, each of the memory bare cores comprises a plurality of memory cells, characterized in that: The storage controller comprises: A plurality of master device interfaces, used for communicating with the master device, wherein each master device interface is a multi-IO parallel interface; a bad unit management module, coupled to the plurality of master device interfaces, and used to map the address ranges of the corresponding good storage units in the to-be-accessed storage area to the corresponding master device interfaces respectively according to the current configuration mode and the current good and bad information of each storage unit in the to-be-accessed storage area of ​​the memory stack; Among them, the storage controller provides multiple configuration modes to cope with different usage scenarios, the current configuration mode is selected from the multiple configuration modes, and the mapping relationship between the address range of the good storage unit in the storage area to be accessed and the multiple master device interfaces changes with the change of the current configuration mode.

2. The storage controller according to claim 1, wherein: The number of the plurality of master device interfaces is m, where m is an integer greater than 1, and the configuration mode includes at least two of the following (1) to (3): (1) Bandwidth priority mode: m master device interfaces are used simultaneously, and the bad unit management module divides the address range of all good storage units in the storage area to be accessed by m, and then maps them to each of the master device interfaces in an evenly distributed manner; (2) Capacity priority mode: each of the master device interfaces is used separately, and the bad unit management module maps the address range of all good storage units in the storage area to be accessed to m master device interfaces accordingly, so that all good storage units in the storage area to be accessed can be accessed by the master device; (3) Bandwidth and capacity balance mode: a of the master device interfaces are used simultaneously, b of the master device interfaces are used individually, and a+b=m, wherein the bad unit management module maps the address ranges of all good storage units in the storage area to be accessed to the m master device interfaces accordingly, and the address ranges of the good storage units mapped by a of the master device interfaces are the same in size.

3. The storage controller according to claim 2, wherein: In the capacity priority mode, under the premise of not exceeding the maximum limit of the master device interface, the bad unit management module centrally maps the address range of the bad storage units in the storage area to be accessed to the same master device interface; And / or, in the bandwidth and capacity balance mode, the bad unit management module maps the address range of all bad storage units in the storage area to be accessed to at least one master device interface of the b master device interfaces.

4. The storage controller according to any one of claims 1 to 3, characterized in that: The bad unit management module includes a recording unit for storing the current good and bad information; and / or the memory bare core is a DRAM bare core, and the main device interface is an AXI interface or a CHI interface or an AHB interface.

5. The storage controller according to claim 4, wherein: The current good and bad information includes the current number and address range of good storage units and the number and address range of bad storage units in the storage area to be accessed, and the current good and bad information is obtained based on the bad point address information of the memory stack when it leaves the factory, or based on the bad point address information updated on the basis of the bad point address information of the memory stack when it leaves the factory; wherein the bad point address information of the memory stack when it leaves the factory is obtained by performing a bad point test on the memory stack before it leaves the factory.

6. The storage controller according to claim 5, characterized in that: The bad cell management module updates the bad pixel address information based on the bad pixel address information of the memory stack when it leaves the factory, including at least one of the following (1) to (2): (1) when the number of errors of a certain storage address or a certain storage address exceeds a threshold value during the use of the memory stack, the certain storage address or the certain storage address is used as a new bad pixel address, so as to update the bad pixel address information based on the bad pixel address information of the memory stack when it leaves the factory; (2) The bad cell management module also includes a built-in self-test unit, which performs a built-in self-test on the memory stack after the memory stack leaves the factory to detect new bad pixel addresses generated in the memory stack, and then updates the bad pixel address information based on the bad pixel address information of the memory stack when it leaves the factory.

7. The storage controller according to claim 6, wherein: The bad cell management module is further used to determine whether the number of unrepaired bad pixel addresses contained in the storage unit where the new bad pixel address is located is greater than or equal to a corresponding threshold after updating the bad pixel address information, and if so, mark the storage unit where the new bad pixel address is located as a bad storage unit to update the current good and bad information, and if not, the storage unit where the new bad pixel address is located is still reserved as a good storage unit; When the new bad storage unit is marked, the current good or bad information is updated.

8. The storage controller according to claim 7, wherein: Each of the storage units is configured with redundant resources; The bad cell management module is also used to determine whether the new bad point address can be redundantly repaired using the corresponding redundant resources after obtaining the new bad point address and before determining whether the number of unrepaired bad point addresses contained in the storage unit where the new bad point address is located is greater than or equal to the corresponding threshold. If so, the new bad point address is redundantly repaired using the corresponding redundant resources.

9. The storage controller according to claim 4, wherein: The storage controller is arranged in the buffer bare core, the main device is located in the logic bare core, and the logic bare core and the buffer bare core are integrated in the same plane or integrated together in a three-dimensional stacking manner.

10. The storage controller according to claim 9, wherein: The plurality of memory bare cores in the memory stack are stacked together in a three-dimensional stacking manner, and the buffer bare core is integrated with the memory stack in a three-dimensional stacking manner using through silicon vias.

11. The storage controller according to any one of claims 1 to 3 and 5 to 10, characterized in that: The bad cell management module further includes a mode register for configuring the multiple configuration modes and selecting the current configuration mode from the multiple configuration modes.

12. The storage controller according to any one of claims 1 to 3 and 5 to 10, characterized in that: The memory stack is divided into multiple storage areas, and the multiple memory bare cores in each storage area share row addresses and column addresses. Each storage area serves as a sub-storage system and corresponds to a group of multiple master device interfaces and a bad unit management module to implement molecular system management of the memory stack.

13. A three-dimensional stacked memory, characterized in that: It comprises a memory stack and a memory controller as described in any one of claims 1 to 12, wherein the memory controller is arranged in a buffer bare core, and the memory stack comprises three-dimensionally stacked multi-layer memory bare cores, wherein the multi-layer memory bare cores are hybrid bonded to each other and to the buffer bare core through silicon vias.

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