System-level verification method and test system for RISC-V reconfigurable multi-core processor chip

Abstract

The embodiment of the invention relates to the technical field of integrated circuits, in particular to a system-level verification method and test system for an RISC-V reconfigurable multi-core processor chip, and the method comprises the steps: firstly, verifying a hardware state; the hardware state comprises core configuration of the reconfigurable multi-core processor, internal storage, interruption, states of a plurality of cores and configuration of a control state register; then, verifying the basic software; the verification of the basic software comprises the following steps of: lightening a chip of the reconfigurable multi-core processor, starting an operating system, and verifying bottom-layer driving software and a board-level support package; and finally, verifying cooperative work of the upper software and the multi-core chip software and hardware system. According to the system-level verification method provided by the embodiment of the invention, verification of a system-level peripheral scheme and verification of basic software adaptation are carried out on the RISC-V reconfigurable multi-core processor chip by simulating related hardware peripherals, and compatibility and continuous optimization between software and hardware are ensured.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of integrated circuit technology, and particularly to a system-level verification method and a test system for a RISC-V reconfigurable multi-core processor chip. Background Art

[0002] RISC-V is an open-source reduced instruction set architecture, with a completely open-source compiler, development tools, and software development environment. Any group or company can use it for hardware or software development and design free of charge. Compared with the expensive ARM architecture and Intel's x86 architecture, RISC-V has various advantages such as modularity, fewer instructions, open source, and free of charge. With the open ecosystem, flexibility, and high customizability brought by open source, the RISC-V open instruction set architecture has become a new choice for building a computing ecosystem.

[0003] Since the current mainstream chip instruction set architectures are ARM and x86, as a relatively new instruction set architecture, the development of the related software and hardware ecosystem of RISC-V is relatively poor. The current pain point is the lack of software and hardware that can adapt to the RISC-V architecture. Many applications have not been optimized and adapted on the RISC-V architecture, and a large number of experiments and tests are required to complete the adaptation. The traditional verification methods through external devices such as FPGAs and development boards require a lot of development work, resulting in slow speed and high cost. There is still a lack of a fast, effective, and low-cost verification method for RISC-V reconfigurable multi-core processor chips. Summary of the Invention

[0004] The embodiments of the present application provide a system-level verification method and a test system for a RISC-V reconfigurable multi-core processor chip. By simulating relevant hardware peripherals, the system-level verification of the peripheral solution and the verification of the basic software adaptation of the RISC-V reconfigurable multi-core processor chip are carried out to ensure the compatibility and continuous optimization between software and hardware.

[0005] To solve the above technical problems, in a first aspect, the embodiments of the present application provide a system-level verification method for a RISC-V reconfigurable multi-core processor chip, including the following steps: First, verify the hardware status; the hardware status includes: the core configuration of the reconfigurable multi-core processor, memory, interrupts, the status of multiple cores, and the control status register configuration; then, verify the basic software; verifying the basic software includes: turning on the chip of the reconfigurable multi-core processor and starting the operating system, and verifying the underlying driver software and the board support package; finally, verify the upper-layer software and the coordinated operation of the multi-core chip software and hardware system.

[0006] In some exemplary embodiments, verifying the hardware status includes: Step 1: Design a virtual development board and peripherals according to the chip under test, and write relevant codes for the core settings of the reconfigurable multi-core processor, the virtual development board, and the peripherals based on Qemu; Step 2: Run Qemu to test whether the virtual development board can work properly. If not, return to Step 1; if so, proceed to Step 3; Step 3: Query in Qemu whether the peripherals can be recognized. If not, return to Step 1; if so, perform the next processing.

[0007] In some exemplary embodiments, verifying the basic software includes: Step 4: Design the basic software, drivers, and various board support packages, and perform configurations related to the startup of the operating system; Step 5: Verify whether the basic software and the operating system can run properly. If not, return to Step 4; if so, perform the next processing.

[0008] In some exemplary embodiments, in Step 4, based on the multi-level startup boot model of the RISC-V processor, perform configurations related to the startup of the operating system.

[0009] In some exemplary embodiments, in Step 5, the method for verifying whether the basic software and the operating system can run properly includes: verifying and analyzing by analyzing the logs of the startup of the operating system and the basic software.

[0010] In some exemplary embodiments, verifying the upper-layer software and the coordinated operation of the multi-core chip software and hardware system includes: Step 6: Run a benchmark test program to evaluate the performance of the chip under test; Step 7: Verify whether the application software can run. If it cannot run, return to Step 6 to troubleshoot the cause and run the benchmark test program again; Check whether the application software can run by analyzing the running logs of the application software; Step 8: According to the verification results of the benchmark test in Step 7, perform software and hardware co-optimization.

[0011] In some exemplary embodiments, the benchmark test program is a general processor benchmark test program, or uses the basic applications of the reconfigurable multi-core processor for testing; when testing the display supported by the chip under test, the benchmark test program includes basic tests of the display and the graphical interface.

[0012] In a second aspect, an embodiment of the present application provides a test system for a RISC-V reconfigurable multi-core processor chip, including: a benchmark program, a software launcher, an operating system, a virtual development board and its peripherals, a chip under test interface, and a chip under test that are connected in sequence; the virtual development board and its peripherals, the chip under test interface, and the chip under test are used to implement the first-stage verification; the first-stage verification includes: verifying the hardware state; the hardware state includes: the core configuration of the reconfigurable multi-core processor, memory, interrupts, the states of multiple cores, and the control status register configuration; the software launcher, the operating system, the virtual development board and its peripherals, the chip under test interface, and the chip under test are used to implement the second-stage verification; the second-stage verification includes: verifying the basic software; the verification of the basic software includes: turning on the chip of the reconfigurable multi-core processor and starting the operating system, and verifying the underlying driver software and the board support package; on the basis of the success of the first-stage verification and the second-stage verification, the third-stage verification is completed through the benchmark program; the third-stage verification includes: verifying the upper-layer software and the coordinated operation of the multi-core chip software and hardware system.

[0013] In some exemplary embodiments, the chip under test is used to extract the attributes of the actual chip under test, and based on the Qom mechanism of Qemu, the basic attributes of the chip under test are extracted and simulated; the chip under test interface provides a software interface layer for the chip under test and the basic test platform; the virtual development board and its peripherals are designed and implemented based on Qemu, and are used to provide the necessary peripheral conditions and virtual hardware environment for chip startup.

[0014] In some exemplary embodiments, the software launcher and the operating system are used to provide the basic software and operating system environment for chip startup and lighting; the benchmark program provides software-level benchmark performance testing and functional testing, and the completion of the test vectors of the benchmark program can effectively evaluate whether the performance of the chip under test can meet the basic design requirements.

[0015] The technical solution provided by the embodiment of the present application has at least the following advantages:

[0016] An embodiment of the present application provides a system-level verification method and test system for a RISC-V reconfigurable multi-core processor chip. The method includes the following steps: First, verify the hardware state; the hardware state includes: the core configuration of the reconfigurable multi-core processor, memory, interrupts, the states of multiple cores, and the control status register configuration; then, verify the basic software; the verification of the basic software includes: turning on the chip of the reconfigurable multi-core processor and starting the operating system, and verifying the underlying driver software and the board support package; finally, verify the upper-layer software and the coordinated operation of the multi-core chip software and hardware system.

[0017] In view of the current situation that the test cycle required for the system test of a processor chip system is long, the verification efficiency is low, and the function test is not comprehensive enough, this application proposes a system-level verification method and test system for a RISC-V reconfigurable multi-core processor chip. Compared with FPGA or other traditional verification methods, the software virtualization method can eliminate physical processes such as PCB design, board making, and peripheral welding, and can achieve system simulation more quickly, environmentally friendly, and economically. The simulation efficiency using virtualization is also greatly improved compared with FPGA simulation. The experimental results of simulation verification can be given within only 1 day, which is more convenient and fast.

[0018] In addition, the method provided by this application allows users to customize the development and quickly perform co-verification of the chip's software and hardware systems for chip functions, and verify the unreasonable parts of the preliminary design of the processor system to assist in rapid design iteration, greatly shortening the test verification process and speed of the multi-core heterogeneous chip, shortening the market cycle of the multi-core heterogeneous chip, and accelerating its iteration rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments. Unless otherwise stated, the figures in the drawings do not constitute a proportional limitation.

[0020] Figure 1 It is a schematic flowchart of a system-level verification method for a RISC-V reconfigurable multi-core processor chip provided by an embodiment of this application;

[0021] Figure 2 It is a structural block diagram of a test verification system for a RISC-V reconfigurable multi-core processor chip provided by an embodiment of this application;

[0022] Figure 3 It is a schematic flowchart of a test verification system for a RISC-V reconfigurable multi-core processor chip provided by an embodiment of this application;

[0023] Figure 4 It is a code example diagram for initializing a reconfigurable multi-core processor in the first-stage verification provided by an embodiment of this application;

[0024] Figure 5 It is a schematic structural diagram of a hardware system provided by an embodiment of this application;

[0025] Figure 6 It is a schematic startup flowchart of the second-stage verification provided by an embodiment of this application;

[0026] Figure 7 It is a verification result diagram of the first-stage verification (taking the serial port as an example) provided by an embodiment of this application;

[0027] Figure 8 Verification result diagram of the second-stage verification (taking general startup as an example) provided by an embodiment of the present application. Detailed implementation manners

[0028] As can be seen from the background art, the existing software and hardware adaptable to the RISC-V architecture are insufficient, and many applications have not been optimized and adapted on the RISC-V architecture. Completing the adaptation requires a large amount of experiments and tests. The traditional verification method using external devices such as FPGAs and development boards has a lot of development work, resulting in slow speed and high cost. At present, there is still a lack of a fast, effective and low-cost verification method for RISC-V reconfigurable multi-core processor chips.

[0029] RISCV processors usually provide three modes: M-mode (Machine Mode), S-mode (Supervisor Mode), and U-mode (User Mode). Among them, Machine Mode (M-mode) is the bottom layer mode and is a mode that every standard RISC-V processor must implement. It has the highest privilege, which means it will run directly on the hardware using physical addresses. When the CPU is powered on, it will be in M-mode. The machine mode has the ability to intercept and handle exceptions and can access all control status registers (CSRs) in other modes. Programs running in M-mode are essentially trusted because they have full access to the machine implementation. M-mode is usually used to manage the secure execution environment on RISCV. Generally, the SBI firmware runs in M-mode to provide this service for the operating system. Supervisor Mode (S-mode): Supervisor Mode (S-mode) is two levels above Machine Mode (M-mode). User Mode (U-mode): In this mode, it is in the user space and runs user programs. The privilege level of U-mode is the lowest, and it usually runs application programs.

[0030] Parallel computing is a key technology for handling complex computational problems and large-scale data processing tasks. As the demand for computing power in scientific research and industrial applications grows, traditional serial computing (where a single processor executes tasks sequentially) can no longer meet these needs. Parallel computing significantly improves processing speed and efficiency by using multiple processors (or computing nodes) simultaneously to execute computational tasks. This computing method plays a crucial role in fields such as scientific simulations, data analysis, image processing, and large-scale computer graphics processing. Parallel computing is a key technology for handling complex computational problems and large-scale data processing tasks. As the demand for computing power in scientific research and industrial applications grows, traditional serial computing (where a single processor executes tasks sequentially) can no longer meet these needs. Parallel computing significantly improves processing speed and efficiency by using multiple processors (or computing nodes) simultaneously to execute computational tasks. This computing method plays a crucial role in fields such as scientific simulations, data analysis, image processing, and large-scale computer graphics processing.

[0031] The Reconfigurable Multi Core System (RMCS) is an important technical branch in the development of multi-core systems on a chip and is also one of the important solutions for parallel computing. Reconfigurable multi-core is an SoC design solution that combines the advantages of high speed and low power consumption of ASICs and the flexibility of software programming of general-purpose processors. RMCS generally uses programmable hardware to integrate a large number of controllable IPs to achieve, and its specific functions depend on the configuration rules of the programmable IPs. RMCS can integrate and configure a variable number of heterogeneous computing resources and on-chip shared storage resources according to requirements, and can reconfigure the underlying hardware through software programming in different application scenarios to form an algorithm-specific circuit structure, achieving a good balance in terms of speed and flexible configuration. The large number of reconfigurable IP core arrays at its bottom layer determines that it is more suitable for data access-regular Computation Intensive tasks than general-purpose processors. The hardware-level reconfiguration technology of RMCS blurs the division of labor between software and hardware in the computing system. While retaining the advantages of ASIC specialization and high speed, it solves the problem of single application scenarios of ASICs by using multiple reconfiguration modes of the on-chip computing core array; RMCS retains software programming based on general-purpose processors as a means of hardware configuration, and under the premise of greatly improving the system's computing performance, achieves general adaptation and flexible switching in multiple types of intensive computing scenarios.

[0032] The system-level test and verification of current reconfigurable multi-core chips face many challenges. Existing technologies are all targeted at the instruction set architectures of ARM and x86, and no verification solutions for the RISC-V architecture have been proposed yet. Secondly, for reconfigurable multi-core processors, the efficient collaborative work between different cores and the consistency test of each interface and peripheral are also crucial. At the same time, due to the complexity of the system, ensuring the compatibility between software and hardware and continuous optimization are also important purposes of system-level testing.

[0033] Among them, a related technology designed a RomCode with functions such as clock control, multi-core startup, and image migration for the multi-core ARM processor SoC chip. To ensure the stability and correctness of the RomCode design, FPGA prototype verification was completed based on Palladium and Haps. The verification results show that the designed RomCode functions normally and runs stably, improving the chip tape-out success rate, accelerating the software development progress, and effectively supporting the function verification of other modules of the SoC chip. However, this technology is carried out based on the ARM instruction set and does not verify the feasibility of the RISC-V instruction set. Another related technology provides a method, a host computer, and a storage medium for debugging external devices based on Qemu, aiming to improve the efficiency, convenience, and accuracy of simulating the hardware environment of external devices and reduce the probability of hardware damage during the debugging of external devices. However, this method does not consider the complexity of multi-core system collaborative testing and cannot perform system-level testing of software and hardware collaboration on the chip.

[0034] In response to the problems raised by the existing technologies, the existing FPGA method is used for verification. The FPGA model provides accurate and fast simulation, but due to the long synthesis and routing time, it is more challenging to modify. The functional-level models (such as Spike, QEMU) are fast and easy to modify in simulation, and the simulation granularity can penetrate into the processor internal to meet the basic function verification requirements. Therefore, the embodiments of this application provide a system-level verification method for a RISC-V reconfigurable multi-core processor chip, and use a functional-level model (Qemu) to perform rapid prototype verification on the prototype system composed of the reconfigurable multi-core processor chip.

[0035] In addition, the existing methods do not take into account the problem of software and hardware collaboration, and do not take into account the collaborative complexity of the software and hardware system of the reconfigurable multi-core processor. Due to the complexity after the integration of the software and hardware system, a lot of manpower and material resources are often wasted to troubleshoot problems. In view of this feature, the embodiment of the present application adopts a multi-level verification method when designing the verification platform, and verifies the multi-core chip in stages by means of software virtual hardware peripherals, underlying software and operating system, and upper-level application verification, and the adaptation of the underlying basic software can be completed through virtual peripherals to build a richer application system. Compared with the prior art, it has better flexibility and can freely configure the number of cores and peripherals in the reconfigurable multi-core processor. And it can verify the functional operation of the upper-level application software on the platform, and according to the results of the verification, the core configuration and peripheral configuration of the reconfigurable multi-core processor are optimized in a targeted manner.

[0036] In order to solve the above technical problems, the embodiment of the present application provides a system-level verification method and test system for a RISC-V reconfigurable multi-core processor chip, which includes the following steps: first, verify the hardware status; the hardware status includes: the core configuration, memory, interrupt, status of multiple cores and control status register configuration of the reconfigurable multi-core processor; then, verify the basic software; verify the basic software includes: lighting up the chip of the reconfigurable multi-core processor and starting the operating system, verifying the underlying driver software and board support package; finally, verifying the upper-layer software and the collaborative work of the multi-core chip hardware and software system. The embodiment of the present application provides a system-level verification method and test system for a RISC-V reconfigurable multi-core processor chip, which verifies the system-level peripheral solution and basic software adaptation of the RISC-V reconfigurable multi-core processor chip by simulating related hardware peripherals, ensuring compatibility and continuous optimization between hardware and software. The present application also builds a test verification system through Qemu to provide a realistic peripheral environment for the chip to be tested, and tests and verifies the functions of the chip to be tested, evaluates performance and optimizes design by running test cases.

[0037] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present application can be implemented.

[0038] refer to Figure 1 The present application embodiment provides a system-level verification method for a RISC-V reconfigurable multi-core processor chip, comprising the following steps:

[0039] Step S1: Verify the hardware status; the hardware status includes: the core configuration of the reconfigurable multi-core processor, memory, interrupts, the status of multiple cores, and the control status register configuration.

[0040] Step S2: Verify the basic software; verifying the basic software includes: turning on the chip of the reconfigurable multi-core processor and starting the operating system, and verifying the underlying driver software and board support package.

[0041] Step S3: Verify the upper-layer software and the coordinated operation of the multi-core chip software and hardware system.

[0042] In some embodiments, verifying the hardware status in step S1 includes the following steps:

[0043] Step 1: Design a virtual development board and peripherals according to the chip to be tested, and write relevant code for the core settings of the reconfigurable multi-core processor, the virtual development board, and the peripherals based on Qemu.

[0044] Step 2: Test whether the virtual development board can work properly by running Qemu. If not, return to step 1; if so, proceed to step 3.

[0045] Step 3: Query whether the peripherals can be recognized in Qemu. If not, return to step 1; if so, proceed to the next process.

[0046] In some embodiments, verifying the basic software in step S2 includes:

[0047] Step 4: Design the basic software, drivers, and various board support packages, and perform configurations related to the startup of the operating system.

[0048] Step 5: Verify whether the basic software and the operating system can run properly. If not, return to step 4; if so, proceed to the next process.

[0049] In some embodiments, in step 4, based on the multi-level startup boot model of the RISC-V processor, perform configurations related to the startup of the operating system.

[0050] In some embodiments, in step 5, the method for verifying whether the basic software and the operating system can run properly includes: verifying and analyzing by analyzing the logs of the startup of the operating system and the basic software.

[0051] In some embodiments, verifying the upper-layer software and the coordinated operation of the multi-core chip software and hardware system in step S2 includes the following steps:

[0052] Step 6: Run a benchmark program to evaluate the performance of the chip to be tested.

[0053] Step 7. Verify whether the application software can run. If it cannot run, return to Step 6 to troubleshoot the cause and run the benchmark program again; check whether the application software can run by analyzing the running log of the application software.

[0054] Step 8. Perform co-optimization of software and hardware according to the verification results of the benchmark test in Step 7.

[0055] In some embodiments, the benchmark program is a general-purpose processor benchmark program or uses the basic applications of a reconfigurable multi-core processor for testing; when testing the display supported by the chip under test, the benchmark program includes basic tests for display and graphical interface.

[0056] It should be noted that the benchmark program can be a type of application program supported by the chip under test. The benchmark program can use general-purpose processor benchmark programs such as spec int 2006 or use the basic applications of the designed reconfigurable multi-core processor for testing.

[0057] For example, if the chip under test supports display, the benchmark program should include basic tests for display and graphical interface. The benchmark program should be written to be repeatable to obtain accurate measurement results. Variables should be controlled during testing, such as closing unnecessary background processes to reduce the influence of external factors. Finally, execute the test, collect data, and analyze the results to identify performance bottlenecks or verify the performance improvement of the system.

[0058] See Figure 2 , the embodiment of the present application provides a test system for a RISC-V reconfigurable multi-core processor chip, including: a benchmark program, a software launcher, an operating system, a virtual development board and its peripherals, a chip under test interface, and a chip under test that are connected in sequence; the virtual development board and its peripherals, the chip under test interface, and the chip under test are used to implement the first-stage verification; the first-stage verification includes: verifying the hardware status; the hardware status includes: the core configuration of the reconfigurable multi-core processor, memory, interrupts, the status of multiple cores, and the control status register configuration; the software launcher, the operating system, the virtual development board and its peripherals, the chip under test interface, and the chip under test are used to implement the second-stage verification; the second-stage verification includes: verifying the basic software; the verification of the basic software includes: turning on the chip of the reconfigurable multi-core processor and starting the operating system, and verifying the underlying driver software and board support package; on the basis of the success of the first-stage verification and the second-stage verification, the third-stage verification is completed through the benchmark program; the third-stage verification includes: verifying the upper-layer software and the collaborative work of the multi-core chip software and hardware system.

[0059] In some embodiments, the chip under test is used to extract the attributes of the real chip under test. Based on the Qom mechanism of Qemu, the basic attributes of the chip under test are extracted for simulation. The chip under test interface provides a software interface layer for the chip under test and the basic test platform. The virtual development board and its peripherals are designed and implemented based on Qemu, and are used to provide the necessary peripheral conditions and virtual hardware environment for chip startup.

[0060] In some embodiments, the software launcher and the operating system are used to provide the basic software and operating system environment for chip startup and lighting. The benchmark test program provides benchmark performance tests and functional tests at the software level. Using this benchmark test program as a test vector, the performance of the chip under test can be effectively evaluated based on the completion of this test vector to determine whether it can meet the basic design requirements.

[0061] When designing this system verification platform, a multi-level verification method is adopted. The multi-core chip is verified in stages by verifying software virtual hardware peripherals, underlying software and operating system, and upper-layer applications. The underlying basic software can be adapted through virtual peripherals to build a richer application system. Based on the many problems existing in the above-mentioned multi-core heterogeneous chip test and verification, the basic content of the present invention constructs a test system as Figure 2 shown. The test system is mainly composed of five parts: the chip under test, the chip under test interface, the virtual development board and its peripherals, the software launcher and the operating system, and the benchmark test program.

[0062] The above system mainly has the following three functions and can complete chip testing and verification in three stages respectively:

[0063] The first stage of verification: mainly the verification of the hardware state; for the characteristics of the reconfigurable multi-core processor, verify the core configuration, memory, interrupts, states of multiple cores, and control status register configuration of the reconfigurable multi-core processor;

[0064] The second stage of verification: mainly the verification of the basic software; on the basis of the successful verification in the first stage, verify the chip lighting, startup of the operating system, basic software functions such as underlying driver software and board support package for the chip of the reconfigurable multi-core processor;

[0065] The third stage of verification: mainly the verification of the upper-layer software and the coordinated operation of the multi-core chip software and hardware system; on the basis of the successful verification in the first and second stages, perform simulation verification on whether the upper-layer software with corresponding functions can run on the reconfigurable multi-core processor, and adapt and optimize the upper-layer software system for virtual hardware and operating system, so that it can finally run on real hardware.

[0066] QEMU (Quick Emulator) is an open-source virtualization software that provides hardware-level virtualization support. It adopts advanced virtualization technologies, has high operating efficiency, good stability, and supports multiple architectures. QEMU can simulate multiple processor architectures, such as x86, ARM, RISC-V, etc., enabling it to run operating systems and programs designed for another hardware architecture on one type of hardware. At the same time, QEMU is open-source software with clear module division, a stable core architecture, and a highly active development community, which can be used for the design of customized multi-core heterogeneous test and verification platforms.

[0067] The system and method described in this invention run on the Ubuntu22.04 platform, and its Qemu version is Qemu8.1.0. It mainly includes the verification of hardware status, the verification of basic software, and the functional verification of the upper-layer software and the cooperation between multi-core chips' software and hardware, such as Figure 3 As shown, the overall working steps of the system are as follows:

[0068] The verification work in the first stage:

[0069] Step 1: Design a virtual development board and peripherals according to the chip under test, and write relevant codes for the core settings of the reconfigurable multi-core processor, the virtual development board, and the peripherals based on Qemu.

[0070] Among them, the core of the reconfigurable multi-core processor should write relevant codes in Qemu. Adopting the object-oriented design idea, inherit the basic SysBusDevice attribute and create a new SoC and initialize it. When initializing, the maximum number of cores, the minimum number of cores, and the default number of cores of the reconfigurable multi-core processor should be specified. At the same time, for the number of computing CPUs and scheduling CPUs in the reconfigurable multi-core processor, the method of macro definition is used for setting.

[0071] For example, in Figure 5 , Core0 is a scheduling CPU, while Core1 - Core7 are CPUs dedicated to computing; the macro definition can be carried out when initializing the SoC, as shown in the following code:

[0072] #define management_cpu_count 1

[0073] #define compute_cpu_count 7

[0074] After defining the type of the reconfigurable multi-core processor, it is also necessary to initialize it. The initialization can refer to Figure 4As shown in the code, the object_property_set_str() function will perform basic type settings on each core of the reconfigurable multi-core processor to ensure its alignment and consistency with the verified hardware properties.

[0075] The peripheral solution should be a minimum system that can complete the basic functions of the chip under test, generally including devices such as Universal Asynchronous Receiver / Transmitter (UART), Ethernet (Eth), and Serial Peripheral Interface (SPI).

[0076] As Figure 5 shown, it is a schematic of the minimum system of a multi-core RISC-V chip under test, which mainly includes multiple 64-bit RISC-V CPU cores, the core and software interrupt CLINT, and the peripheral interrupt PLIC, memory devices such as ROM, RAM, FLASH, and DDR, as well as peripherals including but not limited to GPIO, UART, Ethernet, and SPI.

[0077] In specific implementation, first define the corresponding device addresses of different peripherals and interrupts to construct the base addresses of the interrupts and devices required by the system. The addresses defined here will be filled into the initialization functions of each subsequent device and associated in the virtual machine. The following example shows the definition of the sizes of three memory units, ROM, SRAM, and FLASH, and their corresponding addresses. Users can build their own virtual development board by modifying the following entries and address units.

[0078] static const MemMapEntry virt_memmap[] = {

[0079] [VIRT_MOM] = {0x00000000, 0x20000};

[0080] [VIRT_SRAM] = {0x0020000, 0xe0000};

[0081] [VIRT_FLASH] = {0x20000000, 0x2000000};

[0082] [VIRT_UART] = {0x10000000, 0x1000};

[0083] };

[0084] Secondly, write relevant functions in the Qemu project files to set up memory, interrupts, and peripherals, initialize the functions, and register the code modules of the virtual development board. Then, determine the sizes and actual parameters of each peripheral according to the actual situation of the hardware circuit to be simulated. For example, for the serial port device, by calling serial_mm_init() in Qemu, register the address of [VIRT_UART] in the above code block to this function, and use this function to initialize the serial port and set its initial attributes. Alternatively, based on this, you can write your own code to implement a new serial port object to add user-defined serial port devices.

[0085] Step 2: Run Qemu to test whether the virtual development board can work properly. If the system cannot work properly, return to Step 1 to check the virtual development board, memory, peripherals, and interrupt scheme. You can use software debugging tools such as running the Qemu virtual machine and GDB (GNU symbolic debugger) to check whether the virtual development board can work.

[0086] Step 3: Query in Qemu whether the peripherals can be recognized; for example, whether the serial port and interrupts have been added. If they cannot be recognized, return to Step 1 to check the virtual development board, memory, peripherals, and interrupt scheme. You can use software debugging tools such as serial port printing and GDB (GNU symbolic debugger) to query whether the peripherals can be recognized.

[0087] Verification in the second stage:

[0088] Step 4: Design the basic software, drivers, and various board support packages (BSP), and perform configurations related to the operating system startup.

[0089] Step 5: Verify whether the basic software and the operating system can run properly. If they cannot run, return to Step 4 for further processing. The method to verify whether the basic software and the operating system can run properly is to verify and analyze by analyzing the logs of the operating system and basic software startup.

[0090] To achieve the above verification goals, the specific implementation process of the second-stage verification described in Step 4 can be as Figure 6 shown:

[0091] Figure 6 is the multi-level startup boot model of the RISC-V processor, which consists of five parts. The solid arrows represent loading, and the dashed arrows represent jumps between stages.

[0092] (1) ZSBL (M-mode ROM) stage:

[0093] ZSBL is the abbreviation of Zero Stage Boot Loader, which is usually stored in ROM. It is the first code executed after the system is powered on. It is usually very small and has limited functions. Its main responsibility is to initialize the most basic hardware settings, including the CPU core and memory, and prepare for the subsequent stage of the boot loader.

[0094] (2) FSBL / U-Boot SPL (M-mode LOADER) stage:

[0095] The second stage is the First Stage Boot Loader or the Secondary Program Loader of U-Boot, which usually runs in Machine mode (M-mode). The boot program in this stage further initializes the hardware, including the clock, power management, and peripherals, and loads the boot program for the next stage.

[0096] (3) OpenSBI (M-mode RUNTIME) stage:

[0097] SBI (Supervisor Binary Interface) is the interface between the operating system kernel and Machine mode. OpenSBI (Open Source Supervisor Binary Interface) is an open-source implementation of SBI, aiming to provide a general Supervisor Binary Interface layer to support communication between firmware and operating systems on different processor architectures. As a runtime environment in M-mode, OpenSBI provides an SBI implementation for RISC-V. The software in this stage provides a set of standard services for the operating system, such as timers, interrupt management, etc.

[0098] (4) U-Boot (S-mode BOOTLOADER) stage:

[0099] U-Boot (Universal Boot Loader) is an open-source project that evolved from FADSROM, 8xxROM, and PPCBOOT following the GPL terms. U-boot is mainly used as a boot loader for embedded systems and can support various computer system architectures. Its main function is to boot the system. In this stage, U-Boot runs as a full-featured boot program in Supervisor mode (S-mode). It can support complex boot scenarios such as network booting and reading data from different storage media. It usually provides a user interface that allows users to select different boot options or perform system configuration.

[0100] (5) Linux (S-mode OS) Phase:

[0101] Finally, the operating system itself starts in supervisor mode (S-mode). Taking Linux as an example here, the Linux kernel takes over the hardware, continues with system initialization, loads the required drivers, and finally starts the user space program to complete the system startup process.

[0102] Verification in the third phase:

[0103] Step 6: Run a benchmark program to evaluate the performance of the chip under test;

[0104] Step 7: Verify whether the application software can run. If it cannot run, return to Step 6 to troubleshoot the reason and run the benchmark program again; Check whether the application software can run by analyzing the running logs of the application software;

[0105] Step 8: Perform software-hardware co-optimization according to the verification results of the benchmark test in Step 7;

[0106] Through experimental verification of the method proposed in this application, it is proved to be feasible. As Figure 7 shown, the first-phase verification (taking the serial port as an example); as Figure 8 shown, the second-phase verification (taking general startup as an example).

[0107] It should be noted that the system-level verification method for the reconfigurable multi-core heterogeneous chip system described in the present invention can also be applied to multi-core chips of ARM and x86. However, the corresponding test programs, operating systems, software drivers, and hardware peripherals need to be replaced with processor chips of the corresponding architectures.

[0108] With the above technical solutions, the embodiments of the present application provide a system-level verification method and test system for a RISC-V reconfigurable multi-core processor chip. The method includes the following steps: First, verify the hardware status; the hardware status includes: core configuration, memory, interrupt, status of multiple cores, and control status register configuration of the reconfigurable multi-core processor; Then, verify the basic software; verifying the basic software includes: verifying the chip lighting and startup of the operating system, underlying driver software, and board support package for the chip of the reconfigurable multi-core processor; Finally, verify the upper-layer software and the coordinated operation of the multi-core chip software-hardware system.

[0109] In view of the current situation that the test cycle required for the system test of processor chips is long, the verification efficiency is low, and the function test is not comprehensive enough, the present application proposes a system-level verification method and test system for a RISC-V reconfigurable multi-core processor chip. Compared with FPGA or other traditional verification methods, the software virtualization method can eliminate physical processes such as PCB design, board making, and peripheral welding, and can realize system simulation more quickly, environmentally friendly, and economically. The simulation efficiency using virtualization is also greatly improved compared with FPGA simulation. The experimental results of simulation verification can be given within only 1 day, which is more convenient and fast.

[0110] In addition, the method provided by the present application allows users to customize the development and quickly perform co-verification of the chip's software and hardware systems for chip functions, and verify and assist in rapid design iteration for the unreasonable parts in the preliminary design of the processor system, greatly shortening the test verification process and speed of the multi-core heterogeneous chip, shortening the market cycle of the multi-core heterogeneous chip, and accelerating its iteration rate.

[0111] Those of ordinary skill in the art can understand that the above embodiments are specific examples for implementing the present application. In actual applications, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A system-level verification method for a RISC-V reconfigurable multi-core processor chip, characterized in that, It includes the following steps: Verify the hardware status; The hardware status includes: the core configuration of the reconfigurable multi-core processor, memory, interrupts, the status of multiple cores, and the control status register configuration; Verify the basic software; the verification of the basic software includes: power on the chip of the reconfigurable multi-core processor and start the operating system, and verify the underlying driver software and board support package; Verify the upper-layer software and the collaborative work of the multi-core chip hardware and software system.

2. The system-level verification method for a RISC-V reconfigurable multi-core processor chip according to claim 1, characterized in that, The verification of the hardware status includes: Step 1: Design a virtual development board and peripherals according to the chip to be tested, and write the relevant code for the core settings of the reconfigurable multi-core processor, the virtual development board and peripherals based on Qemu; Step 2: Run Qemu to test whether the virtual development board can work properly. If not, return to Step 1; if so, enter Step 3; Step 3: Query whether the peripherals can be recognized in Qemu. If not, return to Step 1; if so, proceed to the next step.

3. The system-level verification method for a RISC-V reconfigurable multi-core processor chip according to claim 2, characterized in that, The verification of the basic software includes: Step 4: Design the basic software, drivers, and various board support packages, and perform the configuration related to the startup of the operating system; Step 5: Verify whether the basic software and the operating system can run properly. If not, return to Step 4; if so, proceed to the next step.

4. The system-level verification method for a RISC-V reconfigurable multi-core processor chip according to claim 3, characterized in that, In Step 4, perform the configuration related to the startup of the operating system based on the multi-level startup boot model of the RISC-V processor.

5. The system-level verification method for a RISC-V reconfigurable multi-core processor chip according to claim 3, characterized in that, In Step 5, the method for verifying whether the basic software and the operating system can run properly includes: verifying and analyzing by analyzing the logs of the startup of the operating system and the basic software.

6. The system-level verification method for a RISC-V reconfigurable multi-core processor chip according to claim 3, characterized in that, The verification of the upper-layer software and the collaborative work of the multi-core chip hardware and software system includes: Step 6: Run a benchmark test program to evaluate the performance of the chip to be tested; Step 7: Verify whether the application software can run. If it cannot run, return to Step 6 to troubleshoot the cause and run the benchmark test program again; check whether the application software can run by analyzing the running logs of the application software; Step 8: Perform software and hardware collaborative optimization according to the verification results of the benchmark test in Step 7.

7. The system-level verification method for a RISC-V reconfigurable multi-core processor chip according to claim 6, characterized in that, The benchmark test program is a general processor benchmark test program, or uses the basic applications of the reconfigurable multi-core processor for testing; when testing the display supported by the chip to be tested, the benchmark test program includes the basic tests of display and graphical interface.

8. A test system for a RISC-V reconfigurable multi-core processor chip, characterized in that, It includes: A benchmark test program, a software launcher, an operating system, a virtual development board and its peripherals, an interface of the chip to be tested, and the chip to be tested connected in sequence; The virtual development board and its peripherals, the interface of the chip to be tested, and the chip to be tested are used to implement the first-stage verification; The first-stage verification includes: verifying the hardware status; the hardware status includes: the core configuration of the reconfigurable multi-core processor, memory, interrupts, the status of multiple cores, and the control status register configuration; The software launcher, together with the operating system, the virtual development board and its peripherals, the interface of the chip under test, and the chip under test, is used to implement the second-stage verification. The second-stage verification includes: verifying the basic software. The verification of the basic software includes: verifying the chip lighting of the reconfigurable multi-core processor chip, the startup of the operating system, and the underlying driver software and board support package. On the basis of the successful completion of the first-stage verification and the second-stage verification, the third-stage verification is completed through the benchmark test program. The third-stage verification includes: verifying the upper-layer software and the coordinated operation of the multi-core chip software and hardware system.

9. The test system for a RISC-V reconfigurable multi-core processor chip according to claim 8, characterized in that,The chip under test is used to extract the attributes of the actual chip under test, and based on the Qom mechanism of Qemu, the basic attributes of the chip under test are extracted for simulation. The interface of the chip under test provides a software interface layer for the chip under test and the basic test platform. The virtual development board and its peripherals are designed and implemented based on Qemu, and are used to provide the necessary peripheral conditions and virtual hardware environment for chip startup.

10. The test system of the RISC-V reconfigurable multi-core processor chip according to claim 8, wherein, The software launcher and the operating system are used to provide the basic software and operating system environment for chip startup lighting. The benchmark test program provides benchmark performance testing and functional testing at the software level. The performance of the chip under test can be effectively evaluated by the completion of the test vectors of the benchmark test program to determine whether it can meet the basic design requirements.

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