Three-level boost inverter based on switched capacitor and its modulation strategy

Abstract

The present invention proposes a three-level boost inverter based on switched capacitors and its modulation strategy, comprising: a switched capacitor voltage regulating circuit and an F-type three-phase full-bridge inverter circuit; the switched capacitor voltage regulating circuit is responsible for increasing the DC bus voltage and generating three voltage levels; and the F-type full-bridge inverter circuit is responsible for converting the three voltage levels into three-phase voltages, and realizing three-phase voltage output through the combined action of the switched capacitor circuit and the three-phase bridge arm. At the same time, based on the characteristics of the inverter, a new SVPWM modulation strategy is proposed to control the on-off of the switch tube and realize the self-balancing of the capacitor voltage. While realizing three-phase three-level output, the present application can double the voltage modulation range, and without large inductance, it can effectively reduce losses and improve power density.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronic DC / AC conversion, and in particular relates to a three-level boost inverter based on switched capacitors and a modulation strategy thereof. Background Art

[0002] Inverters, as the hub between renewable energy sources (such as photovoltaic or wind power) and the power grid, play a crucial role in the widespread adoption of renewable energy. Traditional photovoltaic inverters use a boost circuit to increase the supply voltage, indirectly improving the inverter's voltage conversion ratio. However, they are essentially two-level voltage source inverters with a boost stage inserted. Two-level voltage source inverters suffer from high output harmonics and require bulky filtering circuits. Furthermore, the boost stage inductor used in this inverter topology is large, increasing equipment cost and reducing power density. Furthermore, the copper and iron losses of the inductor vary positively with inductor size, leading to increased power consumption. Z-source multilevel inverters offer boost capabilities and address the high output harmonics of two-level voltage source inverters. However, the voltage source gain of a Z-source multilevel inverter is determined by the ratio of shoot-through to non-shoot-through states within a switching cycle. The shoot-through state reduces the inverter's voltage conversion ratio, increasing switching stress when modulating the same AC waveform. This also requires larger capacitors and inductors, further increasing equipment manufacturing costs and reducing power density. Summary of the Invention

[0003] To address this issue, the present invention proposes a three-level boost inverter based on switched capacitors. A novel SVPWM modulation strategy is proposed for this inverter to control the on / off switching of the switches and achieve self-balancing of the capacitor voltage. The inverter comprises a switched capacitor voltage regulator circuit and an F-type full-bridge inverter circuit. The switched capacitor voltage regulator circuit is responsible for boosting the DC bus voltage and generating three voltage levels. The F-type full-bridge inverter circuit converts the three voltage levels into three-phase voltage. The combined action of the switched capacitor circuit and the three-phase bridge arms results in a three-phase voltage output.

[0004] In a first aspect, a three-level boost inverter based on switched capacitors according to the present invention comprises: a switched capacitor voltage regulating circuit and an F-type three-phase full-bridge inverter circuit; wherein the switched capacitor voltage regulating circuit is composed of a switching transistor. T 1. Switching tube T 2. Diode D 1. Diode D 2. Capacitor C 1 and capacitor C 2 composition; wherein, the switch tube T 1. Connect one end to a DC voltage source V dc , and the other end is connected to the switch tube T 2 and diodeD 1. The diode D 1 The other end is connected to the capacitor C 1 and F type three-phase full-bridge inverter circuit; the capacitor C 1The other end is connected to the switch tube T 2. Diode D 2 and F-type three-phase full-bridge inverter circuit, the diode D 2 The other end is also connected to the capacitor C 2 and F type three-phase full-bridge inverter circuit; the switch tube T 1 and switch tube T 2 is a complementary relationship, the switch tube T 1 is turned on and the switch tube T 2 Shutdown is defined as the N state of the front-stage switched capacitor voltage regulator circuit, the switch tube T 1 is turned off and the switch tube T 2 conduction is defined as the P state of the front-stage switched capacitor voltage regulator circuit. The F-type three-phase full-bridge inverter circuit is composed of A, B, and C three-phase bridge arms.

[0005] The three-phase bridge arm includes:

[0006] Phase A bridge arm, consisting of switch tube T a1 , switch tube T a2 , switch tube T a3 and switch tube T a4 composition;

[0007] The B-phase bridge arm consists of a switch tube T b1 , switch tube T b2 , switch tube T b3 and switch tube T b4 composition;

[0008] The C phase bridge arm consists of a switch tube T c1 , switch tube T c2 , switch tube T c3 and switch tube T c4 composition;

[0009] Wherein, the A-phase bridge arm, the B-phase bridge arm and the C-phase bridge arm are connected in parallel;

[0010] Taking phase A as an example, in order to ensure that the inverter circuit does not short-circuit and the switch tube has low loss when switching, the switch tube Ta1 ~ T a4 Follow the principle of two switch tubes being on and two switch tubes being off. T a1 and T a3 With switch tube T a2 and T a4 Complementary, that is, switching tube T a1 and T a3 If the switch is turned on, T a2 and T a4 Shutdown, this state is defined as the P state of the A-phase bridge arm; the switch tube T a2 and T a4 If the switch is turned on, T a1 and T a3 The switch is turned off, which is defined as the N state of the A-phase bridge arm. T x2 and T x3 On and switch T x1 and T x4 Shutdown is defined as the O state of the A-phase bridge arm; the P, O, and N states of the B-phase bridge arm and the C-phase bridge arm are the same as the P, O, and N states described for the A-phase bridge arm. The three-phase full-bridge inverter circuit adopts a three-level space vector modulation strategy, decomposes the voltage reference vector into an α-β coordinate system, and realizes three-phase AC output by synthesizing the basic voltage vector.

[0011] Preferably, the three-level boost inverter based on switched capacitors described in the present application further includes:

[0012] When the switch is turned on T 1. Turn off the switch tube T 2, then the capacitance C 1 and capacitor C 2 parallel charging, the output voltage of the switched capacitor voltage regulation circuit is V dc ;

[0013] When the switch is turned off T 1. Turn on the switch tube T 2, then the capacitance C 1 and capacitor C 2 Series discharge, switched capacitor voltage regulator circuit in capacitorC The positive output voltage of 1 is 2 V dc , in capacitor C The negative output voltage of 1 is V dc .

[0014] Preferably, when the switch capacitor voltage regulating circuit turns on the switch tube T 1. Turn off the switch tube T 2. The output voltage is V dc When the switch T a2 and switch tube T a4 conduction, switch tube T a1 and switch tube T a3 Turn off; switch tube T b2 and switch tube T b4 conduction, switch tube T b1 and switch tube T b3 Turn off; switch tube T c2 and switch tube T c4 conduction, switch tube T c1 and switch tube T c3 Turn off; this corresponds to the NNNN state described above, where the first N represents the switching capacitor voltage regulation circuit T 1 conduction, T 2 is turned off, the output voltage is V dc ; The second N represents the switch tube of phase A T a2 and switch tube T a4 On and switch T a1 and switch tube T a3 Turn off; the third N represents the switch tube of phase B T b2 and switch tube T b4 On and switch T b1 and switch tube T b3 Turn off; the fourth N represents the switch tube of phase C T c2 and switch tubeT c4 On and switch T c1 and switch tube T c3 Turn off; at this time the capacitor C 1 and capacitor C 2 In charging state, the three-phase voltage of inverter level A, B and C U an , U bn and U cn Both are 0.

[0015] Preferably, when the switch capacitor voltage regulating circuit turns on the switch tube T 1. Turn off the switch tube T 2. The output voltage is V dc When the switch T a2 and switch tube T a3 conduction, switch tube T a1 and switch tube T a4 Turn off; switch tube T b2 and switch tube T b3 conduction, switch tube T b1 and switch tube T b4 Turn off; switch tube T c2 and switch tube T c3 conduction, switch tube T c1 and switch tube T c4 Turn off; this corresponds to the NOOO state described above, where the first N represents the switching capacitor voltage regulation circuit T 1 conduction, T 2 is turned off, the output voltage is V dc ; The second O represents the switch tube of phase A T a2 and switch tube T a3 On and switch T a1 and switch tube T a4 Shutdown; the third O represents the switch tube of phase B T b2 and switch tubeT b3 On and switch T b1 and switch tube T b4 Shutdown; the fourth O represents the switch tube of phase C T c2 and switch tube T c3 On and switch T c1 and switch tube T c4 Turn off; at this time the capacitor C 1 and capacitor C 2 In charging state, the three-phase voltage of inverter level A, B and C U an , U bn and U cn Both are 0.

[0016] Preferably, when the switch capacitor voltage regulating circuit turns off the switch tube T 1. Turn on the switch tube T 2. Capacitor C 1 and capacitor C 2 Series discharge, capacitor C The positive output voltage of 1 is 2 V dc ,capacitance C 1 Negative output voltage is V dc When the switch T a2 and switch tube T a4 conduction, switch tube T a1 and switch tube T a3 Turn off; switch tube T b2 and switch tube T b4 conduction, switch tube T b1 and switch tube T b3 Turn off; switch tube T c2 and switch tube T c4 conduction, switch tube T c1 and switch tube T c3 Turn off; this corresponds to the PNNN state described above, where the first P represents the switch tube of the switched capacitor voltage regulation circuitT 1 is turned off and the switch tube T 2 is turned on, the output voltage is 2 V dc ; The second N represents the switch tube of phase A T a2 and switch tube T a4 On and switch T a1 and switch tube T a3 Turn off; the third N represents the switch tube of phase B T b2 and switch tube T b4 On and switch T b1 and switch tube T b3 Turn off; the fourth N represents the switch tube of phase C T c2 and switch tube T c4 On and switch T c1 and switch tube T c3 Shutdown, the three-phase voltage of inverter stages A, B and C U an , U bn and U cn Both are 0.

[0017] Preferably, when the switch capacitor voltage regulating circuit turns on the switch tube T 1. Turn off the switch tube T 2. The output voltage is V dc When the switch T a1 and switch tube T a3 conduction, switch tube T a2 and switch tube T a4 Turn off; switch tube T b1 and switch tube T b3 conduction, switch tube T b2 and switch tube T b4 Turn off; switch tube T c1 and switch tube T c3 conduction, switch tubeT c2 and switch tube T c4 This corresponds to the NPPP state described above, where the first N represents the switching capacitor voltage regulation circuit. T 1 conduction, T 2 is turned off, the output voltage is V dc ; The second P represents the switch tube of phase A T a1 and switch tube T a3 On and switch T a2 and switch tube T a4 Turn off; the third P represents the switch tube of phase B T b1 and switch tube T b3 On and switch T b2 and switch tube T b4 Turn off; the fourth P represents the switch tube of phase C T c1 and switch tube T c3 On and switch T c2 and switch tube T c4 Turn off; at this time the capacitor C 1 and capacitors C 2 In the charging state, the three-phase voltage of inverter level A, B and C U an , U bn and U cn Both V dc .

[0018] Preferably, when the switch capacitor voltage regulating circuit turns off the switch tube T 1. Turn on the switch tube T 2. Capacitor C 1 and capacitor C 2 Series discharge, capacitor C The positive output voltage of 1 is 2 V dc ,capacitance C 1 Negative output voltage is V dc When the switch T a2 and switch tubeT a3 conduction, switch tube T a1 and switch tube T a4 Turn off; switch tube T b2 and switch tube T b3 conduction, switch tube T b1 and switch tube T b4 Turn off; switch tube T c2 and switch tube T c3 conduction, switch tube T c1 and switch tube T c4 Turn off; this corresponds to the POOO state described above, where the first P represents the switch tube of the switched capacitor voltage regulation circuit T 1 is turned off and switch tube T2 is turned on, the output voltage is 2 V dc ; The second O represents the switch tube of phase A T a2 and switch tube T a3 On and switch T a1 and switch tube T a4 Shutdown; the third 0 represents the switch tube of phase B T b2 and switch tube T b3 On and switch T b1 and switch tube T b4 Turn off; the fourth 0 represents the switch tube of phase C T c2 and switch tube T c3 On and switch T c1 and switch tube T c4 Shutdown, the three-phase voltage of inverter stages A, B and C U an , U bn and U cn Both V dc .

[0019] Preferably, when the switch capacitor voltage regulating circuit turns off the switch tubeT 1. Turn on the switch tube T 2. Capacitor C 1 and capacitor C 2 Series discharge, capacitor C The positive output voltage of 1 is 2 V dc ,capacitance C 1 Negative output voltage is V dc When the switch T a1 and switch tube T a3 conduction, switch tube T a2 and switch tube T a4 Turn off; switch tube T b1 and switch tube T b3 conduction, switch tube T b2 and switch tube T b4 Turn off; switch tube T c1 and switch tube T c3 conduction, switch tube T c2 and switch tube T c4 Turn off; this corresponds to the PPPP state described above, where the first P represents the switching capacitor voltage regulation circuit T 1 off, T 2 is turned on, the output voltage is 2 V dc ; The second P represents the switch tube of phase A T a1 and switch tube T a3 On and switch T a2 and switch tube T a4 Turn off; the third P represents the switch tube of phase B T b1 and switch tube T b3 On and switch T b2 and switch tube T b4 Turn off; the fourth P represents the switch tube of phase C T c1 and switch tube T c3 On and switch Tc2 and switch tube T c4 Shutdown; three-phase voltage of inverter stages A, B, and C U an , U bn and U cn Both are 2 V dc .

[0020] Preferably, when the switch capacitor voltage regulating circuit turns on the switch tube T 1. Turn off the switch tube T 2. The output voltage is V dc When the switch T a1 and switch tube T a3 conduction, switch tube T a2 and switch tube T a4 Turn off; switch tube T b1 and switch tube T b3 conduction, switch tube T b2 and switch tube T b4 Turn off; switch tube T c1 and switch tube T c3 Turn off, switch tube T c2 and switch tube T c4 This corresponds to the NPPN state described above, where the first N represents the switch tube of the switched capacitor voltage regulation circuit. T 1 is turned on and the switch tube T 2 is turned off, the output voltage is V dc ; The second P represents the switch tube of phase A T a1 and switch tube T a3 On and switch T a2 and switch tube T a4 Turn off; the third P represents the switch tube of phase B T b1 and switch tube T b3 On and switch T b2 and switch tubeT b4 Turn off; the fourth N represents the switch tube of phase C T c1 and switch tube T c3 Turn off and switch T c2 and switch tube T c4 At this time, the capacitor C 1 and capacitor C 2 In parallel charging state, the three-phase voltage of inverter stages A, B and C U an , U bn and U cn They are: V dc / 3, V dc / 3,-2 V dc / 3.

[0021] Preferably, when the switch capacitor voltage regulating circuit turns off the switch tube T 1. Turn on the switch tube T 2. Capacitor C 1 and capacitor C 2 Series discharge, capacitor C The positive output voltage of 1 is 2 V dc ,capacitance C 1 Negative output voltage is V dc When the switch T a2 and switch tube T a3 conduction, switch tube T a1 and switch tube T a4 Turn off; switch tube T b2 and switch tube T b3 conduction, switch tube T b1 and switch tube T b4 Turn off; switch tube T c1 and switch tube T c3 Turn off, switch tube T c2 and switch tube T c4This corresponds to the POON state described above, where the first P represents the switch tube of the switched capacitor voltage regulation circuit. T 1 is turned off and the switch tube T 2 is turned on, the output voltage is 2 V dc ; The second O represents the switch tube of phase A T a2 and switch tube T a3 On and switch T a1 and switch tube T a4 Shutdown; the third O represents the B phase T b2 and switch tube T b3 On and switch T b1 and switch tube T b4 Turn off; the fourth N represents the switch tube of phase C T c2 and switch tube T c4 On and switch T c1 and switch tube T c3 Shutdown, the three-phase voltage of inverter stages A, B and C U an , U bn and U cn They are: V dc / 3, V dc / 3,-2 V dc / 3.

[0022] Preferably, when the switch capacitor voltage regulating circuit turns off the switch tube T 1. Turn on the switch tube T 2. Capacitor C 1 and capacitor C 2 Series discharge, capacitor C The positive output voltage of 1 is 2 V dc ,capacitance C 1 Negative output voltage is V dc When the switch T a1 and switch tube T a3 conduction, switch tube Ta2 and switch tube T a4 Turn off; switch tube T b1 and switch tube T b3 conduction, switch tube T b2 and switch tube T b4 Turn off; switch tube T c2 and switch tube T c3 conduction, switch tube T c1 and switch tube T c4 Turn off; this corresponds to the PPPO state described above, where the first P represents the switch tube of the switched capacitor voltage regulation circuit T 1 is turned off and the switch tube T 2 is turned on, the output voltage is 2 V dc ; The second P represents the switch tube of phase A T a1 and switch tube T a3 On and switch T a2 and switch tube T a4 Turn off; the third P represents the switch tube of phase B T b1 and switch tube T b3 On and switch T b2 and switch tube T b4 Shutdown; the fourth O represents the switch tube of phase C T c2 and switch tube T c3 On and switch T c1 and switch tube T c4 Shutdown, the three-phase voltage of inverter stages A, B and C U an , U bn and U cn They are: V dc / 3, V dc / 3,-2 V dc / 3.

[0023] Preferably, when the switch capacitor voltage regulating circuit turns on the switch tube T 1. Turn off the switch tube T 2. The output voltage is V dc When the switch T a1 and switch tube T a3 conduction, switch tube T a2 and switch tube T a4 Turn off; switch tube T b2 and switch tube T b4 conduction, switch tube T b1 and switch tube T b3 Turn off; switch tube T c2 and switch tube T c4 conduction, switch tube T c1 and switch tube T c3 Turn off; this corresponds to the NPNN state described above, where the first N represents the switch tube of the switched capacitor voltage regulator circuit T 1 is turned on and the switch tube T 2 is turned off, the output voltage is V dc ; The second P represents the switch tube of phase A T a1 and switch tube T a3 On and switch T a2 and switch tube T a4 Turn off; the third N represents the switch tube of phase B T b2 and switch tube T b4 On and switch T b1 and switch tube T b3 Turn off; the fourth N represents the switch tube of phase C T c2 and switch tube T c4 On and switch T c1 and switch tube T c3 Turn off; at this time the capacitor C 1 and capacitorC 2 In charging state, the three-phase voltage of inverter level A, B and C U an , U bn and U cn In order: 2 V dc / 3,- V dc / 3,- V dc / 3.

[0024] Preferably, when the switch capacitor voltage regulating circuit turns off the switch tube T 1. Turn on the switch tube T 2. Capacitor C 1 and capacitor C 2 Series discharge, capacitor C The positive output voltage of 1 is 2 V dc ,capacitance C 1 Negative output voltage is V dc When the switch T a2 and switch tube T a3 conduction, switch tube T a1 and switch tube T a4 Turn off; switch tube T b2 and switch tube T b4 conduction, switch tube T b1 and switch tube T b3 Turn off; switch tube T c2 and switch tube T c4 conduction, switch tube T c1 and switch tube T c3 Turn off; this corresponds to the PONN state described above, where the first P represents the switch tube of the switched capacitor voltage regulator circuit T 1 is turned off and the switch tube T 2 is turned on, the output voltage is 2 V dc ; The second O represents the switch tube of phase A T a2 and switch tube T a3 On and switch Ta1 and switch tube T a4 Turn off; the third N represents the switch tube of phase B T b2 and switch tube T b4 On and switch T b1 and switch tube T b3 Turn off; the fourth N represents the switch tube of phase C T c2 and switch tube T c4 On and switch T c1 and switch tube T c3 Shutdown, the three-phase voltage of inverter stages A, B and C U an , U bn and U cn In order: 2 V dc / 3,- V dc / 3,- V dc / 3.

[0025] Preferably, when the switch capacitor voltage regulating circuit turns off the switch tube T 1. Turn on the switch tube T 2. Capacitor C 1 and capacitor C 2 Series discharge, capacitor C The positive output voltage of 1 is 2 V dc ,capacitance C 1 Negative output voltage is V dc When the switch T a1 and switch tube T a3 conduction, switch tube T a2 and switch tube T a4 Turn off; switch tube T b2 and switch tube T b3 conduction, switch tube T b1 and switch tube T b4 Turn off; switch tube T c2and switch tube T c3 conduction, switch tube T c1 and switch tube T c4 Turn off; this corresponds to the PPOO state described above, where the first P represents the switch tube of the switched capacitor voltage regulation circuit T 1 is turned off and the switch tube T 2 is turned on, the output voltage is 2 V dc ; The second P represents the switch tube of phase A T a1 and switch tube T a3 On and switch T a2 and switch tube T a4 Shutdown; the third O represents the switch tube of phase B T b2 and switch tube T b3 On and switch T b1 and switch tube T b4 Shutdown; the fourth O represents the switch tube of phase C T c2 and switch tube T c3 On and switch T c1 and switch tube T c4 Shutdown, the three-phase voltage of inverter stages A, B and C U an , U bn and U cn In order: 2 V dc / 3,- V dc / 3,- V dc / 3.

[0026] Preferably, when the switch capacitor voltage regulating circuit turns off the switch tube T 1. Turn on the switch tube T 2. Capacitor C 1 and capacitor C 2 Series discharge, capacitor C The positive output voltage of 1 is 2 V dc ,capacitance C 1 Negative output voltage is Vdc When the switch T a1 and switch tube T a3 conduction, switch tube T a2 and switch tube T a4 Turn off; switch tube T b2 and switch tube T b3 conduction, switch tube T b1 and switch tube T b4 Turn off; switch tube T c2 and switch tube T c4 conduction, switch tube T c1 and switch tube T c3 This corresponds to the PPON state described above, where the first P represents the switch tube of the switched capacitor voltage regulation circuit. T 1 is turned off and the switch tube T 2 is turned on, the output voltage is 2 V dc ; The second P represents the switch tube of phase A T a1 and switch tube T a3 On and switch T a2 and switch tube T a4 Shutdown; the third O represents the switch tube of phase B T b2 and switch tube T b3 On and switch T b1 and switch tube T b4 Turn off; the fourth N represents the switch tube of phase C T c2 and switch tube T c4 On and switch T c1 and switch tube T c3 Shutdown, the three-phase voltage of inverter stages A, B and C U an , U bn and U cn They are: Vdc ,0,- V dc .

[0027] Preferably, when the switch capacitor voltage regulating circuit turns off the switch tube T 1. Turn on the switch tube T 2. Capacitor C 1 and capacitor C 2 Series discharge, capacitor C The positive output voltage of 1 is 2 V dc ,capacitance C 1 Negative output voltage is V dc When the switch T a1 and switch tube T a3 conduction, switch tube T a2 and switch tube T a4 Turn off; switch tube T b1 and switch tube T b3 conduction, switch tube T b2 and switch tube T b4 Turn off; switch tube T c2 and switch tube T c4 conduction, switch tube T c1 and switch tube T c3 Turn off; this corresponds to the PPPN state described above, where the first P represents the switch tube of the switched capacitor voltage regulation circuit T 1 is turned off and the switch tube T 2 is turned on, the output voltage is 2 V dc ; The second P represents the switch tube of phase A T a1 and switch tube T a3 On and switch T a2 and switch tube T a4 Turn off; the third P represents the switch tube of phase B T b1 and switch tube T b3 On and switch T b2 and switch tube Tb4 Turn off; the fourth N represents the switch tube of phase C T c2 and switch tube T c4 On and switch T c1 and switch tube T c3 Shutdown, the three-phase voltage of inverter stages A, B and C U an , U bn and U cn In order: 2 V dc / 3,2 V dc / 3, -4 V dc / 3.

[0028] Preferably, when the switch capacitor voltage regulating circuit turns off the switch tube T 1. Turn on the switch tube T 2. Capacitor C 1 and capacitor C 2 Series discharge, capacitor C The positive output voltage of 1 is 2 V dc ,capacitance C 1 Negative output voltage is V dc When the switch T a1 and switch tube T a3 conduction, switch tube T a2 and switch tube T a4 Turn off; switch tube T b2 and switch tube T b4 conduction, switch tube T b1 and switch tube T b3 Turn off; switch tube T c2 and switch tube T c4 conduction, switch tube T c1 and switch tube T c3 Turn off; this corresponds to the PPNN state described above, where the first P represents the switch tube of the switched capacitor voltage regulator circuit T 1 is turned off and the switch tube T2 is turned on, the output voltage is 2 V dc ; The second P represents the switch tube of phase A T a1 and switch tube T a3 On and switch T a2 and switch tube T a4 Turn off; the third N represents the switch tube of phase B T b2 and switch tube T b4 On and switch T b1 and switch tube T b3 Turn off; the fourth N represents the switch tube of phase C T c2 and switch tube T c4 On and switch T c1 and switch tube T c3 Shutdown, the three-phase voltage of inverter stages A, B and C U an , U bn and U cn In order: 4 V dc / 3,-2 V dc / 3,-2 V dc / 3.

[0029] In a second aspect, the present invention further proposes an SVPWM modulation strategy for a three-level boost inverter based on switched capacitors, comprising:

[0030] Definition: For the front-stage switched capacitor voltage regulator circuit, P represents the switch tube T 2 is turned on and the switch tube T 1 off, capacitor C 1 and capacitor C 2 Series discharge, capacitor C The positive output voltage of 1 is 2 V dc ,capacitance C 1 Negative output voltage is V dc ; N represents the switch tube T 1 is turned on and the switch tube T 2 off, capacitor C 1 and capacitor C2 parallel charging, the output voltage is V dc ; For the F-type three-phase inverter circuit at the rear stage, P represents the switch tube T x1 and switch tube T x3 On and switch T x2 and switch tube T x4 Turn off; N indicates the switch tube T x1 and switch tube T x3 Turn off and switch T x2 and switch tube T x4 On; O indicates switch tube T x2 and switch tube T x3 On and switch T x1 and switch tube T x4 Shutdown ( x = a , b , c );

[0031] According to the target output voltage amplitude | u ref |Calculate its components in the α-β coordinate system: u α =| u ref |sin( w t), u β =| u ref |cos( w t), determine the sector where the reference vector is located, where the sector where the reference vector is located includes 6 large sectors; the three-level inverter circuit described in this application adopts space vector pulse width modulation, where the basic voltage vector includes 6 zero vectors and 30 effective vectors. Each switching state corresponds to a basic vector. In the basic vector corresponding to the switching state, when the charging vector acts, it will not cause capacitance even if the action time is long. C 1 、 C 2 The voltage fluctuates significantly; when the discharge vector acts, the two capacitors discharge in series to the load to generate 2 V dcWhen the output voltage is released, its stored energy will be released quickly. If the action time is too long, the capacitor voltage will drop sharply. To maintain the stability of the capacitor voltage, this solution uses a regional vector selection strategy to ensure that in any reference voltage vector region, the selected basic vector contains both an effective charging vector to replenish the capacitor energy and the necessary discharge vector to complete the voltage output. The action time of the charging vector is maximized by optimizing the duty cycle distribution. This dynamic charge balance mechanism can effectively suppress voltage fluctuations caused by excessive capacitor discharge and improve the reliability of system operation. Therefore, in the actual modulation strategy, in order to ensure the balance of charge and discharge of the capacitor voltage and take into account the fewer switching times of the switch tube each time the vector changes, the zero vector only selects NNNN, and the short vector only selects NPNN, NPPN, NNPN, NNPP, NNNP, and NPNP.

[0032] Furthermore, using the space vector modulation strategy, taking the first largest sector as an example, when When the reference voltage vector is located in the first small sector, the voltage reference vector u ref By basis vector u 0, u 1, u 2 synthesis; when When the reference voltage vector is located in the second small sector, the voltage reference vector u ref By basis vector u 1, u 3. u 4 synthesis; when When the reference voltage vector is located in the fourth sector, the voltage reference vector u ref By basis vector u 2, u 4. u 5 synthesis; In addition to the above situation, the reference voltage vector is located in the third small sector, the voltage reference vector u ref By basis vector u 1, u 2, u 4 synthesis.

[0033] When the reference vector is in the first small sector in the first large sector, it is composed of vector (N, N, N, N), vector (N, P, P, N), and vector (N, P, N, N);

[0034] Among them, the basic vector (N, N, N, N) is a zero vector, and its duty cycle is recorded as: ;

[0035] The duty cycle of the vector (N, P, P, N) is: ;

[0036] The duty cycle of the vector (N, P, N, N) is: .

[0037] When the reference vector is in the second small sector in the first large sector, it is composed of vector (N, P, N, N), vector (P, P, O, N), and vector (P, P, N, N);

[0038] in:

[0039] The duty cycle of the vector (N, P, N, N) is:

[0040] ;

[0041] The duty cycle of the vector (P, P, O, N) is:

[0042] ;

[0043] The duty cycle of the vector (P, P, N, N) is:

[0044] ;

[0045] When the reference vector is the third small sector in the first large sector, it is composed of vector (N, P, P, N), vector (N, P, N, N), and vector (P, P, O, N);

[0046] in:

[0047] The duty cycle of the vector (N, P, P, N) is:

[0048] ;

[0049] The duty cycle of the vector (N, P, N, N) is:

[0050] ;

[0051] The duty cycle of the vector (P, P, O, N) is:

[0052] ;

[0053] When the reference vector is in the fourth small sector in the first large sector, it is composed of vector (N, P, P, N), vector (P, P, P, N), and vector (P, P, O, N);

[0054] in:

[0055] The duty cycle of the vector (N, P, P, N) is:

[0056] ;

[0057] The duty cycle of the vector (P, P, P, N) is:

[0058] ;

[0059] The duty cycle of the vector (P, P, O, N) is:

[0060] ;

[0061] The basic vector duty cycle of other sectors can be solved by rotating the α-β coordinate system to the first largest sector and using the same expression. According to the reference vector synthesis order set for the first largest sector, the synthesis path of the reference vectors in other large sectors can be determined: the vector synthesis path of the third and fifth largest sectors is the same as that of the first largest sector, and the vector synthesis path of the second, fourth and sixth largest sectors is opposite to that of the first largest sector.

[0062] Compared with the prior art, the present invention has the following beneficial effects:

[0063] The present invention is a three-level boost inverter based on switched capacitors, which can double the voltage modulation range while achieving three-phase three-level output, and has no large inductance, thereby effectively reducing losses.

[0064] This invention features capacitor voltage self-balancing, simplifying the control process compared to traditional three-level topologies and eliminating the capacitor voltage sampling circuit, thereby further reducing costs and increasing power density. This technology is particularly suitable for portable applications requiring a wide voltage range, such as photovoltaic microinverters or outdoor inverters. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] Figure 1 It is a schematic diagram of the topological structure of the three-level boost inverter based on switched capacitors of the present invention.

[0066] Figure 2 These are two working states of the front-stage switched capacitor voltage regulating circuit of the present invention.

[0067] Figure 3 This is a circuit diagram under the action of the NPPN vector of the present invention.

[0068] Figure 4 This is a circuit diagram under the action of the POON vector of the present invention.

[0069] Figure 5 This is a circuit diagram under the action of the PPPO vector of the present invention.

[0070] Figure 6 This is a circuit diagram under the action of the NPPN vector of the present invention.

[0071] Figure 7This is a circuit diagram under the action of the PONN vector of the present invention.

[0072] Figure 8 This is a circuit diagram under the action of the PPOO vector of the present invention.

[0073] Figure 9 This is a circuit diagram under the action of the PPON vector of the present invention.

[0074] Figure 10 This is a circuit diagram under the action of the PPPN vector of the present invention.

[0075] Figure 11 This is a circuit diagram under the action of the PPNN vector of the present invention.

[0076] Figure 12 It is the three-level SVPWM voltage vector diagram of the present invention.

[0077] Figure 13 is the reference vector of the present invention u ref Voltage composite diagram located in the first largest sector. DETAILED DESCRIPTION

[0078] The following description is intended to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are merely examples, and those skilled in the art may conceive of other obvious variations.

[0079] Example 1, as Figure 1 As shown, the present invention relates to a three-level boost inverter circuit based on a switched capacitor, comprising: a switched capacitor voltage regulating circuit and an F-type three-phase full-bridge inverter circuit; wherein the switched capacitor voltage regulating circuit is composed of a switching transistor. T 1. Switching tube T 2. Diode D 1. Diode D 2. Capacitor C 1 and capacitor C 2 composition; wherein, the switch tube T 1. Connect one end to a DC voltage source V dc , and the other end is connected to the switch tube T 2 and diode D 1. The diode D 1 The other end is connected to the capacitor C 1 and F type three-phase full-bridge inverter circuit; the capacitor C 1The other end is connected to the switch tube T 2. Diode D 2 and F-type three-phase full-bridge inverter circuit, the diode D 2 The other end is also connected to the capacitor C2 and F type three-phase full-bridge inverter circuit; the switch tube T 1 and switch tube T 2 is a complementary relationship, the switch tube T 1 is turned on and the switch tube T 2 Shutdown is defined as the N state of the front-stage switched capacitor voltage regulator circuit, the switch tube T 1 is turned off and the switch tube T 2 conduction is defined as the P state of the front-stage switched capacitor voltage regulation circuit. This application adopts a three-level SVPWM modulation strategy. Unlike the traditional three-level SVPWM modulation strategy, this topology has a boost capability and the voltage modulation range is twice that of the traditional three-level SVPWM. Therefore, the three voltage levels are 0, V dc and 2 V dc .

[0080] The three-phase full-bridge inverter circuit is composed of three-phase bridge arms A, B, and C.

[0081] Wherein, the three-phase bridge arm includes:

[0082] Phase A bridge arm, consisting of switch tube T a1 , switch tube T a2 , switch tube T a3 and switch tube T a4 composition;

[0083] The B-phase bridge arm consists of a switch tube T b1 , switch tube T b2 , switch tube T b3 and switch tube T b4 composition;

[0084] The C phase bridge arm consists of a switch tube T c1 , switch tube T c2 , switch tube T c3 and switch tube T c4 composition;

[0085] Wherein, the A-phase bridge arm, the B-phase bridge arm and the C-phase bridge arm are connected in parallel;

[0086] Taking phase A as an example, in order to ensure that the inverter circuit does not short-circuit and the switch tube has low loss when switching, the switch tube T a1~ T a4 Follow the principle of two switch tubes being on and two switch tubes being off. T a1 and T a3 With switch tube T a2 and T a4 Complementary, that is, switching tube T a1 and T a3 If the switch is turned on, T a2 and T a4 Shutdown, this state is defined as the P state of the A-phase bridge arm; the switch tube T a2 and T a4 If the switch is turned on, T a1 and T a3 The switch is turned off, which is defined as the N state of the A-phase bridge arm. T x2 and T x3 The switch is turned on and T x1 and T x4 Shutdown is defined as the O state of the A-phase bridge arm; the P, O, and N states of the B-phase bridge arm and the C-phase bridge arm are the same as the P, O, and N states described for the A-phase bridge arm. The three-phase full-bridge inverter circuit adopts a three-level space vector modulation strategy, decomposes the voltage reference vector into an α-β coordinate system, and realizes three-phase AC output by synthesizing the basic voltage vector.

[0087] Preferably, the switched capacitor voltage regulating circuit of the three-level boost inverter based on switched capacitors described in the present application has two working states, such as Figure 2 Shown is a simplified topology diagram of the main circuit, including:

[0088] State 1:

[0089] When the switch is turned on T 1. Turn off the switch tube T 2, then the capacitance C 1 and capacitor C 2 parallel charging, the output voltage of the switched capacitor voltage regulation circuit is V dc ;

[0090] State 2:

[0091] When the switch is turned offT 1. Turn on the switch tube T 2, then the capacitance C 1 and capacitor C 2 Series discharge, switched capacitor voltage regulator circuit in capacitor C The positive output voltage of 1 is 2 V dc , in capacitor C The negative output voltage of 1 is V dc .

[0092] When the voltage regulating circuit switches between state 1 and state 2 at high frequency, the characteristic that the capacitor voltage cannot change suddenly is used to make the C 1, C 2Maintain voltage balance during the charging and discharging process without additional voltage sampling or closed-loop control. Set a high switching frequency to achieve capacitor self-balancing voltage regulation and stable circuit output V dc and 2 V dc Two levels, combined with F-type full-bridge inverter circuit, line voltage output 0, ± V dc ±2 V dc Five levels, with a modulation range twice that of traditional three-level voltage source inverters.

[0093] Preferably, when the switch capacitor voltage regulating circuit turns on the switch tube T 1. Turn off the switch tube T 2. The output voltage is V dc When the switch T a2 and switch tube T a4 conduction, switch tube T a1 and switch tube T a3 Turn off; switch tube T b2 and switch tube T b4 conduction, switch tube T b1 and switch tube T b3 Turn off; switch tube T c2 and switch tube T c4 conduction, switch tube T c1 and switch tube T c3Turn off; this corresponds to the NNNN state described above, where the first N represents the switching capacitor voltage regulation circuit T 1 conduction, T 2 is turned off, the output voltage is V dc ; The second N represents the switch tube of phase A T a2 and switch tube T a4 On and switch T a1 and switch tube T a3 Turn off; the third N represents the switch tube of phase B T b2 and switch tube T b4 On and switch T b1 and switch tube T b3 Turn off; the fourth N represents the switch tube of phase C T c2 and switch tube T c4 On and switch T c1 and switch tube T c3 Turn off; at this time the capacitor C 1 and capacitor C 2 In charging state, the three-phase voltage of inverter level A, B and C U an , U bn and U cn Both are 0.

[0094] Preferably, when the switch capacitor voltage regulating circuit turns on the switch tube T 1. Turn off the switch tube T 2. The output voltage is V dc When the switch T a2 and switch tube T a3 conduction, switch tube T a1 and switch tube T a4 Turn off; switch tube T b2 and switch tube T b3 conduction, switch tube T b1 and switch tube T b4Turn off; switch tube T c2 and switch tube T c3 conduction, switch tube T c1 and switch tube T c4 Turn off; this corresponds to the NOOO state described above, where the first N represents the switching capacitor voltage regulation circuit T 1 conduction, T 2 is turned off, the output voltage is V dc ; The second O represents the switch tube of phase A T a2 and switch tube T a3 On and switch T a1 and switch tube T a4 Shutdown; the third O represents the switch tube of phase B T b2 and switch tube T b3 On and switch T b1 and switch tube T b4 Shutdown; the fourth O represents the switch tube of phase C T c2 and switch tube T c3 On and switch T c1 and switch tube T c4 Turn off; at this time the capacitor C 1 and capacitor C 2 In charging state, the three-phase voltage of inverter level A, B and C U an , U bn and U cn Both are 0.

[0095] Preferably, when the switch capacitor voltage regulating circuit turns off the switch tube T 1. Turn on the switch tube T 2. Capacitor C 1 and capacitor C 2 Series discharge, capacitor C The positive output voltage of 1 is 2 V dc ,capacitance C 1 Negative output voltage is V dc When the switchT a2 and switch tube T a4 conduction, switch tube T a1 and switch tube T a3 Turn off; switch tube T b2 and switch tube T b4 conduction, switch tube T b1 and switch tube T b3 Turn off; switch tube T c2 and switch tube T c4 conduction, switch tube T c1 and switch tube T c3 Turn off; this corresponds to the PNNN state described above, where the first P represents the switch tube of the switched capacitor voltage regulation circuit T 1 is turned off and the switch tube T 2 is turned on, the output voltage is 2 V dc ; The second N represents the switch tube of phase A T a2 and switch tube T a4 On and switch T a1 and switch tube T a3 Turn off; the third N represents the switch tube of phase B T b2 and switch tube T b4 On and switch T b1 and switch tube T b3 Turn off; the fourth N represents the switch tube of phase C T c2 and switch tube T c4 On and switch T c1 and switch tube T c3 Shutdown, the three-phase voltage of inverter stages A, B and C U an , U bn and U cn Both are 0.

[0096] Preferably, when the switch capacitor voltage regulating circuit turns on the switch tube T 1. Turn off the switch tube T 2. The output voltage is V dc When the switch T a1 and switch tube T a3 conduction, switch tube T a2 and switch tube T a4 Turn off; switch tube T b1 and switch tube T b3 conduction, switch tube T b2 and switch tube T b4 Turn off; switch tube T c1 and switch tube T c3 conduction, switch tube T c2 and switch tube T c4 This corresponds to the NPPP state described above, where the first N represents the switching capacitor voltage regulation circuit. T 1 conduction, T 2 is turned off, the output voltage is V dc ; The second P represents the switch tube of phase A T a1 and switch tube T a3 On and switch T a2 and switch tube T a4 Turn off; the third P represents the switch tube of phase B T b1 and switch tube T b3 On and switch T b2 and switch tube T b4 Turn off; the fourth P represents the switch tube of phase C T c1 and switch tube T c3 On and switch T c2 and switch tube T c4 Turn off; at this time the capacitor C 1 and capacitorsC 2 In the charging state, the three-phase voltage of inverter level A, B and C U an , U bn and U cn Both V dc .

[0097] Preferably, when the switch capacitor voltage regulating circuit turns off the switch tube T 1. Turn on the switch tube T 2. Capacitor C 1 and capacitor C 2 Series discharge, capacitor C The positive output voltage of 1 is 2 V dc ,capacitance C 1 Negative output voltage is V dc When the switch T a2 and switch tube T a3 conduction, switch tube T a1 and switch tube T a4 Turn off; switch tube T b2 and switch tube T b3 conduction, switch tube T b1 and switch tube T b4 Turn off; switch tube T c2 and switch tube T c3 conduction, switch tube T c1 and switch tube T c4 Turn off; this corresponds to the POOO state described above, where the first P represents the switch tube of the switched capacitor voltage regulation circuit T 1 is turned off and switch tube T2 is turned on, the output voltage is 2 V dc ; The second O represents the switch tube of phase A T a2 and switch tube T a3 On and switch T a1 and switch tube T a4 Shutdown; the third 0 represents the switch tube of phase B Tb2 and switch tube T b3 On and switch T b1 and switch tube T b4 Turn off; the fourth 0 represents the switch tube of phase C T c2 and switch tube T c3 On and switch T c1 and switch tube T c4 Shutdown, the three-phase voltage of inverter stages A, B and C U an , U bn and U cn Both V dc .

[0098] Preferably, when the switch capacitor voltage regulating circuit turns off the switch tube T 1. Turn on the switch tube T 2. Capacitor C 1 and capacitor C 2 Series discharge, capacitor C The positive output voltage of 1 is 2 V dc ,capacitance C 1 Negative output voltage is V dc When the switch T a1 and switch tube T a3 conduction, switch tube T a2 and switch tube T a4 Turn off; switch tube T b1 and switch tube T b3 conduction, switch tube T b2 and switch tube T b4 Turn off; switch tube T c1 and switch tube T c3 conduction, switch tube T c2 and switch tube T c4 Turn off; this corresponds to the PPPP state described above, where the first P represents the switching capacitor voltage regulation circuitT 1 off, T 2 is turned on, the output voltage is 2 V dc ; The second P represents the switch tube of phase A T a1 and switch tube T a3 On and switch T a2 and switch tube T a4 Turn off; the third P represents the switch tube of phase B T b1 and switch tube T b3 On and switch T b2 and switch tube T b4 Turn off; the fourth P represents the switch tube of phase C T c1 and switch tube T c3 On and switch T c2 and switch tube T c4 Shutdown; three-phase voltage of inverter stages A, B, and C U an , U bn and U cn Both are 2 V dc .

[0099] Preferably, Figure 3 As shown, when the switch capacitor voltage regulating circuit turns on the switch tube T 1. Turn off the switch tube T 2. The output voltage is V dc When the switch T a1 and switch tube T a3 conduction, switch tube T a2 and switch tube T a4 Turn off; switch tube T b1 and switch tube T b3 conduction, switch tube T b2 and switch tube T b4 Turn off; switch tube T c1and switch tube T c3 Turn off, switch tube T c2 and switch tube T c4 This corresponds to the NPPN state described above, where the first N represents the switch tube of the switched capacitor voltage regulation circuit. T 1 is turned on and the switch tube T 2 is turned off, the output voltage is V dc ; The second P represents the switch tube of phase A T a1 and switch tube T a3 On and switch T a2 and switch tube T a4 Turn off; the third P represents the switch tube of phase B T b1 and switch tube T b3 On and switch T b2 and switch tube T b4 Turn off; the fourth N represents the switch tube of phase C T c1 and switch tube T c3 Turn off and switch T c2 and switch tube T c4 At this time, the capacitor C 1 and capacitor C 2 In parallel charging state, the three-phase voltage of inverter stages A, B and C U an , U bn and U cn They are: V dc / 3, V dc / 3,-2 V dc / 3.

[0100] Preferably, Figure 4 As shown, when the switch capacitor voltage regulating circuit turns off the switch tube T 1. Turn on the switch tube T 2. Capacitor C 1 and capacitor C 2 Series discharge, capacitor C The positive output voltage of 1 is 2V dc ,capacitance C 1 Negative output voltage is V dc When the switch T a2 and switch tube T a3 conduction, switch tube T a1 and switch tube T a4 Turn off; switch tube T b2 and switch tube T b3 conduction, switch tube T b1 and switch tube T b4 Turn off; switch tube T c1 and switch tube T c3 Turn off, switch tube T c2 and switch tube T c4 This corresponds to the POON state described above, where the first P represents the switch tube of the switched capacitor voltage regulation circuit. T 1 is turned off and the switch tube T 2 is turned on, the output voltage is 2 V dc ; The second O represents the switch tube of phase A T a2 and switch tube T a3 On and switch T a1 and switch tube T a4 Shutdown; the third O represents the B phase T b2 and switch tube T b3 On and switch T b1 and switch tube T b4 Turn off; the fourth N represents the switch tube of phase C T c2 and switch tube T c4 On and switch T c1 and switch tube T c3 Shutdown, the three-phase voltage of inverter stages A, B and C U an ,U bn and U cn They are: V dc / 3, V dc / 3,-2 V dc / 3.

[0101] Preferably, Figure 5 As shown, when the switch capacitor voltage regulating circuit turns off the switch tube T 1. Turn on the switch tube T 2. Capacitor C 1 and capacitor C 2 Series discharge, capacitor C The positive output voltage of 1 is 2 V dc ,capacitance C 1 Negative output voltage is V dc When the switch T a1 and switch tube T a3 conduction, switch tube T a2 and switch tube T a4 Turn off; switch tube T b1 and switch tube T b3 conduction, switch tube T b2 and switch tube T b4 Turn off; switch tube T c2 and switch tube T c3 conduction, switch tube T c1 and switch tube T c4 Turn off; this corresponds to the PPPO state described above, where the first P represents the switch tube of the switched capacitor voltage regulation circuit T 1 is turned off and the switch tube T 2 is turned on, the output voltage is 2 V dc ; The second P represents the switch tube of phase A T a1 and switch tube T a3 On and switch T a2 and switch tube T a4Turn off; the third P represents the switch tube of phase B T b1 and switch tube T b3 On and switch T b2 and switch tube T b4 Shutdown; the fourth O represents the switch tube of phase C T c2 and switch tube T c3 On and switch T c1 and switch tube T c4 Shutdown, the three-phase voltage of inverter stages A, B and C U an , U bn and U cn They are: V dc / 3, V dc / 3,-2 V dc / 3.

[0102] Preferably, Figure 6 As shown, when the switch capacitor voltage regulating circuit turns on the switch tube T 1. Turn off the switch tube T 2. The output voltage is V dc When the switch T a1 and switch tube T a3 conduction, switch tube T a2 and switch tube T a4 Turn off; switch tube T b2 and switch tube T b4 conduction, switch tube T b1 and switch tube T b3 Turn off; switch tube T c2 and switch tube T c4 conduction, switch tube T c1 and switch tube T c3 Turn off; this corresponds to the NPNN state described above, where the first N represents the switch tube of the switched capacitor voltage regulator circuitT 1 is turned on and the switch tube T 2 is turned off, the output voltage is V dc ; The second P represents the switch tube of phase A T a1 and switch tube T a3 On and switch T a2 and switch tube T a4 Turn off; the third N represents the switch tube of phase B T b2 and switch tube T b4 On and switch T b1 and switch tube T b3 Turn off; the fourth N represents the switch tube of phase C T c2 and switch tube T c4 On and switch T c1 and switch tube T c3 Turn off; at this time the capacitor C 1 and capacitor C 2 In charging state, the three-phase voltage of inverter level A, B and C U an , U bn and U cn In order: 2 V dc / 3,- V dc / 3,- V dc / 3.

[0103] Preferably, Figure 7 As shown, when the switch capacitor voltage regulating circuit turns off the switch tube T 1. Turn on the switch tube T 2. Capacitor C 1 and capacitor C 2 Series discharge, capacitor C The positive output voltage of 1 is 2 V dc ,capacitance C 1 Negative output voltage is V dc When the switch T a2 and switch tube T a3conduction, switch tube T a1 and switch tube T a4 Turn off; switch tube T b2 and switch tube T b4 conduction, switch tube T b1 and switch tube T b3 Turn off; switch tube T c2 and switch tube T c4 conduction, switch tube T c1 and switch tube T c3 Turn off; this corresponds to the PONN state described above, where the first P represents the switch tube of the switched capacitor voltage regulator circuit T 1 is turned off and the switch tube T 2 is turned on, the output voltage is 2 V dc ; The second O represents the switch tube of phase A T a2 and switch tube T a3 On and switch T a1 and switch tube T a4 Turn off; the third N represents the switch tube of phase B T b2 and switch tube T b4 On and switch T b1 and switch tube T b3 Turn off; the fourth N represents the switch tube of phase C T c2 and switch tube T c4 On and switch T c1 and switch tube T c3 Shutdown, the three-phase voltage of inverter stages A, B and C U an , U bn and U cn In order: 2 V dc / 3,- V dc / 3,- V dc / 3.

[0104] Preferably, Figure 8 As shown, when the switch capacitor voltage regulating circuit turns off the switch tube T 1. Turn on the switch tube T 2. Capacitor C 1 and capacitor C 2 Series discharge, capacitor C The positive output voltage of 1 is 2 V dc ,capacitance C 1 Negative output voltage is V dc When the switch T a1 and switch tube T a3 conduction, switch tube T a2 and switch tube T a4 Turn off; switch tube T b2 and switch tube T b3 conduction, switch tube T b1 and switch tube T b4 Turn off; switch tube T c2 and switch tube T c3 conduction, switch tube T c1 and switch tube T c4 Turn off; this corresponds to the PPOO state described above, where the first P represents the switch tube of the switched capacitor voltage regulation circuit T 1 is turned off and the switch tube T 2 is turned on, the output voltage is 2 V dc ; The second P represents the switch tube of phase A T a1 and switch tube T a3 On and switch T a2 and switch tube T a4 Shutdown; the third O represents the switch tube of phase B T b2 and switch tube T b3 On and switch T b1 and switch tube T b4 Shutdown; the fourth O represents the switch tube of phase CT c2 and switch tube T c3 On and switch T c1 and switch tube T c4 Shutdown, the three-phase voltage of inverter stages A, B and C U an , U bn and U cn In order: 2 V dc / 3,- V dc / 3,- V dc / 3.

[0105] Preferably, Figure 9 As shown, when the switch capacitor voltage regulating circuit turns off the switch tube T 1. Turn on the switch tube T 2. Capacitor C 1 and capacitor C 2 Series discharge, capacitor C The positive output voltage of 1 is 2 V dc ,capacitance C 1 Negative output voltage is V dc When the switch T a1 and switch tube T a3 conduction, switch tube T a2 and switch tube T a4 Turn off; switch tube T b2 and switch tube T b3 conduction, switch tube T b1 and switch tube T b4 Turn off; switch tube T c2 and switch tube T c4 conduction, switch tube T c1 and switch tube T c3 This corresponds to the PPON state described above, where the first P represents the switch tube of the switched capacitor voltage regulation circuit. T 1 is turned off and the switch tube T 2 is turned on, the output voltage is 2V dc ; The second P represents the switch tube of phase A T a1 and switch tube T a3 On and switch T a2 and switch tube T a4 Shutdown; the third O represents the switch tube of phase B T b2 and switch tube T b3 On and switch T b1 and switch tube T b4 Turn off; the fourth N represents the switch tube of phase C T c2 and switch tube T c4 On and switch T c1 and switch tube T c3 Shutdown, the three-phase voltage of inverter stages A, B and C U an , U bn and U cn They are: V dc ,0,- V dc .

[0106] Preferably, Figure 10 As shown, when the switch capacitor voltage regulating circuit turns off the switch tube T 1. Turn on the switch tube T 2. Capacitor C 1 and capacitor C 2 Series discharge, capacitor C The positive output voltage of 1 is 2 V dc ,capacitance C 1 Negative output voltage is V dc When the switch T a1 and switch tube T a3 conduction, switch tube T a2 and switch tube T a4 Turn off; switch tube T b1 and switch tube T b3conduction, switch tube T b2 and switch tube T b4 Turn off; switch tube T c2 and switch tube T c4 conduction, switch tube T c1 and switch tube T c3 Turn off; this corresponds to the PPPN state described above, where the first P represents the switch tube of the switched capacitor voltage regulation circuit T 1 is turned off and the switch tube T 2 is turned on, the output voltage is 2 V dc ; The second P represents the switch tube of phase A T a1 and switch tube T a3 On and switch T a2 and switch tube T a4 Turn off; the third P represents the switch tube of phase B T b1 and switch tube T b3 On and switch T b2 and switch tube T b4 Turn off; the fourth N represents the switch tube of phase C T c2 and switch tube T c4 On and switch T c1 and switch tube T c3 Shutdown, the three-phase voltage of inverter stages A, B and C U an , U bn and U cn In order: 2 V dc / 3,2 V dc / 3, -4 V dc / 3.

[0107] Preferably, Figure 11 As shown, when the switch capacitor voltage regulating circuit turns off the switch tube T 1. Turn on the switch tube T 2. Capacitor C 1 and capacitorC 2 Series discharge, capacitor C The positive output voltage of 1 is 2 V dc ,capacitance C 1 Negative output voltage is V dc When the switch T a1 and switch tube T a3 conduction, switch tube T a2 and switch tube T a4 Turn off; switch tube T b2 and switch tube T b4 conduction, switch tube T b1 and switch tube T b3 Turn off; switch tube T c2 and switch tube T c4 conduction, switch tube T c1 and switch tube T c3 Turn off; this corresponds to the PPNN state described above, where the first P represents the switch tube of the switched capacitor voltage regulator circuit T 1 is turned off and the switch tube T 2 is turned on, the output voltage is 2 V dc ; The second P represents the switch tube of phase A T a1 and switch tube T a3 On and switch T a2 and switch tube T a4 Turn off; the third N represents the switch tube of phase B T b2 and switch tube T b4 On and switch T b1 and switch tube T b3 Turn off; the fourth N represents the switch tube of phase C T c2 and switch tube T c4 On and switch T c1 and switch tube T c3Shutdown, the three-phase voltage of inverter stages A, B and C U an , U bn and U cn In order: 4 V dc / 3,-2 V dc / 3,-2 V dc / 3.

[0108] Embodiment 2: The present invention further proposes an SVPWM modulation strategy for a three-level boost inverter based on switched capacitors, comprising:

[0109] Definition: For the front-stage switched capacitor voltage regulator circuit, P represents the switch tube T 2 is turned on and the switch tube T 1 off, capacitor C 1 and capacitor C 2 Series discharge, capacitor C The positive output voltage of 1 is 2 V dc ,capacitance C 1 Negative output voltage is V dc ; N represents the switch tube T 1 is turned on and the switch tube T 2 off, capacitor C 1 and capacitor C 2 parallel charging, the output voltage is V dc ; For the F-type three-phase inverter circuit at the rear stage, P represents the switch tube T x1 and switch tube T x3 On and switch T x2 and switch tube T x4 Turn off; N indicates the switch tube T x1 and switch tube T x3 Turn off and switch T x2 and switch tube T x4 On; O indicates switch tube T x2 and switch tube T x3 On and switch T x1 and switch tube T x4 Shutdown (x = a , b , c ).

[0110] According to the target output voltage amplitude | u ref |Calculate its components in the α-β coordinate system: u α =| u ref |sin( w t), u β =| u ref |cos( w t), determine the sector where the reference vector is located, where the sector where the reference vector is located includes 6 large sectors; Figure 12 As shown, the three-level inverter circuit described in this application adopts space vector pulse width modulation, in which the basic voltage vector includes 6 zero vectors and 30 effective vectors. Each switching state corresponds to a basic vector. In the basic vector corresponding to the switching state, when the charging vector acts, it will not cause capacitance even if the action time is long. C 1 、 C 2 The voltage fluctuates significantly; when the discharge vector acts, the two capacitors discharge in series to the load to generate 2 V dc When the output voltage is released, its stored energy will be released quickly. If the action time is too long, the capacitor voltage will drop sharply. To maintain the stability of the capacitor voltage, this solution uses a regional vector selection strategy to ensure that in any reference voltage vector region, the selected basic vector contains both an effective charging vector to replenish the capacitor energy and the necessary discharge vector to complete the voltage output. The action time of the charging vector is maximized by optimizing the duty cycle distribution. This dynamic charge balance mechanism can effectively suppress voltage fluctuations caused by excessive capacitor discharge and improve the reliability of system operation. Therefore, in the actual modulation strategy, in order to ensure the balance of charge and discharge of the capacitor voltage and take into account the fewer switching times of the switch tube each time the vector changes, the zero vector only selects NNNN, and the short vector only selects NPNN, NPPN, NNPN, NNPP, NNNP, and NPNP.

[0111] like Figure 12 As shown, the remaining 19 basic vectors are used to form a space vector hexagon, which is divided into six large sectors. Each large sector is divided into four small areas. Any vector can be synthesized from the basic vectors in its small area. The size of the basic vector cannot be changed. The action time of each basic vector can be calculated according to the volt-second balance principle to synthesize the reference vector. The formation of each basic vector is as follows:

[0112] Take the first largest sector as an example:

[0113] When the switch state is (N, N, N, N), the switch tube T 1, T a2 , T a4 , T b2 , T b4 , T c2 , T c4 conduction, switch tube T 2, T a1 , T a3 , T b1 , T b3 , T c1 , T c3 Turn off, the capacitor C 1. C 2 is connected in parallel with the power supply, and the power supply passes through the diode D 1 for capacitor C 1 Charging, through the diode D 2 capacitors C 2 charging, at this time the output voltage of the switched capacitor voltage regulator circuit is V dc , and as the input of the inverter stage, after the action of F-type full-bridge inverter, the three-phase voltage of the inverter stage A, B, and C U an , U bn and U cn Both are 0.

[0114] When the switch state is (N, P, P, N), the switch tube T 1, T a1 , T a3 , T b1 , T b3 , T c2 , T c4 conduction, switch tube T 2, T a2 ,T a4 , T b2 , T b4 , T c1 , T c3 Turn off, the capacitor C 1. C 2 is connected in parallel with the power supply, and the power supply passes through the diode D 1 for capacitor C 1 Charging, through the diode D 2 capacitors C 2 charging, at this time the output voltage of the switched capacitor voltage regulator circuit is V dc , and as the input of the inverter stage, after the action of the F-type full-bridge inverter, the three-phase voltage of the inverter stage A, B and C U an , U bn and U cn They are: V dc / 3, V dc / 3,-2 V dc / 3.

[0115] When the switch state is (N, P, N, N), the switch tube T 1, T a1 , T a3 , T b2 , T b4 , T c2 , T c4 conduction, switch tube T 2, T a2 , T a4 , T b1 , T b3 , T c1 , T c3 Turn off, the capacitor C 1. C 2 is connected in parallel with the power supply, and the power supply passes through the diode D 1 for capacitor C 1 Charging, through the diodeD 2 capacitors C 2 charging, at this time the output voltage of the switched capacitor voltage regulator circuit is V dc , and as the input of the inverter stage, after the action of the F-type full-bridge inverter, the three-phase voltage of the inverter stage A, B and C U an , U bn and U cn In order: 2 V dc / 3,- V dc / 3,- V dc / 3.

[0116] When the switch state is (P, P, O, N), the switch tube T2, T a1 , T a3 , T b2 , T b3 , T c2 , T c4 conduction, switch tube T 1, T a2 , T a4 , T b1 , T b4 , T c1 , T c3 Shutdown, capacitor C 1, C 2Through the switch tube T 2 series discharge, diode D 1. D 2 reverse cutoff, at this time the output voltage of the switched capacitor voltage regulator circuit is 2 V dc , and as the input of the inverter stage, after the action of the F-type full-bridge inverter, the three-phase voltage of the inverter stage A, B and C U an , U bn and U cn They are: V dc ,0,- V dc .

[0117] When the switch state is (P, P, N, N), the switch tube T 2, T a1 , T a3 , T b2 , T b4 , T c2 , T c4 conduction, switch tube T 1, T a2 , T a4 , T b1 , T b3 , T c1 , T c3 Shutdown, capacitor C 1, C 2Through the switch tube T 2 series discharge, diode D 1. D 2 reverse cutoff, at this time the output voltage of the switched capacitor voltage regulator circuit is 2 V dc , and as the input of the inverter stage, after the action of the F-type full-bridge inverter, the three-phase voltage of the inverter stage A, B and C U an , U bn and U cn In order: 4 V dc / 3,-2 V dc / 3,-2 V dc / 3.

[0118] When the switch state is (P, P, P, N), the switch tube T 2, T a1 , T a3 , T b1 , T b3 , T c2 , T c4 conduction, switch tube T 1,T a2 , T a4 , T b2 , T b4 , T c1 , T c3 Shutdown, capacitor C 1, C 2Through the switch tube T 2 series discharge, diode D 1. D 2 reverse cutoff, at this time the output voltage of the switched capacitor voltage regulator circuit is 2 V dc , and as the input of the inverter stage, after the action of the F-type full-bridge inverter, the three-phase voltage of the inverter stage A, B and C U an , U bn and U cn In order: 2 V dc / 3,2 V dc / 3, -4 V dc / 3.

[0119] Furthermore, a space vector modulation strategy is adopted, such as Figure 13 As shown, taking the first largest sector as an example, when When the reference voltage vector is located in the first small sector, the voltage reference vector u ref By basis vector u 0, u 1, u 2 synthesis; when When the reference voltage vector is located in the second small sector, the voltage reference vector u ref By basis vector u 1, u 3. u 4 synthesis; when When the reference voltage vector is located in the fourth sector, the voltage reference vector u ref By basis vector u 2, u 4. u 5 synthesis; In addition to the above situation, the reference voltage vector is located in the third small sector, the voltage reference vector u ref By basis vector u 1, u2, u 4 synthesis.

[0120] When synthesizing the voltage reference vector, the following conditions must be met as much as possible: 1) Within a switching cycle, if there is a long or medium vector that discharges the capacitors in series, a short vector that charges the capacitors in parallel should be selected whenever possible to ensure capacitor voltage balance; 2) When the switch state changes, the principle of minimum switching times should be adopted, and a single-step switching path should be preferred, that is, only the switching state of one bridge arm should be changed, and simultaneous switching of multiple bridge arms should be avoided as much as possible; 3) Within a switching cycle, the base voltage vectors at the beginning and end must be the same to avoid switch operation when switching cycles are connected within the same sector.

[0121] The above three measures can effectively reduce switching losses, lower the even harmonic components of the output waveform, maintain capacitor voltage self-balance, and improve circuit reliability. Therefore, this modulation strategy adopts a five-segment symmetrical wave generation. The order of action of the basic voltage vectors in each sector is summarized in Table 1.

[0122] Table 1 Basic voltage vector action sequence table

[0123]

[0124] For the first largest sector:

[0125] Set the reference voltage u ref Decomposed into the α-β axis: u α =| u ref |sin( w t), u β =| u ref |cos( w t);

[0126] When the reference vector is in the first small sector in the first large sector, it is composed of vector (N, N, N, N), vector (N, P, P, N), and vector (N, P, N, N);

[0127] Among them, the basic vector (N, N, N, N) is a zero vector, and its duty cycle is recorded as: ;

[0128] The duty cycle of the vector (N, P, P, N) is: ;

[0129] The duty cycle of the vector (N, P, N, N) is: .

[0130] When the reference vector is in the second small sector in the first large sector, it is composed of vector (N, P, N, N), vector (P, P, O, N), and vector (P, P, N, N);

[0131] in:

[0132] The duty cycle of the vector (N, P, N, N) is:

[0133] ;

[0134] The duty cycle of the vector (P, P, O, N) is:

[0135] ;

[0136] The duty cycle of the vector (P, P, N, N) is:

[0137] ;

[0138] When the reference vector is the third small sector in the first large sector, it is composed of vector (N, P, P, N), vector (N, P, N, N), and vector (P, P, O, N);

[0139] in:

[0140] The duty cycle of the vector (N, P, P, N) is:

[0141] ;

[0142] The duty cycle of the vector (N, P, N, N) is:

[0143] ;

[0144] The duty cycle of the vector (P, P, O, N) is:

[0145] ;

[0146] When the reference vector is in the fourth small sector in the first large sector, it is composed of vector (N, P, P, N), vector (P, P, P, N), and vector (P, P, O, N);

[0147] in:

[0148] The duty cycle of the vector (N, P, P, N) is:

[0149] ;

[0150] The duty cycle of the vector (P, P, P, N) is:

[0151] ;

[0152] The duty cycle of the vector (P, P, O, N) is:

[0153] ;

[0154] The basic vector duty cycle of other sectors can be solved by rotating the α-β coordinate system to the first largest sector and using the same expression. According to the reference vector synthesis order set for the first largest sector, the synthesis path of the reference vectors in other large sectors can be determined: the vector synthesis path of the third and fifth largest sectors is the same as that of the first largest sector, and the vector synthesis path of the second, fourth and sixth largest sectors is opposite to that of the first largest sector.

[0155] The above shows and describes the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions merely illustrate the principles of the present invention. Various changes and modifications may be made to the present invention without departing from the spirit and scope of the present invention. Such changes and modifications are intended to fall within the scope of the present invention. The scope of protection claimed by the present invention is defined by the appended claims and their equivalents.

Claims

1. A three-level boost inverter based on switched capacitors, characterized in that: include: Switch capacitor voltage regulation circuit and F-type three-phase full-bridge inverter circuit; wherein, the switch capacitor voltage regulation circuit is composed of a switch tube T 1. Switching tube T 2. Diode D 1. Diode D 2. Capacitor C 1 and capacitor C 2 composition; wherein, the switch tube T 1. Connect one end to a DC voltage source V dc , and the other end is connected to the switch tube T 2 and diode D 1. The diode D 1 The other end is connected to the capacitor C 1 and F type three-phase full-bridge inverter circuit; the capacitor C 1The other end is connected to the switch tube T 2. Diode D 2 and F-type three-phase full-bridge inverter circuit, the diode D 2 The other end is also connected to the capacitor C 2 and F type three-phase full-bridge inverter circuit; the switch tube T 1 and switch tube T 2 is a complementary relationship; the F-type three-phase full-bridge inverter circuit is composed of three-phase bridge arms A, B, and C; Phase A bridge arm, consisting of switch tube T a1 , switch tube T a2 , switch tube T a3 and switch tube T a4 composition; The B-phase bridge arm consists of a switch tube T b1 , switch tube T b2 , switch tube T b3 and switch tube T b4 composition; The C phase bridge arm consists of a switch tube T c1 , switch tube T c2 , switch tube T c3 and switch tube T c4 composition; When the switch T 1. Switching tube T a2 , switch tube T a4 , switch tube T b2 , switch tube T b4 , switch tube T c2 , T c4 The switch is turned on and T 2. Switching tube T a1 , switch tube T a3 , switch tube T b1 , switch tube T b3 , switch tube T c1 , switch tube T c3 Turn off, the capacitor C 1. Capacitor C 2 is connected in parallel with the power supply, and the power supply passes through the diode D 1 for capacitor C 1 Charging, through the diode D 2 capacitors C 2 charging, at this time the output voltage of the switched capacitor voltage regulator circuit is V dc , and as the input of the inverter stage, after the action of F-type full-bridge inverter, the three-phase voltage of the inverter stage A, B, and C U an , U bn and U cn Both are 0.

2. The three-level boost inverter based on switched capacitor according to claim 1, characterized in that: The three-phase bridge arm, include: Wherein, the A-phase bridge arm, the B-phase bridge arm and the C-phase bridge arm are connected in parallel; The three-phase full-bridge inverter circuit adopts a space vector pulse width modulation (SVPWM) strategy to decompose the voltage reference vector into an α-β coordinate system and realizes a three-phase AC output by synthesizing basic voltage vectors.

3. A three-level boost inverter based on switched capacitors according to any one of claims 1-2, characterized in that: Also includes: When the switch is turned on T 1. Turn off the switch tube T 2, then the capacitance C 1 and capacitor C 2 parallel charging, the output voltage of the switched capacitor voltage regulation circuit is V dc ; When the switch is turned off T 1. Turn on the switch tube T 2, then the capacitance C 1 and capacitor C 2 Series discharge, switched capacitor voltage regulator circuit in capacitor C The positive output voltage of 1 is 2 V dc , in capacitor C The negative output voltage of 1 is V dc .

4. The three-level boost inverter based on switched capacitor according to claim 3, characterized in that: When the switch T 1. Switching tube T a1 , switch tube T a3 , switch tube T b1 , switch tube T b3 , switch tube T c2 , switch tube T c4 The switch is turned on and T 2. Switching tube T a2 , switch tube T a4 , switch tube T b2 , switch tube T b4 , switch tube T c1 , switch tube T c3 Turn off, the capacitor C 1. Capacitor C 2 is connected in parallel with the power supply, and the power supply passes through the diode D 1 for capacitor C 1 Charging, through the diode D 2 capacitors C 2 charging, at this time the output voltage of the switched capacitor voltage regulator circuit is V dc , and as the input of the inverter stage, after the action of the F-type full-bridge inverter, the three-phase voltage of the inverter stage A, B and C U an , U bn and U cn They are: V dc / 3, V dc / 3,-2 V dc / 3; When the switch T 1. Switching tube T a1 , switch tube T a3 , switch tube T b2 , switch tube T b4 , switch tube T c2 , switch tube T c4 conduction, switch tube T 2. Switching tube T a2 , switch tube T a4 , switch tube T b1 , switch tube T b3 , switch tube T c1 , switch tube T c3 Turn off, the capacitor C 1. Capacitor C 2 is connected in parallel with the power supply, and the power supply passes through the diode D 1 for capacitor C 1 Charging, through the diode D 2 capacitors C 2 charging, at this time the output voltage of the switched capacitor voltage regulator circuit is V dc , and as the input of the inverter stage, after the action of the F-type full-bridge inverter, the three-phase voltage of the inverter stage A, B and C U an , U bn and U cn In order: 2 V dc / 3,- V dc / 3,- V dc / 3.

5. The three-level boost inverter based on switched capacitor according to claim 3, characterized in that: When the switch tube T2, the switch tube T a1 , switch tube T a3 , switch tube T b2 , switch tube T b3 , switch tube T c2 , switch tube T c4 conduction, switch tube T 1. Switching tube T a2 , switch tube T a4 , switch tube T b1 , switch tube T b4 , switch tube T c1 , switch tube T c3 Shutdown, capacitor C 1. Capacitor C 2Through the switch tube T 2 series discharge, diode D 1. Diode D 2 reverse cutoff, at this time the output voltage of the switched capacitor voltage regulator circuit is 2 V dc , and as the input of the inverter stage, after the action of the F-type full-bridge inverter, the three-phase voltage of the inverter stage A, B and C U an , U bn and U cn They are: V dc ,0,- V dc ; When the switch T 2. Switching tube T a1 , switch tube T a3 , switch tube T b2 , switch tube T b4 , switch tube T c2 , switch tube T c4 conduction, switch tube T 1. Switching tube T a2 , switch tube T a4 , switch tube T b1 , switch tube T b3 , switch tube T c1 , switch tube T c3 Shutdown, capacitor C 1. Capacitor C 2Through the switch tube T 2 series discharge, diode D 1 and diode D 2 reverse cutoff, at this time the output voltage of the switched capacitor voltage regulator circuit is 2 V dc , and as the input of the inverter stage, after the action of the F-type full-bridge inverter, the three-phase voltage of the inverter stage A, B and C U an , U bn and U cn In order: 4 V dc / 3,-2 V dc / 3,-2 V dc / 3; When the switch T 2. Switching tube T a1 , switch tube T a3 , switch tube T b1 , switch tube T b3 , switch tube T c2 , switch tube T c4 conduction, switch tube T 1. Switching tube T a2 , switch tube T a4 , switch tube T b2 , switch tube T b4 , switch tube T c1 , switch tube T c3 Shutdown, capacitor C 1. Capacitor C 2Through the switch tube T 2 series discharge, diode D 1 and diode D 2 reverse cutoff, at this time the output voltage of the switched capacitor voltage regulator circuit is 2 V dc , and as the input of the inverter stage, after the action of the F-type full-bridge inverter, the three-phase voltage of the inverter stage A, B and C U an , U bn and U cn In order: 2 V dc / 3,2 V dc / 3, -4 V dc / 3.

6. A modulation strategy for a three-level boost inverter based on switched capacitors according to any one of claims 1 to 5, characterized in that: Definition: For the front-stage switched capacitor voltage regulator circuit, P represents the switch tube T 2 is turned on and the switch tube T 1 off, capacitor C 1 and capacitor C 2 Series discharge, capacitor C The positive output voltage of 1 is 2 V dc ,capacitance C 1 Negative output voltage is V dc ; N represents the switch tube T 1 is turned on and the switch tube T 2 off, capacitor C 1 and capacitor C 2 parallel charging, the output voltage is V dc ; For the F-type three-phase inverter circuit at the rear stage, P represents the switch tube T x1 and switch tube T x3 On and switch T x2 and switch tube T x4 Turn off; N indicates the switch tube T x1 and switch tube T x3 Turn off and switch T x2 and switch tube T x4 On; O indicates switch tube T x2 and switch tube T x3 On and switch T x1 and switch tube T x4 Shutdown ( x = a , b , c ); According to the target output voltage amplitude | u ref |Calculate its components in the α-β coordinate system: u α =| u ref |sin( w t), u β =| u ref |cos( w t), determine the sector where the reference vector is located, where the sector where the reference vector is located includes 6 large sectors; When the reference vector is in the first small sector in the first large sector, it is composed of vector (N, N, N, N), vector (N, P, P, N), and vector (N, P, N, N); Among them, the basic vector (N, N, N, N) is a zero vector, and its duty cycle is recorded as: D 0=(2 V dc -3 u α - u β ) / (2 V dc ); The duty cycle of the vector (N, P, P, N) is: D 2= u β / V dc ; The duty cycle of the vector (N, P, N, N) is: D 1=(3 u α - u β ) / (2 V dc ).

7. The modulation strategy according to claim 6, characterized in that: When the reference vector is in the second small sector in the first large sector, it is composed of vector (N, P, N, N), vector (P, P, O, N), and vector (P, P, N, N); Where: The duty cycle of the vector (N, P, N, N) is: D 1=(4 V dc -3 u α - u β ) / (2 V dc )； The duty cycle of the vector (P, P, O, N) is: D 4= u β / V dc ; The duty cycle of the vector (P, P, N, N) is: D 3=(3 u α - u β -2 V dc ) / (2 V dc )。 8. The modulation strategy according to claim 6, characterized in that: When the reference vector is the third small sector in the first large sector, it is composed of vector (N, P, P, N), vector (N, P, N, N), and vector (P, P, O, N); Where: The duty cycle of the vector (N, P, P, N) is: D 2=1+( u β -3 u α ) / (2 V dc )； The duty cycle of the vector (N, P, N, N) is: D 1=1- u β / V dc ; The duty cycle of the vector (P, P, O, N) is: D 4=( u β +3 u α ) / (2 V dc )-1。 9. The modulation strategy according to claim 6, characterized in that: When the reference vector is in the fourth small sector in the first large sector, it is composed of vector (N, P, P, N), vector (P, P, P, N), and vector (P, P, O, N); Where: The duty cycle of the vector (N, P, P, N) is: D 2=2-( u β +3 u α ) / (2 V dc )； The duty cycle of the vector (P, P, P, N) is: D 5= u β / V dc -1; The duty cycle of the vector (P, P, O, N) is: D 4=(3 u α - u β ) / (2 V dc )； The basic vector duty cycle of other sectors only needs to be rotated in the α-β coordinate system to the first largest sector and solved using the same expression; according to the reference vector synthesis order set for the first largest sector, the synthesis path of the reference vectors in other large sectors is determined: among them, the vector synthesis path of the third and fifth largest sectors is the same as that of the first largest sector, and the vector synthesis path of the second, fourth and sixth largest sectors is opposite to that of the first largest sector.

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