Super-junction IGBT (Insulated Gate Bipolar Translator) device with split gate structure and preparation method of super-junction IGBT device

Abstract

The invention belongs to the technical field of power semiconductor devices, and relates to a super-junction IGBT device with a split gate structure and a preparation method of the super-junction IGBT device. The device comprises collector metal, a P-type collector, an N-type field stop layer, a super junction N column, a super junction P column, a P-type buried layer, a trench gate structure and a trench emitter structure which are sequentially stacked from bottom to top, and the trench gate structure and the trench emitter structure are connected with an N-type charge storage layer, a P-type base region and an N + emitter region. The P columns / N columns of the device are alternately arranged in the Y direction, the cell width is reduced, meanwhile, the parasitic PMOS introduced by only adding one photoetching plate acts, and the device has high channel density and a wide short-circuit safe working area. In addition, the Miller capacitance of the super-junction IGBT is reduced, the negative gate capacitance effect is suppressed, the surge current of the device is reduced, and the control capability of the gate of the device on dv / dt is improved. According to the invention, an extra path is provided for redundant holes stored in the drift region, the turn-off speed of the device is obviously improved, and the switching loss is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductor devices, and particularly relates to a superjunction IGBT device with a split gate structure and a preparation method thereof. Background Art

[0002] The insulated gate bipolar transistor IGBT combines the advantages of the field effect transistor MOSFET and the bipolar crystalline transistor BJT, and has developed into one of the core electronic components in modern power electronic circuits. The IGBT has both the advantages of the MOSFET being easy to drive, having a low input impedance, and a fast switching speed, and the advantages of the BJT having a large on-state current density, a low on-state voltage drop, low losses, and good stability. As the mainstream power switching device in medium and high power power electronic circuits, the insulated gate bipolar transistor IGBT is widely used in the power electronic systems of new energy vehicles, new energy power generation, smart grids, high-speed railways, ship drives, motor drives, industrial control, uninterruptible power supplies, variable frequency household appliances, etc., and has a crucial impact on the performance and reliability of the system, and is known as the "CPU" in the industrial field. Since the advent of the IGBT, through continuous technological innovation, the device structure and process technology of the IGBT have achieved great development, significantly improving the performance and reliability of the device. Due to its excellent performance, the IGBT has become a research hotspot and the main development direction of power devices.

[0003] The IGBT uses a drift region with a low doping concentration to achieve high voltage resistance. However, there is a certain proportional relationship limitation between the breakdown voltage and the on-resistance, that is, the "silicon limit". In order to break through the "silicon limit", the superjunction theory was proposed: alternating N and P columns are introduced into the drift region, and the lateral depletion of the N and P columns is used to improve the electric field distribution, thereby obtaining higher voltage resistance. Superjunction devices are widely used in Schottky diodes, MOSFETs, and IGBTs due to their high voltage resistance and low on-resistance performance. Compared with traditional silicon-based IGBT devices, the superjunction IGBT has higher voltage resistance under the same drift region length. When the device is turned off, the depletion of the PN junction between the N and P columns will accelerate the extraction of carriers, thereby reducing the turn-off loss. For the superjunction IGBT structure, since the P column region is directly connected to the P-type base region, when the device conducts forward, the P column region provides a hole extraction channel, affecting the conductance modulation level in the SJ drift region during forward conduction, making the carrier concentration distribution in the device drift region not optimized, and restricting the improvement of the trade-off relationship between the forward on-state voltage drop and the turn-off loss of the device. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to propose a superjunction IGBT device with a split-gate structure and a manufacturing method thereof in view of the problems existing in the prior art, so as to reduce the cell width of the device, reduce the switching loss of the superjunction IGBT device, improve the short-circuit withstand ability of the device, and improve the trade-off between the forward conduction voltage Vceon and the turn-off loss Eoff of the device.

[0005] To solve the above technical problems, the technical solution of the present invention is as follows:

[0006] A superjunction IGBT device with a split-gate structure defines the three-dimensional directions of the device in a three-dimensional rectangular coordinate system: the lateral direction of the device is defined as the X-axis direction, the vertical direction of the device is defined as the Z-axis direction, and the longitudinal direction of the device, i.e., the third-dimensional direction, is defined as the Y-axis direction.

[0007] Its cell structure includes: a collector metal 1, a P-type collector 2, and an N-type field-stop layer 3 stacked in sequence from bottom to top along the Z-axis direction. Above the N-type field-stop layer 3, there are a superjunction N column 5 and a superjunction P column 4 in contact with each other on the side. Above the superjunction P column 4, there is a P-type buried layer 6. Above the superjunction N column 5 and the P-type buried layer 6 along the X-axis direction, there are a trench gate structure and a trench emitter structure.

[0008] The trench gate structure includes a split-gate dielectric layer 7-1, a split-gate electrode 8 above the split-gate dielectric layer 7-1, a polysilicon gate dielectric layer 7-2 above the split-gate electrode 8, and a polysilicon gate electrode 9 in the polysilicon gate dielectric layer 7-2; the trench emitter structure includes a split-gate dielectric layer 7-1, a split-gate electrode 15 above the split-gate dielectric layer 7-1, a polysilicon emitter dielectric layer 7-3 above the split-gate electrode 15, and a polysilicon emitter electrode 13 in the polysilicon emitter dielectric layer 7-3.

[0009] Above the superjunction N column 5 and the P-type buried layer 6, and between the trench gate structure and the trench emitter structure, there is an N-type charge storage layer 14. Along the Z-axis direction, above the N-type charge storage layer 14, there is a P-type base region 12. Above the P-type base region 12, there are an N+ emitter region 10 and a P+ contact region 11. Above the N+ emitter region 10 and above the P+ contact region 11, there is an emitter metal 16; the P-type buried layer 6 is only located above the superjunction P column 4 and not above the superjunction N column 5; the P-type buried layer 6 is in contact with the N-type charge storage layer 14 along the Z-axis direction; the superjunction N column 5 and the superjunction P column 4 are arranged alternately along the Y-axis direction; the N+ emitter region 10 and the P+ contact region 11 are arranged in sequence along the X-axis direction.

[0010] The polysilicon gate electrode 9 is connected to the N-type charge storage layer 14, P-type base region 12, N+ emitter region 10, and isolation electrode 8 through the polysilicon gate dielectric layer 7-2; the polysilicon emitter electrode 13 is connected to the N-type charge storage layer 14, P-type base region 12, and P+ contact region 11 through the polysilicon emitter dielectric layer 7-3;

[0011] The isolation gate electrode 8 is connected to the N-type charge storage layer 14 and the P-type buried layer 6 at the bottom of the left trench through the isolation gate dielectric layer 7-1; the isolation gate electrode 8 is equipotential with the emitter metal 16; the split gate electrode 15 is connected to the P-type buried layer 6 through the isolation gate dielectric layer 7-1; the split gate electrode 15, polysilicon emitter electrode 13, and isolation gate 8 are equipotential with the emitter metal 16;

[0012] In the Z-axis direction, the depths of the polysilicon gate electrode 9 and the polysilicon emitter electrode 13 exceed the depth of the P-type base region 12; the depths of the trench gate structure and the trench emitter structure are greater than the junction depth of the N-type charge storage layer 14 and less than the junction depth of the P-type buried layer 6; the thickness of the isolation gate dielectric layer 7-1 of the trench gate structure is greater than the thicknesses of the polysilicon gate dielectric layer 7-2 and the polysilicon emitter dielectric layer 7-3, and the doping concentration of the P-type buried layer 6 is greater than the doping concentration of the superjunction P column 4; the P-type buried layer 6 cannot be completely depleted before the device breaks down.

[0013] As a preferred embodiment, an N- drift region 17 is introduced between the superjunction N column 5 and the superjunction P column 4 and the N-type field stop layer 3 in the Z-axis direction, and the doping concentration of the N- drift region 17 is lower than the doping concentration of the superjunction N column 5.

[0014] As a preferred embodiment, the polysilicon gate electrode 13 is connected to the split gate electrode 15 through the polysilicon emitter dielectric layer 7-3; the split gate electrode 15 is connected to the N-type charge storage layer 14 and the P-type buried layer 6 at the bottom of the right trench through the isolation gate dielectric layer 7-1; the split gate electrode 15 is led out from the top of the device.

[0015] As a preferred embodiment, the isolation gate electrode 8 is led out from the top of the device; the extension depth of the N+ emitter region 10 at the top layer of the P-type base region 12 is less than the extension depth of the P+ contact region 11 at the top layer of the P-type base region 12.

[0016] As a preferred embodiment, a trench collector structure penetrating the N-type field stop layer 3 and the P-type collector 2 is introduced on the back of the device. The trench collector structure includes a trench collector 20 and a trench collector dielectric layer 19 on its periphery. The trench collector 20 is equipotential with the collector metal 1, and the trench collector 20 is isolated from the P-type collector 2, N-type field stop layer 3, superjunction P column 4, and superjunction N column 5 through the trench collector dielectric layer 19.

[0017] As a preferred embodiment, the extension depth of the N+ emitter region 10 at the top layer of the P-type base region 12 is less than the extension depth of the P+ contact region 11 at the top layer of the P-type base region 12; the isolation gate electrode 8 is led out from the top of the device.

[0018] As a preferred embodiment, an N- drift region 17 is introduced between the superjunction N column 5, the superjunction P column 4 and the N-type field stop layer 3 in the Z direction, and the doping concentration of the N- drift region 17 is lower than that of the superjunction N column 5.

[0019] The present invention also provides a second superjunction IGBT device with a split gate structure.

[0020] Define the three-dimensional directions of the device in a three-dimensional rectangular coordinate system: define the lateral direction of the device as the X-axis direction, define the vertical direction of the device as the Z-axis direction, and the longitudinal direction of the device, i.e., the third dimension direction, as the Y-axis direction:

[0021] Its cell structure includes: a collector metal 1, a P-type collector region 2, an N-type field stop layer 3 stacked in sequence from bottom to top along the Z-axis direction. Above the N-type field stop layer 3, there are a superjunction N column 5 and a superjunction P column 4 in contact with each other on the side. Above the superjunction P column 4, there is a P-type buried layer 6. Along the X-axis direction above the superjunction N column 5 and the P-type buried layer 6, there are a trench gate structure and a trench emitter structure.

[0022] The trench gate structure includes an isolation gate dielectric layer 7-1 and a polysilicon trench emitter electrode 18 above the isolation gate dielectric layer 7-1.

[0023] An N-type charge storage layer 14 is provided between the superjunction N column 5 and the P-type buried layer 6, above the trench gate structure and the trench emitter structure. Along the Z-axis direction, a P-type base region 12 is provided above the N-type charge storage layer 14. Above the P-type base region 12, there are an N+ emitter region 10 and a P+ contact region 11. Above the N+ emitter region 10 and above the P+ contact region 11, there is an emitter metal 16; the P-type buried layer 6 is only located above the superjunction P column 4 and not above the superjunction N column 5; the P-type buried layer 6 is in contact with the N-type charge storage layer 14 along the Z-axis direction; the superjunction N column 5 and the superjunction P column 4 are arranged alternately along the Y-axis direction; the N+ emitter region 10 and the P+ contact region 11 are arranged in sequence along the X-axis direction.

[0024] The polysilicon gate electrode 9 is connected to the N-type charge storage layer 14, the P-type base region 12, and the N+ emitter region 10 through a polysilicon gate dielectric layer 7-2; the isolation gate electrode 8 is connected to the P-type buried layer 6 through an isolation gate dielectric layer 7-1; the isolation gate electrode 8 and the emitter metal 16 are at the same potential.

[0025] The polysilicon trench emitter electrode 18 is connected to the P+ contact region 11, the P-type base region 12, the N-type charge storage layer 14, and the P-type buried layer 6 at the bottom of the right trench through the isolation gate dielectric layer 7-1; the polysilicon trench emitter electrode 18, the isolation gate electrode 8, and the emitter metal 16 are at the same potential.

[0026] In the Z-axis direction, the depth of the polysilicon gate electrode 9 exceeds the depth of the P-type base region 12; the depths of the trench gate structure and the trench emitter structure are greater than the junction depth of the N-type charge storage layer 14 and less than the junction depth of the P-type buried layer 6; the thickness of the isolation gate dielectric layer 7-1 of the trench gate structure is greater than the thickness of the polysilicon gate dielectric layer 7-2, and the doping concentration of the P-type buried layer 6 is greater than the doping concentration of the superjunction P column 4; the P-type buried layer 6 cannot be completely depleted before the device breakdown.

[0027] The present invention also provides a method for manufacturing a superjunction IGBT device with a split gate structure, including the following steps:

[0028] Step 1: Use an N-type doped single-crystal silicon wafer as the substrate.

[0029] Step 2: Epitaxially grow N-type doped silicon on the single-crystal silicon wafer, and then etch back the excess silicon on the surface to form an N-type doped drift region.

[0030] Step 3: Deposit a protective layer on the silicon wafer surface, lithographically expose a window for trench silicon etching, and etch out the P column region trench.

[0031] Step 4: Epitaxially grow P-type doped silicon in the P column region trench, where the last epitaxial growth of the P column uses a higher doping, fill the P column trench, and then remove the excess P-type silicon through chemical mechanical planarization.

[0032] Step 5: Epitaxially grow N-type silicon on the silicon wafer, and then etch back the excess silicon on the surface to form the N-type charge storage layer 14.

[0033] Step 6: Epitaxially grow P-type silicon on the silicon wafer, and then etch back the excess silicon on the surface to form the P-type base region 12.

[0034] Step 7: Deposit a protective layer on the silicon wafer surface, lithographically expose a window for trench silicon etching, and simultaneously etch out the gate electrode trench and the emitter trench.

[0035] Step 8: Grow a sacrificial oxide layer on the sidewalls of the trench in an O2 atmosphere at 1050°C to 1150°C, then remove the sacrificial oxide layer, and then grow a gate oxide layer on the sidewalls of the trench in an O2 atmosphere at 1050°C to 1150°C.

[0036] Step 9: Deposit polysilicon on the dielectric layer at 750°C to 950°C, and then etch back the excess polysilicon on the surface.

[0037] Step 10: Etch the gate electrode trench and the emitter trench;

[0038] Step 11: Grow a gate oxide layer in the etched gate electrode trench and emitter trench under an O2 atmosphere at 1050°C to 1150°C;

[0039] Step 12: Deposit polysilicon on the dielectric layer in Step 8 at 750°C to 950°C, and then etch back the excess polysilicon on the surface;

[0040] Step 13: Grow a pre-oxidation layer on the silicon wafer surface, and obtain the N+ emitter region 10 by ion implantation of N-type impurities. The ion implantation energy is 60 - 100 keV, and the ion implantation dose is 10 14 ~10 15 / cm 2 ; Obtain the P+ contact region 11 by ion implantation of P-type impurities. The ion implantation energy is 50 - 100 keV, and the ion implantation dose is 10 14 ~10 15 / cm 2 ;

[0041] Step 14: Deposit metal on the front side of the device to fabricate the emitter metal 16;

[0042] Step 15: Flip the silicon wafer, and obtain the N-type field stop layer 3 by ion implantation of N-type impurities. The ion implantation energy is 200 - 500 keV; the ion implantation dose is 10 12 ~10 14 / cm 2 ; Use laser annealing; obtain the P+ collector 2 by ion implantation of P-type impurities. The ion implantation energy is 50 - 100 keV, and the ion implantation dose is 10 12 ~10 15 / cm 2 ;

[0043] Step 16: Deposit metal to fabricate the collector metal 1.

[0044] The present invention also provides a preparation method for a second superjunction IGBT device with a split gate structure, including the following steps:

[0045] Step 1: Use an N-type doped single-crystal silicon wafer as the substrate;

[0046] Step 2: Epitaxially grow N-type doped silicon on the single-crystal silicon wafer, and then etch back the excess silicon on the surface to form an N-type doped drift region;

[0047] Step 3: Deposit a protective layer on the silicon wafer surface, lithographically expose a window for trench silicon etching, and etch out the P-column region trench;

[0048] Step 4: Epitaxially grow P-type doped silicon in the trench area of the P pillar. For the last epitaxial growth of the P pillar, a higher doping is used. Fill the trench of the P pillar, and then remove the excess P-type silicon through chemical mechanical planarization;

[0049] Step 5: Epitaxially grow N-type silicon on the silicon wafer, and then etch back the excess silicon on the surface to form the N-type charge storage layer 14;

[0050] Step 6: Epitaxially grow P-type silicon on the silicon wafer, and then etch back the excess silicon on the surface to form the P-type base region 12;

[0051] Step 7: Grow a pre-oxidation layer on the surface of the silicon wafer. Obtain the N+ emitter region 10 by ion implantation of N-type impurities. The ion implantation energy is 60 - 100 keV, and the ion implantation dose is 10 14 ~10 15 / cm 2 , obtain the P+ contact region 11 by ion implantation of P-type impurities. The ion implantation energy is 50 - 100 keV, and the ion implantation dose is 10 14 ~10 15 / cm 2 ;

[0052] Step 8: Deposit a protective layer on the surface of the silicon wafer, lithographically expose a window for trench silicon etching, and simultaneously etch out the gate electrode trench and the emitter trench;

[0053] Step 9: Grow a sacrificial oxide layer on the sidewalls of the trench in an O2 atmosphere at 1050 °C - 1150 °C, then remove the sacrificial oxide layer, and then grow a gate oxide layer on the sidewalls of the trench in an O2 atmosphere at 1050 °C - 1150 °C;

[0054] Step 10: Deposit polysilicon on the dielectric layer at 750 °C - 950 °C, and then etch back the excess polysilicon on the surface;

[0055] Step 11: Etch the gate electrode trench and the emitter trench;

[0056] Step 12: Grow a gate oxide layer in the etched gate electrode trench and emitter trench in an O2 atmosphere at 1050 °C - 1150 °C;

[0057] Step 13: Deposit polysilicon on the dielectric layer in Step 9 at 750 °C - 950 °C, and then etch back the excess polysilicon on the surface;

[0058] Step 14: Deposit metal on the front side of the device to fabricate the emitter metal 16;

[0059] Step 15: Flip the silicon wafer, obtain the N-type field stop layer 3 by ion implantation of N-type impurities. The ion implantation energy is 200 - 500 keV; the ion implantation dose is 10 12 ~1014 / cm 2 , laser annealing is adopted; P+ collector 2 is fabricated by ion implantation of P-type impurities, the ion implantation energy is 50 - 100 keV, and the ion implantation dose is 10 12 ~10 15 / cm 2 ;

[0060] Step 16: Deposit metal to fabricate collector metal 1.

[0061] The working principle of the present invention is as follows:

[0062] Different from the traditional superjunction IGBT, the P-columns / N-columns of the newly proposed superjunction IGBT are arranged in the Y direction, which not only optimally separates the sizes of the surface MOS structure and the superjunction structure, but also unbinds the binding relationship between the widths of the N-columns, P-columns and the device cell width of the traditional superjunction IGBT, enabling the device to have a smaller cell width, increasing the channel density, reducing its forward conduction voltage drop, and through the parasitic PMOS interaction formed by combining with structures such as P-type base region 12, N-type charge storage layer 14, P-type doped region 6, split gate electrode 15, polysilicon emitter electrode 13, etc., a high-performance device with high channel density and wide short-circuit safe operating area is obtained, greatly reducing the switching loss.

[0063] When the polysilicon gate electrode 9 of the device is connected to a high potential higher than the device threshold voltage, the collector metal 1 is connected to a high potential, and the emitter metal 16, isolation gate electrode 8, split gate electrode 15, polysilicon emitter electrode 13 are connected to a low potential, the device operates in the on state. The P-type buried layer 6 only located on the superjunction P-column 4 enables the superjunction N-column 5 to be directly connected to the N-type charge storage layer 14, so that when electrons are injected into the superjunction N-column 5, there is a shorter flow path, reducing the forward conduction voltage drop of the device. At the same time, the self-biased PMOS structure composed of the P-type base region 12, N-type charge storage layer 14, P-type buried layer 6, split gate electrode 15, and polysilicon emitter electrode 13 is in the off state, ensuring that the superjunction P-column 4 in the drift region floats, enabling the device to further increase the hole concentration in the drift region on the emitter side when the cell width is reduced, enhancing the conductance modulation level in the on state of the drift region, improving the performance of the device in the forward conduction state, and further reducing the forward conduction voltage drop of the device.

[0064] When the voltage of the device collector metal 1 is very high, the device enters the saturation state. As the potential of the collector metal 1 increases, the potential of the N-type charge storage layer 14 also increases. Due to the non-full depletion caused by the high doping of the P-type buried layer 6 and its position relationship completely above the superjunction P column 4, the P-type buried layer 6 has a very good clamping effect on its own voltage and the voltage of the N-type charge storage layer 14, greatly reducing the high saturation current density caused by the reduction of the cell width. And because the P-type buried layer 6 is only located on the superjunction P column 4, the current has better uniformity in the superjunction N column 5 region, fully improving the dynamic avalanche breakdown and short-circuit safety problems caused by the reduction of the cell width, enabling the proposed superjunction IGBT device to have both a high channel density and a wide short-circuit safe operating area. And because electrons need to flow through the superjunction N column 5 to be injected into the superjunction P column 4, the saturation current density is further reduced and the short-circuit safety is improved.

[0065] When the polysilicon gate electrode 9, emitter metal 16, isolation gate electrode 8, split gate electrode 15, and polysilicon emitter electrode 13 of the device are connected to a low potential and the collector metal 1 is connected to a high potential, the device operates in the blocking state. The lateral depletion of the superjunction N column 5 and superjunction P column 4 flattens the electric field in three dimensions, improving the breakdown voltage. And the P-type buried layer 6 and the trench emitter structure can effectively shield the influence of the N-type charge storage layer 14 on the breakdown voltage of the device, thereby improving the limitation of the doping concentration of the charge storage layer on the breakdown characteristics of the device. In addition, the thick isolation gate dielectric layer at the bottom of the trench is beneficial to alleviating the electric field concentration effect at the bottom of the trench, further increasing the breakdown voltage.

[0066] When the emitter metal 16, isolation gate electrode 8, split gate electrode 15, and polysilicon emitter electrode 13 of the device are connected to a low potential, the collector metal 1 is connected to a high potential, and the polysilicon gate electrode 9 is switched from a low potential to a high potential, the device turns from the off state to the on state. When the gate voltage is low, the PMOS conducts, and part of the hole current flows through the PMOS, effectively suppressing the increase in the potential under the N-type charge storage layer, thereby suppressing the negative gate capacitance effect, reducing the device surge current, and improving the device's gate control ability for dv / dt.

[0067] When the emitter metal 16, isolation gate electrode 8, split gate electrode 15, and polysilicon emitter electrode 13 of the device are connected to a low potential, the collector metal 1 is connected to a high potential, and the polysilicon gate electrode 9 is switched from a high potential to a low potential, the device turns from the on state to the off state. The lateral PN junction between the superjunction N column 5 and superjunction P column 4 will be quickly depleted. At the same time, the turn-on of the PMOS provides a path for the extraction of holes from the superjunction P column 4 to the P+ contact region 11, improving the switching speed of the device, reducing the switching loss of the device, and the shorter polysilicon gate electrode 9 reduces the gate area. And the grounded isolation gate electrode 8 under the polysilicon gate electrode 9 separates a part of the gate capacitance C GCis converted into the gate-emitter capacitance C GE , further reducing the Miller capacitance C GC , further improving the switching speed and reducing the switching loss.

[0068] The beneficial effects of the present invention are as follows:

[0069] Based on the traditional trench superjunction IGBT, the present invention introduces a trench gate structure, an emitter trench gate structure, and a P-type buried layer. Different from the traditional superjunction IGBT, the P-columns / N-columns of the newly proposed superjunction IGBT are arranged in the Y direction, which not only optimally separates the sizes of the surface MOS structure and the superjunction structure, but also decouples the binding relationship between the widths of the N-columns / P-columns and the device cell width of the traditional superjunction IGBT, enabling it to have a smaller cell width, increasing the channel density, reducing its forward conduction voltage drop. Moreover, the self-biased PMOS composed of the P-type base region 12, the N-type charge storage layer 14, the P-type buried layer 6, the split gate electrode 15, and the polysilicon emitter electrode 13 not only further reduces the forward conduction voltage drop of the device, but also when the device is saturated, due to the high doping of the P-type buried layer 6 and its position relationship only above the superjunction P-column 4 and not at the position of the superjunction N-column 5, the voltage clamping effect of the P-type buried layer 6 and the N-type charge storage layer 14 is better, further reducing the saturation current density of the superjunction IGBT, and can fully improve the short-circuit safety problem caused by the reduction of the cell width, enabling the proposed superjunction IGBT device to simultaneously have a high channel density and a wide short-circuit safe operating area. And because the P-type buried layer 6 is only located on the superjunction P-column 4 and not above the superjunction N-column 5, it can be realized only by adding one more photolithography mask, which not only simplifies the process flow, optimizes the current concentration problem caused by the reduction of the cell width, improves the dynamic avalanche ability of the device, and also enables the superjunction N-column 5 to be directly connected to the N-type charge storage layer 14, providing a shorter conduction path for carriers and further reducing the conduction voltage drop of the device. In addition, the presence of the split gate structure can significantly reduce the Miller capacitance of the superjunction IGBT device. Even when the device cell width is reduced and the channel density is increased, its Miller capacitance is still significantly reduced. Additionally, during the turn-on process of the device, when the collector voltage is relatively low, the PMOS conducts, and part of the hole current flows through the PMOS, effectively suppressing the increase in the potential below the N-type charge storage layer, thereby suppressing the negative gate capacitance effect, reducing the device surge current, and improving the device's gate control ability for dv / dt. During the turn-off process of the device, due to its lower Miller capacitance C GC of the novel superjunction IGBT device structure, the turn-off speed of the device is increased, and as V CE increases, the PMOS turns on, and the excess holes stored in the drift region obtain an additional path, further increasing the turn-off speed of the device and greatly reducing the switching loss. Description of the Drawings

[0070] Figure 1 Schematic diagram of the cell structure of a traditional superjunction IGBT;

[0071] Figure 2 Schematic diagram of the cell structure of a superjunction IGBT device with a split gate structure provided in Embodiment 1 of the present invention;

[0072] Figure 3 Schematic diagram of the cell structure of a superjunction IGBT device with a split gate structure provided in Embodiment 2 of the present invention;

[0073] Figure 4 Schematic diagram of the cell structure of a superjunction IGBT device with a split gate structure provided in Embodiment 3 of the present invention;

[0074] Figure 5 Schematic diagram of the cell structure of a superjunction IGBT device with a split gate structure provided in Embodiment 4 of the present invention;

[0075] Figure 6 Schematic diagram of the cell structure of a superjunction IGBT device with a split gate structure provided in Embodiment 5 of the present invention after removing the emitter metal 16;

[0076] Figure 7 Schematic diagram of the cell structure of a superjunction IGBT device with a split gate structure provided in Embodiment 6 of the present invention after removing the emitter metal 16;

[0077] Figure 8 Schematic diagram of the cell structure of a superjunction IGBT device with a split gate structure provided in Embodiment 7 of the present invention;

[0078] Figure 9 Schematic diagram of the cell structure of a superjunction IGBT device with a split gate structure provided in Embodiment 8 of the present invention;

[0079] Figure 10 Schematic diagram of the process of forming an N-type substrate for a superjunction IGBT device with a split gate structure provided in Embodiment 1 of the present invention;

[0080] Figure 11 Schematic diagram of the process of forming an N-type drift region 5 for a superjunction IGBT device with a split gate structure provided in Embodiment 1 of the present invention;

[0081] Figure 12 Schematic diagram of the process of etching to form a trench in the P-column region for a superjunction IGBT device with a split gate structure provided in Embodiment 1 of the present invention;

[0082] Figure 13It is a process schematic diagram after filling the superjunction P pillar region 4 with a surface P-type buried layer 6 in a superjunction IGBT device with a split gate structure provided in Embodiment 1 of the present invention;

[0083] Figure 14 It is a process schematic diagram of forming an N-type charge storage layer 14 in a superjunction IGBT device with a split gate structure provided in Embodiment 1 of the present invention;

[0084] Figure 15 It is a process schematic diagram after forming a P-type base region 12 in a superjunction IGBT device with a split gate structure provided in Embodiment 1 of the present invention;

[0085] Figure 16 It is a process schematic diagram after etching to form a gate electrode trench and an emitter trench in a superjunction IGBT device with a split gate structure provided in Embodiment 1 of the present invention;

[0086] Figure 17 It is a process schematic diagram after forming a gate dielectric layer 7-1 in a superjunction IGBT device with a split gate structure provided in Embodiment 1 of the present invention;

[0087] Figure 18 It is a process schematic diagram after depositing polycrystalline silicon to form a separated gate electrode 8 and a split gate electrode 15 in a superjunction IGBT device with a split gate structure provided in Embodiment 1 of the present invention;

[0088] Figure 19 It is a process schematic diagram of etching a gate electrode trench and an emitter trench in a superjunction IGBT device with a split gate structure provided in Embodiment 1 of the present invention;

[0089] Figure 20 It is a process schematic diagram after growing a polysilicon gate dielectric layer 7-2 and a polysilicon emitter dielectric layer 7-3 in a superjunction IGBT device with a split gate structure provided in Embodiment 1 of the present invention;

[0090] Figure 21 It is a process schematic diagram after depositing polycrystalline silicon to form a polysilicon gate electrode 9 and a polysilicon emitter electrode 13 in a superjunction IGBT device with a split gate structure provided in Embodiment 1 of the present invention;

[0091] Figure 22 It is a process schematic diagram after forming an N+ emitter region 10 and a P+ contact 11 in a superjunction IGBT device with a split gate structure provided in Embodiment 1 of the present invention;

[0092] Figure 23 It is a process schematic diagram after forming an emitter metal 16 in a superjunction IGBT device with a split gate structure provided in Embodiment 1 of the present invention;

[0093] Figure 24 It is a process schematic diagram after forming the N-type field stop layer 3 and the P-type collector 2 of a superjunction IGBT device with a split-gate structure provided in Embodiment 1 of the present invention;

[0094] Figure 25 It is a process schematic diagram after forming the collector metal 1 of a superjunction IGBT device with a split-gate structure provided in Embodiment 1 of the present invention;

[0095] In the attached drawings, the list of components represented by each label is as follows:

[0096] 1 is the collector metal, 2 is the P-type collector, 3 is the N-type field stop layer, 4 is the superjunction P pillar, 5 is the superjunction N pillar, 6 is the P-type buried layer, 7 is the polysilicon gate trench electrode, 7-1 is the isolation gate dielectric layer, 7-2 is the polysilicon gate dielectric layer, 7-3 is the polysilicon emitter dielectric layer, 7-4 is the polysilicon gate trench dielectric layer, 8 is the isolation gate electrode, 9 is the polysilicon gate electrode, 10 is the N+ emitter region, 11 is the P+ contact region, 12 is the P-type base region, 13 is the polysilicon emitter electrode, 14 is the N-type charge storage layer, 15 is the split gate electrode, 16 is the emitter metal, 17 is the N-drift region, 18 is the polysilicon trench emitter electrode, 19 is the trench collector dielectric layer, 20 is the trench collector. Specific embodiments

[0097] The following illustrates the embodiments of the present invention through specific specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0098] Embodiment 1

[0099] An embodiment of a superjunction IGBT device with a split-gate structure, as Figure 2 shown, defines the three-dimensional directions of the device in a three-dimensional rectangular coordinate system: defines the lateral direction of the device as the X-axis direction, defines the vertical direction of the device as the Z-axis direction, and the longitudinal direction of the device, i.e., the third-dimensional direction, as the Y-axis direction

[0100] Its cell structure includes: the collector metal 1, the P-type collector 2, and the N-type field stop layer 3 stacked in sequence from bottom to top along the Z-axis direction. Above the N-type field stop layer 3, there are a superjunction N pillar 5 and a superjunction P pillar 4 in contact with each other on the side. Above the superjunction P pillar 4, there is a P-type buried layer 6. Along the X-axis direction above the superjunction N pillar 5 and the P-type buried layer 6, there are a trench gate structure and a trench emitter structure.

[0101] The trench gate structure includes a separation gate dielectric layer 7-1, a separation gate electrode 8 above the separation gate dielectric layer 7-1, a polysilicon gate dielectric layer 7-2 above the separation gate electrode 8, and a polysilicon gate electrode 9 within the polysilicon gate dielectric layer 7-2; the trench emitter structure includes a separation gate dielectric layer 7-1, a split gate electrode 15 above the separation gate dielectric layer 7-1, a polysilicon emitter dielectric layer 7-3 above the split gate electrode 15, and a polysilicon emitter electrode 13 within the polysilicon emitter dielectric layer 7-3;

[0102] An N-type charge storage layer 14 is provided above the superjunction N column 5 and the P-type buried layer 6, between the trench gate structure and the trench emitter structure. Along the Z-axis direction, a P-type base region 12 is provided above the N-type charge storage layer 14, an N+ emitter region 10 and a P+ contact region 11 are provided above the P-type base region 12, and an emitter metal 16 is provided above the N+ emitter region 10 and above the P+ contact region 11; the P-type buried layer 6 is only located above the superjunction P column 4 and not above the superjunction N column 5; the P-type buried layer 6 is in contact with the N-type charge storage layer 14 along the Z-axis direction; the superjunction N columns 5 and the superjunction P columns 4 are arranged alternately along the Y-axis direction; the N+ emitter regions 10 and the P+ contact regions 11 are arranged in sequence along the X-axis direction;

[0103] The polysilicon gate electrode 9 is connected to the N-type charge storage layer 14, the P-type base region 12, the N+ emitter region 10, and the split electrode 8 through the polysilicon gate dielectric layer 7-2; the polysilicon emitter electrode 13 is connected to the N-type charge storage layer 14, the P-type base region 12, and the P+ contact region 11 through the polysilicon emitter dielectric layer 7-3;

[0104] The separation gate electrode 8 is connected to the N-type charge storage layer 14 and the P-type buried layer 6 at the bottom of the left trench through the separation gate dielectric layer 7-1; the separation gate electrode 8 is at the same potential as the emitter metal 16; the split gate electrode 15 is connected to the P-type buried layer 6 through the separation gate dielectric layer 7-1; the split gate electrode 15, the polysilicon emitter electrode 13, the separation gate 8 are at the same potential as the emitter metal 16;

[0105] In the Z-axis direction, the depths of the polysilicon gate electrode 9 and the polysilicon emitter electrode 13 exceed the depth of the P-type base region 12; the depths of the trench gate structure and the trench emitter structure are greater than the junction depth of the N-type charge storage layer 14 and less than the junction depth of the P-type buried layer 6; the thickness of the separation gate dielectric layer 7-1 of the trench gate structure is greater than the thicknesses of the polysilicon gate dielectric layer 7-2 and the polysilicon emitter dielectric layer 7-3, and the doping concentration of the P-type buried layer 6 is greater than the doping concentration of the superjunction P column 4; the P-type buried layer 6 cannot be fully depleted before the device breaks down. The cell width of the superjunction IGBT device is smaller than that of the traditional superjunction IGBT device.

[0106] This embodiment also provides a method for manufacturing a superjunction IGBT device with a split-gate structure, including the following manufacturing steps:

[0107] Step 1: As shown in Figure 10 , use an N-type doped single-crystal silicon wafer as the substrate;

[0108] Step 2: As shown in Figure 11 , epitaxially grow N-type doped silicon on the single-crystal silicon wafer, and then etch back the excess silicon on the surface to form an N-type doped drift region;

[0109] Step 3: As shown in Figure 12 , deposit a protective layer on the silicon wafer surface, lithographically pattern a window for trench silicon etching, and etch out the P-column region trenches;

[0110] Step 4: As shown in Figure 13 , epitaxially grow P-type doped silicon in the P-column region trenches, where the last epitaxial growth of the P-column uses a higher doping, fill the P-column trenches, and then remove the excess P-type silicon by chemical mechanical planarization;

[0111] Step 5: As shown in Figure 14 , epitaxially grow N-type silicon on the silicon wafer, and then etch back the excess silicon on the surface to form an N-type charge storage layer 14;

[0112] Step 6: As shown in Figure 15 , epitaxially grow P-type silicon on the silicon wafer, and then etch back the excess silicon on the surface to form a P-type base region 12;

[0113] Step 7: As shown in Figure 16 , deposit a protective layer on the silicon wafer surface, lithographically pattern a window for trench silicon etching, and simultaneously etch out the gate electrode trenches and the emitter trenches;

[0114] Step 8: As shown in Figure 17 , grow a sacrificial oxide layer on the sidewalls of the trenches in an O2 atmosphere at 1050°C to 1150°C, then remove the sacrificial oxide layer, and then grow a gate oxide layer on the sidewalls of the trenches in an O2 atmosphere at 1050°C to 1150°C;

[0115] Step 9: As shown in Figure 18 , deposit polysilicon on the dielectric layer at 750°C to 950°C, and then etch back the excess polysilicon on the surface;

[0116] Step 10: As shown in Figure 19 , etch the gate electrode trenches and the emitter trenches;

[0117] Step 11: As shown in Figure 20 , grow a gate oxide layer in the etched gate electrode trenches and emitter trenches in an O2 atmosphere at 1050°C to 1150°C;

[0118] Step 12: As shown in Figure 21 Figure 21 , deposit polysilicon on the dielectric layer in step 8 at 750°C to 950°C, and then etch back the excess polysilicon on the surface;

[0119] Step 13: As shown in Figure 22 Figure 22 , grow a pre-oxidation layer on the silicon wafer surface, and obtain the N+ emitter region 10 by ion implantation of N-type impurities. The ion implantation energy is 60 - 100 keV, and the ion implantation dose is 10 14 ~10 15 / cm 2 , and obtain the P+ contact region 11 by ion implantation of P-type impurities. The ion implantation energy is 50 - 100 keV, and the ion implantation dose is 10 14 ~10 15 / cm 2 ;

[0120] Step 14: As shown in Figure 23 Figure 23 , deposit metal on the front side of the device to fabricate the emitter metal 16;

[0121] Step 15: As shown in Figure 24 Figure 24 , flip the silicon wafer, and obtain the N-type field stop layer 3 by ion implantation of N-type impurities. The ion implantation energy is 200 - 500 keV; the ion implantation dose is 10 12 ~10 14 / cm 2 , and perform laser annealing; obtain the P+ collector 2 by ion implantation of P-type impurities. The ion implantation energy is 50 - 100 keV, and the ion implantation dose is 10 12 ~10 15 / cm 2 ;

[0122] Step 16: As shown in Figure 25 Figure 25 , deposit metal to fabricate the collector metal.

[0123] This embodiment also provides a preparation method for a second superjunction IGBT device with enhanced carrier concentration, including the following manufacturing steps:

[0124] Step 1: Use an N-type doped single-crystal silicon wafer as the substrate;

[0125] Step 2: Epitaxially grow N-type doped silicon on the single-crystal silicon wafer, and then etch back the excess silicon on the surface to form an N-type doped drift region;

[0126] Step 3: Deposit a protective layer on the silicon wafer surface, lithographically expose a window for trench silicon etching, and etch out the P-column region trench;

[0127] Step 4: Epitaxially grow P-type doped silicon in the trench area of the P column, where the last epitaxial growth of the P column uses a higher doping level, fill the trench of the P column, and then remove the excess P-type silicon by chemical mechanical planarization;

[0128] Step 5: Epitaxially grow N-type silicon on the silicon wafer, and then etch back the excess silicon on the surface to form the N-type charge storage layer ·4;

[0129] Step 6: Epitaxially grow P-type silicon on the silicon wafer, and then etch back the excess silicon on the surface to form the P-type base region 12;

[0130] Step 7: Grow a pre-oxidation layer on the surface of the silicon wafer, obtain the N+ emitter region 10 by ion implantation of N-type impurities, the ion implantation energy is 60 - 100 keV, and the ion implantation dose is 10 14 ~10 15 / cm 2 ; obtain the P+ contact region 11 by ion implantation of P-type impurities, the ion implantation energy is 50 - 100 keV, and the ion implantation dose is 10 14 ~10 15 / cm 2 ;

[0131] Step 8: Deposit a protective layer on the surface of the silicon wafer, lithographically pattern a window for trench silicon etching, and simultaneously etch out the gate electrode trench and the emitter trench;

[0132] Step 9: Grow a sacrificial oxide layer on the sidewalls of the trench in an O2 atmosphere at 1050 °C - 1150 °C, then remove the sacrificial oxide layer, and then grow a gate oxide layer on the sidewalls of the trench in an O2 atmosphere at 1050 °C - 1150 °C;

[0133] Step 10: Deposit polysilicon on the dielectric layer at 750 °C - 950 °C, and then etch back the excess polysilicon on the surface;

[0134] Step 11: Etch the gate electrode trench and the emitter trench;

[0135] Step 12: Grow a gate oxide layer in the etched gate electrode trench and emitter trench in an O2 atmosphere at 1050 °C - 1150 °C;

[0136] Step 13: Deposit polysilicon on the dielectric layer in Step 9 at 750 °C - 950 °C, and then etch back the excess polysilicon on the surface;

[0137] Step 14: Deposit metal on the front side of the device to fabricate the emitter metal 16;

[0138] Step 15: Flip the silicon wafer, obtain the N-type field stop layer 3 by ion implantation of N-type impurities, the ion implantation energy is 200 - 500 keV; the ion implantation dose is 10 12 ~1014 / cm 2 Adopt laser annealing; P+ collector 2 is fabricated by ion implantation of P-type impurities, the ion implantation energy is 50-100 keV, and the ion implantation dose is 10 12 ~10 15 / cm 2 ;

[0139] Step 16: Deposit metal to fabricate collector metal 1.

[0140] Embodiment 2

[0141] An embodiment of a superjunction IGBT device with a split-gate structure, as Figure 3 shown. The difference between this embodiment and Embodiment 1 lies in that an N-drift region 17 is introduced between the superjunction N column 5 and the superjunction P column 4 and the N-type field-stop layer 3 in the Z-axis direction, and the doping concentration of the N-drift region 17 is lower than that of the superjunction N column 5.

[0142] The introduction of the N-drift region helps to make up for the limitations in the superjunction process and fabricate a superjunction IGBT with a higher voltage rating.

[0143] Embodiment 3

[0144] This embodiment provides a superjunction IGBT device with a split-gate structure, as Figure 4 ,

[0145] Define the three-dimensional directions of the device in a three-dimensional rectangular coordinate system: Define the lateral direction of the device as the X-axis direction, define the vertical direction of the device as the Z-axis direction, and the longitudinal direction of the device, i.e., the third dimension direction, as the Y-axis direction. Its characteristics are as follows:

[0146] Its cell structure includes: Collector metal 1, P-type collector 2, and N-type field-stop layer 3 stacked in sequence from bottom to top along the Z-axis direction. Above the N-type field-stop layer 3, there are a superjunction N column 5 and a superjunction P column 4 in contact with each other on the side. Above the superjunction P column 4, there is a P-type buried layer 6. Along the X-axis direction above the superjunction N column 5 and the P-type buried layer 6, there are a trench gate structure and a trench emitter structure.

[0147] The trench gate structure includes a split-gate dielectric layer 7-1 and a polysilicon trench emitter electrode 18 above the split-gate dielectric layer 7-1.

[0148] Above the superjunction N pillar 5 and the P-type buried layer 6, between the trench gate structure and the trench emitter structure, there is an N-type charge storage layer 14. Along the Z-axis direction, above the N-type charge storage layer 14, there is a P-type base region 12. Above the P-type base region 12, there are an N+ emitter region 10 and a P+ contact region 11. Above the N+ emitter region 10 and above the P+ contact region 11, there is an emitter metal 16; the P-type buried layer 6 is only located above the superjunction P pillar 4 and not above the superjunction N pillar 5; the P-type buried layer 6 is in contact with the N-type charge storage layer 14 along the Z-axis direction; the superjunction N pillars 5 and the superjunction P pillars 4 are arranged alternately along the Y-axis direction; the N+ emitter regions 10 and the P+ contact regions 11 are arranged in sequence along the X-axis direction;

[0149] The polysilicon gate electrode 9 is connected to the N-type charge storage layer 14, the P-type base region 12, and the N+ emitter region 10 through a polysilicon gate dielectric layer 7-2; the split gate electrode 8 is connected to the P-type buried layer 6 through a split gate dielectric layer 7-1; the split gate electrode 8 and the emitter metal 16 are at the same potential;

[0150] The polysilicon trench emitter electrode 18 is connected to the P+ contact region 11, the P-type base region 12, the N-type charge storage layer 14, and the P-type buried layer 6 at the bottom of the right trench through a split gate dielectric layer 7-1; the polysilicon trench emitter electrode 18 and the split gate electrode 8 are at the same potential as the emitter metal 16;

[0151] In the Z-axis direction, the depth of the polysilicon gate electrode 9 exceeds the depth of the P-type base region 12; the depth of the trench gate structure and the trench emitter structure is greater than the junction depth of the N-type charge storage layer 14 and less than the junction depth of the P-type buried layer 6; the thickness of the split gate dielectric layer 7-1 of the trench gate structure is greater than the thickness of the polysilicon gate dielectric layer 7-2, and the doping concentration of the P-type buried layer 6 is greater than the doping concentration of the superjunction P pillar 4; the P-type buried layer 6 cannot be completely depleted before the device breaks down.

[0152] By introducing the polysilicon trench emitter electrode 18, it helps with electrode extraction, simplifies the process flow, reduces parasitics, improves device reliability, and improves the yield.

[0153] Example 4

[0154] An embodiment of a superjunction IGBT device with a split gate structure, as Figure 5 shown. The difference between this embodiment and Embodiment 1 is that the polysilicon gate electrode 13 is connected to the split gate electrode 15 through a polysilicon emitter dielectric layer 7-3; the split gate electrode 15 is connected to the N-type charge storage layer 14 and the P-type buried layer 6 at the bottom of the right trench through a split gate dielectric layer 7-1; the split gate electrode 15 is led out from the top of the device.

[0155] Leading out the split gate electrode 15 from the top of the device helps simplify the process flow, reduce parasitics, and the enlarged area of the split gate electrode 15 helps improve the electric field distribution at the bottom of the trench and enhance device reliability.

[0156] Example 5

[0157] An embodiment of a superjunction IGBT device with a split gate structure, as Figure 6 shown. The difference between this embodiment and Embodiment 1 is that the isolation gate electrode 8 is led out from the top of the device; the extension depth of the N+ emitter region 10 at the top layer of the P-type base region 12 is less than the extension depth of the P+ contact region 11 at the top layer of the P-type base region 12.

[0158] In this embodiment, by reducing the extension depth of the emitter region along the top layer of the base region, the channel density of the MOS structure is reduced. As the extension depth of the emitter region along the top layer of the base region decreases, the depth of the gate electrode connected to the emitter region through the gate dielectric layer and extending in the same direction can also be reduced, reducing the saturation current density, improving the safe operating area SCSOA of the device, enhancing the uniformity of the on-state current, improving the reliability of the device, improving its temperature characteristics, facilitating the reduction of the gate capacitance, thereby increasing the switching speed of the device, reducing the switching loss of the device and the requirements for the gate drive circuit ability, and improving the trade-off relationship between the forward on-state voltage Vceon and the turn-off loss Eoff of the device.

[0159] Example 6

[0160] An embodiment of a superjunction IGBT device with a split gate structure, as Figure 7 shown. The difference between this embodiment and Embodiment 4 is that the extension depth of the N+ emitter region 10 at the top layer of the P-type base region 12 is less than the extension depth of the P+ contact region 11 at the top layer of the P-type base region 12; the isolation gate electrode 8 is led out from the top of the device.

[0161] In this embodiment, a semi-surrounding split gate is introduced into the right trench, which is symmetrical to the left side, optimizing the overall internal electric field distribution of the device and improving device reliability.

[0162] Example 7

[0163] An embodiment of a superjunction IGBT device with a split gate structure, as Figure 8 shown. The difference between this embodiment and Embodiment 5 is that an N- drift region 17 is introduced between the superjunction N column 5, the superjunction P column 4 and the N-type field stop layer 3 in the Z direction, and the doping concentration of the N- drift region 17 is lower than the doping concentration of the superjunction N column 5.

[0164] The introduction of the N- drift region in this embodiment helps make up for the limitations in the superjunction process and fabricate a superjunction IGBT with a higher voltage rating.

[0165] Example 8

[0166] An embodiment of a superjunction IGBT device with a split-gate structure, as Figure 9 shown. The difference between this embodiment and Embodiment 1 lies in that a trench collector structure penetrating the N-type field-stop layer 3 and the P-type collector 2 is introduced on the back of the device. The trench collector structure includes a trench collector 20 and a trench collector dielectric layer 19 on its periphery. The trench collector 20 is at the same potential as the collector metal 1. The trench collector 20 is isolated from the P-type collector 2, the N-type field-stop layer 3, the superjunction P pillar 4, and the superjunction N pillar 5 through the trench collector dielectric layer 19.

[0167] This embodiment introduces a trench collector structure with a trench collector 20 and a trench collector dielectric layer 19. A depletion layer will be formed on the surface of the contacted N-type field-stop layer 3 to bear part of the reverse voltage, thereby greatly improving the reverse breakdown voltage of the device, enhancing the reliability of the device, and solving the problem that the reverse breakdown voltage of the device is lower than the forward breakdown voltage due to the existence of the FS layer in the traditional structure, and the voltage withstand of the device decreases during AC application.

[0168] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

[0169] The above embodiments are only illustrative of the principles and effects of the present invention and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A super junction IGBT device with a split gate structure, wherein the three-dimensional direction of the device is defined by a three-dimensional rectangular coordinate system: the lateral direction of the device is defined as the X-axis direction, the vertical direction of the device is defined as the Z-axis direction, and the longitudinal direction of the device, i.e., the third dimension, is defined as the Y-axis direction, characterized in that: The cell structure comprises: a collector metal (1), a P-type collector (2), and an N-type field stop layer (3) which are stacked in sequence from bottom to top along the Z-axis direction; a super-junction N column (5) and a super-junction P column (4) which are in contact with each other on the side surfaces are arranged above the N-type field stop layer (3); a P-type buried layer (6) is arranged above the super-junction P column (4); and a trench gate structure and a trench emitter structure are arranged above the super-junction N column (5) and the P-type buried layer (6) along the X-axis direction. The trench gate structure comprises a separation gate dielectric layer (7-1), a separation gate electrode (8) above the separation gate dielectric layer (7-1), a polysilicon gate dielectric layer (7-2) above the separation gate electrode (8), and a polysilicon gate electrode (9) in the polysilicon gate dielectric layer (7-2); the trench emitter structure comprises a separation gate dielectric layer (7-1), a split gate electrode (15) above the separation gate dielectric layer (7-1), a polysilicon emitter dielectric layer (7-3) above the split gate electrode (15), and a polysilicon emitter electrode (13) in the polysilicon emitter dielectric layer (7-3); An N-type charge storage layer (14) is provided above the super-junction N column (5) and the P-type buried layer (6), between the trench gate structure and the trench emitter structure; along the Z-axis direction, a P-type base region (12) is provided above the N-type charge storage layer (14); an N+ emitter region (10) and a P+ contact region (11) are provided above the P-type base region (12); an emitter metal (16) is provided above the N+ emitter region (10) and above the P+ contact region (11); the P-type buried layer (6) is only located above the super-junction P column (4) and not above the super-junction N column (5); the P-type buried layer (6) is in contact with the N-type charge storage layer (14) along the Z-axis direction; the super-junction N column (5) and the super-junction P column (4) are alternately arranged along the Y-axis direction; the N+ emitter region (10) and the P+ contact region (11) are arranged in sequence along the X-axis direction; The polysilicon gate electrode (9) is connected to the N-type charge storage layer (14), the P-type base region (12), the N+ emitter region (10), and the split electrode (8) through the polysilicon gate dielectric layer (7-2); the polysilicon emitter electrode (13) is connected to the N-type charge storage layer (14), the P-type base region (12), and the P+ contact region (11) through the polysilicon emitter dielectric layer (7-3); The separation gate electrode (8) is connected to the N-type charge storage layer (14) and the P-type buried layer (6) at the bottom of the left trench through the separation gate dielectric layer (7-1); the separation gate electrode (8) and the emitter metal (16) are at the same potential; the split gate electrode (15) is connected to the P-type buried layer (6) through the separation gate dielectric layer (7-1); the split gate electrode (15), the polysilicon emitter electrode (13), the separation gate (8) and the emitter metal (16) are at the same potential; The depth of the polysilicon gate electrode (9) and the polysilicon emitter electrode (13) in the Z-axis direction exceeds the depth of the P-type base region (12); the depth of the trench gate structure and the trench emitter structure is greater than the junction depth of the N-type charge storage layer (14) and less than the junction depth of the P-type buried layer (6); the thickness of the separation gate dielectric layer (7-1) of the trench gate structure is greater than the thickness of the polysilicon gate dielectric layer (7-2) and the polysilicon emitter dielectric layer (7-3); the doping concentration of the P-type buried layer (6) is greater than the doping concentration of the super junction P column (4); and the P-type buried layer (6) cannot be completely exhausted before the device breaks down.

2. The super junction IGBT device with a split gate structure according to claim 1, characterized in that: An N-drift region (17) is introduced between the super junction N column (5), the super junction P column (4) and the N-type field stop layer (3) in the Z-axis direction, and the doping concentration of the N-drift region (17) is lower than the doping concentration of the super junction N column (5).

3. The super junction IGBT device with a split gate structure according to claim 1, characterized in that: The polysilicon gate electrode (13) is connected to the split gate electrode (15) through the polysilicon emitter dielectric layer (7-3); the split gate electrode (15) is connected to the N-type charge storage layer (14) and the P-type buried layer (6) at the bottom of the right trench through the separation gate dielectric layer (7-1); and the split gate electrode (15) is led out from the top of the device.

4. The super junction IGBT device with a split gate structure according to claim 1, characterized in that: The separation gate electrode (8) is led out from the top of the device; the extension depth of the N+ emitter region (10) at the top layer of the P-type base region (12) is less than the extension depth of the P+ contact region (11) at the top layer of the P-type base region (12).

5. The super junction IGBT device with a split gate structure according to claim 1, characterized in that: A trench collector structure penetrating an N-type field stop layer (3) and a P-type collector (2) is introduced at the back of the device. The trench collector structure comprises a trench collector (20) and a trench collector dielectric layer (19) on its peripheral side. The trench collector (20) has the same potential as the collector metal (1). The trench collector (20) is isolated from the P-type collector (2), the N-type field stop layer (3), the super junction P column (4) and the super junction N column (5) by the trench collector dielectric layer (19).

6. The super junction IGBT device with a split gate structure according to claim 3, characterized in that: The extension depth of the N+ emitter region (10) at the top layer of the P-type base region (12) is less than the extension depth of the P+ contact region at the top layer of the P-type base region (12); and the separation gate electrode (8) is led out from the top of the device.

7. The super junction IGBT device with a split gate structure according to claim 3, characterized in that: An N-drift region (17) is introduced between the super junction N column (5), the super junction P column (4) and the N-type field stop layer (3) in the Z direction, and the doping concentration of the N-drift region (17) is lower than the doping concentration of the super junction N column (5).

8. A super junction IGBT device with a split gate structure, characterized in that: The three-dimensional direction of the device is defined in a three-dimensional rectangular coordinate system: the lateral direction of the device is defined as the X-axis direction, the vertical direction of the device is defined as the Z-axis direction, and the longitudinal direction of the device, i.e. the third dimension, is defined as the Y-axis direction. The characteristics are: The cell structure comprises: a collector metal (1), a P-type collector (2) and an N-type field stop layer (3) which are stacked in sequence from bottom to top along the Z-axis direction; a super-junction N column (5) and a super-junction P column (4) which are in contact with each other on the side surfaces are arranged above the N-type field stop layer (3); a P-type buried layer (6) is arranged above the super-junction P column (4); and a trench gate structure and a trench emitter structure are arranged above the super-junction N column (5) and the P-type buried layer (6) along the X-axis direction. The trench gate structure comprises a separation gate dielectric layer (7-1), a polysilicon trench emitter electrode (18) above the separation gate dielectric layer (7-1), An N-type charge storage layer (14) is provided above the super-junction N column (5) and the P-type buried layer (6), between the trench gate structure and the trench emitter structure; along the Z-axis direction, a P-type base region (12) is provided above the N-type charge storage layer (14); an N+ emitter region (10) and a P+ contact region (11) are provided above the P-type base region (12); an emitter metal (16) is provided above the N+ emitter region (10) and above the P+ contact region (11); the P-type buried layer (6) is only located above the super-junction P column (4) and not above the super-junction N column (5); the P-type buried layer (6) is in contact with the N-type charge storage layer (14) along the Z-axis direction; the super-junction N column (5) and the super-junction P column (4) are alternately arranged along the Y-axis direction; the N+ emitter region (10) and the P+ contact region (11) are arranged in sequence along the X-axis direction; The polysilicon gate electrode (9) is connected to the N-type charge storage layer (14), the P-type base region (12), and the N+ emitter region (10) through the polysilicon gate dielectric layer (7-2); the separation gate electrode (8) is connected to the P-type buried layer (6) through the separation gate dielectric layer (7-1); the separation gate electrode (8) and the emitter metal (16) have the same potential; The polysilicon trench emitter electrode (18) is connected to the P+ contact region (11), the P-type base region (12), the N-type charge storage layer (14), and the P-type buried layer (6) at the bottom of the right trench through the separation gate dielectric layer (7-1); the polysilicon trench emitter electrode (18), the separation gate electrode (8) and the emitter metal (16) are at the same potential; The depth of the polysilicon gate electrode (9) in the Z-axis direction exceeds the depth of the P-type base region (12); the depth of the trench gate structure and the trench emitter structure is greater than the junction depth of the N-type charge storage layer (14) and less than the junction depth of the P-type buried layer (6); the thickness of the separation gate dielectric layer (7-1) of the trench gate structure is greater than the thickness of the polysilicon gate dielectric layer (7-2); the doping concentration of the P-type buried layer (6) is greater than the doping concentration of the super junction P column (4); and the P-type buried layer (6) cannot be completely depleted before the device breaks down.

9. The method for preparing a super junction IGBT device with a split gate structure according to claim 1, characterized in that: The following steps are involved: Step 1: Using N-type doped single crystal silicon wafer as substrate; Step 2: epitaxially grow N-type doped silicon on a single crystal silicon wafer, and then reversely etch away excess silicon on the surface to form an N-type doped drift region; Step 3: deposit a protective layer on the surface of the silicon wafer, photolithography a window to perform trench silicon etching, and etch out a P column area trench; Step 4: epitaxially grow P-type doped silicon in the P-pillar region trench, wherein the last epitaxial growth of the P-pillar adopts a higher doping, fills the P-pillar trench, and then removes excess P-type silicon by chemical mechanical planarization; Step 5: epitaxially growing N-type silicon on the silicon wafer, and then reversely etching away excess silicon on the surface to form an N-type charge storage layer (14); Step 6: epitaxially grow P-type silicon on the silicon wafer, and then reversely etch away excess silicon on the surface to form a P-type base region (12); Step 7: deposit a protective layer on the surface of the silicon wafer, photolithography a window to perform trench silicon etching, and simultaneously etch out the gate electrode trench and the emitter trench; Step 8: growing a sacrificial oxide layer on the sidewall of the trench in an O2 atmosphere at 1050° C. to 1150° C., then removing the sacrificial oxide layer, and then growing a gate oxide layer on the sidewall of the trench in an O2 atmosphere at 1050° C. to 1150° C.; Step 9: depositing polysilicon on the dielectric layer at 750° C. to 950° C., and then reverse etching away excess polysilicon on the surface; Step 10: Etching the gate electrode trench and the emitter trench; Step 11: growing a gate oxide layer in the etched gate electrode trench and emitter trench in an O2 atmosphere at 1050° C. to 1150° C.; Step 12: depositing polysilicon on the dielectric layer in step 8 at 750° C. to 950° C., and then reverse etching away excess polysilicon on the surface; Step 13: grow a pre-oxidation layer on the surface of the silicon wafer, and produce an N+ emitter region (10) by ion implantation of N-type impurities, with an ion implantation energy of 60 to 100 keV and an ion implantation dose of 10 14 ~10 15 / cm 2 , ion implantation of P-type impurities to obtain a P+ contact region (11), the ion implantation energy is 50-100 keV, the ion implantation dose is 10 14 ~10 15 / cm 2 ; Step 14: Depositing metal on the front side of the device to make emitter metal (16); Step 15: Turn the silicon wafer over and ion-implant N-type impurities to obtain an N-type field stop layer (3). The ion implantation energy is 200-500 keV and the ion implantation dose is 10 12 ~10 14 / cm 2 , laser annealing is adopted; ion implantation of P-type impurities is performed to obtain a P+ collector (2), the ion implantation energy is 50-100 keV, the ion implantation dose is 10 12 ~10 15 / cm 2 ; Step 16: Deposit metal to make collector metal (1).

10. The method for preparing a super junction IGBT device with a split gate structure according to claim 1, characterized in that: The following steps are involved: Step 1: Using N-type doped single crystal silicon wafer as substrate; Step 2: epitaxially grow N-type doped silicon on a single crystal silicon wafer, and then reversely etch away excess silicon on the surface to form an N-type doped drift region; Step 3: deposit a protective layer on the surface of the silicon wafer, photolithography a window to perform trench silicon etching, and etch out a P column area trench; Step 4: epitaxially grow P-type doped silicon in the P-pillar region trench, wherein the last epitaxial growth of the P-pillar adopts a higher doping, fills the P-pillar trench, and then removes excess P-type silicon by chemical mechanical planarization; Step 5: epitaxially growing N-type silicon on the silicon wafer, and then reversely etching away excess silicon on the surface to form an N-type charge storage layer (14); Step 6: epitaxially grow P-type silicon on the silicon wafer, and then reversely etch away excess silicon on the surface to form a P-type base region (12); Step 7: Grow a pre-oxidation layer on the surface of the silicon wafer, and produce an N+ emitter region (10) by ion implantation of N-type impurities, with an ion implantation energy of 60 to 100 keV and an ion implantation dose of 10 14 ~10 15 / cm 2 , ion implantation of P-type impurities to obtain a P+ contact region (11), the ion implantation energy is 50-100 keV, the ion implantation dose is 10 14 ~10 15 / cm 2 ; Step 8: deposit a protective layer on the surface of the silicon wafer, photolithography a window to perform trench silicon etching, and simultaneously etch out the gate electrode trench and the emitter trench; Step 9: growing a sacrificial oxide layer on the sidewall of the trench in an O2 atmosphere at 1050° C. to 1150° C., then removing the sacrificial oxide layer, and then growing a gate oxide layer on the sidewall of the trench in an O2 atmosphere at 1050° C. to 1150° C.; Step 10: depositing polysilicon on the dielectric layer at 750° C. to 950° C., and then reverse etching away excess polysilicon on the surface; Step 11: Etching the gate electrode trench and the emitter trench; Step 12: growing a gate oxide layer in the etched gate electrode trench and emitter trench in an O2 atmosphere at 1050° C. to 1150° C.; Step 13: depositing polysilicon on the dielectric layer in step 9 at 750° C. to 950° C., and then reverse etching away excess polysilicon on the surface; Step 14: Depositing metal on the front side of the device to make emitter metal (16); Step 15: Turn the silicon wafer over and ion-implant N-type impurities to obtain an N-type field stop layer (3). The ion implantation energy is 200-500 keV and the ion implantation dose is 10 12 ~10 14 / cm 2 , laser annealing is adopted; ion implantation of P-type impurities is performed to obtain a P+ collector (2), the ion implantation energy is 50-100 keV, the ion implantation dose is 10 12 ~10 15 / cm 2 ; Step 16: Deposit metal to make collector metal (1).

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