Semiconductor wafer surface chip detection method and system

Abstract

The invention belongs to the technical field of chip detection, and discloses a semiconductor wafer surface chip detection method and system, and the method comprises the steps: taking an electromagnetic feature vector as a positive sample instruction signal, and constructing a positive sample database; scanning an electromagnetic radiation signal of a chip on the surface of the semiconductor wafer to be detected, and outputting an electromagnetic radiation signal to be matched after performing windowing and framing processing on the electromagnetic radiation signal; uploading the electromagnetic radiation signal to be matched to a positive sample database for area interception processing, measuring the distance between an interception result and any positive sample instruction signal in the positive sample database, and obtaining a chip electromagnetic state detection result; simulating a chip impedance mismatching condition, and generating a reflected signal defect qualitative set according to a simulation result; and matching defects of the chip on the surface of the semiconductor wafer to be detected, and predicting the service life of the chip on the surface of the semiconductor wafer to be detected in combination with a chip electromagnetic state detection result. According to the invention, non-surface and non-dominant defects of the chip can be detected according to an electromagnetic reflection signal.

Description

Technical Field

[0001] The present invention relates to the technical field of chip detection, and particularly relates to a method and system for detecting chips on the surface of a semiconductor wafer. Background Art

[0002] A semiconductor wafer is a thin slice made of single-crystal semiconductor material (usually silicon, and there are also gallium arsenide, silicon carbide, etc.). As a carrier for manufacturing chips, nano-scale circuit structures can be processed on its surface through processes such as lithography, etching, and deposition. The chips on the surface of a semiconductor wafer refer to multiple chip (Chip / Die) units simultaneously manufactured on the surface of an uncut wafer through micro-nano processes.

[0003] However, in the current detection process of chips on the surface of a semiconductor wafer, it is impossible to evaluate the corresponding state behavior according to the electromagnetic vector and impedance condition of the chips. When the chips are working, they will generate reflected electromagnetic waves. If these signals are not utilized, it is easy to miss important diagnostic bases, resulting in the inability to detect the subtle structural damage behavior of the chips, and further leading to the situation of missing potential defects, reducing the efficiency of chip detection.

[0004] Therefore, how to provide a method and system for detecting chips on the surface of a semiconductor wafer is an urgent problem to be solved at present. Summary of the Invention

[0005] Embodiments of the present invention provide a method and system for detecting chips on the surface of a semiconductor wafer to solve the problem in the prior art that the subtle structural damage behavior of chips cannot be detected.

[0006] To provide a basic understanding of some aspects of the disclosed embodiments, a simple summary is given below. This summary part is not a general review, nor is it intended to identify key / important constituent elements or delineate the protection scope of these embodiments. Its sole purpose is to present some concepts in a simple form as a prelude to the subsequent detailed description.

[0007] According to a first aspect of an embodiment of the present invention, a method for detecting chips on the surface of a semiconductor wafer is provided.

[0008] In one embodiment, the method for detecting chips on the surface of a semiconductor wafer includes: Using a feature extraction algorithm to obtain the electromagnetic feature vector corresponding to the chips on the surface of a defect-free semiconductor wafer, and using the electromagnetic feature vector as a positive sample instruction signal to construct a positive sample database; Scanning the electromagnetic radiation signal of the chips on the surface of the semiconductor wafer to be measured by using near-field probe technology, and after performing windowing and frame division processing on the electromagnetic radiation signal, using a feature extraction algorithm to output the electromagnetic radiation signal to be matched; Upload the electromagnetic radiation signal to be matched to the positive sample database for regional interception processing, measure the distance between the interception result and any positive sample instruction signal in the positive sample database, and obtain the chip electromagnetic state detection result; Process multiple forms of defects on the chips on the surface of a defect-free semiconductor wafer, simulate the chip impedance mismatch situation, and generate a set of qualitative defect reflection signals based on the simulation results; Match the defects of the chips on the surface of the semiconductor wafer to be tested according to the set of qualitative defect reflection signals, and combine the defect results with the chip electromagnetic state detection results to predict the lifespan of the chips on the surface of the semiconductor wafer to be tested.

[0009] In one embodiment, processing multiple forms of defects on the chips on the surface of a defect-free semiconductor wafer, simulating the chip impedance mismatch situation, and generating a set of qualitative defect reflection signals based on the simulation results includes: Generate modeling parameters based on the defect types of the chips on the surface of the semiconductor wafer, construct a chip simulation model according to the modeling parameters and the chip structure on the surface of the semiconductor wafer, and add a test signal in the simulation to observe the reflection signal of the chip; Use a feature extraction algorithm to extract a set of feature signals including peak amplitude and phase shift from the reflection signal, associate the set of feature signals with the defect types, and construct a set of mapping relationships according to the association results; Analyze the impedance mismatch performance of the chips on the surface of the semiconductor wafer according to the set of mapping relationships, and quantify the defect emission coefficient and defect resonance offset of the chips on the surface of the semiconductor wafer based on the impedance mismatch performance to generate a set of qualitative defect reflection signals.

[0010] According to the second aspect of the embodiments of the present invention, a chip detection system for the surface of a semiconductor wafer is provided.

[0011] In one embodiment, the chip detection system for the surface of a semiconductor wafer includes: A positive sample database construction module, configured to use a feature extraction algorithm to obtain the electromagnetic feature vectors corresponding to the chips on the surface of a defect-free semiconductor wafer, and use the electromagnetic feature vectors as positive sample instruction signals to construct a positive sample database; A signal processing and feature extraction module, configured to scan the electromagnetic radiation signals of the chips on the surface of the semiconductor wafer to be tested by using near-field probe technology, and after performing windowing and frame division processing on the electromagnetic radiation signals, use a feature extraction algorithm to output the electromagnetic radiation signals to be matched; An electromagnetic state detection and matching module, configured to upload the electromagnetic radiation signals to be matched to the positive sample database for regional interception processing, measure the distance between the interception result and any positive sample instruction signal in the positive sample database, and obtain the chip electromagnetic state detection result; A defect characterization set generation module, configured to process various forms of defects on the chips on the surface of a defect-free semiconductor wafer, simulate the chip impedance mismatch situation, and generate a reflection signal defect characterization set according to the simulation results; A chip life prediction and judgment module, configured to match the defects of the chips on the surface of the semiconductor wafer to be tested according to the reflection signal defect characterization set, and combine the defect results with the chip electromagnetic state detection results to predict the life of the chips on the surface of the semiconductor wafer to be tested.

[0012] According to a third aspect of an embodiment of the present invention, a computer device is provided.

[0013] In one embodiment, the computer device includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the steps of the above method are implemented.

[0014] According to a fourth aspect of an embodiment of the present invention, a computer-readable storage medium is provided.

[0015] In one embodiment, a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the above method are implemented.

[0016] The technical solution provided by the embodiment of the present invention may include the following beneficial effects: By analyzing the electromagnetic eigenvector to reflect the intrinsic electromagnetic behavior of the chip without defects, and using the defect-free eigenvector as a standard template, the present invention can quickly and accurately match the signals collected in the future, realize the rapid detection of the chip, and at the same time, based on the impedance mismatch and reflection signal change caused by the defect, form an identifiable physical pattern. Furthermore, according to the electromagnetic reflection signal, the non-surface and non-explicit defects of the chip can be detected.

[0017] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention.

[0019] Figure 1 is a flowchart of a method for detecting chips on the surface of a semiconductor wafer shown according to an exemplary embodiment; Figure 2 is a schematic block diagram of a system for detecting chips on the surface of a semiconductor wafer shown according to an exemplary embodiment; Figure 3 is a schematic structural diagram of a computer device shown according to an exemplary embodiment. Detailed Implementation Modes

[0020] The following description and the accompanying drawings fully illustrate specific implementation modes herein, enabling those skilled in the art to practice them. Parts and features of some implementation modes can be included in or replace parts and features of other implementation modes. The scope of the implementation modes herein includes the entire scope of the claims and all available equivalents of the claims. In this document, terms such as "first", "second", etc. are only used to distinguish one element from another, without requiring or implying any actual relationship or order between these elements. In fact, the first element can also be called the second element, and vice versa. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a structure, device or equipment comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or also includes elements inherent to such structure, device or equipment. Without further limitation, an element defined by the statement "comprising one..." does not exclude the presence of additional identical elements in the structure, device or equipment comprising the said element. The various embodiments herein are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other.

[0021] In this document, terms such as "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. This is only for the convenience of describing this document and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation on the present invention. In the description of this document, unless otherwise specified and limited, the terms "installed", "connected", "coupled" should be understood in a broad sense. For example, it can be a mechanical connection or an electrical connection, or can also be the communication inside two elements. It can be directly connected or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances.

[0022] In this document, unless otherwise stated, the term "plurality" means two or more.

[0023] In this document, the character " / " indicates that the objects before and after are in an "or" relationship. For example, A / B means: A or B.

[0024] In this document, the term "and / or" is an associative relationship describing an object, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B these three relationships.

[0025] It should be understood that although the various steps in the flowchart are sequentially shown according to the indication of the arrows, these steps are not necessarily executed sequentially in the order indicated by the arrows. Unless there is a clear description in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the figure may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same moment, but can be executed at different moments. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0026] Each module in the device or system of the present application can be implemented in whole or in part by software, hardware, and their combination. The above-mentioned modules can be embedded in the processor of the computer device in hardware form or be independent of it, or can be stored in the memory of the computer device in software form, so as to facilitate the processor to call and execute the operations corresponding to each of the above modules.

[0027] Without conflict, the embodiments in the present invention and the features in the embodiments can be combined with each other.

[0028] Figure 1 An embodiment of the chip detection method on the surface of a semiconductor wafer according to the present invention is shown.

[0029] In this alternative embodiment, the chip detection method on the surface of the semiconductor wafer includes: Step S101, using a feature extraction algorithm to obtain the electromagnetic feature vector corresponding to the chip on the surface of the defect-free semiconductor wafer, and taking the electromagnetic feature vector as a positive sample instruction signal to construct a positive sample database; Step S102, using a near-field probe technique to scan the electromagnetic radiation signal of the chip on the surface of the semiconductor wafer to be tested, and after performing windowing and framing processing on the electromagnetic radiation signal, using a feature extraction algorithm to output the electromagnetic radiation signal to be matched; Step S103, uploading the electromagnetic radiation signal to be matched to the positive sample database for region intercepting processing, measuring the distance between the interception result and any positive sample instruction signal in the positive sample database, and obtaining the chip electromagnetic state detection result; Step S104, processing various forms of defects on the chip on the surface of the defect-free semiconductor wafer to simulate the chip impedance mismatch situation, and generating a reflection signal defect qualitative set according to the simulation result; Step S105, matching the defects of the chip on the surface of the semiconductor wafer to be tested according to the reflection signal defect qualitative set, and combining the defect result with the chip electromagnetic state detection result to predict the life of the chip on the surface of the semiconductor wafer to be tested.

[0030] In this alternative embodiment, when using a feature extraction algorithm to obtain the electromagnetic feature vector corresponding to the chip on the surface of a defect-free semiconductor wafer and constructing a positive sample database with the electromagnetic feature vector as the positive sample instruction signal, the near-field probe technology can be used to scan the electromagnetic radiation signal of the chip on the surface of the defect-free semiconductor wafer, and obtain the scanning current frequency, scanning time series, signal time reception series, and scanning duration; determine the calibration frequency according to the scanning time series, signal time reception series, and scanning current frequency, calculate the total phase delay degree of the calibration frequency within the scanning duration to obtain the delay time of the electromagnetic radiation signal; compensate the received electromagnetic radiation signal according to the delay time, and resample the compensated electromagnetic radiation signal according to the original number of sampling points to obtain the calibrated electromagnetic radiation signal; reconstruct the time-domain signal according to the calibrated electromagnetic radiation signal to obtain the true spectrum of the electromagnetic radiation signal as the electromagnetic feature vector, and use the electromagnetic feature vector as the positive sample instruction signal to construct a positive sample database.

[0031] It should be noted that the chip on the surface of the defect-free semiconductor wafer proposed in this embodiment is a chip without scratches, particle contamination, cracks, bubbles or residual photoresist on the surface, the metal interconnect line width or pitch is ≤±2% of the production standard value, the line edge roughness should be ≤1.5 nm, the grain size needs to be ≤50 nm, the resistivity needs to be ≤2.0 μΩ·cm, and at the same time, the leakage current in the crystal parameters is less than 0.5 μA / cm 2 , under the condition of a test temperature of 25°C; the static holding current SRAM <10 pA / cell, under the conditions of a test temperature of 25°C and a voltage of 08V; the refresh leakage current (DRAM) <1 fA / cell / ms, under the condition of a test temperature of 85°C; and the wafer-level threshold voltage uniformity ≤±30 mV, the coupling coefficient of adjacent signal lines (spacing = 3×line width) ≤-40 dB, under the condition of a working frequency of 5; at the same time, the radiation intensity difference ≤±0.5 dB (scanning step 5 μm), the deviation of the radiation intensity at the chip edge from the central region ≤±1 dB, and in order to ensure the quality of the positive sample database, the film thickness error of the deposition or etching process control of the chip on the surface of the defect-free semiconductor wafer is less than ±5%, and there is no deformation or electrical performance drift caused by thermal stress when working in the temperature range of -40°C to 125°C, that is, the chip that simultaneously meets the requirements of complete physical structure, qualified electrical performance and stable process is the chip on the surface of the defect-free semiconductor wafer proposed in this embodiment.

[0032] It should be noted that in the process of scanning the electromagnetic radiation signal of the chip on the surface of a defect-free semiconductor wafer using the near-field probe technology and obtaining the scanning current frequency, scanning time series, signal time reception sequence, and scanning duration, a scanning test platform needs to be built, and a near-field probe (specifically, it can be an electric field or magnetic field type), a scanning platform, a signal acquisition device (such as a spectrum analyzer, a high-speed oscilloscope, or an ADC acquisition card), an amplifier, a chip power supply and excitation system, and a control and synchronization module are prepared. At the same time, the chip on the surface of the semiconductor wafer to be tested is fixed on the platform, its working state is configured to ensure that the power supply, clock, and input signal are normal, so that it generates a stable electromagnetic radiation signal in the normal functional state. The scanning parameters are set, including the spatial boundary of the scanning area, the step distance, the probe scanning height, the sampling duration and sampling frequency at each point, to ensure the spatial resolution and time accuracy. The scanning process is started through the control system, and the probe moves to the predetermined scanning points in turn on the two-dimensional plane, and the electromagnetic signal is collected at each point. The collected signal is a time series, and the position information of each sampling point, the start and end time of sampling (used to generate the scanning time series), the received original electromagnetic waveform (signal time reception sequence) are recorded, and the main frequency component is extracted as the scanning current frequency at this point. The high-speed circuits inside the chip inevitably generate high-frequency current / voltage changes when performing specific tasks, and these changes continuously repeat according to clear functional behavior rules, thus presenting stable and repeatable electromagnetic leakage characteristics in terms of frequency and time. On the premise of controlling the power supply, clock, environmental interference, and excitation conditions, the signal can be stably captured and analyzed by a high-precision near-field probe, and the electromagnetic radiation signal of the chip on the surface of a defect-free semiconductor wafer can be obtained.

[0033] The process of extracting the characteristics of the electromagnetic radiation signal to obtain the electromagnetic vector is to use the electromagnetic radiation signal as vector components to form a three-dimensional vector representation, which can be obtained by arranging multiple directional probes or rotating a single probe to sample in different directions in turn. During the sampling process, each component signal needs to be synchronously collected to ensure time-domain alignment. Then, after band-pass filtering and denoising the collected signals, the short-time Fourier transform (STFT) or wavelet transform is applied to extract the time-frequency characteristics of the signals in each direction, and parameters such as the main frequency, energy, and phase in each direction are extracted. Furthermore, the amplitude vector and phase vector of the electric field or magnetic field are respectively formed, and according to the need, a complex vector (a complex form representing the amplitude and phase) can be further synthesized. The electromagnetic vectors at each measurement point are spliced to construct a spatial distribution map, and the electromagnetic vector field can be reconstructed.

[0034] In this optional embodiment, the calculation formula for the delay time of the electromagnetic radiation signal is: ; where D shift represents the delay time of the electromagnetic radiation signal, and g measuredrepresents the scanning current frequency, Δg represents the frequency error, T represents the sampling duration, and F T represents the total overall phase delay degrees corresponding to the corrected frequency of the sampling duration T.

[0035] In this alternative embodiment, when uploading the electromagnetic radiation signal to be matched to the positive sample database for region interception processing, measuring the distance between the interception result and any positive sample instruction signal in the positive sample database, and obtaining the chip electromagnetic state detection result, the electromagnetic radiation signal to be uploaded can be obtained for amplification and correction processing, and region interception processing can be performed on the electromagnetic radiation signal to be matched according to the preset interception requirements, and morphological recognition can be performed on the intercepted region; comparing the morphological recognition result with the positive sample database, if there is no morphological recognition result in the positive sample database, the region interception processing is re-implemented until there is a region interception in the positive sample database; if there is a morphological recognition result in the positive sample database, the electromagnetic radiation signal to be matched is directly matched from the positive sample database, and the shortest edit distance between the morphological recognition result and the matching result is judged; judging the difference between the shortest edit distance and the distance threshold, and identifying the chip electromagnetic state detection result of the electromagnetic radiation signal to be matched according to the difference result.

[0036] It should be explained that in the process of obtaining the chip electromagnetic state detection result, the near-field probe technology is used to scan the chip in the defect-free state, including the scanning current frequency, the scanning time series, the signal time reception series and the scanning duration, so as to obtain the stable electromagnetic response of the defect-free state chip, provide high-quality raw data for subsequent calibration, modeling and comparison matching, perform time-axis translation compensation on the original received signal by calculating the delay time of the electromagnetic radiation signal, and resample the compensated signal according to the original number of sampling points to obtain a group of time-domain reconstructed signals, which is convenient to eliminate the signal misalignment problem caused by system delay or equipment error.

[0037] Convert the corrected time-domain signal to the frequency domain to obtain the spectral feature vector, which is used as the positive sample instruction signal and stored in the positive sample database to obtain a characteristic standard of a defect-free chip, providing a reference for subsequent identification and comparison; Obtain the chip electromagnetic radiation signal to be matched, perform amplification and correction processing on it, perform region interception processing according to the spatial window, perform morphological recognition on the intercepted region (such as waveform pattern, feature distribution, etc.), select the key feature region for matching, improve the accuracy and efficiency, and prepare for the subsequent comparison for pattern matching. If there is no match for the morphological recognition result in the positive sample library, re-intercept; if there is a match for the morphological recognition result: calculate the edit distance (such as the shortest edit distance); compare with the set distance threshold to judge the degree of difference; obtain the current electromagnetic state of the chip, quantitatively compare the actual electromagnetic performance of the chip with the defect-free state, the edit distance represents the matching degree, the larger the difference → the greater the difference → the more abnormal the state, and detect whether the chip is in a normal, degraded, abnormal, etc. state.

[0038] In this alternative embodiment, when processing various forms of defects on the chips on the surface of a defect-free semiconductor wafer to simulate the chip impedance mismatch situation and generating a set of qualitative defect reflection signals based on the simulation results, modeling parameters can be generated based on the defect types of the chips on the surface of the semiconductor wafer. A chip simulation model can be constructed according to the modeling parameters and the chip structure on the surface of the semiconductor wafer, and a test signal can be added during the simulation to observe the reflection signal of the chip. The feature extraction algorithm is used to extract a set of feature signals including peak amplitude and phase shift from the reflection signal, associate the set of feature signals with the defect types, and construct a set of mapping relationships according to the association results. The impedance mismatch performance of the chips on the surface of the semiconductor wafer is analyzed according to the set of mapping relationships, and the defect emission coefficient and defect resonance offset of the chips on the surface of the semiconductor wafer are quantified based on the impedance mismatch performance to generate a set of qualitative defect reflection signals.

[0039] In this alternative embodiment, when using the feature extraction algorithm to extract a set of feature signals including peak amplitude and phase shift from the reflection signal, associating the set of feature signals with the defect types, and constructing a set of mapping relationships according to the association results, the reflection signal can be decomposed to generate a number of vector signals, the vector signals can be divided into intervals, and the signal fluctuation degree of the vector signals within the intervals can be calculated. Based on the signal fluctuation degree, the fluctuation sequence of the vector signals is obtained, and the distribution eigenvalue of the vector signals is obtained according to the corresponding fluctuation sequences of the vector signals to obtain the phase shift degree of the vector signals. The adaptive threshold of the vector signals is analyzed according to the phase shift degree, and the amplitude of the vector signals is extracted based on the adaptive threshold. The peak amplitude of the vector signals is analyzed based on the extraction results. The peak amplitude and the phase shift degree are combined as the set of feature signals of the reflection signal, and the set of feature signals is associated with the defect types to construct a set of mapping relationships.

[0040] In this alternative embodiment, the calculation formula for the signal fluctuation degree is: ; where H ab represents the signal fluctuation degree of the b-th interval of the a-th vector signal, c represents the total number of signals in the b-th interval of the a-th vector signal, y ab(d-1,d) represents the slope between the (d - 1)-th signal and the d-th signal in the b-th interval of the a-th vector signal, y ab(d,d+1) represents the slope between the d-th signal and the (d + 1)-th signal in the b-th interval of the a-th vector signal, y abd represents the d-th signal in the b-th interval of the a-th vector signal, represents the mean value of all signals in the b-th interval of the a-th vector signal.

[0041] In this alternative embodiment, when obtaining the fluctuation sequence of the vector signal based on the degree of signal fluctuation, and obtaining the distribution characteristic value of the vector signal according to the corresponding fluctuation sequence of each vector signal, and obtaining the phase offset degree of the vector signal, the degree of signal fluctuation can be sorted in ascending order, and the sorting result is used as the fluctuation sequence of the vector signal, and the possibility of each signal as a segmentation point is obtained based on the difference between the signals in the fluctuation sequence; a segmentation point is selected based on the feasibility result, and the vector signal is divided into a peak part and a phase part by using the segmentation point, and the distribution characteristic values of the peak part and the phase part are judged based on the distribution state of the vector signal; the offset part of the corresponding fluctuation sequence of each vector signal is obtained by using the distribution characteristic value, a reference sequence of the fluctuation sequence is generated according to the offset part, and the phase offset degree of the vector signal is obtained by combining the interval corresponding to the fluctuation sequence.

[0042] It should be explained that in the process of generating the defect qualitative set of the reflected signal, different defect types (such as scratches, etching residues, and doping non-uniformities) are artificially simulated on the chips on the surface of the defect-free semiconductor wafer, modeling parameters (such as depth, position, and dielectric change) are generated based on the defect types, a simulation model is constructed, and an electromagnetic test signal is injected into the model, and the reflected signal is recorded. Furthermore, a virtual experimental platform that can reproduce the electromagnetic characteristic changes caused by defects can be created. At the same time, a feature extraction algorithm is used to extract the peak amplitude and phase offset from the reflected signal to construct a feature signal set, which represents the electromagnetic response behaviors corresponding to different defects. The complex waveform data can be converted into comparable and classifiable vector features. The extracted feature signal set is associated with the defect type to form a complete mapping set, indicating that a certain type of defect is associated with a certain set of feature signals (such as a certain phase offset + peak amplitude) to construct a defect recognition knowledge base to realize the ability to reverse the defect type from the electromagnetic response signal.

[0043] The reflected signal is decomposed into multiple vector signals, each vector signal is partitioned, the degree of signal fluctuation is calculated within each interval, the complex waveform is disassembled into smaller granularity data segments, and the activity degree and perturbation characteristics of each segment of the signal are reflected by the degree of fluctuation, which lays a foundation for peak / phase feature extraction. The degree of fluctuation values are arranged in ascending order to form a fluctuation sequence, and the segmentation point (specifically, the phase / peak boundary) is judged based on the signal difference. The vector signal is divided into a phase part and a peak part, and their distribution characteristic values are analyzed respectively, and the phase offset degree is calculated. Quantifying the phase offset by using the distribution change is an important signal dimension for defect recognition.

[0044] An adaptive threshold is generated according to the fluctuation characteristics of the phase offset. In each signal interval, the threshold is used to screen out the significantly changed regions (i.e., peaks); the peak amplitude and the phase offset are used as a set of reflected signal feature vectors and bound to the defect type to form a defect qualitative set of the reflected signal, which provides a reference library for the reflected signals found in real-time detection and improves the recognition accuracy.

[0045] Figure 2 An embodiment of the chip detection system for the semiconductor wafer surface of the present invention is shown.

[0046] In this alternative embodiment, the chip detection system for the semiconductor wafer surface includes: A positive sample database construction module 201, configured to obtain an electromagnetic feature vector corresponding to a chip on the surface of a defect-free semiconductor wafer by using a feature extraction algorithm, and use the electromagnetic feature vector as a positive sample instruction signal to construct a positive sample database; A signal processing feature extraction module 202, configured to scan the electromagnetic radiation signal of the chip on the surface of the semiconductor wafer to be measured by using a near-field probe technology, and after performing windowing and framing processing on the electromagnetic radiation signal, output a to-be-matched electromagnetic radiation signal by using a feature extraction algorithm; An electromagnetic state detection and matching module 203, configured to upload the to-be-matched electromagnetic radiation signal to the positive sample database for region interception processing, measure the distance between the interception result and any positive sample instruction signal in the positive sample database, and obtain a chip electromagnetic state detection result; A defect qualitative set generation module 204, configured to process various forms of defects on the chip on the surface of the defect-free semiconductor wafer, simulate the chip impedance mismatch situation, and generate a reflection signal defect qualitative set according to the simulation result; A chip life prediction and judgment module 205, configured to match the defects of the chip on the surface of the semiconductor wafer to be measured according to the reflection signal defect qualitative set, and combine the defect result with the chip electromagnetic state detection result to predict the life of the chip on the surface of the semiconductor wafer to be measured.

[0047] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as Figure 3 shown. The computer device includes a processor, a memory, and a network interface connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store static information and dynamic information data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the steps in the above method embodiment are implemented.

[0048] Those skilled in the art can understand, Figure 3The structure shown is only a block diagram of some structures related to the solution of the present invention, and does not constitute a limitation on the computer device to which the solution of the present invention is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0049] In addition, the present invention also provides a computer device, including a memory and a processor. A computer program is stored in the memory, and when the processor executes the computer program, the steps in the above method embodiments are implemented.

[0050] Furthermore, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0051] Those of ordinary skill in the art can understand that all or part of the processes in the above method embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the above method embodiments. Among them, any reference to a memory, storage, database or other medium used in the embodiments provided by the present invention can include at least one of non-volatile and volatile memories. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0052] The present invention is not limited to the structure already described and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present invention is only limited by the appended claims.

Claims

1. A method for detecting chips on the surface of a semiconductor wafer, characterized in that, Including: Using a feature extraction algorithm to obtain the electromagnetic feature vector corresponding to the chip on the surface of a defect-free semiconductor wafer, and using the electromagnetic feature vector as a positive sample instruction signal to construct a positive sample database; Adopting near-field probe technology to scan the electromagnetic radiation signal of the chip on the surface of the semiconductor wafer to be measured, and after performing windowing and framing processing on the electromagnetic radiation signal, using a feature extraction algorithm to output the electromagnetic radiation signal to be matched; Uploading the electromagnetic radiation signal to be matched to the positive sample database for region truncation processing, measuring the distance between the truncation result and any positive sample instruction signal in the positive sample database, and obtaining the chip electromagnetic state detection result; Processing various forms of defects on the chip on the surface of a defect-free semiconductor wafer to simulate the chip impedance mismatch situation, and generating a reflection signal defect qualitative set according to the simulation results; Matching the defects of the chip on the surface of the semiconductor wafer to be measured according to the reflection signal defect qualitative set, and combining the defect result with the chip electromagnetic state detection result to predict the life of the chip on the surface of the semiconductor wafer to be measured.

2. The chip detection method on the surface of a semiconductor wafer according to claim 1, characterized in that, The step of using a feature extraction algorithm to obtain the electromagnetic feature vector corresponding to the chip on the surface of a defect-free semiconductor wafer, and using the electromagnetic feature vector as a positive sample instruction signal to construct a positive sample database includes: Adopting near-field probe technology to scan the electromagnetic radiation signal of the chip on the surface of a defect-free semiconductor wafer, and obtaining the scanning current frequency, scanning time series, signal time reception series, and scanning duration; Determining the correction frequency according to the scanning time series, signal time reception series, and scanning current frequency, calculating the total phase delay degree of the correction frequency within the scanning duration, and obtaining the delay time of the electromagnetic radiation signal; Compensating the received electromagnetic radiation signal according to the delay time, and resampling the compensated electromagnetic radiation signal according to the original number of sampling points to obtain the corrected electromagnetic radiation signal; Reconstructing the time-domain signal according to the corrected electromagnetic radiation signal to obtain the true spectrum of the electromagnetic radiation signal as the electromagnetic feature vector, using the electromagnetic feature vector as a positive sample instruction signal, and constructing a positive sample database.

3. The chip detection method for the surface of a semiconductor wafer according to claim 2, wherein The calculation formula for the delay time of the electromagnetic radiation signal is: ； where D shift represents the delay time of the electromagnetic radiation signal, g measured represents the scanning current frequency, Δg represents the frequency error, T represents the sampling duration, F T represents the total overall phase delay degrees corresponding to the sampling duration T correction frequency.

4. The chip detection method on the surface of a semiconductor wafer according to claim 3, characterized in that, The step of uploading the electromagnetic radiation signal to be matched to the positive sample database for region truncation processing, measuring the distance between the truncation result and any positive sample instruction signal in the positive sample database, and obtaining the chip electromagnetic state detection result includes: Obtaining the electromagnetic radiation signal to be matched to be uploaded for amplification and correction processing, performing region truncation processing on the electromagnetic radiation signal to be matched according to preset truncation requirements, and performing morphological recognition on the truncated region; Comparing the morphological recognition result with the positive sample database. If the morphological recognition result does not exist in the positive sample database, re-performing region truncation processing until the region truncation exists in the positive sample database; If the morphological recognition result exists in the positive sample database, directly matching the electromagnetic radiation signal to be matched in the positive sample database, and judging the shortest edit distance between the morphological recognition result and the matching result; Judging the difference between the shortest edit distance and the distance threshold, and identifying the chip electromagnetic state detection result of the electromagnetic radiation signal to be matched according to the difference result.

5. A method for detecting chips on the surface of a semiconductor wafer according to claim 1, characterized in that, Processing various forms of defects on the chips on the surface of a defect-free semiconductor wafer, simulating the impedance mismatch situation of the chips, and generating a qualitative set of reflection signal defects based on the simulation results includes: Generating modeling parameters based on the defect types of the chips on the surface of the semiconductor wafer, constructing a chip simulation model according to the modeling parameters and the chip structure on the surface of the semiconductor wafer, and adding a test signal in the simulation to observe the reflection signal of the chip; Using a feature extraction algorithm to extract a set of feature signals including peak amplitude and phase shift from the reflection signal, associating the set of feature signals with the defect types, and constructing a mapping relationship set according to the association results; Analyzing the impedance mismatch performance of the chips on the surface of the semiconductor wafer according to the mapping relationship set, and quantifying the defect emission coefficient and defect resonance offset of the chips on the surface of the semiconductor wafer based on the impedance mismatch performance to generate a qualitative set of reflection signal defects.

6. A method for detecting chips on the surface of a semiconductor wafer according to claim 5, characterized in that, The defect types of the chips on the surface of the semiconductor wafer include scratches, etching residues, and non-uniform doping.

7. A method for detecting chips on the surface of a semiconductor wafer according to claim 6, characterized in that, The using a feature extraction algorithm to extract a set of feature signals including peak amplitude and phase shift from the reflection signal, associating the set of feature signals with the defect types, and constructing a mapping relationship set according to the association results includes: Decomposing the reflection signal to generate a number of vector signals, performing interval division on the vector signals, and calculating the signal fluctuation degree of the vector signals within the interval; Obtaining the fluctuation sequence of the vector signals based on the signal fluctuation degree, obtaining the distribution characteristic values of the vector signals according to the corresponding fluctuation sequences of the vector signals, and obtaining the phase shift degree of the vector signals; Analyzing the adaptive threshold of the vector signals according to the phase shift degree, extracting the amplitude of the vector signals based on the adaptive threshold, and analyzing the peak amplitude of the vector signals based on the extraction results; Combining the peak amplitude and the phase shift degree as the set of feature signals of the reflection signal, and associating the set of feature signals with the defect types to construct a mapping relationship set.

8. A method for detecting chips on the surface of a semiconductor wafer according to claim 7, wherein, The calculation formula for the signal fluctuation degree is: ； Where, H ab represents the signal fluctuation degree of the b-th interval of the a-th vector signal, c represents the total number of signals in the b-th interval of the a-th vector signal, y ab(d-1,d) represents the slope between the (d - 1)-th signal and the d-th signal in the b-th interval of the a-th vector signal, y ab(d,d+1) represents the slope between the d-th signal and the (d + 1)-th signal in the b-th interval of the a-th vector signal, y abd represents the d-th signal in the b-th interval of the a-th vector signal, represents the mean value of all signals in the b-th interval of the a-th vector signal.

9. The chip detection method on the surface of a semiconductor wafer according to claim 8, wherein The obtaining the fluctuation sequence of the vector signals based on the signal fluctuation degree, obtaining the distribution characteristic values of the vector signals according to the corresponding fluctuation sequences of the vector signals, and obtaining the phase shift degree of the vector signals includes: Sorting the signal fluctuation degrees in ascending order, taking the sorting result as the fluctuation sequence of the vector signals, and obtaining the possibility of each signal as a segmentation point according to the differences between the signals in the fluctuation sequence; Selecting a segmentation point based on the feasibility results, dividing the vector signals into two parts, peak and phase, using the segmentation point, and judging the distribution characteristic values of the peak and phase parts based on the distribution state of the vector signals; Obtaining the offset part of the corresponding fluctuation sequence of each vector signal using the distribution characteristic values, generating a reference sequence of the fluctuation sequence according to the offset part, and combining the interval corresponding to the fluctuation sequence to obtain the phase shift degree of the vector signals.

10. A chip detection system for the surface of a semiconductor wafer, characterized in that, Including: A positive sample database construction module for using a feature extraction algorithm to obtain the electromagnetic feature vectors corresponding to the chips on the surface of a defect-free semiconductor wafer, and taking the electromagnetic feature vectors as positive sample command signals to construct a positive sample database; A signal processing feature extraction module, which is used to scan the electromagnetic radiation signal of the chips on the surface of the semiconductor wafer to be measured by using the near-field probe technology, and after performing windowing and framing processing on the electromagnetic radiation signal, output the electromagnetic radiation signal to be matched by using the feature extraction algorithm; An electromagnetic state detection and matching module, which is used to upload the electromagnetic radiation signal to be matched to the positive sample database for region intercepting processing, measure the distance between the interception result and any positive sample command signal in the positive sample database, and obtain the chip electromagnetic state detection result; A defect qualitative set generation module, which is used to process various forms of defects on the chips on the surface of the defect-free semiconductor wafer, simulate the chip impedance mismatch situation, and generate a reflection signal defect qualitative set according to the simulation result; A chip life prediction and judgment module, which is used to match the defects of the chips on the surface of the semiconductor wafer to be measured according to the reflection signal defect qualitative set, and combine the defect results with the chip electromagnetic state detection results to predict the life of the chips on the surface of the semiconductor wafer to be measured.

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