SIP (Session Initiation Protocol) packaging ceramic substrate for communication module and preparation method thereof

Abstract

The invention discloses an SIP (Session Initiation Protocol) packaging ceramic substrate for a communication module. The SIP packaging ceramic substrate comprises a multi-layer ceramic substrate and a microstrip line structure arranged in the multi-layer ceramic substrate, the multi-layer ceramic substrate is provided with a TOP surface and a BTM surface, and the multi-layer ceramic substrate comprises a TOP layer, a middle layer and a BTM layer; the preparation method comprises the steps of tape casting slurry formula and precise thickness control, via hole laser manufacturing, inner electrode printing, raw ceramic lamination and lamination, raw ceramic warm water isostatic pressing, block segmentation and glue discharging and sintering. According to the high-density wiring technology HDI adopted by the invention, the line width and the spacing can be reduced to 0.05 mm, and the packaging density and the packaging performance are greatly improved. According to the technology, more I / O and grounding welding spot layouts can be realized in the ceramic substrate, and the requirement of high-density multi-chip packaging is met.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit packaging, and particularly to a SIP packaging ceramic substrate for a communication module and a preparation method thereof. Background Art

[0002] SIP (System-in-Package) for a communication module can integrate multiple different communication function chips into a standard package body to realize a module with certain system or subsystem functions.

[0003] The trend of new packaging technologies is towards miniaturization, integration, and an increasing number of I (input), O (output), and GND (Ground) interfaces with higher reliability. This requires the packaging substrate to have a coefficient of thermal expansion closer to that of silicon-based and gallium arsenide semiconductor materials, enabling more layers and higher-density wiring technologies, as well as more I / O / GND interface design technologies, etc., to meet the requirements of multi-chip packaging.

[0004] For traditional SIP packaging using PCB boards with epoxy resin or polytetrafluoroethylene as the substrate, on the one hand, its coefficient of thermal expansion is one order of magnitude larger than that of ceramics, usually 10 - 20 ppm / °C, while the alumina ceramic used in HTCC (High Temperature Cofired Ceramic) technology has a coefficient of thermal expansion of 5 - 7 ppm / °C, which is comparable to that of silicon-based and gallium arsenide, improving reliability.

[0005] For SIP packaging of PCB boards with epoxy resin or polytetrafluoroethylene as the substrate, its multi-layer manufacturing process mostly uses copper cladding, re-etching, and lamination processes. When designing and manufacturing the circuit, the minimum line width and the gap between lines are usually 0.1 mm, while the corresponding HTCC process technology is 0.05 mm. Using the HTCC technology can improve the wiring density, increase the integration degree, and make the volume smaller; In recent years, ceramic technology has also been used for packaging. The welding method usually uses a lead frame or a surface-mounted Pad (pad). Its packaging has few I / O and ground GND solder joints and a low solder joint density; in new packages with high functional integration and multi-chip module MCM packaging, more chips need to be surface-mounted; in addition, to meet higher RF performance, designers usually design more ground pads. The present invention uses multi-layer wiring and BGA technology to replace the traditional lead frame technology to meet the requirements of new packages. The interconnection between multiple chip modules is realized through micro-holes and micro-connection channels. This technology can provide more electrical connections in a limited space while maintaining low signal loss and high bandwidth, optimizing the performance of the communication module. Summary of the Invention

[0006] In view of this, the present invention adopts the high-temperature co-fired HTCC technology. According to the requirements of high-density I / O solder joints and ground solder joints for SIP packaging, a BGA-packaged SIP packaging ceramic substrate is designed and manufactured. The circuit and via design of HTCC can realize more chip I / O and ground solder joint layouts, achieving high-density packaging of chips. By adopting a multi-layer structure circuit and using high-density interlayer interconnection, ceramic lamination, and isostatic pressing, the thickness of the chip packaging substrate is reduced, realizing thin packaging. The BGA-type solder joint design has a very high solder joint density, improving the packaging density of the chip; To achieve the above object, the present invention adopts the following technical solutions: A SIP packaging ceramic substrate for a communication module, comprising a multi-layer ceramic substrate and a microstrip line structure provided in the multi-layer ceramic substrate; The multi-layer ceramic substrate is provided with a TOP surface and a BTM surface, and the multi-layer ceramic substrate includes a TOP layer, an intermediate layer, and a BTM layer; The microstrip line forms a path inside the multi-layer ceramic substrate, connecting the packaging circuit, matching circuit, and Pad on the TOP surface with the BGA solder joints on the BTM surface; The TOP layer of the multi-layer ceramic substrate is provided with semiconductor chip I / O lines (chip Input lines and chip Output lines), a matching circuit, a ground line, micro blind vias, and their Pads, corresponding to the BGA solder joints on the BTM layer of the multi-layer ceramic substrate through the middle-layer microstrip lines and buried vias; The intermediate layer of the multi-layer ceramic substrate is printed with surface microstrip lines and buried vias; At the bottom of the BTM layer of the multi-layer ceramic substrate, there are 112 BGA-type solder joints numbered from 1 to 112, realizing the connection of the I / O interfaces and grounding of the chips on the TOP layer with the circuit, and achieving high-density packaging of the chips.

[0007] Further, the multi-layer ceramic substrate has a total of 6 layers, wherein the first layer is printed with the TOP surface on the surface, the second to sixth layers are printed with surface layers, and the sixth layer is printed with the BTM surface on the reverse side; and the second to sixth layers are provided with micro blind vias, buried vias, and wiring circuits that are electrically connected to the TOP layer and the BTM layer.

[0008] Further, micro blind vias are provided on the TOP layer and the BTM layer of the multi-layer ceramic substrate, and buried vias are provided in the intermediate layer.

[0009] A preparation method for a SIP packaging ceramic substrate for a communication module, comprising the following steps: Step 1) Mix alumina powder, manganese dioxide, chromium sesquioxide, and silicon dioxide and ball-mill them until the D50 particle size reaches less than 1.5 microns, and then dry them at 100 °C to prepare ceramic powder; Step 2) Add polyvinyl butyral, fish oil, polyethylene glycol, xylene, and n-butanol as solvents to the ceramic powder in Step 1) above, and perform ball milling and slurry mixing for 24 hours to prepare a ceramic slurry; Step 3) Degas the ceramic slurry in Step 2) above in a vacuum degassing device for 2 - 4 hours. According to the required thickness of the green ceramic tape for tape casting, control the degassing viscosity within the range; Step 4) Prepare the HTCC ceramic slurry in Step 3) above into a green ceramic film tape with the required thickness through a tape casting forming device; Step 5) Cut the green ceramic film tape in Step 4) into green ceramic film pieces with the required dimensions; Step 6) Punch holes in the green ceramic film pieces according to the circuit design and process requirements. The punching includes positioning holes, micro blind holes, and buried holes; Step 7) According to the design requirements of high-density circuits and high-density BGA solder joints in the SIP module, perform high-density wiring; adopt the screen printing process, and use tungsten paste to fill the micro blind holes and buried holes and print the circuit on the green ceramic pieces in Step 6) to achieve high-density multi-layer circuit printing on the TOP layer, intermediate layer, and BTM layer; Fill the holes in the hole columns of the punched film pieces with tungsten paste by means of stencil printing. The vias are full and round, and there are no collapses or voids in the hole columns; perform metal layer printing on the surface of the film pieces with vias through screen printing. After printing the pattern, ensure that the pattern is complete without missing parts; Among them, L1 - L4 represent the printed conduction lines on the ceramic surface, and H1 - H5 represent the hole filling in the Z direction perpendicular to the surface of the ceramic substrate and the conduction lines along the Z direction. In particular, Figure 7 and Figure 8 respectively represent the surface and bottom surface of the sixth layer of the substrate. There is no printed circuit on the sixth layer surface, only vias exist; Step 8) Corresponding relationship between the TOP layer lines and pads and the BTM layer pad: The TOP layer lines and pads are connected to the high-density lines in the intermediate layer through micro blind holes. The high-density lines in the intermediate layer are connected through buried holes. The BGA solder joints in the BTM layer are connected to the intermediate layer lines through micro blind holes, so that the welding lines and pads of the semiconductor chips in the TOP layer form a one-to-one correspondence with the BGA solder joints in the BTM layer; Step 9) Set input, output signal pads, and ground pads on the BTM layer; Step 10) Perform lamination, isostatic pressing, and slitting according to the design structure of the ceramic substrate; Perform lamination and pressing according to the design structure of the ceramic substrate. Stack the film pieces with printed patterns together through the positioning hole Mark to make the blocks have a certain strength for easy transfer of the process; After the lamination is completed, the membrane is subjected to warm water isostatic pressing: the colloid in the cast membrane reaches the best softening point at 80°C, and the interpenetration effect between layers is the best; after the laminated block is evacuated, it is placed in an isostatic press and subjected to warm water pressing under greater pressure to make the ceramics evenly stressed and compactly pressed, thereby improving the bonding strength of the green ceramics and the strength of the ceramics after sintering. The water temperature is 80°C, the pressure is 5-70MPa, and the pressure is maintained for 5-30 minutes.

[0010] The isostatically pressed blocks are preheated on a heating platform and cut into independent small units using a laser device or a cutting knife.

[0011] Step 11) Degreasing and co-firing the single ceramic substrate cut in step 10) in a reducing atmosphere furnace at 1500° C.-1600° C. to obtain a SIP package ceramic substrate.

[0012] Furthermore, in a method for preparing a SIP packaged ceramic substrate for a communication module, the mass percentages of alumina powder, manganese dioxide, chromium trioxide, silicon dioxide, polyvinyl butyral, fish oil, and polyethylene glycol added in steps 1) and 2) are: Alumina Al2O3: 45%-60%; Manganese dioxide MnO2: 0.5%-3%; Chromium trioxide Cr2O3: 0.5%-2%; Silicon dioxide SiO2: 1%-8%; Xylene: as solvent, 10%-25%; n-Butanol: as solvent, 10%-25%; Polyvinyl butyral PVB: as adhesive, 3%-10%; Fish oil: as a dispersant, 0.3%-2%; Polyethylene glycol PEG: as plasticizer, 1%-5%.

[0013] The beneficial effects of the present invention are as follows: 1) The ceramic substrate prepared by the present invention has a lower thermal expansion coefficient (5-7ppm / °C), can better match silicon-based and gallium arsenide materials, and provide better thermal stability and reliability.

[0014] 2) The high-density wiring technology (HDI) used in the present invention can reduce the line width and spacing to 0.05mm, greatly improving the density and performance of the package. This technology enables more I / O and grounding solder joints to be laid out in the ceramic substrate, meeting the requirements of high-density multi-chip packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 To invent a process flow chart; Figure 2 This is the circuit diagram of the TOP layer of the ceramic substrate of the present invention; Figure 3 It is a position diagram of the second layer circuit structure L1 and the TOP layer hole filling H1 of the ceramic substrate of the present invention; Figure 4 It is a position diagram of the third layer circuit structure L2 and the second layer filled hole H2 of the ceramic substrate of the present invention; Figure 5 This is a position diagram of the fourth layer circuit structure L3 and the third layer filled hole H3 of the ceramic substrate of the present invention; Figure 6 It is a position diagram of the circuit structure L4 of the BTM layer of the ceramic substrate of the present invention and the fourth layer filled hole H4; Figure 7 This is a position diagram of the hole H5 filled in the fifth layer and the BTM layer of the ceramic substrate of the present invention; Figure 8 This is a BGA solder joint diagram of the BTM layer of the ceramic substrate of the present invention; In the figure: A, ground line; B, chip input line; C, matching line; D, chip output line; F, micro blind via; G, microstrip line; H, buried via. DETAILED DESCRIPTION

[0016] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0017] like Figure 2-8 As shown, a SIP package ceramic substrate for a communication module is designed with a multi-layer ceramic substrate having a TOP (top) surface and a BTM (bottom) surface; A microstrip transmission line structure is designed, and a stripline transmission line formed by tungsten slurry is used to form a passage inside the multilayer ceramic substrate to connect the pad on the TOP surface and the spherical solder joint on the BTM surface; HTCC ceramic slurry preparation, using micron-sized alumina powder, adding manganese oxide, chromium oxide, silicon dioxide and other powders, partially reducing its sintering temperature, adding xylene, anhydrous ethanol and other organic solvents, and then adding polyvinyl butyral (PVB) resin, fish oil dispersant, polyethylene glycol plasticizer, ball milling in a ball mill barrel to fully mix, vacuum remove bubbles and let stand, and then tape casting to make a green ceramic film strip with a thickness of 20µm-200µm, and cut into green ceramic sheets with a length and width of 150mm*150mm; According to the design of SIP package ceramic substrate, laser drilling is performed on the raw ceramic sheet, tungsten paste is used to fill the holes, and high-density multi-layer circuits are screen-printed; According to the designed structure, the layers are stacked, isostatically pressed, cut, degreased and co-fired in a 1500-1600℃ reducing atmosphere furnace to make a SIP package ceramic substrate; The TOP layer of the SIP package ceramic substrate is mainly designed with semiconductor chip I / O circuits, matching circuits, grounding circuits, vias and their pads, and the corresponding BGA solder joints 1-112 on the BTM layer; The second to sixth layers of the SIP package ceramic substrate are designed with holes and high-density wiring circuits that are electrically connected to the TOP layer and the BTM; this ceramic substrate provides a carrier for the integration of communication chips and devices and enables high-density wiring; the prepared SIP package ceramic substrate for the communication module has a total of 6 layers, where the first layer has the TOP surface printed on the surface, the second to sixth layers have the surface layer printed, and the sixth layer has the BTM surface printed on the reverse side; At the bottom of the BTM layer of the SIP package ceramic substrate, 1-112 BGA-type solder joints are designed to realize the I / O interface and grounding of the chips and circuits on the TOP layer, and achieve high-density chip packaging; in this embodiment, solder joints 31, 32, 94, and 95 are all grounding pads, solder joint 79 is an input pad, and solder joint 109 is an output pad.

[0018] As Figure 1 shown, a preparation method process of a SIP package ceramic substrate for a communication module includes: tape casting slurry formulation and precise thickness control, laser via fabrication, inner electrode printing, green ceramic lamination, warm isostatic pressing of green ceramic, bar block cutting, debinding and sintering.

[0019] Specifically, 1) Mix alumina powder, manganese dioxide, chromium sesquioxide, and silicon dioxide and ball mill them until the D50 particle size reaches less than 1.5 microns, and then dry at 100 °C; 2) Add polyvinyl butyral, fish oil, and polyethylene glycol to the ceramic powder in step 1) and ball mill and mix the slurry for 24 hours to prepare a ceramic slurry with a certain viscosity; Taking the HTCC ceramic slurry as 100%, the types and amounts of chemical substances are as follows: 1) Types and amounts of organic compounds used: Xylene: As a solvent, 10%-25%; n-Butanol: As a solvent, 10%-25%; Polyvinyl butyral PVB: As an adhesive, 3%-10%; Fish oil: As a dispersant, 0.3%-2%; Polyethylene glycol PEG: As a plasticizer, 1%-5%.

[0020] 2) Range of types and amounts of ceramic compounds used: Aluminum oxide (Al2O3): 45%-60% Manganese dioxide (MnO2): 0.5%-3% Chromium sesquioxide (Cr2O3): 0.5% - 2% Silicon dioxide (SiO2): 1% - 8% ; Combined with Example 1, after the HTCC ceramic slurry is mixed, at room temperature of 25°C ± 5°C, the measured viscosity is ; Combined with Example 2, for the HTCC ceramic slurry at room temperature of 25°C ± 5°C, the measured viscosity is ; Combined with Example 3, for the HTCC ceramic slurry at room temperature of 25°C ± 5°C, the measured viscosity is ; 3) The above-mentioned 3) ceramic slurry is degassed in a vacuum degassing equipment for 2 - 4 hours. According to the required thickness of the cast green ceramic, the degassing viscosity is controlled within range.

[0021] 4) The above-mentioned 3) HTCC ceramic slurry is used to prepare a green ceramic film strip with the required thickness through a tape casting equipment; 5) The above-mentioned 4) green ceramic film strip is cut into green ceramic film pieces with a length and width of 150mm * 150mm; 6) The green ceramic film pieces are punched on the 5) green ceramic pieces according to the circuit design and process requirements; 7) According to the design requirements of the high - density circuit and high - density BGA solder joints of the SIP module, the present invention adopts a high - density wiring technology, as shown in the following figures: 8) According to the high - density wiring technology, a screen printing process is adopted to make circuits with a minimum line width of 50um and a minimum distance between the line edges of 50um to meet the requirements of the SIP module; 9) Adopt screen printing to Figure 2-6 circuits, and use tungsten paste to fill holes and print circuits on the 6) green ceramic pieces; 10) The pad conduction correspondence, as shown in Figure 2 the TOP - layer circuit and pad, Figure 2-6 the internal conduction high - density circuit and vias, Figure 7-8 the BTM - layer BGA solder joint pad diagram corresponding to the TOP - layer circuit and Pad one by one; 11) The conduction between the TOP - layer circuit pad and the BTM - layer circuit pad is realized through vias and multiple intermediate circuits; 12) The ceramic substrate inputs and outputs signals through pad79 and pad109 respectively; 13) Stacking, isostatic pressing, and slitting are carried out according to the designed structure of the ceramic substrate; 14) The single-piece ceramic substrates cut in 13) are degreased and co-fired in a reducing atmosphere furnace at 1500°C - 1600°C to obtain SIP package ceramic substrates.

[0022] In traditional SIP packages, PCB boards based on epoxy resin or polytetrafluoroethylene materials are usually adopted. These materials have relatively high thermal expansion coefficients (10 - 20 ppm / °C), resulting in limited reliability in high-frequency and high-power applications. In contrast, the alumina ceramic substrates adopted in the present invention have lower thermal expansion coefficients (5 - 7 ppm / °C), can better match silicon-based and gallium arsenide materials, and provide better thermal stability and reliability.

[0023] In addition, the line widths and spacings of traditional PCB materials are usually larger. The common minimum line width and spacing are 0.1 mm. However, through the high-density wiring technology (HDI) adopted in the present invention, the line widths and spacings can be reduced to 0.05 mm, greatly improving the packaging density and performance. This technology enables more I / O and ground solder joint layouts to be realized in the ceramic substrate, meeting the requirements of high-density multi-chip packaging.

[0024] Implementation and superiority of the high-density wiring technology (HDI) of the present invention in ceramic substrates: The application of the high-density wiring technology (HDI) in ceramic substrates realizes high integration and high performance through the following key technical points: 1. Micro blind via and buried via technology: In the ceramic substrate of the present invention, micro blind vias (Blind Via) are designed in the TOP layer and the BTM layer, and buried vias (Buried Via) are designed in the intermediate layer, which are used to connect circuits between different layers. By restricting the depth of the holes, this design can effectively save space and increase the number of circuit board layers without damaging the overall structure of the ceramic substrate.

[0025] 2. Microstrip line structure and signal transmission optimization: To achieve efficient signal transmission, a microstrip line structure is adopted inside the ceramic substrate of the present invention, which helps to reduce electromagnetic interference (EMI) and signal loss; among them, the microstrip line is precisely manufactured through screen printing technology.

[0026] 3. High-density conductive layer design: The HDI design of the ceramic substrate of the present invention realizes a higher line density in the same space by adopting a tiny line width. The minimum designed line width is 50 um.

[0027] Application and advantages of the high-density packaging BGA technology of the present invention: The application of BGA packaging technology in ceramic substrates has brought significant improvements in packaging density and performance. By adopting the BGA solder joint design, the ceramic substrate BGA packaging of the present invention provides 112 solder joints, thus achieving high-density I / O interfaces and ground solder joints within a limited space, which makes it possible for multi-chip module (MCM) packaging.

[0028] 1. High-density I / O interface design: In traditional packaging, the number of solder joints in the lead frame packaging technology is limited and the solder joint density is low, while BGA packaging can achieve a higher solder joint density to meet the requirements of communication modules for integration and the number of I / O interfaces. Through the high-density BGA solder joint design, the ceramic substrate of the present invention can achieve a higher density of chip connections within the same substrate area.

[0029] 2. Thermal management and heat dissipation optimization: Another advantage of BGA packaging technology lies in its excellent thermal management performance. Due to the excellent thermal conductivity of ceramic materials, compared with traditional PCB materials, ceramic substrates can dissipate heat more effectively, reducing performance degradation caused by heat accumulation. In addition, BGA packaging can evenly distribute heat, reducing the risk of local overheating.

[0030] 3. Signal integrity and reliability improvement: Since the ceramic substrate itself has a low dielectric constant and loss factor, its signal transmission performance is better than that of traditional PCB materials; with the help of BGA packaging, the electrical performance is further optimized. By reducing signal crosstalk and improving signal integrity, the performance of communication modules is significantly improved.

Claims

1. A SIP package ceramic substrate for a communication module, characterized in that, It includes a multi-layer ceramic substrate and a microstrip line disposed within the multi-layer ceramic substrate; The multi-layer ceramic substrate is provided with a TOP surface and a BTM surface, and the multi-layer ceramic substrate includes a TOP layer, an intermediate layer, and a BTM layer; The microstrip line forms a path within the multi-layer ceramic substrate to connect the Pad on the TOP surface and the BGA solder joints on the BTM surface; The TOP layer of the multi-layer ceramic substrate is provided with chip I / O lines, a matching circuit, a grounding line, micro blind vias, and pads; The intermediate layer of the multi-layer ceramic substrate is printed with surface microstrip lines and buried vias, and through the intermediate layer microstrip lines and buried vias, it corresponds to the BGA solder joints on the BTM layer of the multi-layer ceramic substrate; At the bottom of the BTM layer of the multi-layer ceramic substrate, there are 112 BGA solder joints, which realize the connection of the I / O interface and grounding of the chip on the TOP layer to the circuit, and realize the high-density packaging of the chip; 2. The SIP encapsulated ceramic substrate for a communication module according to claim 1, wherein The multi-layer ceramic substrate has a total of 6 layers, where the first layer is printed with the TOP surface on the surface, the second to sixth layers are printed with surface layers, and the sixth layer is printed with the BTM surface on the reverse side; and the second to sixth layers are provided with micro blind vias, buried vias, and wiring circuits that are electrically connected to the TOP layer and the BTM layer; 3. The SIP package ceramic substrate for a communication module according to claim 1, characterized in that, The TOP layer and the BTM layer of the multi-layer ceramic substrate are provided with micro blind vias, and buried vias are provided in the intermediate layer; Among them, the micro blind via Blind Via connects the ceramic surface layer circuit and the inner layer circuit; the buried via Buried Via is located inside the ceramic substrate and is used to connect the circuits between the inner layers of the ceramic substrate.

4. A preparation method of a SIP packaged ceramic substrate for a communication module, characterized in that, It includes the following steps: Step 1) Mix alumina powder, manganese dioxide, chromium sesquioxide, and silicon dioxide and ball-mill them until the D50 particle size reaches less than 1.5 microns, and then dry them at 100 °C to prepare a ceramic powder; Step 2) Add polyvinyl butyral, fish oil, polyethylene glycol, xylene, and n-butanol as solvents to the ceramic powder in the above step 1), and ball-mill and mix the slurry for 24 hours to prepare a ceramic slurry; Step 3) Degas the ceramic slurry obtained in the above step 2) in a vacuum degassing device for 2 - 4 hours. According to the required thickness of the tape-cast green ceramic, control the degassed viscosity within ; Step 4) Use the HTCC ceramic slurry in the above step 3) to prepare a green ceramic film tape with the required thickness through a tape casting equipment; Step 5) Cut the green ceramic film tape in the above step 4) into green ceramic film sheets with the required size; Step 6) Punch the green ceramic film sheets according to the circuit design and process requirements, including positioning holes, micro blind vias, and buried vias; Step 7) According to the design requirements of the high-density lines and high-density BGA solder joints of the SIP module, adopt high-density wiring, and use a screen printing process to fill the micro blind vias and buried vias and print the circuit on the green ceramic sheet in step 6) with tungsten paste to realize the high-density multi-layer circuit printing of the TOP layer, the intermediate layer, and the BTM layer; Step 8) The corresponding relationship between the TOP layer lines and pads and the BTM layer pads: The TOP layer lines and pads are connected to the high-density lines in the intermediate layer through micro blind vias, the high-density lines in the intermediate layer are connected through buried vias, and the BGA solder joints on the BTM layer are connected to the intermediate layer lines through micro blind vias, so that the welding lines and pads of the semiconductor chip on the TOP layer and the BGA solder joints on the BTM layer form a one-to-one correspondence; Step 9) Set input, output signal pads and grounding pads on the BTM layer; Step 10) Stacking, isostatic pressing, and cutting according to the designed structure of the ceramic substrate; Step 11) Debinding and co-firing the single ceramic substrates cut in Step 10) in a reducing atmosphere furnace at 1500°C - 1600°C to obtain SIP package ceramic substrates.

5. The preparation method of a SIP package ceramic substrate for a communication module according to claim 4, characterized in that, The mass percentages of the aluminum oxide powder, manganese dioxide, chromium sesquioxide, silicon dioxide, polyvinyl butyral, fish oil, and polyethylene glycol added in Steps 1) and 2) are as follows: Aluminum oxide Al2O3: 45% - 60%; Manganese dioxide MnO2: 0.5% - 3%; Chromium sesquioxide Cr2O3: 0.5% - 2%; Silicon dioxide SiO2: 1% - 8%; Xylene: as a solvent, 10% - 25%; n-Butanol: as a solvent, 10% - 25%; Polyvinyl butyral PVB: as an adhesive, 3% - 10%; Fish oil: as a dispersant, 0.3% - 2%; Polyethylene glycol PEG: as a plasticizer, 1% - 5%.

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