Multi-channel data acquisition recording storage system and method

Abstract

The invention discloses a multichannel data acquisition recording storage system and method.The system comprises a plurality of recording daughter cards, a recording storage unit and an upper computer, and each recording daughter card receives sampling messages obtained through multichannel data acquisition; the daughter card FPGA analyzes the sampling message, generates a fault wave recording message, writes the fault wave recording message into a daughter card DDR sending cache module, and sends the fault wave recording message to a wave recording storage unit; a wave recording storage unit FPGA writes the fault wave recording message into a DDR wave recording storage module according to a preset read-write mechanism, and a CPU control module reads and writes fault wave recording data in the fault wave recording message within a preset time as a fault wave recording file into an SSD hard disk storage module; and the upper computer reads the fault recording file in the SSD storage module, analyzes the fault recording file and displays a recording waveform corresponding to the fault recording file. According to the invention, the expenditure of CPU processor software is obviously reduced, and high-speed recording of fault data is realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of power systems, and particularly relates to a multi-channel data acquisition, recording and storage system and method. Background Art

[0002] In a power system, in order to diagnose faults and analyze accidents, a fault recording device is used to record the changes of key electrical parameters during the operation of the system. These parameters include, but are not limited to, voltage, current, frequency, power, etc., especially the changes during a fault or abnormal condition in the power system. With the development of the power system, applications such as digital substation protection and measurement, high-voltage DC control protection, transformer active protection, and new energy systems have put forward higher requirements for distributed multi-channel data acquisition and high-speed recording. High-speed recording can capture the changes of electrical signals during the fault process of the power system in real time and with high precision, providing detailed information about the fault moment, and providing a scientific basis for fault diagnosis and accident analysis.

[0003] Traditional fault recording devices mainly use two methods to achieve data recording and processing: one is based on a single main control processor architecture, and combines multi-processor parallel processing technology to achieve functions such as real-time data acquisition, synchronous signal processing, and network communication. The other is to adopt a distributed structure design, that is, the data collected by the acquisition unit is transmitted to the main processor module via a high-speed communication bus for further analysis, processing, storage, display printing, and data sharing, so as to complete the entire fault recording process. Traditional fault recording devices have several limitations and are difficult to meet the requirements of high-speed recording in modern power systems.

[0004] In order to adapt to the rapid development of the power system, high-speed recording devices must have high-performance hardware and rich background software, as well as a stable storage function, strong network capabilities, and communication capabilities. However, this transformation also brings new challenges. For example, although high-speed recording can provide more detailed data records, this increases the complexity and cost of the system, and also puts forward higher requirements for data processing and storage. In addition, high-speed recording devices need to solve the problems of data compression and scalability to ensure that the collected data can be effectively exported for use by other systems or devices. Moreover, how to ensure the durability of the hard disk and the security of the data, and avoid the physical damage and data loss risks caused by frequent reading and writing, are also new problems faced by high-speed recording devices.

[0005] Prior art document 1 (CN117271160A) discloses a data recording method and device based on a multi-core processor, in which a non-real-time system and a real-time system are respectively run on different cores of the multi-core processor, and the two systems use shared memory as a medium.

[0006] The prior art 2 (CN105548777A) discloses a fault recorder device based on dual-CPU parallel recording and storage, which includes an analog signal conditioning module, a digital quantity isolation module, an AD conversion module, a timing module, an FPGA module, a power supply module, and two CPU modules, and realizes the synchronous operation of two CPU modules with completely the same hardware structure and independent of each other in the same fault recorder device with the same operating system and application program, so as to improve the reliability of the device operation and storage.

[0007] However, both of the above two methods use multi-chip or multi-core processors as the core controllers and implement the fault recording function in the form of software programs. Their deficiencies are as follows: First, since the traditional recorder device uses ordinary RAM storage to achieve data communication and interaction among modules, when a large amount of data is transmitted, the arbitration mechanism and time-division multiplexing will reduce the data transmission efficiency and processing speed. Second, as the core of the traditional recorder device, the main control processor will have a sharp increase in software overhead when the amount of fault data suddenly becomes large, which may cause the loss of recorded data that has not been stored in the hard disk. In addition, the system program and the recorded data share the data bus and the storage medium, and frequent reading and writing are likely to cause physical damage to the memory and the device to crash. Finally, the processor performance of the existing recorder device is low, the processing speed is slow, and the storage capacity is limited, which cannot meet the higher requirements put forward by the large-capacity power system for the fault recorder device. Summary of the Invention

[0008] To solve the deficiencies existing in the prior art, the present invention provides a multi-channel data acquisition recording and storage system and method, which completes fault recording based on the heterogeneous cooperative processing method of FPGA (Field-Programmable Gate Array) and CPU processors. Among them, the FPGA completes functions such as acquisition message parsing, fault start detection, fault data extraction, fault message construction, fault message transmission, and fault data caching; the CPU completes functions such as timing writing of the recorded file to the SSD hard disk and construction of the recorded file index list. Most of the data extraction and transmission links in fault recording are completed by the FPGA, significantly reducing the software overhead of the CPU processor, realizing high-speed recording of fault data, and ensuring no data loss.

[0009] The present invention adopts the following technical solutions.

[0010] The first aspect of the present invention provides a multi-channel data acquisition and fault recording storage system, which includes multiple fault recording sub-cards, a fault recording storage unit, and a host computer. Each fault recording sub-card includes a sub-card FPGA and a sub-card DDR transmission buffer module. Each fault recording sub-card receives sampling messages obtained from multi-channel data acquisition. The sub-card FPGA analyzes the sampling messages and generates fault recording messages. The sub-card FPGA writes the fault recording messages into the sub-card DDR transmission buffer module and sends the fault recording messages in the sub-card DDR transmission buffer module to the fault recording storage unit. The fault recording storage unit includes a fault recording storage unit FPGA, a CPU control module, a DDR fault recording storage module, and an SSD hard disk storage module. The fault recording storage unit receives the fault recording messages sent by the fault recording sub-cards. The fault recording storage unit FPGA writes the fault recording messages into the corresponding channel's fault recording storage subspace in the DDR fault recording storage module according to a preset reading and writing mechanism. The CPU control module polls the fault recording storage subspace of each channel according to a timing interrupt mechanism, reads the fault recording data in the fault recording messages within a preset time, and writes it as a fault recording file into the SSD hard disk storage module. The host computer is connected to the fault recording storage unit and is used to read the fault recording files in the SSD hard disk storage module, parse the fault recording files, and display the fault recording waveforms corresponding to the fault recording files.

[0011] Optionally, the fault recording sub-card further includes a DMA transmission module, and the fault recording storage unit further includes a corresponding DMA reception module. The DMA transmission module is used to access the sub-card DDR transmission buffer module and send the fault recording messages in the sub-card DDR transmission buffer module to the DMA reception module. The DMA reception module receives the fault recording messages and writes them into the corresponding channel's fault recording storage subspace in the DDR fault recording storage module according to the channels.

[0012] Optionally, the number of channels for each fault recording sub-card to receive sampling messages is 8. Each fault recording sub-card includes 1 Ethernet transmission interface, and sends the fault recording messages of 8 channels to the fault recording storage unit through the Ethernet transmission interface.

[0013] Optionally, the fault recording storage unit includes 8 Ethernet reception interfaces and simultaneously receives the fault recording messages of 8 fault recording sub-cards.

[0014] Optionally, the fault recording storage unit FPGA writes the fault recording messages into the DDR fault recording storage module according to a preset reading and writing mechanism, including:

[0015] Query the current receive read pointer and receive write pointer of the fault recording storage unit FPGA;

[0016] If the current receive write pointer is not equal to the current receive read pointer minus 1, write the fault recording messages into the corresponding channel's fault recording storage subspace in the DDR fault recording storage module, and write a preset number of bytes each time;

[0017] After the fault recording message is written, write the data block descriptor, mark this fault recording message as a newly written message, and increment the receive write pointer by 1;

[0018] If the current receive write pointer is equal to the current receive read pointer minus 1, then do not write the fault recording message. The FPGA of the recording storage unit generates a recording backpressure suppression message and sends it to the recording sub-card;

[0019] When the recording sub-card receives the backpressure suppression message, stop sending the fault recording message to the recording storage unit.

[0020] Optionally, the CPU control module polls the recording storage subspace of each channel according to the timer interrupt mechanism, reads and writes the fault recording data in the fault recording messages within a preset time as a fault recording file to the SSD hard disk storage module, including:

[0021] When the FPGA of the recording storage unit receives a fault recording message, it generates an interrupt every preset time. The CPU control module responds to the interrupt and traverses the receive write pointer and receive read pointer of the recording storage subspace of all channels to determine the number of valid messages of the recording data;

[0022] Obtain the number of valid messages of the recording data of all channels of each receive interface of the recording storage unit;

[0023] Write the channel number read this time to the SSD storage module. Read multiple fault recording messages in the valid messages according to the channel. When the read fault recording messages meet the maximum number of recording entries for writing to the SSD hard disk storage module or the read time exceeds the preset time window, the CPU control module writes the read fault recording messages to the SSD hard disk storage module until the fault recording messages with the number of valid messages of all channels of this receive interface are written to the SSD hard disk storage module.

[0024] Optionally, the fault recording file name is named according to the corresponding channel number and the fault occurrence time, and a file index table is established with the file name.

[0025] The second aspect of the present invention provides a multi-channel data acquisition and recording storage method, which is implemented based on the heterogeneous cooperative architecture of FPGA and CPU processors. The method includes:

[0026] Use multiple recording sub-cards to receive the sampling messages obtained by multi-channel data acquisition. The FPGA of the sub-card parses the sampling messages to obtain sampling data and generates fault recording messages;

[0027] The FPGA of the recording storage unit writes the fault recording messages into the recording storage subspace of the corresponding channel in the DDR recording storage module according to the preset reading and writing mechanism;

[0028] The CPU control module responds to the timing interrupt, generates a fault recording file from the fault recording message in the DDR recording storage module, and writes it into the SSD hardware storage module;

[0029] The host computer reads the fault recording file in the SSD hardware storage module, parses the fault recording file, and displays the recording waveform corresponding to the fault recording file.

[0030] Optionally, the daughter card FPGA parses the sampling message to obtain sampling data and generates a fault recording message, including:

[0031] The daughter card FPGA parses the sampling message to obtain sampling data, preprocesses the sampling data, and writes the preprocessed sampling data into the local circular buffer;

[0032] The daughter card FPGA determines whether the fault overlimit starts and ends. When the fault overlimit starts, it captures the write address value of the local circular buffer as the reference point of the recording overlimit, calculates the start address and end address of the fault recording, and obtains the sampling data before, during, and after the fault overlimit based on the start address and end address as the fault recording data;

[0033] The daughter card FPGA calculates the start sampling time of the fault recording, and forms a fault recording message with the sampling channel number corresponding to the fault recording data, the start sampling time of the fault recording, the number of recording points, the recording duration, the recording sampling value conversion coefficient, and the fault recording data.

[0034] The third aspect of the present invention provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the computer program is loaded into the processor, it implements the above multi-channel data acquisition and recording storage method.

[0035] The fourth aspect of the present invention provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the above multi-channel data acquisition and recording storage method.

[0036] Compared with the prior art, the beneficial effects of the present invention at least include:

[0037] The heterogeneous cooperative processing method based on an FPGA plus a CPU processor in the present invention is used to complete the high-speed recording of fault data. Among them, the FPGA completes functions such as acquisition message parsing, fault start detection, fault data extraction, fault message construction, fault message transmission, and fault data caching; the CPU completes functions such as regularly writing the recorded wave file to the SSD hard disk and constructing the index list of the recorded wave file. Most of the data extraction and transmission in fault recording are completed by the FPGA, significantly reducing the software overhead of the CPU processor, achieving high-speed recording of fault data, and ensuring no data loss. The present invention designs a DDR recording storage module and an SSD hardware storage module, improving the integrity and accuracy of fault data recording and further increasing the recording storage speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings. Among them:

[0039] Figure 1 is a functional schematic diagram of a recording storage system for multi-channel data acquisition provided by an embodiment of the present invention;

[0040] Figure 2 is a schematic flow diagram of writing to the SSD provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0041] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will clearly and completely describe the technical solutions of the present invention in conjunction with the drawings in the embodiments of the present invention. The embodiments described in this application are only a part of the embodiments of the present invention, rather than all embodiments. Based on the spirit of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0042] To solve the above technical problems, in combination with Figure 1 as shown, Embodiment 1 of the present invention provides a multi-channel data acquisition high-speed recording storage system, and the system includes a plurality of recording sub-cards, a recording storage unit, and a host computer, where:

[0043] Each recording sub-card includes a sub-card FPGA and a sub-card DDR transmission buffer module;

[0044] Each recording sub - card receives the sampled messages obtained from multi - channel data acquisition. The FPGA in the sub - card parses the sampled messages and generates fault recording messages. The FPGA in the sub - card writes the fault recording messages into the DDR transmission buffer module in the sub - card and sends the fault recording messages in the DDR transmission buffer module of the sub - card to the recording storage unit.

[0045] The recording storage unit includes an FPGA in the recording storage unit, a CPU control module, a DDR (Double Data Rate Synchronous Dynamic Random Access Memory) recording storage module, and an SSD (Solid State Drive) hard disk storage module.

[0046] The recording storage unit receives the fault recording messages sent by the recording sub - card. The FPGA in the recording storage unit writes the fault recording messages into the corresponding channel's recording storage subspace in the DDR recording storage module according to a preset read - write mechanism. The CPU control module polls the recording storage subspace of each channel according to a timing interrupt mechanism, reads the fault recording data in the fault recording messages within a preset time, and writes it into the SSD hard disk storage module as a fault recording file.

[0047] The host computer, which is connected to the recording storage unit, is used to read the fault recording file in the SSD hard disk storage module, parse the fault recording file, and display the recording waveform corresponding to the fault recording file.

[0048] In this embodiment, a DDR recording storage module and an SSD hardware storage module are designed. The double - layer storage mechanism ensures the integrity and accuracy of fault recording on the one hand, and improves the speed of recording storage and host computer display on the other hand.

[0049] Optionally, the recording sub - card further includes a DMA transmission module, and the recording storage unit further includes a corresponding DMA reception module. The DMA transmission module is used to access the DDR transmission buffer module in the sub - card and send the fault recording messages in the DDR transmission buffer module of the sub - card to the DMA reception module. The DMA reception module receives the fault recording messages and writes them into the corresponding channel's recording storage subspace in the DDR recording storage module according to the channel.

[0050] In this way, through the DMA method, there is no need for the CPU to process data byte by byte, reducing the CPU's participation time in the data transmission process, and thus significantly improving the data transmission speed. Moreover, when the DMA transmission module and the DMA reception module transmit data, they can improve the integrity and accuracy of the data.

[0051] Optionally, the number of channels for each waveform recording sub - card to receive sampling messages is 8. Each waveform recording sub - card includes 1 Ethernet sending interface, and sends the fault waveform recording messages of 8 channels to the waveform recording storage unit through the Ethernet sending interface.

[0052] Optionally, the waveform recording storage unit includes 8 Ethernet receiving interfaces, and simultaneously receives the fault waveform recording messages of 8 waveform recording sub - cards.

[0053] In this embodiment, the system can receive at most 64 fault waveform recording messages from the front - end sampling channels, increasing the number of fault waveform recording messages for waveform recording sampling, and thus improving the waveform recording speed.

[0054] Optionally, the FPGA of the waveform recording storage unit writes the fault waveform recording messages into the DDR waveform recording storage module according to a preset read - write mechanism, including:

[0055] Query the current receive read pointer and receive write pointer of the FPGA of the waveform recording storage unit;

[0056] If the current receive write pointer is not equal to the current receive read pointer minus 1, write the fault waveform recording message into the waveform recording storage subspace corresponding to the channel in the DDR waveform recording storage module, writing a preset number of bytes each time;

[0057] After the fault waveform recording message is written, write the data block descriptor, mark this fault waveform recording message as a newly written message, and increment the receive write pointer by 1;

[0058] If the current receive write pointer is equal to the current receive read pointer minus 1, then do not write the fault waveform recording message. The FPGA of the waveform recording storage unit generates a waveform recording back - pressure suppression message and sends it to the waveform recording sub - card;

[0059] When the waveform recording sub - card receives the back - pressure suppression message, it stops sending the fault waveform recording message to the waveform recording storage unit.

[0060] In this way, not only is the DMA interaction method simplified, and the waveform recording storage speed is further improved with a faster DMA interaction method; moreover, the back - pressure suppression message mechanism can prevent data overflow, effectively protecting the waveform recording storage system from being affected by overload, and effectively improving the performance and reliability of the waveform recording storage system.

[0061] Optionally, the CPU control module polls the waveform recording storage subspace of each channel according to a timing interrupt mechanism, reads and writes the fault waveform recording data in the fault waveform recording messages within a preset time as a fault waveform recording file into the SSD hard disk storage module, including:

[0062] When the FPGA of the waveform recording storage unit receives a fault waveform recording message, an interrupt is generated every preset time. The CPU control module responds to the interrupt, traverses the receive write pointer and receive read pointer corresponding to the waveform recording storage subspace of all channels, and determines the number of valid messages of the waveform recording data;

[0063] Obtain the number of valid packets of the recorded wave data of all channels of each receiving interface of the recorded wave storage unit;

[0064] Write the channel number read this time to the SSD storage module. Read multiple fault recorded wave packets according to the channel in the valid packets. When the read fault recorded wave packets meet the maximum number of recorded wave entries for writing to the SSD hard disk storage module or the read time exceeds the preset time window, the CPU control module writes the read fault recorded wave packets to the SSD hard disk storage module until the fault recorded wave packets of the number of valid packets of all channels of this receiving interface are written to the SSD hard disk storage module.

[0065] Optionally, the name of the fault recorded wave file is named according to the corresponding channel number and the fault occurrence time, and a file index table is established with the file name. In this way, by establishing the file index table, it helps the upper computer to directly read the SSD according to the recorded wave file index, obtain the corresponding fault recorded wave file, thereby improving the speed of recorded wave storage and display.

[0066] Embodiment 2 of the present invention provides a multi-channel data acquisition and recorded wave storage method. This method uses FPGA to implement functions such as acquisition packet parsing, fault start detection, fault data extraction, fault packet construction, fault packet transmission, and fault data caching. The CPU processor is only responsible for writing the final recorded wave file to the SSD. Specifically, it includes the following steps:

[0067] Step 1, use multiple recorded wave daughter cards to receive the sampled packets obtained by multi-channel data acquisition. The FPGA of the daughter card parses the sampled packets to obtain sampled data and generates fault recorded wave packets. Step 1 specifically includes:

[0068] Step 1.1, use multiple recorded wave daughter cards to receive the sampled packets periodically sent by the acquisition unit. Each recorded wave daughter card receives multiple Ethernet sampled packets. The FPGA of the daughter card parses the sampled packets to obtain sampled data, records the arrival time of the sampled packets, preprocesses the sampled data, and writes the preprocessed sampled data into the local circular buffer.

[0069] Specifically, the FPGA parses the sampled packets to obtain sampled data, including: the sampled packets include status monitoring quantities such as address, type, sampling unit temperature, reference voltage, etc., and the sampled data code value.

[0070] Specifically, the preprocessing of the sampled data code value includes: removing sampling abnormal points, calculating the zero drift of the sampled value, and correcting the zero drift of the sampled value, etc.

[0071] Step 1.2, when the FPGA of the daughter card detects that the sampled data is greater than the fault overlimit threshold value, it is determined that the fault starts. When it detects that the sampled data is less than the fault return threshold value, it is determined that the fault ends.

[0072] Step 1.3, write 1 sampled value to each address in the circular buffer. When a fault overlimit occurs in the sampled data, the sub-card FPGA captures the write address value of the circular buffer as the reference point for the wave recording overlimit moment; based on the address value corresponding to the wave recording overlimit moment, subtract the number of points of the wave recording before the fault as the starting address of the fault wave recording; based on the address value corresponding to the wave return moment, add the number of points of the wave recording after the fault as the ending address of the fault wave recording.

[0073] Specifically, the maximum number of points for fault wave recording is 10,000, and the capacity of the circular buffer can cover the sampled value data volume of one wave recording.

[0074] Step 1.4, the sub-card FPGA reads the sampled data between the starting address and the ending address of the fault wave recording in the circular buffer to obtain the sampled value data before, during, and after the fault as the fault wave recording data;

[0075] Step 1.5, the sub-card FPGA calculates and obtains the occurrence moment of the fault sampled value by backtracking according to the 4 parameters of the sampling message sending interval, the arrival moment of the sampling message, the sequence number of the fault overlimit sampled value in the message, and the sampling data transmission delay.

[0076] Specifically, the occurrence moment of the fault sampled value = the arrival moment of the sampling message - the sampling message sending interval - the sampling data transmission delay + the sequence number of the current sampling point × the sampling period.

[0077] Step 1.6, the sub-card FPGA packs the sampling channel number corresponding to the fault wave recording data, the fault occurrence time, the number of wave recording points, the wave recording duration, the wave recording sampled value conversion coefficient, and all fault data into a fault wave recording message. The sampled value conversion coefficient is used to convert the sampled value code value into an analog quantity value.

[0078] Step 1.7, the size of each fault wave recording message is set to 8KB. If the length of the wave recording data is greater than 8K bytes, packetization processing is performed, and the long-time fault data is separated and framed into multiple 8K-byte fault wave recording messages. The message contains a field for the number of wave recording sampled value points, indicating the number of wave recording sampled value points included in this frame of wave recording message.

[0079] Step 1.8, in the sub-card DDR send buffer module, create send buffer sub-spaces for wave recording messages of multiple channels. The data format of each send buffer sub-space for wave recording messages is 1024 8K-byte spaces, and set up a read-write pointer mechanism and a TBD (Transmit Data Block Descriptor) linked list mechanism that implement the DMA (Direct Memory Access) function; the TBD data block descriptor mainly contains two pieces of information: the length of the transmitted message in bytes and the valid set bit of the transmitted message.

[0080] Step 1.9, the multi-channel fault recording messages generated in Step 1.6 are directly written by the sub-card FPGA polling into the sub-card DDR transmission buffer module.

[0081] Specific steps: The sub-card FPGA first queries the current read pointer and write pointer. If the write pointer is not equal to the value of the read pointer minus 1 (P tw !=(P tr -1)), then the recording message is normally written into the sub-card DDR transmission buffer module. Each time, an 8K-byte space is written. After the message is written, the current TBD is written to the corresponding position in the TBD linked list, and the write pointer is incremented by 1; if the write pointer is equal to the value of the read pointer minus 1 (P tw =(P tr -1)), that is, the write pointer is about to catch up with the read pointer, then the recording message is no longer written.

[0082] This embodiment simplifies the DMA interaction method and further improves the speed of recording storage with a faster DMA interaction method.

[0083] Step 1.10, the sub-card FPGA alternately queries the write pointer and read pointer of each recording channel. If the read pointer is not equal to the write pointer (P tr ! = P tw ), then the TBD data block descriptor of the corresponding channel is read, and according to the transmission data length, the corresponding recording message is read from the transmission buffer subspace and written into the transmission buffer of the Gigabit Ethernet link layer and then the transmission is started; if the read pointer is equal to the write pointer (P tr =P tw ), it means that the current transmission buffer subspace has been read empty and there is no new recording message, so there is no need to send.

[0084] Step 1.11, each recording sub-card can receive up to 8 channels of front-end sampling data. In order to collect the recording data of multiple recording sub-cards into 1 recording storage unit, each recording sub-card is only equipped with 1 Gigabit Ethernet interface, and the fault recording messages of the front-end 8 sampling channels are collected and sent through this 1 Gigabit Ethernet interface.

[0085] Step 1.12, the Gigabit Ethernet sends the collected recording messages to the recording storage unit through the backplane bus. At the same time, the Gigabit Ethernet also receives the backpressure control message from the recording storage unit. If the recording storage unit sends a backpressure control message to stop recording, then the Gigabit Ethernet stops sending the recording message; if the recording storage unit sends a backpressure release message to resume recording, then the Gigabit Ethernet continues to send the recording message.

[0086] Step 1.13: The waveform recording storage unit has 8 Gigabit Ethernet ports and can receive waveform recording messages from 8 waveform recording sub-cards simultaneously. Therefore, it can receive up to 64 channels of fault waveform recording messages from the front-end sampling channels at most. After receiving a waveform recording message on each Gigabit Ethernet port, the FPGA of the waveform recording storage unit first parses the field information in the message header to obtain the front-end sampling channel number corresponding to the waveform recording message.

[0087] Step 2: The FPGA of the waveform recording storage unit writes the fault waveform recording messages into the corresponding channel's waveform recording storage subspace in the DDR waveform recording storage module according to the preset read / write mechanism.

[0088] Step 3: The CPU control module, in response to the periodic interrupt, generates a fault waveform recording file from the fault waveform recording messages in the DDR waveform recording storage module and writes it into the SSD hard disk storage module.

[0089] Specifically, the storage part of the waveform recording storage unit includes a DDR waveform recording storage module and an SSD hard disk storage module. The DDR waveform recording storage module divides 64 waveform recording storage subspaces according to physical channels, and the size of each waveform recording storage subspace is 4096 * 8K bytes.

[0090] In Step 2, the waveform recording messages are written into the waveform recording storage subspace according to the front-end sampling channel numbers parsed in Step 1.13. Each waveform recording storage subspace is also set with read / write pointers and an RBD (Received Data Descriptor) linked list mechanism. The waveform recording messages are directly written into the waveform recording storage subspace of the DDR waveform recording storage module by the FPGA of the waveform recording storage unit.

[0091] Specific steps: First, query the current receive read pointer P rr and receive write pointer P rw of the waveform recording storage unit FPGA. If the write pointer is not equal to the read pointer minus 1 (P rw != (P rr - 1)), the waveform recording message is written into the DDR waveform recording storage module. Each time, an 8K-byte space is written. After the message is written, a data block descriptor is written to mark this message data as a newly written message, and the write pointer is incremented by 1. If the write pointer is equal to the read pointer minus 1 (P rw = (P rr - 1)), that is, the write pointer is about to catch up with the read pointer, then the waveform recording message is no longer written, and a waveform recording backpressure suppression message is generated.

[0092] In Step 3, the periodic interrupt is generated by the FPGA of the waveform recording storage unit every 100 milliseconds, which can improve the data writing efficiency of the SSD. The CPU control module responds to this interrupt, polls the waveform recording storage subspaces of each channel, reads the accumulated fault waveform recording data during these 100 milliseconds, and writes this section of fault waveform recording data into the SSD hard disk storage module as a single file. This can ensure that the data is written into the storage medium efficiently and completely.

[0093] Specifically, in combination with Figure 2 as shown, the process of writing the fault recording data into the SSD hard disk storage module is as follows:

[0094] S1. When the FPGA of the recording storage unit receives the fault recording, an interrupt is generated every 100 ms. The CPU control module responds to the interrupt and traverses the receive read pointer and receive write pointer (i.e., the transceiver pointer) of all channels of the Ethernet receive interface to determine the number of valid message packets of the recording data. The difference between the transceiver pointers is the number of valid message packets;

[0095] S2. Obtain the number of valid message packets of the recording data for all channels of this network interface;

[0096] S3. Write the channel number read this time;

[0097] S4. Read multiple recording message packets according to the channel number. When the recording message packets meet the maximum number of entries or the reading time exceeds the time window, the processor writes the recording data to the SSD hard disk storage module;

[0098] S5. Determine whether all channels of this network interface have been processed. If not, repeat S3 to S5 until the recording data of all channels of this network interface is written to the SSD hard disk storage module.

[0099] Step 3: The host computer reads the fault recording file in the SSD hard disk storage module, parses the fault recording file, and displays the recording waveform corresponding to the fault recording file.

[0100] Optionally, the fault recording file name is named according to the corresponding channel number and the fault occurrence time, the file suffix is ".dat", and a file index table is established with the file name to facilitate query by the host computer software.

[0101] Specifically, the fault recording file is in the format shown in Table 1.

[0102] Table 1

[0103]

[0104] It should be noted that the offset address here is relative to the file format. The file can be stored in the SSD or transmitted to the host computer, not necessarily only in the SSD.

[0105] Specifically, the host computer recording display software directly reads the SSD according to the fault recording file index, obtains the corresponding fault recording file, and displays the waveform according to the information such as the channel number, fault occurrence time, number of recording points, recording duration, unit coefficient, etc. described in the file.

[0106] Embodiment 3 of the present invention provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the computer program is loaded into the processor, the method described in Embodiment 2 is implemented.

[0107] Embodiment 4 of the present invention provides a computer-readable storage medium storing a computer program, which when executed by a processor implements the method described in Embodiment 2.

[0108] Compared with the prior art, the beneficial effects of the present invention at least include:

[0109] The present invention completes the high-speed fault data recording based on the heterogeneous cooperative processing method of FPGA plus CPU processors. Among them, FPGA completes functions such as acquisition message parsing, fault start detection, fault data extraction, fault message construction, fault message transmission, and fault data caching; CPU completes functions such as timing writing of the recording file to the SSD hard disk and construction of the recording file index list. Most of the data extraction and transmission in fault recording are completed by FPGA, significantly reducing the software overhead of the CPU processor, realizing the high-speed fault data recording, and ensuring no data loss. The present invention designs a DDR recording storage module and an SSD hard disk storage module, improving the integrity and accuracy of fault data recording and further increasing the recording storage speed.

[0110] It should be understood that the sequence numbers of the steps in the above embodiments do not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

[0111] The present disclosure may be a system, a method, and / or a computer program product. The computer program product may include a computer-readable storage medium having thereon computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0112] A computer-readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example—but not limited to—an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanically encoded device such as a punch card or raised structures in grooves having instructions stored thereon, and any suitable combination of the foregoing. The computer-readable storage medium as used herein is not construed as being a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated through a waveguide or other transmission medium (e.g., an optical pulse through an optical fiber cable), or an electrical signal transmitted through a wire.

[0113] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to respective computing / processing devices, or can be downloaded to an external computer or an external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include a copper transmission cable, an optical fiber transmission, a wireless transmission, a router, a firewall, a switch, a gateway computer, and / or an edge server. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in each computing / processing device.

[0114] Computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state-setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, etc., and conventional procedural programming languages such as the "C" language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider). In some embodiments, by using the state information of the computer-readable program instructions to customize an electronic circuit, such as a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit can execute the computer-readable program instructions to implement various aspects of the present disclosure.

[0115] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: the specific implementation manners of the present invention can still be modified or equivalently replaced, and any modification or equivalent replacement that does not depart from the spirit and scope of the present invention shall be covered by the protection scope of the claims of the present invention.

Claims

1. A multi-channel data acquisition and recording storage system, comprising a plurality of recording sub-cards, a recording storage unit and a host computer, characterized in that: Each wave recording sub-card includes a sub-card FPGA and a sub-card DDR sending buffer module; Each wave recording sub-card receives the sampling message obtained by multi-channel data acquisition, and the sub-card FPGA analyzes the sampling message and generates a fault wave recording message; the sub-card FPGA writes the fault wave recording message into the sub-card DDR sending buffer module, and sends the fault wave recording message in the sub-card DDR sending buffer module to the wave recording storage unit; The recording storage unit includes a recording storage unit FPGA, a CPU control module, a DDR recording storage module, and an SSD hard disk storage module; The recording storage unit receives the fault recording message sent by the recording subcard, and the recording storage unit FPGA writes the fault recording message into the recording storage subspace of the corresponding channel in the DDR recording storage module according to the preset reading and writing mechanism. The CPU control module polls the recording storage subspace of each channel according to the timing interrupt mechanism, reads and writes the fault recording data in the fault recording message within the preset time into the SSD hard disk storage module as a fault recording file; The host computer is connected to the recording storage unit, and is used for reading the fault recording file in the SSD hard disk storage module, analyzing the fault recording file, and displaying the recording waveform corresponding to the fault recording file.

2. The multi-channel data acquisition, recording and storage system according to claim 1, characterized in that: The wave recording sub-card also includes a DMA sending module, and the wave recording storage unit also includes a corresponding DMA receiving module. The DMA sending module is used to access the sub-card DDR sending buffer module, and send the fault wave recording message in the sub-card DDR sending buffer module to the DMA receiving module. The DMA receiving module receives the fault wave recording message and writes it into the wave recording storage sub-space of the corresponding channel in the DDR wave recording storage module according to the channel.

3. The multi-channel data acquisition, recording and storage system according to claim 1, characterized in that: The number of channels for each wave recording sub-card to receive sampling messages is 8. Each wave recording sub-card includes an Ethernet transmission interface, and sends the fault wave recording messages of 8 channels to the wave recording storage unit through the Ethernet transmission interface.

4. The multi-channel data acquisition, recording and storage system according to claim 3, characterized in that: The wave recording storage unit includes 8 Ethernet receiving interfaces, and receives the fault wave recording messages of 8 wave recording sub-cards at the same time.

5. The multi-channel data acquisition, recording and storage system according to claim 1, characterized in that: The recording storage unit FPGA writes the fault recording message into the DDR recording storage module according to the preset reading and writing mechanism, including: Query the current receiving read pointer and receiving write pointer of the wave recording storage unit FPGA; If the current receiving write pointer is not equal to the current receiving read pointer minus 1, the fault recording message is written into the recording storage subspace of the corresponding channel in the DDR recording storage module, and the preset number of bytes is written each time; After the fault recording message is written, the data block descriptor is written, and the fault recording message is marked as a newly written message, and the receiving write pointer is increased by 1; If the current receiving write pointer is equal to the current receiving read pointer minus 1, the fault recording message is not written, and the recording storage unit FPGA generates a recording back pressure suppression message and sends it to the recording subcard; When the wave recording sub-card receives the back pressure suppression message, it stops sending the fault wave recording message to the wave recording storage unit.

6. The multi-channel data acquisition, recording and storage system according to claim 1, characterized in that: The CPU control module polls the recording storage subspace of each channel according to the timing interrupt mechanism, reads the fault recording data in the fault recording message within the preset time and writes it into the SSD hard disk storage module as a fault recording file, including: When the recording storage unit FPGA receives the fault recording message, an interrupt is generated every preset time, and the CPU control module responds to the interrupt to traverse the receiving write pointer and receiving read pointer of the recording storage subspace of all channels to determine the number of valid messages of the recording data; Obtain the number of valid messages of the recording data of all channels of each receiving interface of the recording storage unit; The channel number for this reading is written into the SSD storage module, and multiple fault recording messages are read in the valid message according to the channel. When the fault recording message read meets the maximum number of recording entries written to the SSD hard disk storage module or the reading time exceeds the preset time window, the CPU control module writes the read fault recording message into the SSD hard disk storage module until the fault recording messages of the valid message quantity of all channels of the receiving interface are written into the SSD hard disk storage module.

7. The multi-channel data acquisition, recording and storage system according to claim 1, characterized in that: The fault recording file name is named according to the corresponding channel number and fault occurrence time, and a file index table is established based on the file name.

8. A multi-channel data acquisition, recording and storage method, applied to the multi-channel data acquisition, recording and storage system as claimed in any one of claims 1 to 7, characterized in that: The method is implemented based on a heterogeneous collaborative architecture of FPGA and CPU processors, and the method includes: Multiple wave recording daughter cards are used to receive sampling messages obtained by multi-channel data acquisition. The daughter card FPGA analyzes the sampling messages to obtain sampling data and generate fault wave recording messages. The recording storage unit FPGA writes the fault recording message into the recording storage subspace of the corresponding channel in the DDR recording storage module according to the preset reading and writing mechanism; The CPU control module responds to the timing interruption, generates a fault recording file from the fault recording message in the DDR recording storage module and writes it into the SSD hardware storage module; The host computer reads the fault recording file in the SSD hardware storage module, parses the fault recording file, and displays the recording waveform corresponding to the fault recording file.

9. The multi-channel data acquisition, recording and storage method according to claim 8, characterized in that: The daughter card FPGA parses the sampled message to obtain the sampled data and generates a fault recording message, including: The daughter card FPGA parses the sampling message to obtain the sampling data and pre-processes the sampling data, and writes the pre-processed sampling data into the local ring buffer; The daughter card FPGA determines whether the fault exceeds the limit and ends. When the fault exceeds the limit, it captures the write address value of the local ring buffer as the reference point of the recording exceeding the limit, and calculates the starting address and ending address of the fault recording. Based on the starting address and the ending address, the sampling data before, during and after the fault exceeds the limit are obtained as the fault recording data. The daughter card FPGA calculates the fault recording start sampling time, and composes a fault recording message with the sampling channel number, fault recording start sampling time, recording points, recording duration, recording sampling value conversion coefficient and fault recording data corresponding to the fault recording data.

10. An electronic device, comprising a processor and a storage medium; characterized in that: The storage medium is used to store instructions; The processor is configured to operate according to the instructions to execute the steps of the method according to claim 8 or 9.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the method according to claim 8 or 9 are implemented.

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