Storage unit and storage device

Abstract

The present invention provides a memory cell and memory device. The memory cell includes a first semiconductor structure, a low-resistance silicon alloy, and a second semiconductor structure stacked in sequence. The first and second semiconductor structures are arranged crosswise and have different majority carrier types. The low-resistance silicon alloy is arranged at the intersection of the first and second semiconductor structures, connecting them to form a PN junction structure. The memory cell can read and write data based on the off state and on state of the PN junction structure. The present invention is a unique device structure that can use the characteristics of the PN junction to achieve data reading and writing. It can also be miniaturized in parallel with the logic process, and the unit size can be as small as 4F. 2 This significantly increases the storage capacity of existing static memories. During device operation, the PN junction characteristics can be combined to control device read and write operations. Cell leakage control fully utilizes the reverse cutoff characteristics of the PN junction to further reduce power consumption.

Description

Technical Field

[0001] The present application relates to the field of memory devices, and in particular to a memory unit and a memory device. Background Art

[0002] Currently, static random access memory (SRAM) structures are all based on SRAM (Static Random Access Memory). Its basic storage unit is typically composed of multiple transistors, with 4T / 6T / 8T / 9T / 10T units being common. This configuration of multiple transistors results in a large basic storage unit size, low device density, and very limited SRAM capacity on a single chip. Furthermore, the SRAM manufacturing process is complex, with requirements for each transistor and strict performance constraints between transistors.

[0003] In data structures, L1 / L2 / L3 serve as caches, and their capacity determines the computing speed of the entire chip. SRAM capacity or bandwidth has already limited the high computing power requirements of current AI. Breaking through SRAM is one way to overcome the memory wall. However, as the feature size of SRAM memory cells continues to shrink, planar processes and manufacturing technologies have become challenging and costly, with no significant gains seen at the 14nm to 7nm node. There is a need to provide a new type of memory device that can effectively reduce the memory cell area and increase the density of memory devices.

[0004] It should be noted that the above introduction to the technical background is merely intended to provide a clear and complete description of the technical solutions of this application and facilitate understanding by those skilled in the art. Simply because these solutions are described in the background technology section of this application, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0005] An object of the present invention is to provide a memory device structure to achieve higher device density.

[0006] In order to solve the above problems, in a first aspect, a memory cell is provided, comprising a first semiconductor structure, a low-resistance silicon alloy, and a second semiconductor structure stacked in sequence;

[0007] The first semiconductor structure and the second semiconductor structure are arranged to intersect each other, and the majority carrier types of the first semiconductor structure and the second semiconductor structure are different;

[0008] The low-resistance silicon alloy is provided at the intersection of the first semiconductor structure and the second semiconductor structure, respectively connecting the first semiconductor structure and the second semiconductor structure to form a PN junction structure;

[0009] The memory cell is configured to represent different data values ​​according to an off state and an on state of the PN junction structure.

[0010] This invention utilizes the unidirectional conduction properties of the PN junction to store data by forming a low-resistance PN junction channel. This ingeniously exploits the PN junction's properties to achieve volatile storage. This fundamentally differs from existing NVM (non-volatile memory) devices, such as PCM (phase change memory), MRAM (magnetic random access memory), and RRAM (resistive random access memory), which utilize phase changes, magnetic moments, and conductive filaments to program the material at the intersection. The PN junction structure offers a low turn-on voltage and mature manufacturing processes. The design of this memory cell allows for device miniaturization in tandem with logic processing, and allows for multi-layer stacking, significantly increasing the storage capacity of existing static memories. The reverse-blocking properties of the PN junction can also be exploited to control leakage in unselected cells, further reducing power consumption. This results in a reduction in chip area, increased capacity, and, consequently, improved computing speed while reducing power consumption.

[0011] The memory cell is configured such that: when the PN junction structure is in the on state, it represents a "1" signal, and when the PN junction structure is in the off state, it represents a "0" signal. Different data values ​​are represented by the on and off states of the PN junction structure.

[0012] The first semiconductor structure is a P-type semiconductor structure, and the second semiconductor structure is an N-type semiconductor structure; alternatively, the first semiconductor structure is an N-type semiconductor structure, and the second semiconductor structure is a P-type semiconductor structure; the P-type semiconductor structure is made of P-type low-resistance silicon material, and the N-type semiconductor structure is made of N-type low-resistance silicon material. The device's fabrication process is highly compatible with existing logic processes, is mature, and offers low manufacturing costs.

[0013] On the other hand, the present invention also provides a memory device including a memory cell array and a peripheral circuit;

[0014] The memory cell array comprises a first semiconductor structure array, a low-resistance silicon alloy array, and a second semiconductor structure array stacked in sequence;

[0015] The first semiconductor structure array includes: a plurality of first semiconductor structures sequentially arranged along a first direction, each of the first semiconductor structures extending along a second direction;

[0016] The second semiconductor structure array includes: a plurality of second semiconductor structures sequentially arranged along the second direction, each of the second semiconductor structures extending along the first direction;

[0017] The low-resistance silicon alloy array includes: a plurality of low-resistance silicon alloys, each of the low-resistance silicon alloys is correspondingly arranged at an intersection of the first semiconductor structure and the second semiconductor structure;

[0018] The majority carrier types of the first semiconductor structure and the second semiconductor structure are different, and each of the low-resistance silicon alloys is respectively connected to the corresponding first semiconductor structure and the second semiconductor structure to form a PN junction structure;

[0019] The off state and the on state of the PN junction structure are used to represent different data values.

[0020] Arraying the basic storage units of the first aspect can realize the storage of large amounts of data, thereby saving chip area, increasing capacity, and thereby improving computing speed and reducing power consumption.

[0021] When the PN junction structure is in the on state, it is used to represent a "1" signal, and when the PN junction structure is in the off state, it is used to represent a "0" signal. Different data values ​​are represented by the on state and the off state of the PN junction structure.

[0022] The first semiconductor structure is a P-type semiconductor structure, and the second semiconductor structure is an N-type semiconductor structure; or, the first semiconductor structure is an N-type semiconductor structure, and the second semiconductor structure is a P-type semiconductor structure.

[0023] The N-type semiconductor structure is made of N-type low-resistance silicon material; the low-resistance silicon alloy is stacked on top of the N-type semiconductor structure; the P-type semiconductor structure is made of P-type low-resistance silicon material, and the P-type semiconductor structure is stacked on top of the N-type semiconductor structure and the low-resistance silicon alloy. The device's fabrication process is highly compatible with existing logic processes, is mature, and offers low manufacturing costs.

[0024] The system further includes a spacer medium, which is disposed between adjacent first semiconductor structures, between adjacent second semiconductor structures, and between the first semiconductor structure array and the second semiconductor structure array.

[0025] The peripheral circuit is used to operate the memory cell array; the peripheral circuit includes a word line driving circuit and a bit line driving circuit, which are used to drive any memory cell in the memory cell array to write data; the peripheral circuit also includes a read circuit, which is used to read data from any memory cell.

[0026] It comprises multiple layers of memory cell arrays, which are stacked in sequence along a third direction.

[0027] Compared with the prior art, the beneficial effects of the present invention mainly include the following: 1) The minimum characteristic unit area can reach 4F 2 , device density is greatly improved; 2) The design of the memory cell can shrink the cell device synchronously with the logic process, greatly improving the storage capacity of the existing static memory; 3) The reverse cutoff characteristics of the PN junction can be used to control the leakage of unselected cells, further reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 The present invention provides a schematic diagram of a storage unit structure.

[0030] Figure 2 The present invention provides a schematic structural diagram of a storage device.

[0031] Figure 3 The present invention provides a schematic diagram of a readout circuit principle. DETAILED DESCRIPTION

[0032] The foregoing and other technical aspects, features, and functions of the present invention are clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. Directional terms such as up, down, left, right, front, and back, used in the following embodiments, are intended solely to refer to the directions in the accompanying drawings. Therefore, the directional terms used are for illustrative purposes only and are not intended to limit the present invention.

[0033] The following detailed description of the various embodiments of the present application is provided in conjunction with the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present application to facilitate a better understanding of the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0034] The steps in the following embodiments do not correspond one-to-one to the steps in the summary of the invention.

[0035] Example 1

[0036] like Figure 1 FIG2 is a schematic diagram of a storage unit structure provided by an embodiment of the present invention.

[0037] refer to Figure 1The memory cell is a three-dimensional stacked structure, including a first semiconductor structure 1, a low-resistance silicon alloy 3, and a second semiconductor structure 2 stacked in sequence; in the memory cell, the first semiconductor structure 1 and the second semiconductor structure 2 are arranged to cross each other, and a low-resistance silicon alloy 3 is arranged at the intersection of the first semiconductor structure 1 and the second semiconductor structure 2. The low-resistance silicon alloy 3 connects the first semiconductor structure 1 and the second semiconductor structure 2 respectively to form a PN junction structure.

[0038] It should be understood that in order to form a PN junction, the majority carrier types of the first semiconductor structure 1 and the second semiconductor structure 2 are different, namely, one is a P-type semiconductor and the other is an N-type semiconductor. In this embodiment, the first semiconductor structure 1 is an N-type semiconductor structure, which is composed of an N-type low-resistance silicon material formed by an ion implantation process; the second semiconductor structure 2 is a P-type semiconductor structure, which is composed of a P-type low-resistance silicon material formed by an ion implantation process. In other embodiments, the first semiconductor structure 1 can also be a P-type semiconductor structure, and the second semiconductor structure 2 can be an N-type semiconductor structure. The formation method is not limited to the ion implantation process, as long as it can achieve doping to form a P / N-type semiconductor.

[0039] This basic memory cell can be programmed into different states or levels, specifically, depending on whether the PN junction structure is in the off or on state, to represent different data values, thereby enabling information storage. For example, by applying a forward configuration voltage to the memory cell, turning the PN junction on, a current (typically in the order of hundreds of nanoamps to microamps) flows through, representing a "1" signal. By applying a reverse configuration voltage to the memory cell, turning the PN junction off, no current flows, representing a "0" signal. In other words, the memory cell can be set to either of two states, with each cell storing a single bit.

[0040] Example 2

[0041] The second embodiment provides a memory device, which is further formed based on the memory unit in the first embodiment. Figure 2 FIG2 is a schematic diagram of the structure of a memory device provided by an embodiment of the present invention.

[0042] refer to Figure 2 The memory device includes a memory cell array and a peripheral circuit; it should be understood that the memory cell array is obtained by arranging the memory cells in the first embodiment in an array. Figure 2, the memory cell array is also a three-dimensional stacked structure (not shown in the figure, illustrated in a plan view), including a first semiconductor structure array, a low-resistance silicon alloy array, and a second semiconductor structure array stacked in sequence. Among them, the first semiconductor structure array includes: a plurality of first semiconductor structures 1 arranged in sequence along the first direction, each first semiconductor structure 1 extends along the second direction; the second semiconductor structure array includes: a plurality of second semiconductor structures 2 arranged in sequence along the second direction, each second semiconductor structure 2 extends along the first direction; the low-resistance silicon alloy array includes: a plurality of low-resistance silicon alloys 3, each low-resistance silicon alloy 3 is correspondingly arranged at the intersection of the first semiconductor structure 1 and the second semiconductor structure 2, and each low-resistance silicon alloy 3 is respectively connected to the corresponding first semiconductor structure 1 and the second semiconductor structure 2 to form a PN junction structure. It should be understood that in this embodiment, the first direction and the second direction are perpendicular to each other, and the first direction is Figure 2 The Y direction of the plane shown, the second direction is Figure 2 X direction of the plane shown.

[0043] It should be understood that in order to form a PN junction, the majority carrier types of the first semiconductor structure 1 and the second semiconductor structure 2 are different, namely, one is a P-type semiconductor and the other is an N-type semiconductor. In this embodiment, the first semiconductor structure 1 is an N-type semiconductor structure, which is composed of an N-type low-resistance silicon material formed by an ion implantation process; the second semiconductor structure 2 is a P-type semiconductor structure, which is composed of a P-type low-resistance silicon material formed by an ion implantation process. In other embodiments, the first semiconductor structure 1 can also be a P-type semiconductor structure, and the second semiconductor structure 2 can be an N-type semiconductor structure. The formation method is not limited to the ion implantation process, as long as it can achieve doping to form a P / N-type semiconductor.

[0044] In this embodiment, the first semiconductor structure array, the low-resistance silicon alloy array and the second semiconductor structure array are stacked upward in sequence, that is, the bottom layer is the first semiconductor structure array, the low-resistance silicon alloy array stack is formed on the first semiconductor structure array, and the second semiconductor structure array stack is formed on the first semiconductor structure array and the low-resistance silicon alloy array.

[0045] In this embodiment, the memory device includes a layer of memory cell array as an example; in other embodiments, the memory device may include multiple layers of memory cell arrays, which are stacked in sequence along a third direction. The third direction is perpendicular to both the first direction and the second direction, i.e. Figure 2 Z direction of the plane shown.

[0046] In this embodiment, the memory device is further provided with a spacer dielectric for leakage isolation. The spacer dielectric is an insulating dielectric, such as silicon oxide or silicon nitride. Taking silicon oxide as an example, it can generally be formed using thermal oxidation, atomic layer deposition, or plasma-enhanced chemical vapor deposition. The specific selection can be adjusted according to the process node. It is understood that an insulating dielectric is provided for leakage isolation between adjacent first semiconductor structures 1, between adjacent second semiconductor structures 2, and between the first semiconductor structure array and the second semiconductor structure array.

[0047] Similarly, each memory cell in a memory cell array can be programmed into different states or levels. This means that each PN junction structure can be programmed to represent different data values, depending on whether it is in the off or on state, to store information. For example, by applying a forward configuration voltage to a memory cell, when the PN junction is in the on state, a current (typically in the order of hundreds of nanoamps to microamps) flows through it, representing a "1" signal; or by applying a reverse configuration voltage to a memory cell, when the PN junction is in the off state, no current flows through it, representing a "0" signal. In other words, each memory cell can be set to either of two states, storing one bit per cell, ultimately achieving information storage. In this memory cell array, by maintaining the written data state at all times while the power is on, data can be stored for extended periods of time.

[0048] To operate each memory cell in the memory cell array, certain peripheral circuits need to be set up. For example, to access any memory cell, a word line driver circuit and a bit line driver circuit can be set up. The target memory cell is accessed by selectively activating the word line and bit line corresponding to the cell. That is, the word line driver circuit and the bit line driver circuit can activate the corresponding first semiconductor structure 1 and second semiconductor structure 2, and then operate the PN junction structure formed at the intersection of the first semiconductor structure 1 and the second semiconductor structure 2 (such as applying voltage to write data). Figure 2 As shown, the bit line driving circuit includes an odd bit line driver 40 and an even bit line driver 41 , and the word line driving circuit includes an odd word line driver 50 and an even word line driver 51 .

[0049] Similarly, in order to read the stored information, a readout circuit is also provided to read the data of any storage unit. Figure 3The figure shows a schematic diagram of the principle of a readout circuit. For a selected memory cell, a low-resistance PN junction channel is formed from the second semiconductor structure 2 to the first semiconductor structure 1. When the voltage opens the channel, a current flows (usually about 100 nA-μA level), which is considered to be a successful write of "1". This "1" signal can be detected by the readout circuit. When the operating voltage writes "0" to the selected cell, it means that no current flows, and this "0" signal can be detected by the readout circuit. In this embodiment, after the NMOS switch in the readout circuit is turned on, the high / low level is read out through the differential amplifier circuit. Figure 3 As shown in Figure 1, for a selected memory cell, current flows outward from the word line (WL), denoted as I-WL. Iref refers to a reference current or intermediate current level determined by process and device characteristics. When the selected memory cell is conducting, I-WL is approximately in the hundreds of nanoamps to microamps range. When the cell is off, there is virtually no current or only a leakage current of tens of nanoamps, meaning I-WL is zero or only tens of nanoamps. When the I-WL of the input differential amplifier circuit is in the hundreds of nanoamps to microamps range (i.e., conducting), I-WL is compared with Iref, causing Iref to be pulled high, ultimately reading a high level. When I-WL of the input differential amplifier circuit is zero or only tens of nanoamps (i.e., off), I-WL is compared with Iref, causing Iref to be pulled low, ultimately reading a low level. In this embodiment, NMOS switches are selected because they offer greater drive capability on the same logic process platform and device size.

[0050] The memory cell and memory device provided by this application can achieve higher device density, and its minimum characteristic unit area is 2F 2F=4F 2 , F refers to the half-interval of the characteristic unit size; and the device architecture can shrink the unit device synchronously with the logic process, which can be used for both embedded storage and independent large storage arrays, and has a wide range of application scenarios; in addition, PN junction technology is already very mature, and its reverse cutoff characteristics can be used to control the leakage of unselected units, which can further reduce power consumption.

[0051] In order to facilitate the description of the present invention, some common English nouns or letters are used for illustrative reference only and are not intended to be restrictive or specific. The scope of protection of the present invention should not be limited by their possible Chinese translations or specific letters.

[0052] It should also be noted that, in this article, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

Claims

1. A storage unit, characterized in that: comprising a first semiconductor structure, a low-resistance silicon alloy, and a second semiconductor structure stacked in sequence; The first semiconductor structure and the second semiconductor structure are arranged to intersect each other, and the majority carrier types of the first semiconductor structure and the second semiconductor structure are different; The low-resistance silicon alloy is provided at the intersection of the first semiconductor structure and the second semiconductor structure, respectively connecting the first semiconductor structure and the second semiconductor structure to form a PN junction structure; The memory cell is configured to represent different data values ​​according to an off state and an on state of the PN junction structure.

2. A storage unit according to claim 1, characterized in that: The memory cell is configured such that: when the PN junction structure is in the on state, it is used to represent a "1" signal; when the PN junction structure is in the off state, it is used to represent a "0" signal.

3. A storage unit according to claim 1, characterized in that: The first semiconductor structure is a P-type semiconductor structure, and the second semiconductor structure is an N-type semiconductor structure; Alternatively, the first semiconductor structure is an N-type semiconductor structure, and the second semiconductor structure is a P-type semiconductor structure; The P-type semiconductor structure is a P-type low-resistance silicon material, and the N-type semiconductor structure is an N-type low-resistance silicon material.

4. A memory device, characterized in that: including a memory cell array and peripheral circuits; The memory cell array comprises a first semiconductor structure array, a low-resistance silicon alloy array, and a second semiconductor structure array stacked in sequence; The first semiconductor structure array includes: a plurality of first semiconductor structures sequentially arranged along a first direction, each of the first semiconductor structures extending along a second direction; The second semiconductor structure array includes: a plurality of second semiconductor structures sequentially arranged along the second direction, each of the second semiconductor structures extending along the first direction; The low-resistance silicon alloy array includes: a plurality of low-resistance silicon alloys, each of the low-resistance silicon alloys is correspondingly arranged at an intersection of the first semiconductor structure and the second semiconductor structure; The majority carrier types of the first semiconductor structure and the second semiconductor structure are different, and each of the low-resistance silicon alloys is respectively connected to the corresponding first semiconductor structure and the second semiconductor structure to form a PN junction structure; The off state and the on state of the PN junction structure are used to represent different data values.

5. The memory device according to claim 4, wherein: When the PN junction structure is in the on state, it is used to represent a "1" signal, and when the PN junction structure is in the off state, it is used to represent a "0" signal.

6. The memory device according to claim 4, wherein: The first semiconductor structure is a P-type semiconductor structure, and the second semiconductor structure is an N-type semiconductor structure; Alternatively, the first semiconductor structure is an N-type semiconductor structure, and the second semiconductor structure is a P-type semiconductor structure.

7. The memory device according to claim 6, wherein: The N-type semiconductor structure is an N-type low-resistance silicon material; The low-resistance silicon alloy stack is formed on the N-type semiconductor structure; The P-type semiconductor structure is a P-type low-resistance silicon material, and the P-type semiconductor structure is stacked and formed on the N-type semiconductor structure and the low-resistance silicon alloy.

8. The memory device according to claim 4, wherein: The system further includes a spacer medium, which is disposed between adjacent first semiconductor structures, between adjacent second semiconductor structures, and between the first semiconductor structure array and the second semiconductor structure array.

9. The memory device according to claim 4, wherein: The peripheral circuit is used to operate the memory cell array; The peripheral circuit includes a word line driving circuit and a bit line driving circuit, which are used to drive any memory cell in the memory cell array to write data; The peripheral circuit further includes a readout circuit for reading out data from any one of the storage cells.

10. The memory device according to claim 4, wherein: It comprises multiple layers of memory cell arrays, which are stacked in sequence along a third direction.

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