Data transmission method, communication system and electronic equipment

Abstract

The embodiment of the invention provides a data transmission method, a communication system and electronic equipment. Relates to the technical field of communication, and is used for reducing the area of a communication system while increasing the number of Ethernet interfaces. The communication system comprises at least one processor core, a convergence distribution module and a plurality of interfaces, the at least one processor core is used for sending a first data frame and first indication information to the aggregation distribution module, the first indication information is used for indicating at least one interface in the plurality of interfaces, and the first data frame is a data frame corresponding to the at least one first message; and the convergence distribution module is used for sending a first target data frame through at least one interface indicated by the first indication information, and the first target data frame is determined by the convergence distribution module according to a multi-channel access control MAC protocol and the first data frame.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and in particular, to a data transmission method, a communication system, and an electronic device. Background Art

[0002] Fieldbus is an industrial data bus used to solve communication problems between different devices in industrial fields. For example, the devices can include intelligent instruments, controllers, and actuators, etc. Industrial Ethernet is a unit network based on the standard Ethernet protocol (IEEE 802.3), that is, industrial Ethernet uniformly adopts IEEE 802.3 in terms of physical medium, number of nodes, distance, bandwidth, checksum, and diagnosis. Compared with fieldbus, industrial Ethernet has greater advantages in terms of transmission rate, manufacturing cost, and usage cost. Therefore, industrial Ethernet has replaced fieldbus and is widely used in various fields, such as industrial automation, robot control, robotics, automated production, and other fields that require communication. With the rapid development of industrial Ethernet technology, the corresponding communication protocols are also increasing. Currently, more than 20 communication protocols have been recognized, and the most representative communication protocols include Ethernet Industry Protocol (EtherNet / IP), Ethernet Control Automation Technology (EtherCAT), and Profinet of industrial Ethernet protocol, etc. However, when applying industrial Ethernet technology to a chip, the chip cannot support all communication protocols, which cannot meet the selection needs of users and reduces the user experience.

[0003] Currently, programmable technology is used to enable a processor core to support multiple communication protocols. The processor core sends and receives packets through an interface (such as a Medium Independent Interface (MII)), and the processor core implements the functions of the Media Access Control (MAC) protocol. When the processor is set on a chip, the chip can thus support multiple communication protocols.

[0004] However, when using a processor core to implement the functions of the MAC protocol, the number of processor cores corresponds one-to-one with the number of MIIs. If one more MII needs to be supported, one more processor core needs to be added, increasing the area and cost of the communication system. Summary of the Invention

[0005] This application provides a data transmission method, a communication system, and an electronic device, which are used to reduce the area of the communication system while increasing the number of Ethernet interfaces.

[0006] To achieve the above object, the present application adopts the following technical solutions:

[0007] In a first aspect, a communication system is provided. The communication system includes: at least one processor core, an aggregation and distribution module, and multiple interfaces (for example, it may include a media-independent interface); the at least one processor core is configured to send a first data frame and first indication information to the aggregation and distribution module, the first indication information is used to indicate at least one of the multiple interfaces, and the first data frame is a data frame corresponding to at least one first message; the aggregation and distribution module is configured to send a first target data frame through at least one interface indicated by the first indication information, and the first target data frame is determined by the aggregation and distribution module according to the media access control (MAC) protocol and the first data frame.

[0008] In the technical solution provided by the present application, when sending at least one first message, the at least one processor core sends the first data frame and the first indication information corresponding to the at least one first message to the aggregation and distribution module. The aggregation and distribution module determines the first target data frame according to the MAC protocol and the first data frame, and sends the first target data frame through at least one interface indicated by the first indication information among the multiple interfaces. The aggregation and distribution module realizes the function of the MAC protocol, and the aggregation and distribution module realizes the function originally implemented by the processor core, reducing the load of the processor core, so that at least one processor core can correspond to multiple interfaces. Figure 1 When the shown communication system sends a message, the processor core directly sends the target data frame corresponding to the message through the interface, and the processor core realizes the function of the MAC protocol, so that one processor core can only correspond to one interface. Since the area and cost of the aggregation and distribution module are smaller than those of the processor core, therefore, the technical solution provided by the present application increases the number of interfaces while reducing the area and cost of the communication system; further, when the communication system is integrated on a chip, the area of the chip is correspondingly reduced.

[0009] In a possible implementation manner of the first aspect, the aggregation and distribution module includes an aggregation and distribution circuit; the aggregation and distribution circuit is configured to determine the first target data frame according to the MAC protocol and the first data frame; and is further configured to send the first target data frame through at least one interface. In the above possible implementation manner, through the aggregation and distribution circuit, not only the aggregation and distribution function is realized, but also the MAC function is realized, reducing the load of the processor core.

[0010] In a possible implementation of the first aspect, the aggregation and distribution module includes an aggregation and distribution circuit and multiple digital circuits, and the multiple digital circuits correspond to multiple interfaces one by one; the aggregation and distribution circuit is configured to send a first data frame to the digital circuits corresponding to at least one interface according to first indication information; the digital circuit is further configured to determine a first target data frame according to the MAC protocol and the first data frame; the digital circuit is further configured to send the first target data frame through at least one interface. In the above possible implementation, the aggregation and distribution function is implemented through the aggregation and distribution circuit, and the MAC function is implemented through the digital circuit, improving the efficiency of the communication system.

[0011] In a possible implementation of the first aspect, the interface includes a media-independent interface. In the above possible implementation, the physical layer connected to the media-independent interface can support different media types.

[0012] In a possible implementation of the first aspect, the first target data frame includes multiple data frames, and the length of each data frame in the multiple data frames is greater than or equal to a first threshold. In the above possible implementation, the length of each data frame conforms to the MAC protocol, improving the transmission rate and efficiency.

[0013] In a possible implementation of the first aspect, the communication system further includes: multiple physical layers, and the multiple physical layers correspond to the multiple interfaces one by one; the aggregation and distribution module is specifically configured to send the first target data frame to the corresponding physical layer through at least one interface. In the above possible implementation, each interface corresponds to a physical layer, improving the transmission efficiency.

[0014] In a possible implementation of the first aspect, at least one processor core includes a reduced instruction set computer. In the above possible implementation, the reduced instruction set computer has the advantages of small area, low cost, and low power consumption. By setting the reduced instruction set computer in the communication system, the area, cost, and power consumption of the communication system are reduced.

[0015] In a possible implementation of the first aspect, at least one processor core is further configured to obtain at least one first message and process the at least one first message to obtain a first data frame. In the above possible implementation, the first data frame is generated by the processor core, that is, part of the MAC function is implemented by the processor core, reducing the area of the communication system.

[0016] In a second aspect, a communication system is provided. The communication system includes: at least one processor core, an aggregation and distribution module, and a plurality of interfaces (for example, it may include a media-independent interface); the aggregation and distribution module is configured to receive second data frames through each of the plurality of interfaces, where the second data frames are data frames corresponding to at least one second message; the aggregation and distribution module is further configured to store the second target data frame and send second indication information to at least one processor core, where the second indication information is used to instruct the at least one processor core to read the second target data frame from the aggregation and distribution module, and the second target data frame is determined by the aggregation and distribution module according to the media access control (MAC) protocol and the second data frame.

[0017] In the technical solution provided in this application, when receiving at least one second message, the aggregation and distribution module receives the second data frames corresponding to the at least one second message through the interfaces, determines the second target data frame according to the MAC protocol and the second data frames, stores the second target data frame, and sends the second indication information to at least one processor core. The aggregation and distribution module implements the function of the MAC protocol, and the aggregation and distribution module implements the function originally implemented by the processor core, reducing the load of the processor core, so that at least one processor core can correspond to a plurality of interfaces. Figure 1 In the communication system shown in [reference], when receiving a message, the processor core directly receives and processes the data frame through the interface to obtain the target data frame, that is, the function of the MAC protocol is implemented by the processor core, so that one processor core can only correspond to one interface. Since the area and cost of the aggregation and distribution module are smaller than those of the processor core, therefore, the technical solution provided in this application increases the number of interfaces while reducing the area and cost of the communication system; further, when the communication system is integrated on a chip, the area of the chip is correspondingly reduced.

[0018] In a possible implementation manner of the second aspect, the aggregation and distribution module includes an aggregation and distribution circuit; the aggregation and distribution circuit is configured to receive second data frames through each of the plurality of interfaces; the aggregation and distribution circuit is further configured to determine the second target data frame according to the MAC protocol and the second data frames; the aggregation and distribution circuit is further configured to store the second target data frame and send second indication information to at least one processor core. In the above possible implementation manner, the aggregation and distribution circuit not only implements the aggregation and distribution function, but also implements the MAC function, reducing the load of the processor core.

[0019] In a possible implementation of the second aspect, the aggregation and distribution module includes an aggregation and distribution circuit and multiple digital circuits, and the multiple digital circuits correspond to multiple interfaces one by one; the digital circuit is configured to receive a second data frame through the corresponding interface; the digital circuit is configured to determine a second target data frame according to the MAC protocol and the second data frame; the aggregation and distribution circuit is further configured to store multiple second target data frames and send second indication information to at least one processor core. In the above possible implementation, the aggregation and distribution function is implemented through the aggregation and distribution circuit, and the MAC function is implemented through the digital circuit, improving the efficiency of the communication system.

[0020] In a possible implementation of the second aspect, the interface includes a media-independent interface. In the above possible implementation, the physical layer connected to the media-independent interface can support different media types.

[0021] In a possible implementation of the second aspect, the second target data frame includes multiple data frames, and the length of each data frame in the multiple data frames is greater than or equal to a first threshold. In the above possible implementation, the length of each data frame conforms to the MAC protocol, improving the transmission rate and efficiency.

[0022] In a possible implementation of the second aspect, the communication system further includes multiple physical layers, and the multiple physical layers correspond to the multiple interfaces one by one. The aggregation and distribution module is specifically further configured to receive a second data frame from the corresponding physical layer through the interface. In the above possible implementation, each interface corresponds to a physical layer, improving the transmission efficiency.

[0023] In a possible implementation of the second aspect, at least one processor core includes a reduced instruction set computer. In the above possible implementation, the reduced instruction set computer has the advantages of small area, low cost, and low power consumption. By setting the reduced instruction set computer in the communication system, the area, cost, and power consumption of the communication system are reduced.

[0024] In a possible implementation of the second aspect, at least one processor core is configured to read the second target data frame from the aggregation and distribution module based on the second indication information and process the second target data frame to obtain at least one second message.

[0025] In a possible implementation of the second aspect, the aggregation and distribution module is further configured to forward the second target data frame to at least one of the multiple interfaces according to preset information, and the preset information includes at least one interface. In the above possible implementation, the forwarding efficiency is improved.

[0026] In a third aspect, a data transmission method is provided. The method is applied to a communication system, and the communication system includes: at least one processor core, an aggregation and distribution module, and multiple interfaces; the at least one processor core sends a first data frame and first indication information to the aggregation and distribution module, the first indication information is used to indicate at least one of the multiple interfaces, and the first data frame is a data frame corresponding to at least one first packet; the aggregation and distribution module sends a first target data frame through the at least one interface indicated by the first indication information, and the first target data frame is determined by the aggregation and distribution module according to the media access control (MAC) protocol and the first data frame.

[0027] In a possible implementation manner of the third aspect, the aggregation and distribution module includes an aggregation and distribution circuit. The aggregation and distribution module sending the first target data frame through at least one interface includes: the aggregation and distribution circuit determines the first target data frame according to the MAC protocol and the first data frame; the aggregation and distribution circuit sends the first target data frame through at least one interface.

[0028] In a possible implementation manner of the third aspect, the aggregation and distribution module includes an aggregation and distribution circuit and multiple digital circuits, and the multiple digital circuits correspond to the multiple interfaces one by one. The aggregation and distribution module sending the first target data frame through the at least one interface indicated by the first indication information includes: the aggregation and distribution circuit sends the first data frame to the digital circuits corresponding to the at least one interface according to the first indication information; the digital circuits determine the first target data frame according to the MAC protocol and the first data frame; the digital circuits send the first target data frame through at least one interface.

[0029] In a possible implementation manner of the third aspect, the interface includes a media independent interface.

[0030] In a possible implementation manner of the third aspect, the first target data frame includes multiple data frames, and the length of each data frame in the multiple data frames is greater than or equal to a first threshold.

[0031] In a possible implementation manner of the third aspect, the communication system further includes multiple physical layers, and the multiple physical layers correspond to the multiple interfaces one by one. The aggregation and distribution module sending the first target data frame through at least one interface includes: the aggregation and distribution module sends the first target data frame to the corresponding physical layer through at least one interface.

[0032] In a possible implementation manner of the third aspect, the at least one processor core includes a reduced instruction set computer.

[0033] In a possible implementation manner of the third aspect, the method further includes: the at least one processor core obtains at least one first packet and processes the at least one first packet to obtain the first data frame.

[0034] Fourth aspect, through a data transmission method, the method is applied to a communication system, and the communication system includes: at least one processor core, an aggregation and distribution module, and multiple interfaces; for each interface among the multiple interfaces, the aggregation and distribution module receives a second data frame through the interface, and the second data frame is a data frame corresponding to at least one second message; the aggregation and distribution module stores the second target data frame, and sends second indication information to at least one processor core, and the second indication information is used to instruct at least one processor core to read the second target data frame from the aggregation and distribution module, and the second target data frame is determined by the aggregation and distribution module according to the media access control (MAC) protocol and the second data frame.

[0035] In a possible implementation manner of the fourth aspect, the aggregation and distribution module includes an aggregation and distribution circuit. The aggregation and distribution module receives the second data frame through the interface, including: the aggregation and distribution circuit receives the second data frame through the interface; the aggregation and distribution module stores the second target data frame, and sends second indication information to at least one processor core, including: the aggregation and distribution circuit determines the second target data frame according to the MAC protocol and the second data frame; the aggregation and distribution circuit stores the second target data frame, and sends second indication information to at least one processor core.

[0036] In a possible implementation manner of the fourth aspect, the aggregation and distribution module includes an aggregation and distribution circuit and multiple digital circuits, and the multiple digital circuits correspond to the multiple interfaces one by one. The aggregation and distribution module receives the second data frame through the interface, including: the digital circuit corresponding to the interface receives the second data frame through the interface; the aggregation and distribution module stores the second target data frame, and sends second indication information to at least one processor core, including: the digital circuit determines the second target data frame according to the MAC protocol and the second data frame; the aggregation and distribution circuit stores the second target data frame, and sends second indication information to at least one processor core.

[0037] In a possible implementation manner of the fourth aspect, the interface includes a media independent interface.

[0038] In a possible implementation manner of the fourth aspect, the second target data frame includes multiple data frames, and the length of each data frame among the multiple data frames is greater than or equal to a first threshold.

[0039] In a possible implementation manner of the fourth aspect, the communication system further includes multiple physical layers, and the multiple physical layers correspond to the multiple interfaces one by one. The aggregation and distribution module receives the second data frame through the interface, including: the aggregation and distribution module receives the second data frame from the corresponding physical layer through the interface.

[0040] In a possible implementation manner of the fourth aspect, at least one processor core includes a reduced instruction set computer.

[0041] In a possible implementation of the fourth aspect, the method further includes: at least one processor core reads a second target data frame from the aggregation and distribution module based on the second indication information, and processes the second target data frame to obtain at least one second message.

[0042] In a possible implementation of the fourth aspect, the method further includes: the aggregation and distribution module forwards the second target data frame to at least one of a plurality of interfaces according to preset information, and the preset information includes at least one interface.

[0043] In a fifth aspect, there is provided an electronic device, which includes a communication system and a memory. The memory is used to store computer instructions. The communication system includes at least one processor core and an aggregation and distribution module. The communication system is the communication system provided in the first aspect or any possible implementation of the first aspect, or the communication system provided in the second aspect or any possible implementation of the second aspect.

[0044] In a sixth aspect, there is provided a computer-readable storage medium storing computer instructions. When the computer instructions run on the communication system, the communication system is caused to execute the data transmission method provided in the third aspect or any possible implementation of the third aspect, or the data transmission method provided in the fourth aspect or any possible implementation of the fourth aspect.

[0045] In a seventh aspect, there is provided a computer program product containing instructions. When the computer program product runs on the communication system, the communication system is caused to execute the data transmission method provided in the third aspect or any possible implementation of the third aspect, or the data transmission method provided in the fourth aspect or any possible implementation of the fourth aspect.

[0046] It can be understood that for the data transmission method, electronic device, computer-readable storage medium, and computer program product provided above, the devices or apparatuses that execute the transmission method all include all the features of the above communication system. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding communication system provided above, and will not be elaborated here. Description of the Drawings

[0047] Figure 1 It is a schematic structural diagram of a communication system provided by an embodiment of the present application;

[0048] Figure 2 It is a schematic structural diagram of a communication system provided by an embodiment of the present application;

[0049] Figure 3 It is a flowchart of a data transmission method provided by an embodiment of the present application;

[0050] Figure 4 A schematic structural diagram of another communication system provided by an embodiment of the present application;

[0051] Figure 5 A schematic structural diagram of yet another communication system provided by an embodiment of the present application;

[0052] Figure 6 A schematic structural diagram of another communication system provided by an embodiment of the present application;

[0053] Figure 7 A schematic structural diagram of yet another communication system provided by an embodiment of the present application;

[0054] Figure 8 A schematic structural diagram of another communication system provided by an embodiment of the present application;

[0055] Figure 9 A schematic structural diagram of yet another communication system provided by an embodiment of the present application;

[0056] Figure 10 A schematic structural diagram of another communication system provided by an embodiment of the present application;

[0057] Figure 11 A schematic structural diagram of yet another communication system provided by an embodiment of the present application;

[0058] Figure 12 A schematic structural diagram of another communication system provided by an embodiment of the present application;

[0059] Figure 13 A flowchart of another data transmission method provided by an embodiment of the present application. Detailed implementation manners

[0060] In this application, "at least one" means one or more, and "more" means two or more. "And / or" describes the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated with each other are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple. In addition, the embodiments of the present application use words such as "first" and "second" to distinguish between the same items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only to distinguish different thresholds, and do not limit their order. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order.

[0061] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0062] Before introducing the embodiments of the present application, the relevant knowledge of Ethernet is first explained.

[0063] Open System Interconnect (OSI) is a network interconnection model. The OSI model includes a seven-layer framework (physical layer, data link layer, network layer, transport layer, session layer, presentation layer and application layer), where the first layer is the physical layer, and so on, the seventh layer is the application layer. The physical layer and data link layer involved in the embodiments of the present application are introduced and explained below.

[0064] Among them, the physical layer (PHY), as the lowest layer of the OSI model, is used to realize the transmission of bit streams between computer nodes. For example, PHY can include network cards, network cables, Ethernet cables and hubs, etc. PHY can also be called the port physical layer. The PHY chip is a chip that implements the functions of the PHY layer and can be used to send and receive Ethernet data frames. Network devices are connected to each other through PHY chips.

[0065] The data link layer (DLL) includes the logical link control (LLC) and the media access control (MAC). For example, the DLA can include bridges and switches, etc. The MAC can be used to generate and receive data frames, as well as control and connect to the PHY. The LLC can be used to connect to the network layer. The MAC protocol is a link layer protocol that defines the transmission rate of Ethernet (the transmission rate refers to the maximum transmission rate), the transmission mode, the format of data frames in the data link layer, the length of data frames, the filling method of data frames, and the error checking of data frames. Through the MAC protocol, it can be determined whether a data frame can be sent. Among them, the transmission mode includes the half-duplex mode and the full-duplex mode. In the half-duplex mode, sending and receiving cannot be parallel, and in the full-duplex mode, sending and receiving can be carried out simultaneously.

[0066] The medium independent interface (MII) can also be called the media independent interface. The MII includes a data interface and a management interface between the MAC and the PHY. The data interface includes two independent channels for the transmitter and the receiver respectively, and each channel has its own data, clock, and control signals. The management interface is a dual-signal interface, one is the clock signal, and the other is the data signal. Through the management interface, the upper module can monitor and control the PHY. The MII can also be called the Ethernet interface.

[0067] Optionally, the MII can include multiple derivative interfaces. For example, the gigabit medium independent interface (GMII), the serial gigabit medium independent interface (SGMII), the reduced media independent interface (RMII), and the reduced gigabit media independent interface (RGMII), etc.

[0068] Fieldbus is an industrial data bus used to solve the communication problems between different devices in industrial fields. For example, devices can include intelligent instruments, controllers, actuators, etc. Industrial Ethernet is a unit network based on the standard Ethernet protocol (IEEE 802.3), that is, industrial Ethernet uniformly adopts IEEE 802.3 in terms of physical medium, number of nodes, distance, bandwidth, checksum and diagnosis. Compared with fieldbus, industrial Ethernet has greater advantages in terms of transmission rate, manufacturing cost and usage cost. Therefore, industrial Ethernet has replaced fieldbus and is widely used in various fields, such as industrial automation, robot control, robotics, automated production, and other fields that require communication. With the rapid development of industrial Ethernet technology, there are more and more corresponding communication protocols. Currently, more than 20 communication protocols have been recognized, and the most representative communication protocols include EtherCAT, Profinet, and EtherNet / IP, etc. However, when applying industrial Ethernet technology to chips, the chips cannot support all communication protocols, which cannot meet the selection needs of users and reduces the user experience.

[0069] Currently, programmable technology is used to enable the communication system to support multiple communication protocols to meet the selection needs of users. Figure 1 is a schematic structural diagram of a communication system 10, as Figure 1As shown, communication system 10 includes three processor cores. For example, the three processor cores may include a central processing unit (CPU) core 101, programmable real-Time units (PRUs) 102 and 103, a memory 104, an interface 105, and two physical layers (PHYs) 106 - 107. Interface 105 includes two medium independent interfaces (MIIs), and their identification information can be respectively represented as MII 0 and MII 1, as well as four multiplexers: multiplexers 108 to 111. Each PRU corresponds to one MII (for example, PRU 103 corresponds to MII 0, and PRU 104 corresponds to MII 1). Each MII has a corresponding receive (RX) channel and transmit (TX) channel. For example, MII 0 includes receive channel MII0RX and transmit channel MII 0TX, and MII 1 includes receive channel MII 1RX and transmit channel MII 1TX. Among them, each receive channel can be used to receive data signals from each PHY; each transmit channel can be used to send data signals to each PHY. Each multiplexer can be used to combine multiple data signals into one data signal; each PRU can be used to support different communication protocols with different software, that is, each PRU uses programmable technology so that each processor core can support different communication protocols. Each PRU accesses and controls each PHY through the corresponding MII, and reads and writes to the shared memory 102. Figure 1 In the shown communication system, the functions of two medium access control (MAC) protocols are implemented through two processor cores, PRU102 and PRU103, and one processor core (PRU) corresponds to one MII. Optionally, the MII can also be referred to as an Ethernet interface, and the PRU can be a 32-bit reduced instruction set computer (RISC) with an operating frequency of 200 MHz to 25 MHz. Figure 1 Only a partial structure of the communication system is shown. Figure 1 The shown communication system can be provided on a chip.

[0070] However, when using processor cores to implement the functions of the MAC protocol, the number of processor cores and the number of MIIs correspond one by one. If one more Ethernet interface needs to be supported, one more processor core needs to be added, increasing the area and cost of the communication system.

[0071] Based on this, an embodiment of the present application provides a data transmission method, which is applied to a communication system. The communication system includes at least one processor core, an aggregation and distribution module, and multiple interfaces. Each of the multiple interfaces may include a MII or a derivative interface of MII. In this communication system, when sending at least one first message, at least one processor core sends a first data frame and first indication information corresponding to the at least one first message to the aggregation and distribution module. The aggregation and distribution module determines a first target data frame according to the MAC protocol and the first data frame, and the aggregation and distribution module sends the first target data frame through at least one interface indicated by the first indication information among the multiple interfaces. The aggregation and distribution module can implement the function of the MAC protocol. The aggregation and distribution module implements the function originally implemented by the processor core, reducing the load of the processor core, enabling at least one processor core to correspond to multiple interfaces. Since the area and cost of the aggregation and distribution module are smaller than those of the processor core, compared with Figure 1 the case where the processor core in [reference] implements the function of the MAC protocol and one processor core can only correspond to one interface, the solution provided by the embodiment of the present application increases the number of interfaces while reducing the area and cost of the communication system.

[0072] The method provided by the embodiment of the present application can be applied to a communication system with an aggregation and distribution module. The structure of the communication system will be described below.

[0073] Figure 2 FIG. [reference] is a schematic structural diagram of a communication system provided by an embodiment of the present application. The communication system includes a memory, at least one processor core, an aggregation and distribution module, multiple interfaces, multiple PHYs, and a bus. The multiple interfaces and the multiple PHYs are in one-to-one correspondence. For example, the number of the multiple interfaces may be greater than the number of at least one processor core. Figure 2 In [reference], it is taken as an example that the multiple interfaces may include n interfaces and the multiple PHYs may include n PHYs, where n is a positive integer.

[0074] Among them, the memory can be used to store data, software programs, and software modules; it mainly includes a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function, such as a data frame forwarding function or a data frame scheduling function, etc.; the data storage area can store data created according to the use of the communication system, such as data frames. For example, the memory can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous-link dynamic random access memory (SDRAM), double-data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchlink dynamic random access memory (SLDRAM), and direct rambus random access memory (DR RAM). In the embodiments of the present application, the memory can be a shared memory of the communication system.

[0075] The at least one processor core can include one processor core or multiple processor cores. A processor core can also be referred to as a processing core or a core. When the at least one processor core includes multiple processor cores, the multiple processor cores can be processor cores in the same processor or processor cores in different processors. For example, the processor can be a CPU, a microprocessor, and other general-purpose processors, a digital signal processor (DSP), and a neural network processing unit (NPU), etc.

[0076] In addition to being used to implement the aggregation and distribution functions, the aggregation and distribution module is also used to implement some or all of the MAC functions. The MAC functions include the functions defined by the MAC protocol. For example, data frame generation, data frame scheduling, data frame length check, data frame checksum, and data frame padding. The aggregation and distribution module is also used to store data frames. Optionally, the aggregation and distribution module is also used to send data frames to the PHY through an interface, or receive data frames from the PHY through an interface. The aggregation and distribution module is also used to receive first indication information, which is used to indicate at least one interface. The aggregation and distribution module is also used to send second indication information to the processor core, which is used to indicate the processor core to read a second target data frame, and the second target data frame is the data frame corresponding to at least one second message. In the embodiments of the present application, the case where the aggregation and distribution module implements some MAC functions is taken as an example for illustration.

[0077] The interface can be the MII described above or a derivative interface of the MII. The MII or its derivative interface can be collectively referred to as a media-independent interface. For the relevant descriptions of the interface and the PHY, please refer to the above for details and will not be elaborated here.

[0078] The bus can include an address bus, a data bus, a control bus, etc. Data (including data frames) is transmitted between the above components (such as a memory, at least one processor core, an aggregation and distribution module, an interface, and a PHY) through the bus. For example, the bus can be a 32-bit bus. However, for the sake of clear illustration, various buses are labeled as buses in the figure. The bus can be a peripheral component interconnect express (PCIe) bus, or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc.

[0079] In a possible embodiment, at least one processor core, an aggregation and distribution module, multiple interfaces, and a bus are integrated on one chip, and each of the multiple PHYs is integrated on another chip. In another possible embodiment, the memory can be a cache, and the memory, at least one processor core, an aggregation and distribution module, multiple interfaces, and a bus are integrated on one chip, and each of the multiple PHYs is integrated on another chip. The embodiments of the present application do not make specific limitations on this.

[0080] The above communication system can be an electronic device or a system on chip (SoC) applied to an electronic device. The electronic device can be used as a terminal device or a server, such as a server in an industrial site. Optionally, the electronic device includes, but is not limited to: mobile phone, tablet computer, laptop computer, desktop computer, handheld computer, ultra-mobile personal computer (UMPC), mobile internet device (MID), netbook, camera, camera, wearable device (such as smart watch and smart bracelet, etc.), vehicle-mounted device (such as car, bicycle, electric vehicle, train, high-speed train, etc.), virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control, smart home device (such as refrigerator, TV, air conditioner, electric meter, etc.), intelligent robot, workshop device, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, or wireless terminal in smart home, flight device (such as intelligent robot, hot air balloon, drone, airplane), etc.

[0081] Figure 3 FIG. is a flowchart of a data transmission method provided by an embodiment of the present application. The method can be applied to the communication system provided above. The communication system includes: at least one processor core, an aggregation and distribution module, and a plurality of interfaces. The method includes the following steps.

[0082] S301: At least one processor core sends a first data frame and first indication information to the aggregation and distribution module. The first indication information is used to indicate at least one of the plurality of interfaces. The first data frame is a data frame corresponding to at least one first message.

[0083] Specifically, at least one processor core can send the first data frame and the first indication information to the aggregation and distribution module through a bus. For example, the bus can include a 32-bit bus.

[0084] When multiple processor cores send the first data frame and the first indication information to the aggregation and distribution module, the multiple processor cores can be processor cores in the same processor or processor cores in different processors. For example, the multiple processor cores include a first processor core, a second processor core, and a third processor core. The first processor core, the second processor core, and the third processor core can all be processor cores in a CPU, or the first processor core and the second processor core can be processor cores in a CPU, and the third processor core can be a processor core in an NPU. The embodiments of the present application do not make specific limitations in this regard.

[0085] In addition, the processor core can also include a reduced instruction set computer (RISC). For example, RISC can include a PRU and a deterministic real-time unit (DRU), etc. In a possible embodiment, the processor core can be a 32-bit RISC with an operating frequency of 200 MHz to 400 MHz. The processor core can also be referred to as a RISC core or a RISC real-time core. In practical applications, the processor core can implement different functions by running different programs, that is, the functions of the processor core are programmable. For example, the processor core can implement the sending function by running a sending program, and the processor core can also implement the receiving function by running a receiving program.

[0086] Optionally, when at least one processor core includes multiple processor cores, the multiple processor cores can be the same processor cores or different processor cores. For example, the multiple processor cores include a first processor core, a second processor core, and a third processor core. The first processor core, the second processor core, and the third processor core can all be RISC cores; or the first processor core and the second processor core are RISC cores, and the third processor core is a CPU core. The embodiments of the present application do not make specific limitations in this regard.

[0087] Furthermore, for each of the multiple interfaces, the interface can include a MII or a derivative interface of the MII. For example, GMII, SGMII, RMII, and RGMII, etc. The MII or the derivative interface of the MII is collectively referred to as a media-independent interface. The embodiments of the present application do not make specific limitations on the number of interfaces and the number of processor cores. For example, the number of interfaces can be greater than the number of processor cores. Exemplarily, the multiple interfaces can include n interfaces, and at least one processor core can include m processor cores, where n is greater than m, and n and m are positive integers. In practical applications, the number of n is related to the performance of the m processor cores, and can be specifically set according to actual requirements or the experience of relevant staff. The embodiments of the present application do not make specific limitations in this regard.

[0088] In addition, at least one first message may include one first message or multiple first messages. For example, at least one first message may include 20 first messages. The at least one first message may also be referred to as Ethernet data at the third layer (network layer) and above.

[0089] In a possible embodiment, before step S301, at least one processor core obtains at least one first message and processes the at least one first message to obtain a first data frame. For example, at least one processor core may execute a software upper-layer protocol stack and an application program to obtain at least one first message, and the at least one first message may be a message in a sampler or sensor in an industrial field. Optionally, at least one processor may receive third indication information and obtain at least one first message from a memory or other storage area according to the third indication information, where the third indication is used to instruct at least one processor to obtain at least one first message from the memory or other storage area.

[0090] In a possible embodiment, assuming that at least one processor core includes one processor core, the processor core processes at least one first message to obtain a first data frame, which specifically includes: for each first message in the at least one first message, the processor core parses the first message, determines the type of the first message, and splits the first message according to the length corresponding to the type of the first message to obtain multiple sub-data. For each sub-data in the multiple sub-data, the processor core assembles the sub-data to obtain a data frame, where the data frame includes a frame header, sub-data, and a frame tail. Among them, the frame header and the frame tail include some necessary control information. For example, the frame header may include a destination MAC address, a source MAC address, and a protocol type, etc., and the frame tail may include information such as a data frame check sequence (check code). Similarly, the processor core assembles the remaining multiple sub-data to correspondingly obtain multiple data frames, so as to obtain the first data frame corresponding to at least one first message. Exemplarily, when at least one message includes one message, the multiple data frames corresponding to the first message are the first data frame. Among them, the lengths corresponding to different types of messages are different. The length of each data frame conforms to the length specified by the MAC protocol. For example, the MAC protocol stipulates that the minimum length of a data frame is 64 bytes and the maximum length is 1518 bytes.

[0091] Since at least one processor core may include different numbers of processor cores, when the number of processor cores is different, different processor cores obtain the first message and send the first data frame. The following will be introduced and illustrated separately through the following 4 embodiments.

[0092] In the first possible embodiment, the at least one processor core includes one processor core.

[0093] Exemplarily, the schematic structural diagram of the communication system is as Figure 4As shown, at this time, at least one first message is obtained by the processor core and the first data frame is sent. Figure 4 Taking the communication system including 2 interfaces as an example. In this embodiment, one processor core can correspond to multiple interfaces. While increasing the number of interfaces, the area and cost of the communication system are reduced. When some components of the communication system (such as at least one processor core, aggregation and distribution module, interface and bus) are arranged on the chip, the area and cost of the chip are reduced.

[0094] In the second possible embodiment, the at least one processor core includes a first processor core and a second processor core. Optionally, the first processing core and the second processor core can be processor cores in the same processor or in different processors. The following will separately describe different situations.

[0095] In the first case, the first processor core and the second processor core are processor cores in the same processor. The first processor core can be used to obtain at least one first message and send the first data frame. The first processor core can also be called the transmit (TX) core. The second processor core can be used to read the second data frame from the aggregation and distribution module. The second data frame is the data frame corresponding to at least one second message. The second processor core can also be called the receive (RX) core. At this time, the structural schematic diagram of the communication system is as Figure 5 shown. Optionally, the transmit core and the receive core can be specified by the software running on the communication system. Figure 5 Taking the communication system including n interfaces as an example. In this embodiment, setting the first processor core as the transmit core and the second processor core as the receive core reduces the difficulty of software programming in the processor core (including the first processor core and the second processor core).

[0096] In the second case, the first processor core and the second processor core are not processor cores in the same processor. Exemplarily, the structure of the communication system is as Figure 6 shown. The first processor core can be used to obtain at least one first message and write at least one first message into the memory. The first processor core is also used to send the fourth indication information to the second processor core. The fourth indication information is used to instruct the second processor core to read at least one first message from the memory. The second processor core reads and processes at least one first message based on the fourth indication information to obtain the first data frame. The second processor core is also used to send the first data frame to the aggregation and distribution module. Figure 6 Taking the communication system including n interfaces as an example.

[0097] In the third case, the first processor core and the second processor core can be processor cores in the same processor or in different processors. Exemplarily, as Figure 7As shown, both the first processor core and the second processor core can be used to obtain the first message and send the first data frame. In this embodiment, multiple interfaces corresponding to two processor cores are utilized, improving the processing efficiency of the processor. Figure 7 Take a communication system including n interfaces as an example.

[0098] In the third possible embodiment, the at least one processor core includes a first processor core, a second processor core, and a third processor core. Among them, the first processor core is a sending core, the second processor core is a receiving core. The first processor core and the second processor core are processor cores in the same processor. The first processor core and the third processor core can be processor cores in the same processor or in different processors. Exemplarily, as Figure 8 shown, the third processor core can be used to obtain at least one first message and write at least one first message into the memory. The third processor core is also used to send fifth indication information to the first processor core. The fifth indication information is used to instruct the first processor core to read at least one first message from the memory. The first processor core reads and processes at least one first message from the memory to obtain a first data frame, and the first processor core sends the first data frame. The second processor core can be used to read a second data frame from the aggregation and distribution module. Optionally, the sending core and the receiving core can be specified by software running on the communication system. For example, the sending core and the receiving core can be specified by a program running in the third processor core. Figure 8 Take a communication system including 4 interfaces as an example for illustration.

[0099] In the fourth possible embodiment, the at least one processor core includes multiple first processor cores, multiple second processor cores, and a third processor core. The multiple first processor cores can also be referred to as a sending core family, and the multiple second processor cores can also be referred to as a receiving core family. At this time, the schematic structural diagram of the communication system is as Figure 9 shown Figure 9 The functions of the respective processor cores are similar to those of the processor cores shown in the above Figure 8 and will not be elaborated here. Figure 9 Take a communication system including n interfaces as an example for illustration.

[0100] In the above four possible embodiments, the functions of the memory, interfaces, and aggregation and distribution module included in the communication system are similar to those of the memory, interfaces, and aggregation and distribution module included in the communication system shown in Figure 2 and will not be elaborated here. In the above four possible embodiments, when the at least one processor core includes multiple processor cores, the multiple processor cores use the memory and the bus to achieve communication between the multiple processor cores. For example, the bus can include a 32-bit bus.

[0101] Further, at least one processor core sends (schedules) a first data frame to the aggregation and distribution module, specifically including: at least one processor core sends the first data frame according to the priorities of at least one first message. In practical applications, the first data frame may be sent in multiple beats, and multiple data frames are sent in each beat, and the multiple data frames corresponding to the first messages with higher priorities are sent first. Optionally, at least one processor core may also send (schedule) the first data frame according to queue management (i.e., the principle of first in first out), or at least one processor core may also send (schedule) the first data frame at a fixed time period. The embodiments of the present application do not make specific limitations on this.

[0102] Further, the method provided by the embodiments of the present application further includes:

[0103] S302: The aggregation and distribution module sends a first target data frame through at least one interface indicated by the first indication information. The first target data frame is determined by the aggregation and distribution module according to the media access control (MAC) protocol and the first data frame.

[0104] In a possible embodiment, the aggregation and distribution module includes an aggregation and distribution circuit. Combining Figure 8 , the structural schematic diagram of the communication system is as Figure 10 shown. The aggregation and distribution module sends the first target data frame through at least one interface, including: the aggregation and distribution circuit determines the first target data frame according to the MAC protocol and the first data frame; the aggregation and distribution circuit sends the first target data frame through at least one interface. The aggregation and distribution circuit is used to implement the aggregation and distribution functions, as well as some functions of the MAC protocol.

[0105] Specifically, the aggregation and distribution circuit determines the first target data frame according to the MAC protocol and the first data frame, including: the aggregation and distribution circuit checks whether the length of each data frame in the first data frame meets the length range defined according to the MAC protocol. For example, the MAC protocol defines that the minimum length of a data frame is 64 bytes and the maximum length is 1518 bytes. If a certain data frame does not meet the length range defined by the MAC protocol, for example, the length of a certain data frame is less than 64 bytes, the aggregation and distribution circuit fills the data frame according to the padding content defined by the MAC protocol so that the length of the filled data frame is equal to 64 bytes; the aggregation and distribution circuit is also used to perform a check on each data frame, and uses the check code included at the end of each data frame to check the data frame. For example, the FCS check algorithm is used for checking. If a certain data frame is abnormal, the data frame is discarded to obtain the first target data frame.

[0106] In another possible embodiment, the aggregation and distribution module includes an aggregation and distribution circuit and multiple digital circuits. The multiple digital circuits are in one-to-one correspondence with multiple interfaces. Combining Figure 8 , at this time, the structural schematic diagram of the communication system is asFigure 11 As shown in Figure 11 , the aggregation and distribution module sends a first target data frame through at least one interface indicated by the first indication information, including: the aggregation and distribution circuit sends a first data frame to the digital circuits corresponding to at least one interface according to the first indication information; the digital circuits determine the first target data frame according to the MAC protocol and the first data frame; the digital circuits send the first target data frame through at least one interface. Exemplarily, the interfaces indicated by the first indication information may include Interface 1 to Interface 4. The aggregation and distribution circuit respectively sends the first data frame to the digital circuits 1 to 4 corresponding to Interface 1 to Interface 4. The digital circuits 1 and 4 respectively determine the first target data frame according to the MAC protocol and the first data frame; and respectively send the first target data frame through Interface 1 and Interface 4. The aggregation and distribution circuit is used to implement the aggregation and distribution functions, and each digital circuit in the multiple data circuits is used to implement part of the MAC protocol functions. Figure 11 In Figure 11 , taking a communication system including 4 interfaces (which can be respectively represented as Interface 1 to Interface 4) and 4 digital circuits (which can be respectively represented as Digital Circuit 1 to Digital Circuit 4) as an example, Interface 1 corresponds to Digital Circuit 1, and so on, Interface 4 corresponds to Digital Circuit 4.

[0107] Specifically, the digital circuits determine the first target data frame according to the MAC protocol and the first data frame, including: the digital circuits check whether the length of each data frame in the first data frame meets the length range defined according to the MAC protocol. For example, the MAC protocol defines that the minimum length of a data frame is 64 bytes and the maximum length is 1518 bytes. If a certain data frame does not meet the length range defined by the MAC protocol, for example, the length of a certain data frame is less than 64 bytes, the digital circuits fill the data frame with the filling content defined by the MAC protocol so that the length of the filled data frame is equal to 64 bytes; the digital circuits are also used to check each data frame, and check the data frame using the check code included at the end of each data frame. For example, check using the FCS check algorithm. If a certain data frame is abnormal, the data frame is discarded, thereby obtaining the first target data frame.

[0108] Among them, the first target data frame includes multiple data frames, and the length of each data frame in the multiple data frames is greater than or equal to a first threshold. The first threshold is defined by the MAC protocol. For example, the first threshold may be 64 bytes.

[0109] Furthermore, the communication system further includes multiple PHYs, and the multiple PHYs and the multiple interfaces correspond one by one. Exemplarily, such as Figure 12As shown, the communication system may include four interfaces, which can be respectively represented as Interface 1 to Interface 4, and four PHYs, which can be respectively represented as PHY1 to PHY4. Among them, Interface 1 corresponds to PHY1, and so on, Interface 4 corresponds to PHY4. The aggregation and distribution module sends the first target data frame through at least one interface, including: the aggregation and distribution module sends the first target data frame to the corresponding PHY through at least one interface. For example, the aggregation and distribution module sends the first target data frame to PHY3 through Interface 3. Optionally, each of the multiple PHYs can be integrated on a chip, and the PHY can also be referred to as a PHY chip. Figure 12 Taking the communication system including four interfaces and four PHYs as an example.

[0110] Figure 13 It is a flowchart of a data transmission method provided by an embodiment of the present application. This method can be applied to the communication system provided above. This method includes the following steps.

[0111] S130: For each interface among the multiple interfaces, the aggregation and distribution module receives a second data frame through the interface. The second data frame is a data frame corresponding to at least one second message.

[0112] Specifically, the aggregation and distribution module can receive the second data frame through a bus and an interface. For example, the bus can include a 32-bit bus.

[0113] Among them, for each interface among the multiple interfaces, the interface can include MII, or a derivative interface of MII, such as GMII, SGMII, RMII, and RGMII, etc. MII or a derivative interface of MII is collectively referred to as a media-independent interface. The embodiment of the present application does not specifically limit the number of interfaces and the number of processor cores. For example, the number of interfaces can be greater than the number of processor cores. For example, the multiple interfaces can include n interfaces, and at least one processor core can include m processor cores, where n is greater than m, and n and m are integers. In practical applications, the number of n is related to the performance of the m processor cores, and can be specifically set according to actual requirements or the experience of relevant staff. The embodiment of the present application does not specifically limit this.

[0114] In addition, the at least one second message can include two first messages, or can include multiple second messages. The at least one second message can also be referred to as Ethernet data at the third layer (network layer) and above.

[0115] In a possible embodiment, the aggregation and distribution module includes an aggregation and distribution circuit. The aggregation and distribution module receives the second data frame through the interface, including: the aggregation and distribution circuit receives the second data frame through the interface.

[0116] In another possible embodiment, the aggregation and distribution module includes an aggregation and distribution circuit and multiple digital circuits. The multiple digital circuits correspond to the multiple interfaces one by one. For example, interface 1 corresponds to digital circuit 1, and interface n corresponds to digital circuit n. The aggregation and distribution module receives the second data frame through the interface, including: the digital circuit corresponding to the interface receives the second data frame through the interface, and the digital circuit sends the second data frame to the aggregation and distribution circuit through the bus. For example, digital circuit 1 receives the second data frame through interface 1 and sends the second data frame to the aggregation and distribution circuit through the bus. Digital circuit n receives the second data frame through interface n and sends the second data frame to the aggregation and distribution circuit through the bus.

[0117] Furthermore, the communication system further includes multiple PHYs. The multiple PHYs correspond to the multiple interfaces one by one. For example, the communication system includes n interfaces and n PHYs. Interface 1 corresponds to PHY1, and so on. Interface n corresponds to PHYn. The aggregation and distribution module receives the second data frame through the interface, including: the aggregation and distribution module receives the second data frame from the corresponding PHY through the interface. For example, the aggregation and distribution module receives the second data frame from PHY1 through interface 1, and the aggregation and distribution module receives the second data frame from PHYn through interface n. Each PHY in the multiple PHYs can be integrated on a chip, and the PHY can also be referred to as a PHY chip.

[0118] Furthermore, the method provided in the embodiment of the present application further includes:

[0119] S131: The aggregation and distribution module stores the second target data frame and sends second indication information to at least one processor core. The second indication information is used to instruct the at least one processor core to read the second target data frame from the aggregation and distribution module. The second target data frame is determined by the aggregation and distribution module according to the media access control (MAC) protocol and the second data frame.

[0120] In a possible embodiment, the aggregation and distribution module includes an aggregation and distribution circuit. The aggregation and distribution module stores the second target data frame and sends second indication information to at least one processor core, including: the aggregation and distribution circuit determines the second target data frame according to the MAC protocol and the second data frame; the aggregation and distribution circuit stores the second target data frame and sends second indication information to at least one processor core.

[0121] Specifically, the aggregation and distribution circuit determines the second target data frame according to the MAC protocol and the second data frame, including: the aggregation and distribution circuit checks whether the length of each data frame in the second data frame meets the length range defined according to the MAC protocol. For example, the MAC protocol defines that the minimum length of a data frame is 64 bytes and the maximum length is 1518 bytes. If a certain data frame does not meet the length range defined by the MAC protocol, for example, the length of a certain data frame is less than 64 bytes, the aggregation and distribution circuit fills the data frame according to the padding content defined by the MAC protocol so that the length of the filled data frame is equal to 64 bytes; the aggregation and distribution circuit is also used to check each data frame, and uses the check code included at the end of each data frame to check the data frame. For example, it uses the FCS check algorithm for checking. If a certain data frame is abnormal, the data frame is discarded, thereby obtaining the second target data frame.

[0122] In another possible embodiment, the aggregation and distribution module includes an aggregation and distribution circuit and multiple digital circuits. The aggregation and distribution module stores the second target data frame and sends second indication information to at least one processor core, including: the digital circuit receives the second data frame and determines and sends the second target data frame to the aggregation and distribution circuit according to the MAC protocol and the second data frame; the aggregation and distribution circuit stores the second target data frame and sends second indication information to at least one processor core.

[0123] Specifically, the digital circuit checks whether the length of each data frame in the second data frame meets the length range defined according to the MAC protocol. For example, the MAC protocol defines that the minimum length of a data frame is 64 bytes and the maximum length is 1518 bytes. If a certain data frame does not meet the length range defined by the MAC protocol, for example, the length of a certain data frame is less than 64 bytes, the digital circuit fills the data frame according to the padding content defined by the MAC protocol so that the length of the filled data frame is equal to 64 bytes; the digital circuit is also used to check each data frame, and uses the check code included at the end of each data frame to check the data frame. For example, it uses the FCS check algorithm for checking. If a certain data frame is abnormal, the data frame is discarded, thereby obtaining the second target data frame.

[0124] Among them, the second target data frame includes multiple data frames, and the length of each data frame in the multiple data frames is greater than or equal to the first threshold. The first threshold is defined by the MAC protocol. For example, the first threshold can be 64 bytes.

[0125] In addition, when at least one processor core includes multiple processor cores, the multiple processor cores can be processor cores in the same processor or processor cores in different processors. For example, the multiple processor cores include a first processor core, a second processor core, and a third processor core. The first processor core, the second processor core, and the third processor core can all be processor cores in a CPU, or the first processor core and the second processor core can be processor cores in a CPU, and the third processor core can be a processor core in an NPU. The embodiments of the present application do not make specific limitations on this.

[0126] In addition, the processor core can include a reduced instruction set computer (RISC). For example, RISC can include a PRU and a deterministic realtime unit (DRU), etc. In a possible embodiment, the processor core can be a 32-bit RISC with an operating frequency of 200 MHz to 400 MHz. The processor core can also be referred to as a RISC core or a RISC realtime core. In practical applications, the processor core can implement different functions by running different programs, that is, the functions of the processor core are programmable. For example, the processor core can implement a sending function by running a sending program, and the processor core can implement a receiving function by running a receiving program.

[0127] Optionally, when at least one processor core includes multiple processor cores, the multiple processor cores can be the same processor cores or different processor cores. For example, the multiple processor cores include a first processor core, a second processor core, and a third processor core. The first processor core, the second processor core, and the third processor core can all be RISC cores; or the first processor core and the second processor core are RISC cores, and the third processor core is a CPU core. The embodiments of the present application do not make specific limitations on this comparison.

[0128] Further, at least one processor core reads a second target data frame from the aggregation and distribution module based on the second indication information, and processes the second target data frame to obtain at least one second message. Specifically, at least one processor core splits the second target data frame to obtain multiple sub-data, that is, removes the frame headers and frame tails of each data frame included in the second target data frame, correspondingly obtains multiple sub-data, and parses the multiple sub-data to obtain at least one message type, and reorganizes the multiple sub-data belonging to the same message type to obtain at least one second message. Further, at least one processor core writes at least one second message into the memory, and uses the memory to implement communication between multiple processor cores.

[0129] In a possible embodiment, the aggregation and distribution module forwards the second target data frame to at least one of the multiple interfaces according to preset information, where the preset information includes at least one interface. For example, the aggregation and distribution module directly forwards the second target data frame to at least one of the multiple interfaces according to the forwarding entry items pre-configured by at least one processor core during the initialization process. This improves the forwarding efficiency.

[0130] In another possible embodiment, the aggregation and distribution module sends the second target data frame to at least one processor core, and at least one processor core starts the forwarding function and realizes the forwarding through the steps of S301 and S302.

[0131] For the data transmission method provided in this application, on the sending side: at least one processor core obtains and processes at least one first message to obtain a first data frame, and at least one processor core sends the first data frame and first indication information to the aggregation and distribution module. The first indication information is used to indicate at least one interface. The aggregation and distribution module determines a first target data frame according to the MAC protocol and the first data frame, and sends the first target data frame to the corresponding PHY through at least one interface indicated by the indication information; on the receiving side: the aggregation and distribution module receives a second data frame from the corresponding PHY through the interface, and determines a second target data frame according to the MAC protocol and the second data frame. The aggregation and distribution module stores the second target data frame and sends second indication information to at least one processor core. The second indication information is used to indicate that the aggregation and distribution module stores the second target data frame. At least one processor core reads the second target data frame based on the second indication information and processes the second target data frame to obtain at least one second message. During this process, the aggregation and distribution module realizes the function of the MAC protocol. The aggregation and distribution module realizes the function originally implemented by the processor core, reducing the load of the processor core, enabling at least one processor core to correspond to multiple interfaces, where the multiple interfaces are greater than the number of at least one processor core. Since the area and cost of the aggregation and distribution module are smaller than those of the processor core, compared with Figure 1 the processor core implementing the function of the MAC protocol, with one processor core corresponding to one interface, while increasing the number of interfaces, the area and cost of the communication system are reduced.

[0132] Based on this, an embodiment of this application further provides a communication system, which includes at least one processor core, an aggregation and distribution module, and multiple interfaces. The communication system can be the communication system shown in the above Figure 2 、 Figures 4 to 12 . In the embodiment of this application, at least one processor core can be used to execute S301 in the above method embodiment, and / or other steps described herein, etc.; the aggregation and distribution module can be used to execute S302, S130, and S131 in the above method embodiment, and / or other steps described herein, etc.

[0133] It can be understood that all the relevant contents regarding the specific structures of at least one processor core, the aggregation and distribution module, and multiple interfaces, as well as all the steps involved in the above method embodiments, can be cited in the embodiments of this communication system, and the embodiments of this application will not elaborate on them here.

[0134] In another aspect of this application, an electronic device is further provided. The electronic device includes a memory and a communication system. The communication system includes at least one processor core and an aggregation and distribution module. The memory is used to store computer instructions, and the at least one processor core and the aggregation and distribution module are used to execute the computer instructions so that the electronic device implements the data transmission processing method provided above.

[0135] It can be understood that all the relevant contents regarding the steps involved in the above method embodiments can be cited in the embodiments of the communication system and the embodiments of this electronic device, and the embodiments of this application will not elaborate on them here.

[0136] In several embodiments provided by this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed.

[0137] The units described as separate components may or may not be physically separated. The components shown as units may be one physical unit or multiple physical units, that is, they can be located in one place or distributed to multiple different places. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0138] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. The readable storage medium may include various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories, random access memories, magnetic disks, or optical discs. Based on such an understanding, the technical solution of the embodiments of this application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product.

[0139] In another embodiment of this application, a readable storage medium is further provided. Computer-executable instructions are stored in the readable storage medium. When the computer instructions run on the communication system, the communication system is enabled to execute the steps in the above method embodiments.

[0140] In yet another embodiment of the present application, a computer program product is further provided. When the computer program product runs on a communication system, the communication system is caused to execute the steps in the above method embodiments.

[0141] Finally, it should be noted that the above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A communication system, characterized in that, The communication system includes: at least one processor core, an aggregation and distribution module, and multiple interfaces; At least one of the processor cores is configured to send a first data frame and first indication information to the aggregation and distribution module, the first indication information being used to indicate at least one of the multiple interfaces, and the first data frame being a data frame corresponding to at least one first packet; The aggregation and distribution module is configured to send a first target data frame through at least one of the interfaces indicated by the first indication information, the first target data frame being determined by the aggregation and distribution module according to the media access control (MAC) protocol and the first data frame.

2. The communication system according to claim 1, wherein The aggregation and distribution module includes an aggregation and distribution circuit; The aggregation and distribution circuit is configured to determine the first target data frame according to the MAC protocol and the first data frame; The aggregation and distribution circuit is further configured to send the first target data frame through at least one of the interfaces.

3. The communication system according to claim 1, wherein The aggregation and distribution module includes an aggregation and distribution circuit and multiple digital circuits, and the multiple digital circuits correspond to the multiple interfaces one by one; The aggregation and distribution circuit is configured to send the first data frame to the digital circuits corresponding to at least one of the interfaces according to the first indication information; The digital circuit is further configured to determine the first target data frame according to the MAC protocol and the first data frame; The digital circuit is further configured to send the first target data frame through at least one of the interfaces.

4. The communication system according to any one of claims 1-3, wherein The interface includes a media independent interface.

5. The communication system according to any one of claims 1-4, wherein The first target data frame includes multiple data frames, and the length of each of the multiple data frames is greater than or equal to a first threshold.

6. The communication system according to any one of claims 1-5, characterized in that, The communication system further includes: multiple physical layers, and the multiple physical layers correspond to the multiple interfaces one by one; The aggregation and distribution module is specifically configured to send the first target data frame to the corresponding physical layer through at least one of the interfaces.

7. The communication system according to any one of claims 1-6, wherein At least one of the processor cores includes a reduced instruction set computer.

8. The communication system according to any one of claims 1-7, wherein At least one of the processor cores is further configured to obtain the at least one first packet and process the at least one first packet to obtain the first data frame.

9. A communication system, characterized in that, The communication system includes: at least one processor core, an aggregation and distribution module, and multiple interfaces; The aggregation and distribution module is configured to, for each of the multiple interfaces, receive a second data frame through the interface, the second data frame being a data frame corresponding to at least one second packet; The convergence and distribution module is further configured to store the second target data frame and send second indication information to at least one of the processor cores, where the second indication information is used to instruct at least one of the processor cores to read the second target data frame from the convergence and distribution module, and the second target data frame is determined by the convergence and distribution module according to the media access control (MAC) protocol and the second data frame.

10. The communication system according to claim 9, characterized in that, The convergence and distribution module includes a convergence and distribution circuit; The convergence and distribution circuit is configured to receive the second data frame through the interface; The convergence and distribution circuit is further configured to determine the second target data frame according to the MAC protocol and the second data frame; The convergence and distribution circuit is further configured to store the second target data frame and send the second indication information to at least one of the processor cores.

11. The communication system according to claim 9, characterized in that, The convergence and distribution module includes a convergence and distribution circuit and a plurality of digital circuits, and the plurality of digital circuits correspond to the plurality of interfaces one by one; The digital circuit is configured to receive the second data frame through the corresponding interface; The digital circuit is configured to determine the second target data frame according to the MAC protocol and the second data frame; The convergence and distribution circuit is further configured to store a plurality of the second target data frames and send the second indication information to at least one of the processor cores.

12. The communication system according to any one of claims 9-11, wherein The interface includes a media independent interface.

13. The communication system according to any one of claims 9-12, wherein The second target data frame includes a plurality of data frames, and the length of each of the plurality of data frames is greater than or equal to a first threshold.

14. The communication system according to any one of claims 9-13, characterized in that, The communication system further includes a plurality of physical layers, and the plurality of physical layers correspond to the plurality of interfaces one by one, The convergence and distribution module is specifically further configured to receive the second data frame from the corresponding physical layer through the interface.

15. The communication system according to any one of claims 9-14, wherein At least one of the processor cores includes a reduced instruction set computer.

16. The communication system according to any one of claims 9-15, wherein At least one of the processor cores is configured to read the second target data frame from the convergence and distribution module based on the second indication information and process the second target data frame to obtain at least one second message.

17. The communication system according to any one of claims 9-16, wherein The convergence and distribution module is further configured to forward the second target data frame to at least one of the plurality of interfaces according to preset information, and the preset information includes at least one of the interfaces.

18. A data transmission method, characterized in that, The method is applied to a communication system, and the communication system includes: at least one processor core, a convergence and distribution module, and a plurality of interfaces; At least one of the processor cores sends a first data frame and first indication information to the convergence and distribution module, where the first indication information is used to indicate at least one of the plurality of interfaces, and the first data frame is a data frame corresponding to at least one first message; The aggregation and distribution module sends a first target data frame through at least one of the interfaces indicated by the first indication information, where the first target data frame is determined by the aggregation and distribution module according to the media access control (MAC) protocol and the first data frame.

19. The data transmission method according to claim 18, wherein The aggregation and distribution module includes an aggregation and distribution circuit. The aggregation and distribution module sending the first target data frame through at least one of the interfaces includes: The aggregation and distribution circuit determines the first target data frame according to the MAC protocol and the first data frame; The aggregation and distribution circuit sends the first target data frame through at least one of the interfaces.

20. The data transmission method according to claim 18, wherein The aggregation and distribution module includes an aggregation and distribution circuit and a plurality of digital circuits, where the plurality of digital circuits correspond to the plurality of interfaces one by one. The aggregation and distribution module sending the first target data frame through at least one of the interfaces indicated by the first indication information includes: The aggregation and distribution circuit sends the first data frame to the digital circuits corresponding to at least one of the interfaces according to the first indication information; The digital circuits determine the first target data frame according to the MAC protocol and the first data frame; The digital circuits send the first target data frame through at least one of the interfaces.

21. The data transmission method according to any one of claims 18 - 20, characterized in that The interface includes a media independent interface.

22. The data transmission method according to any one of claims 18 - 21, characterized in that The first target data frame includes a plurality of data frames, and the length of each of the plurality of data frames is greater than or equal to a first threshold.

23. The data transmission method according to any one of claims 18-22, characterized in that, The communication system further includes a plurality of physical layers, where the plurality of physical layers correspond to the plurality of interfaces one by one. The aggregation and distribution module sending the first target data frame through at least one of the interfaces includes: The aggregation and distribution module sends the first target data frame to the corresponding physical layer through at least one of the interfaces.

24. The data transmission method according to any one of claims 18 - 23, characterized in that At least one of the processor cores includes a reduced instruction set computer.

25. The data transmission method according to any one of claims 18-24, characterized in that, The method further includes: At least one of the processor cores obtains at least one of the first messages and processes at least one of the first messages to obtain the first data frame.

26. A data transmission method, characterized in that, The method is applied to a communication system, where the communication system includes: at least one processor core, an aggregation and distribution module, and a plurality of interfaces; For each of the plurality of interfaces, the aggregation and distribution module receives a second data frame through the interface, where the second data frame is a data frame corresponding to at least one second message; The aggregation and distribution module stores a second target data frame and sends second indication information to at least one of the processor cores, where the second indication information is used to instruct at least one of the processor cores to read the second target data frame from the aggregation and distribution module, and the second target data frame is determined by the aggregation and distribution module according to the media access control (MAC) protocol and the second data frame.

27. The data transmission method according to claim 26, wherein The aggregation and distribution module includes an aggregation and distribution circuit. The aggregation and distribution module receives a second data frame through the interface, including: The aggregation and distribution circuit receives the second data frame through the interface; The aggregation and distribution module stores a second target data frame and sends second indication information to at least one of the processor cores, including: The aggregation and distribution circuit determines the second target data frame according to the MAC protocol and the second data frame; The aggregation and distribution circuit stores the second target data frame and sends the second indication information to at least one of the processor cores.

28. The data transmission method according to claim 26, wherein The aggregation and distribution module includes an aggregation and distribution circuit and a plurality of digital circuits. The plurality of digital circuits correspond to the plurality of interfaces one by one. The aggregation and distribution module receives a second data frame through the interface, including: The digital circuit corresponding to the interface receives the second data frame through the interface; The aggregation and distribution module stores a second target data frame and sends second indication information to at least one of the processor cores, including: The digital circuit determines the second target data frame according to the MAC protocol and the second data frame; The aggregation and distribution circuit stores the second target data frame and sends the second indication information to at least one of the processor cores.

29. The data transmission method according to any one of claims 26-28, wherein: The interface includes a media independent interface.

30. The data transmission method according to any one of claims 26-29, wherein: The second target data frame includes a plurality of data frames, and the length of each of the plurality of data frames is greater than or equal to a first threshold.

31. The data transmission method according to any one of claims 26-30, characterized in that, The communication system further includes a plurality of physical layers. The plurality of physical layers correspond to the plurality of interfaces one by one. The aggregation and distribution module receives a second data frame through the interface, including: The aggregation and distribution module receives the second data frame from the corresponding physical layer through the interface.

32. The data transmission method according to any one of claims 26-31, wherein: At least one of the processor cores includes a reduced instruction set computer.

33. The data transmission method according to any one of claims 26-32, characterized in that, The method further includes: At least one of the processor cores reads the second target data frame from the aggregation and distribution module based on the second indication information and processes the second target data frame to obtain at least one second message.

34. The data transmission method according to any one of claims 26-33, characterized in that, The method further includes: The aggregation and distribution module forwards the second target data frame to at least one of the plurality of interfaces according to preset information, and the preset information includes at least one of the interfaces.

35. An electronic device, characterized in that, The electronic device includes a communication system and a memory. The memory is used to store computer instructions. The communication system includes at least one processor core and an aggregation and distribution module. The communication system is the communication system according to any one of claims 1-8 or claims 9-17.

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