Scanning circuit and display device

Abstract

The scanning circuit includes: a first clock signal line (CKL); a second clock signal line (CBL); and a first scanning unit (SU1), a first dummy scanning unit (DSU1), and a second scanning unit (SU2), the first scanning unit (SU1), the first dummy scanning unit (DSU1), and the second scanning unit (SU2) being sequentially arranged in a region including the plurality of scanning units and the one or more dummy scanning units (DSU). Each scanning unit includes a first pad (PAD1) and a second pad (PAD2). The first pad (PAD1) includes a gate (G7) of the seventh transistor (T7). The second pad (PAD2) includes a gate (G1) of the first transistor (T1) and a gate (G3) of the third transistor (T3). The first dummy scanning unit (DSU1) includes a first dummy extension (DE1). A first dummy extension (DE1) is connected to a second pad (PAD2) in the second scan cell (SU2), and is configured to transfer one of the first clock signal (CK) or the second clock signal (CB) to a gate (G1) of the first transistor (T1) and a gate (G3) of the third transistor (T3) in the second scan cell (SU2).

Description

Technical Field

[0001] The present invention relates to display technology, and in particular, to a scanning circuit and a display device. Background Art

[0002] An image display device includes a driver for controlling image display in each of a plurality of pixels. The driver is a transistor-based circuit, which includes a gate driving circuit and a data driving circuit. The gate driving circuit is formed by cascading a plurality of shift register units. Each shift register unit outputs a gate driving signal to one of a plurality of gate lines. The gate driving signal from the gate driving circuit scans row by row through the gate lines to control each row of transistors to be in an on / off state. The gate driving circuit can be integrated into an on-array gate (GOA) circuit, and the GOA circuit can be directly formed in the array substrate of the display panel. Summary of the Invention

[0003] In one aspect, the present disclosure provides a scanning circuit, including: a first clock signal line; a second clock signal line; and a first scanning unit, a first dummy scanning unit, and a second scanning unit, which are arranged in sequence in a region including a plurality of scanning units and one or more dummy scanning units; wherein each scanning unit includes a first pad and a second pad; the first pad includes the gate of a seventh transistor; the second pad includes the gates of a first transistor and a third transistor; the first dummy scanning unit includes a first dummy extension; the first dummy extension is connected to the second pad in the second scanning unit and is configured to transmit one of the first clock signal or the second clock signal to the gates of the first transistor and the third transistor in the second scanning unit; and the orthographic projection of the first dummy extension on the substrate at least partially overlaps at least one of the orthographic projection of the first clock signal line on the substrate or the orthographic projection of the second clock signal line on the substrate.

[0004] Optionally, at the position of the region having the first dummy scanning unit, the first dummy extension is connected to one of the first clock signal line or the second clock signal line.

[0005] Optionally, the first dummy extension in the first dummy scanning unit is further connected to the first electrode of a second transistor in the second scanning unit and is configured to transmit one of the first clock signal or the second clock signal to the first electrode of the second transistor in the second scanning unit.

[0006] Optionally, the second scanning unit includes a second extension connected to the first pad in the second scanning unit; wherein, the first pad in the second scanning unit includes the gate of the seventh transistor in the second scanning unit; and the second extension in the second scanning unit is connected to the other one of the first clock signal line or the second clock signal line, and is configured to transmit the other one of the first clock signal or the second clock signal to the gate of the seventh transistor in the second scanning unit.

[0007] Optionally, the first pad in the second scanning unit is connected to the first electrode of the fifth transistor in the second scanning unit; and the second extension in the second scanning unit is configured to transmit the other one of the first clock signal or the second clock signal to the first electrode of the fifth transistor in the second scanning unit through the first pad in the second scanning unit.

[0008] Optionally, the second extension in the second scanning unit is connected to the first electrodes of the fourth transistor and the sixth transistor in the second scanning unit, and is configured to transmit the other one of the first clock signal or the second clock signal to the first electrodes of the fourth transistor and the sixth transistor in the second scanning unit.

[0009] Optionally, the first scanning unit includes a first extension connected to the first pad in the first scanning unit; wherein, the first pad in the first scanning unit includes the gate of the seventh transistor in the first scanning unit; the first pad in the first scanning unit is connected to the first electrode of the fifth transistor in the first scanning unit; and the first extension in the first scanning unit is connected to one of the first clock signal line or the second clock signal line, and is configured to transmit one of the first clock signal or the second clock signal to the gate of the seventh transistor and the first electrode of the fifth transistor in the first scanning unit.

[0010] Optionally, the first pad in the first scanning unit is connected to the first electrode of the fifth transistor in the first scanning unit; and the first extension in the first scanning unit is configured to transmit one of the first clock signal or the second clock signal to the first electrode of the fifth transistor in the first scanning unit through the first pad in the first scanning unit.

[0011] Optionally, the first extension in the first scan unit is connected to the first electrodes of the fourth transistor and the sixth transistor in the first scan unit, and is configured to transmit the other one of the first clock signal and the second clock signal to the first electrodes of the fourth transistor and the sixth transistor in the first scan unit.

[0012] Optionally, the first dummy scan unit further includes a first dummy pad; the first dummy pad in the first dummy scan unit includes the dummy gate of a seventh dummy transistor; and the first dummy extension is connected to the first dummy pad.

[0013] Optionally, the first dummy pad in the first dummy scan unit is not connected to the first dummy electrode of the fifth dummy transistor in the first dummy scan unit; the first dummy electrode and the second dummy electrode of the fifth dummy transistor in the first dummy scan unit and the first dummy electrode and the second dummy electrode of the fourth dummy transistor are part of an integral structure; and the integral structure is configured to be supplied with a second power signal.

[0014] Optionally, the first dummy extension in the first dummy scan unit is not connected to the second dummy electrode of the ninth dummy transistor in the first dummy scan unit; the first dummy electrode and the second dummy electrode of the ninth dummy transistor in the first dummy scan unit are part of an integral structure; and the integral structure is configured to be supplied with a second power signal.

[0015] Optionally, the first extension in the first scan unit is not connected to any component of a dummy transistor or a dummy capacitor in any dummy scan unit; and the first extension in the first scan unit is not connected to any component of a transistor or a capacitor in the second scan unit.

[0016] Optionally, the scan circuit further includes a second dummy scan unit in the region including a plurality of scan units and one or more dummy scan units; wherein, the first scan unit, the second dummy scan unit, the first dummy scan unit, and the second scan unit are arranged in sequence.

[0017] Optionally, the second dummy scan unit is electrically isolated from the first clock signal line and is electrically isolated from the second clock signal line.

[0018] Optionally, the second dummy scan unit includes a second dummy extension in the second dummy scan unit; and the second dummy extension in the second dummy scan unit is electrically isolated from the first clock signal line and is electrically isolated from the second clock signal line.

[0019] Optionally, the second dummy scan unit further includes a first dummy pad connected to the second dummy extension in the second dummy scan unit; and the first dummy pad and the second dummy extension in the second dummy scan unit are electrically isolated from the first clock signal line and are electrically isolated from the second clock signal line.

[0020] Optionally, the second dummy extension in the second dummy scan unit is not connected to any component of the dummy transistor or the dummy capacitor in the first dummy scan unit; and the second dummy extension in the second dummy scan unit is not connected to any component of the transistor or the capacitor in the first scan unit or the second scan unit.

[0021] Optionally, the first dummy pad in the second dummy scan unit is connected to the dummy first electrode of the fifth dummy transistor in the second dummy scan unit; the dummy first electrode and the dummy second electrode of the fifth dummy transistor and the dummy first electrode and the dummy second electrode of the fourth dummy transistor in the second dummy scan unit are part of an integral structure; and the integral structure is configured to be supplied with a second power signal.

[0022] In another aspect, the present disclosure provides a scan circuit including: a first clock signal line; a second clock signal line; and a first scan unit, a first dummy scan unit, and a second scan unit, the first scan unit, the first dummy scan unit, and the second scan unit being arranged in sequence in a region including a plurality of scan units and one or more dummy scan units; wherein each scan unit includes a first pad; the first pad includes the gate of a seventh transistor; the scan circuit further includes a second extension; the second extension is connected to one of the first clock signal line or the second clock signal line at a position in the region having the first dummy scan unit; and the second extension is connected to the first pad in the second scan circuit and is configured to transmit one of the first clock signal or the second clock signal to the gate of the seventh transistor.

[0023] In another aspect, the present disclosure provides a display device including the scan circuit described herein and a display panel connected to the scan circuit. Description of the Drawings

[0024] According to various disclosed embodiments, the following drawings are merely examples for illustrative purposes and are not intended to limit the scope of the present invention.

[0025] Figure 1 is a circuit diagram of a corresponding scan unit of a scan circuit according to some embodiments of the present disclosure.

[0026] Figure 2 showsFigure 1 A timing diagram of the operation of the corresponding scanning unit shown.

[0027] Figure 3 It is a circuit diagram of the corresponding scanning unit of the scanning circuit in some embodiments according to the present disclosure.

[0028] Figure 4 It shows Figure 3 A timing diagram of the operation of the corresponding scanning unit shown.

[0029] Figure 5 It is a circuit diagram of the corresponding scanning unit of the scanning circuit in some embodiments according to the present disclosure.

[0030] Figure 6 It is a circuit diagram of the corresponding scanning unit of the scanning circuit in some embodiments according to the present disclosure.

[0031] Figure 7 It is a circuit diagram of the corresponding scanning unit of the scanning circuit in some embodiments according to the present disclosure.

[0032] Figure 8 It is a circuit diagram of the corresponding scanning unit of the scanning circuit in some embodiments according to the present disclosure.

[0033] Figure 9 It is a plan view of an array substrate in some embodiments according to the present disclosure.

[0034] Figure 10A It is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0035] Figure 10B It is a timing diagram showing the operation of a pixel driving circuit in some embodiments according to the present disclosure.

[0036] Figure 11 It is a schematic diagram showing one or more scanning circuits in a display device in some embodiments according to the present disclosure.

[0037] Figure 12 It is a schematic diagram showing a first scanning circuit in a display device in some embodiments according to the present disclosure.

[0038] Figure 13 It is a schematic diagram showing a second scanning circuit in a display device in some embodiments according to the present disclosure.

[0039] Figure 14A It is a schematic diagram showing the structure of multiple scanning units in multiple rows of a scanning circuit in some embodiments according to the present disclosure.

[0040] Figure 14B It shows Figure 14ASchematic diagram of the structure of the semiconductor material layer in the scanning circuit shown.

[0041] Figure 14C It shows Figure 14A Schematic diagram of the structure of the first conductive layer in the scanning circuit shown.

[0042] Figure 14D It shows Figure 14A Schematic diagram of the structure of the second conductive layer in the scanning circuit shown.

[0043] Figure 14E It shows Figure 14A Schematic diagram of the structure of the first signal line layer in the scanning circuit shown.

[0044] Figure 14F It shows Figure 14A Schematic diagram of the structure of the second signal line layer in the scanning circuit shown.

[0045] Figure 14G It shows Figure 14A Schematic diagram of the connection of the first connection line and the second connection line in the scanning circuit shown.

[0046] Figure 15A Schematic diagram of the structure of multiple scanning units in multiple rows of the scanning circuit according to some embodiments of the present disclosure.

[0047] Figure 15B It shows Figure 15A Schematic diagram of the structure of the semiconductor material layer in the scanning circuit shown.

[0048] Figure 15C It shows Figure 15A Schematic diagram of the structure of the first conductive layer in the scanning circuit shown.

[0049] Figure 15D It shows Figure 15A Schematic diagram of the structure of the second conductive layer in the scanning circuit shown.

[0050] Figure 15E It shows Figure 15A Schematic diagram of the structure of the first signal line layer in the scanning circuit shown.

[0051] Figure 15F It shows Figure 15A Schematic diagram of the structure of the second signal line layer in the scanning circuit shown.

[0052] Figure 15G It shows Figure 15A Schematic diagram of the structure of the third signal line layer in the scanning circuit shown.

[0053] Figure 15His a schematic diagram showing Figure 15A the connection between the first connection line and the second connection line in the scanning circuit shown

[0054] Figure 16A is a schematic diagram showing the structure of multiple scan units in multiple rows of a scanning circuit according to some embodiments of the present disclosure

[0055] Figure 16B is a schematic diagram showing Figure 16A the structure of the semiconductor material layer in the scanning circuit shown

[0056] Figure 16C is a schematic diagram showing Figure 16A the structure of the first conductive layer in the scanning circuit shown

[0057] Figure 16D is a schematic diagram showing Figure 16A the structure of the second conductive layer in the scanning circuit shown

[0058] Figure 16E is a schematic diagram showing Figure 16A the structure of the first signal line layer in the scanning circuit shown

[0059] Figure 16F is a schematic diagram showing Figure 16A the structure of the second signal line layer in the scanning circuit shown

[0060] Figure 16G is a schematic diagram showing Figure 16A the structure of the third signal line layer in the scanning circuit shown

[0061] Figure 17A is a schematic diagram showing the structure of multiple scan units in multiple rows of scan units and one or more dummy scan units in one or more rows of dummy scan units in a scanning circuit according to some embodiments of the present disclosure

[0062] Figure 17B is a schematic diagram showing Figure 17A the structure of the semiconductor material layer in the scanning circuit shown

[0063] Figure 17C is a schematic diagram showing Figure 17A the structure of the first conductive layer in the scanning circuit shown

[0064] Figure 17D is a schematic diagram showing Figure 17A the structure of the second conductive layer in the scanning circuit shown

[0065] Figure 17E is a schematic diagram showing Figure 17ASchematic diagram of the structure of the first signal line layer in the scanning circuit shown.

[0066] Figure 17F It shows Figure 17A Schematic diagram of the structure of the second signal line layer in the scanning circuit shown.

[0067] Figure 17G It shows Figure 17A Schematic diagram of the connection of the first connection line in the scanning circuit shown.

[0068] Figure 18A Schematic diagram of the structure of multiple scan units in multiple rows of scan units and one or more dummy scan units in one or more rows of dummy scan units in the scanning circuit according to some embodiments of the present disclosure.

[0069] Figure 18B It shows Figure 18A Schematic diagram of the structure of the semiconductor material layer in the scanning circuit shown.

[0070] Figure 18C It shows Figure 18A Schematic diagram of the structure of the first conductive layer in the scanning circuit shown.

[0071] Figure 18D It shows Figure 18A Schematic diagram of the structure of the second conductive layer in the scanning circuit shown.

[0072] Figure 18E It shows Figure 18A Schematic diagram of the structure of the first signal line layer in the scanning circuit shown.

[0073] Figure 18F It shows Figure 18A Schematic diagram of the structure of the second signal line layer in the scanning circuit shown.

[0074] Figure 18G It shows Figure 18A Schematic diagram of the structure of the third signal line layer in the scanning circuit shown.

[0075] Figure 18H It shows Figure 18A Schematic diagram of the connection of the first connection line in the scanning circuit shown.

[0076] Figure 19A Schematic diagram of the structure of multiple scan units in multiple rows of scan units and one or more dummy scan units in one or more rows of dummy scan units in the scanning circuit according to some embodiments of the present disclosure.

[0077] Figure 19B It shows Figure 19ASchematic diagram of the structure of the semiconductor material layer in the scanning circuit shown.

[0078] Figure 19C Is a schematic diagram showing Figure 19A Schematic diagram of the structure of the first conductive layer in the scanning circuit shown.

[0079] Figure 19D Is a schematic diagram showing Figure 19A Schematic diagram of the structure of the second conductive layer in the scanning circuit shown.

[0080] Figure 19E Is a schematic diagram showing Figure 19A Schematic diagram of the structure of the first signal line layer in the scanning circuit shown.

[0081] Figure 19F Is a schematic diagram showing Figure 19A Schematic diagram of the structure of the second signal line layer in the scanning circuit shown.

[0082] Figure 19G Is a schematic diagram showing Figure 19A Schematic diagram of the structure of the third signal line layer in the scanning circuit shown.

[0083] Figure 20 Is a schematic diagram showing the structure of a part of one or more scanning circuits according to some embodiments of the present disclosure.

[0084] Figure 21A Is a schematic diagram showing the structure of multiple scanning units in multiple rows of scanning units and one or more dummy scanning units in one or more rows of dummy scanning units in the scanning circuit according to some embodiments of the present disclosure.

[0085] Figure 21B Is a schematic diagram showing Figure 21A Schematic diagram of the structure of the semiconductor material layer in the scanning circuit shown.

[0086] Figure 21C Is a schematic diagram showing Figure 21A Schematic diagram of the structure of the first conductive layer in the scanning circuit shown.

[0087] Figure 21D Is a schematic diagram showing Figure 21A Schematic diagram of the structure of the second conductive layer in the scanning circuit shown.

[0088] Figure 21E Is a schematic diagram showing Figure 21A Schematic diagram of the structure of the first signal line layer in the scanning circuit shown.

[0089] Figure 21F Is a schematic diagram showing Figure 21A Schematic diagram of the structure of the second signal line layer in the scanning circuit shown.

[0090] Figure 21G It shows Figure 21A A schematic diagram showing the connection of the first clock signal line and the second clock signal line in the scanning circuit shown.

[0091] Figure 22A A schematic diagram showing the structure of multiple scan units in multiple scan rows and one or more dummy scan units in one or more rows of dummy scan units in the scanning circuit according to some embodiments of the present disclosure.

[0092] Figure 22B It shows Figure 22A A schematic diagram showing the structure of the semiconductor material layer in the scanning circuit shown.

[0093] Figure 22C It shows Figure 22A A schematic diagram showing the structure of the first conductive layer in the scanning circuit shown.

[0094] Figure 22D It shows Figure 22A A schematic diagram showing the structure of the second conductive layer in the scanning circuit shown.

[0095] Figure 22E It shows Figure 22A A schematic diagram showing the structure of the first signal line layer in the scanning circuit shown.

[0096] Figure 22F It shows Figure 22A A schematic diagram showing the structure of the second signal line layer in the scanning circuit shown.

[0097] Figure 22G It shows Figure 22A A schematic diagram showing the structure of the third signal line layer in the scanning circuit shown.

[0098] Figure 22H It shows Figure 22A A schematic diagram showing the connection of the first clock signal line and the second clock signal line in the scanning circuit shown.

[0099] Figure 23A A schematic diagram showing the structure of multiple scan units in multiple scan rows and one or more dummy scan units in one or more rows of dummy scan units in the scanning circuit according to some embodiments of the present disclosure.

[0100] Figure 23B It shows Figure 23A A schematic diagram showing the structure of the semiconductor material layer in the scanning circuit shown.

[0101] Figure 23C It shows Figure 23A A schematic diagram showing the structure of the first conductive layer in the scanning circuit shown.

[0102] Figure 23D is a schematic diagram showing Figure 23A the structure of the second conductive layer in the scanning circuit shown.

[0103] Figure 23E is a schematic diagram showing Figure 23A the structure of the first signal line layer in the scanning circuit shown.

[0104] Figure 23F is a schematic diagram showing Figure 23A the structure of the second signal line layer in the scanning circuit shown.

[0105] Figure 23G is a schematic diagram showing Figure 23A the structure of the third signal line layer in the scanning circuit shown.

[0106] Figure 23H is a schematic diagram showing Figure 23A the connection of the first clock signal line in the scanning circuit shown. Detailed implementation manners

[0107] The present disclosure will now be described more specifically with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0108] The present disclosure particularly provides a scanning circuit and a display device, which substantially avoid one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, the present disclosure provides a scanning circuit. In some embodiments, the scanning circuit includes a first clock signal line; a second clock signal line; and a first scanning unit, a first dummy scanning unit, and a second scanning unit. In a region including a plurality of scanning units and one or more dummy scanning units, the first scanning unit, the first dummy scanning unit, and the second scanning unit are arranged in sequence. Optionally, each scanning unit includes a first pad and a second pad. Optionally, the first pad includes the gate of a seventh transistor. Optionally, the second pad includes the gates of a first transistor and a third transistor. Optionally, the first dummy scanning unit includes a first dummy extension. Optionally, the first dummy extension is connected to the second pad in the second scanning unit and is configured to transmit one of the first clock signal or the second clock signal to the gates of the first transistor and the third transistor in the second scanning unit. Optionally, the orthographic projection of the first dummy extension on the substrate substantially overlaps at least one of the orthographic projection of the first clock signal line on the substrate or the orthographic projection of the second clock signal line on the substrate.

[0109] In some embodiments, the present disclosure provides one or more scanning circuits. Each of the one or more scanning circuits includes a plurality of cascaded scanning units. Optionally, the plurality of cascaded scanning units are configured to provide a plurality of control signals (e.g., gate scanning signals, reset control signals, or light emission control signals) to multiple rows of sub-pixels. Examples of the scanning circuits include a light emission control signal generation circuit configured to generate light emission control signals for sub-pixels in an array substrate, a reset control signal generation circuit configured to generate reset control signals for sub-pixels in the array substrate, and a gate scanning signal generation circuit configured to generate gate scanning signals for sub-pixels in the array substrate.

[0110] Figure 1 is a circuit diagram of a corresponding scanning unit of the scanning circuit according to some embodiments of the present disclosure. Refer to Figure 1, in some embodiments, each scanning unit includes a first transistor T1 to an eighth transistor T8, a first capacitor C1, and a second capacitor C2. In some embodiments, the gate of the first transistor T1 is electrically connected to a second terminal TM2 configured to provide a first clock signal CK, the first electrode of the first transistor T1 is electrically connected to an input terminal TM1 configured to provide a start signal STV or an output signal Outp from an output terminal of a previous scanning unit, and the second electrode of the first transistor T1 is electrically connected to a first node N1; the gate of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the second terminal TM2 configured to provide the first clock signal CK, and the second electrode of the second transistor T2 is electrically connected to a second node N2; the gate of the third transistor T3 is electrically connected to the second terminal TM2 configured to provide the first clock signal CK, the first electrode of the third transistor T3 is electrically connected to a first power supply signal VGL, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the gate of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to a second power supply signal VGH, and the second electrode of the fourth transistor T4 is electrically connected to an output terminal TM4 configured to output an output signal Outc; the gate of the fifth transistor T5 is electrically connected to a third node N3, the first electrode of the fifth transistor T5 is electrically connected to a third terminal TM3 configured to provide a second clock signal CB, and the second electrode of the fifth transistor T5 is electrically connected to the output terminal TM4 configured to output the output signal Outc; the gate of the sixth transistor T6 is electrically connected to the second node N2, the first electrode of the sixth transistor T6 is electrically connected to the second power supply signal VGH, and the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the seventh transistor T7; the gate of the seventh transistor T7 is electrically connected to the third terminal TM3 configured to provide the second clock signal CB, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1; the gate of the eighth transistor T8 is electrically connected to the first power supply signal VGL, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the third node N3; a first capacitor electrode C11 of the first capacitor C1 is electrically connected to the second node N2, and a second capacitor electrode C12 of the first capacitor C1 is electrically connected to the second power supply signal VGH; and a first capacitor electrode C21 of the second capacitor C2 is electrically connected to the third node N3, and a second capacitor electrode C22 of the second capacitor C2 is electrically connected to the output terminal TM4 configured to output the output signal Outc. In one example, the first transistor T1 to the eighth transistor T8 can be p-type transistors or n-type transistors. In another example, the second power supply signal VGH provides a continuous high-level signal, while the first power supply signal VGL provides a continuous low-level signal.

[0111] Figure 2 is shownFigure 1 The timing diagram of the operation of the corresponding scan unit shown. Refer to Figure 2 , in some embodiments, the operations of each scan unit include a first period p1, a second period p2, a third period p3, a fourth period p4, and a fifth period p5.

[0112] In some embodiments, during the first period p1, the first clock signal CK is provided to the second input terminal TM2. The first transistor T1 and the third transistor T3 are turned on. In addition, during the first period p1, the second clock signal CB is not provided to the third input terminal TM3, and the seventh transistor T7 is turned off.

[0113] In some embodiments, during the first period p1, the first transistor T1 is turned on, and the start signal STV or the output signal Outp from the output terminal of the previous scan unit is provided to the input terminal TM1 and transmitted from the first electrode of the first transistor T1 to the second electrode of the first transistor T1. The start signal STV or the output signal Outp from the output terminal of the previous scan unit is applied to the first node N1. When the first node N1 is set to the voltage level of the start signal STV or the output signal Outp from the output terminal of the previous scan unit, the second transistor T2 is turned on.

[0114] In some embodiments, when the second transistor T2 is turned on, the voltage of the first clock signal CK is provided to the second node N2. The fourth transistor T4 and the sixth transistor T6 are turned on.

[0115] In some embodiments, when the third transistor T3 is turned on, the voltage of the first power supply signal VGL is provided to the second node N2. The fourth transistor T4 and the sixth transistor T6 are turned on.

[0116] In some embodiments, when the fourth transistor T4 is turned on, the voltage of the second power supply signal VGH is provided to the output terminal TM4. The voltage of the second power supply signal VGH is an invalid voltage. During the first period p1, the invalid voltage of the gate driving signal is provided to the nth gate line among the N gate lines, where n and N are positive integers, and 1 ≤ n ≤ N.

[0117] In some embodiments, when the first transistor T1 is turned on, the start signal STV or the output signal Outp from the output terminal of the previous scan unit passes through the first transistor T1 and the eighth transistor T8, and the fifth transistor T5 is turned on. During the first period p1, the second clock signal CB is not provided to the third input terminal TM3 and is not provided to the output terminal TM4. During the first period p1, the effective voltage of the gate driving signal is not provided to the nth gate line.

[0118] In some embodiments, during the second period p2, the supply of the first clock signal CK to the second input terminal TM2 is interrupted. The first transistor T1 and the third transistor T3 are turned off. The first node N1 maintains the voltage of the previous period. Since the first node N1 is held at an effective voltage level (e.g., a low voltage level), the second transistor T2 remains turned on. Although the second transistor T2 is turned on, during the second period p2, the supply of the first clock signal CK to the second input terminal TM2 is interrupted. Accordingly, the fourth transistor T4 and the sixth transistor T6 are turned off. When the fourth transistor T4 is turned off, the voltage of the second power signal VGH is not supplied to the output terminal TM4.

[0119] In some embodiments, during the second period p2, the second clock signal CB is supplied to the third input terminal TM3. The seventh transistor T7 is turned on by the second clock signal CB supplied to the third input terminal TM3. During the second period p2, the first node N1 maintains the voltage of the previous period. The voltage at the first node N1 (e.g., the effective voltage) turns on the fifth transistor T5. During the second period p2, the second clock signal CB is supplied to the output terminal TM4 through the fifth transistor T5 and is supplied to the n-th stage gate line as a gate driving signal.

[0120] In some embodiments, during the third period p3, the supply of the second clock signal CB to the third input terminal TM3 is interrupted. When the supply of the second clock signal CB is interrupted, the seventh transistor T7 is turned off.

[0121] In some embodiments, during the third period p3, the first clock signal CK is supplied to the second input terminal TM2. When the first clock signal CK is supplied to the second input terminal TM2, the first transistor T1 and the third transistor T3 are turned on. During the third period p3, the start signal STV or the output signal Outp from the output terminal of the previous scan unit is interrupted.

[0122] In some embodiments, when the third transistor T3 is turned on, the voltage of the first power signal VGL is supplied to the second node N2. The fourth transistor T4 and the sixth transistor T6 are turned on. When the fourth transistor T4 is turned on, the voltage of the second power signal VGH is supplied to the output terminal TM4. The voltage of the second power signal VGH is an invalid voltage. During the third period p3, an invalid voltage of the gate driving signal is supplied to the n-th stage gate line.

[0123] During the third period p3, the start signal STV or the output signal Outp from the output terminal of the previous scan unit is interrupted. In some embodiments, when the first transistor T1 is turned on, the first node N1 maintains an inactive voltage level (e.g., a high voltage level). The fifth transistor T5 is turned off. During the third period p3, the second clock signal CB is not provided to the output terminal TM4 and is not provided to the nth-stage gate line as a gate driving signal.

[0124] In some embodiments, during the fourth period p4, the second clock signal CB may be provided to the third input terminal TM3. When the second clock signal CB is provided to the third input terminal TM3, the seventh transistor T7 is turned on. During the fourth period p4, the supply of the first clock signal CK to the second input terminal TM2 is interrupted, and the first transistor T1 and the third transistor T3 are turned off. During the fourth period p4, the start signal STV or the output signal Outp from the output terminal of the previous scan unit is interrupted. In some embodiments, when the first transistor T1 is turned off, the first node N1 maintains the voltage of the previous period. The inactive voltage at the first node N1 turns off the fifth transistor T5. During the fourth period p4, the second clock signal CB is not provided to the output terminal TM4 and is not provided to the nth-stage gate line as a gate driving signal.

[0125] In some embodiments, during the fifth period p5, the supply of the second clock signal CB to the third input terminal TM3 is interrupted, and the first clock signal CK is provided to the second terminal TM2. During the fifth period p5, the start signal STV or the output signal Outp from the output terminal of the previous scan unit is interrupted. In some embodiments, when the first transistor T1 is turned on, the first node N1 maintains an inactive voltage level (e.g., a high voltage level). The fifth transistor T5 is turned off. During the fifth period p5, the second clock signal CB is not provided to the output terminal TM4 and is not provided to the nth-stage gate line as a gate driving signal.

[0126] In some embodiments, during the fifth period p5, when the third transistor T3 is turned on, the voltage of the first power signal VGL is provided to the second node N2. The fourth transistor T4 and the sixth transistor T6 are turned on. When the fourth transistor T4 is turned on, the voltage of the second power signal VGH is provided to the output terminal TM4. The voltage of the second power signal VGH is an inactive voltage. During the fifth period p5, the inactive voltage of the gate driving signal is provided to the nth-stage gate line.

[0127] Figure 3 is a circuit diagram of a corresponding scan unit of a scan circuit in some embodiments according to the present disclosure. Refer to Figure 3, in some embodiments, each scanning unit includes a first transistor T1 to an eighth transistor T8, a first capacitor C1, and a second capacitor C2. In some embodiments, the gate of the first transistor T1 is electrically connected to a second terminal TM2 configured to provide a second clock signal CB, the first electrode of the first transistor T1 is electrically connected to an input terminal TM1 configured to provide a start signal STV or an output signal Outp from an output terminal of a previous scanning unit, and the second electrode of the first transistor T1 is electrically connected to a first node N1; the gate of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the second terminal TM2 configured to provide the second clock signal CB, and the second electrode of the second transistor T2 is electrically connected to a second node N2; the gate of the third transistor T3 is electrically connected to the second terminal TM2 configured to provide the second clock signal CB, the first electrode of the third transistor T3 is electrically connected to a first power supply signal VGL, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the gate of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to a second power supply signal VGH, and the second electrode of the fourth transistor T4 is electrically connected to an output terminal TM4 configured to output an output signal Outc; the gate of the fifth transistor T5 is electrically connected to a third node N3, the first electrode of the fifth transistor T5 is electrically connected to a third terminal TM3 configured to provide a first clock signal CK, and the second electrode of the fifth transistor T5 is electrically connected to the output terminal TM4 configured to output the output signal Outc; the gate of the sixth transistor T6 is electrically connected to the second node N2, the first electrode of the sixth transistor T6 is electrically connected to the second power supply signal VGH, and the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the seventh transistor T7; the gate of the seventh transistor T7 is electrically connected to the third terminal TM3 configured to provide the first clock signal CK, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1; the gate of the eighth transistor T8 is electrically connected to the first power supply signal VGL, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the third node N3; the first capacitor electrode C11 of the first capacitor C1 is electrically connected to the second node N2, and the second capacitor electrode C12 of the first capacitor C1 is electrically connected to the second power supply signal VGH; and the first capacitor electrode C21 of the second capacitor C2 is electrically connected to the third node N3, and the second capacitor electrode C22 of the second capacitor C2 is electrically connected to the output terminal TM4 configured to output the output signal Outc. In one example, the first transistor T1 to the eighth transistor T8 can be p-type transistors or n-type transistors. In another example, the second power supply signal VGH provides a continuous high-level signal, while the first power supply signal VGL provides a continuous low-level signal.

[0128] Figure 4 is shownFigure 3 The timing diagram of the operation of the corresponding scanning unit shown. Refer to Figure 4 , in some embodiments, the operation of each scanning unit includes a first period p1, a second period p2, a third period p3, a fourth period p4, and a fifth period p5.

[0129] In some embodiments, during the first period p1, the second clock signal CB is not provided to the second input terminal TM2. The first transistor T1 and the third transistor T3 are turned off. In addition, during the first period p1, the first clock signal CK is provided to the third input terminal TM3, and the seventh transistor T7 is turned on.

[0130] In some embodiments, during the first period p1, the start signal STV or the output signal Outp from the output terminal of the previous scanning unit is not provided to the input terminal TM1. The fifth transistor T5 is turned off. The first clock signal CK does not pass through the fifth transistor T5, and the effective voltage of the gate driving signal is not provided to the nth gate line.

[0131] In some embodiments, during the first period p1, the third transistor T3 is turned off. The first power supply signal VGL does not pass through the third transistor T3. The fourth transistor T4 is turned off.

[0132] In some embodiments, during the second period p2, the supply of the first clock signal CK to the third input terminal TM3 is interrupted. The second clock signal CB is provided to the second input terminal TM2, and the first transistor T1 and the third transistor T3 are turned on. The start signal STV or the output signal Outp from the output terminal of the previous scanning unit is provided to the input terminal TM1 and is transmitted from the first electrode of the first transistor T1 to the second electrode of the first transistor T1. The start signal STV or the output signal Outp from the output terminal of the previous scanning unit is applied to the first node N1. When the first node N1 is set to the voltage level of the start signal STV or the output signal Outp from the output terminal of the previous scanning unit, the second transistor T2 is turned on.

[0133] In some embodiments, when the second transistor T2 is turned on, the voltage of the second clock signal CB is provided to the second node N2. The fourth transistor T4 and the sixth transistor T6 are turned on.

[0134] In some embodiments, when the third transistor T3 is turned on, the voltage of the first power supply signal VGL is provided to the second node N2. The fourth transistor T4 and the sixth transistor T6 are turned on.

[0135] In some embodiments, when the fourth transistor T4 is turned on, the voltage of the second power signal VGH is provided to the output terminal TM4. The voltage of the second power signal VGH is an invalid voltage. During the second period p2, the invalid voltage of the gate driving signal is provided to the nth-stage gate line.

[0136] In some embodiments, when the first transistor T1 is turned on, the start signal STV or the output signal Outp from the output terminal of the previous scan unit passes through the first transistor T1 and the eighth transistor T8, and the fifth transistor T5 is turned on. During the second period p2, the first clock signal CK is not provided to the third input terminal TM3, nor is it provided to the output terminal TM4. During the second period p2, the effective voltage of the gate driving signal is not provided to the nth-stage gate line.

[0137] In some embodiments, during the third period p3, the supply of the second clock signal CB to the second input terminal TM2 is interrupted. The first transistor T1 and the third transistor T3 are turned off. The first node N1 maintains the voltage of the previous period. Since the first node N1 is held at an effective voltage level (e.g., a low voltage level), the second transistor T2 remains turned on. Although the second transistor T2 is turned on, the supply of the second clock signal CB to the second input terminal TM2 is interrupted during the third period p3. Therefore, the fourth transistor T4 and the sixth transistor T6 are turned off. When the fourth transistor T4 is turned off, the voltage of the second power signal VGH is not provided to the output terminal TM4.

[0138] In some embodiments, during the third period p3, the first clock signal CK is provided to the third input terminal TM3. The seventh transistor T7 is turned on by the first clock signal CK provided to the third input terminal TM3. During the third period p3, the first node N1 maintains the voltage of the previous period. The voltage at the first node N1 (e.g., the effective voltage) turns on the fifth transistor T5. During the third period p3, the first clock signal CK passes through the fifth transistor T5, is provided to the output terminal TM4, and is provided to the nth-stage gate line as a gate driving signal.

[0139] In some embodiments, during the fourth period p4, the supply of the first clock signal CK to the third input terminal TM3 is interrupted. When the supply of the first clock signal CK is interrupted, the seventh transistor T7 is turned off.

[0140] In some embodiments, during the fourth period p4, the second clock signal CB is provided to the second input terminal TM2. When the second clock signal CB is provided to the second input terminal TM2, the first transistor T1 and the third transistor T3 are turned on. During the fourth period p4, the start signal STV or the output signal Outp from the output terminal of the previous scan unit is interrupted.

[0141] In some embodiments, when the third transistor T3 is turned on, the voltage of the first power signal VGL is provided to the second node N2. The fourth transistor T4 and the sixth transistor T6 are turned on. When the fourth transistor T4 is turned on, the voltage of the second power signal VGH is provided to the output terminal TM4. The voltage of the second power signal VGH is an invalid voltage. During the fourth period p4, the invalid voltage of the gate driving signal is provided to the n-th stage gate line.

[0142] During the fourth period p4, the start signal STV or the output signal Outp from the output terminal of the previous scan unit is interrupted. In some embodiments, when the first transistor T1 is turned on, the first node N1 maintains an invalid voltage level (e.g., a high voltage level). The fifth transistor T5 is turned off. During the fourth period p4, the first clock signal CK is not provided to the output terminal TM4 and is not provided to the n-th stage gate line as a gate driving signal.

[0143] In some embodiments, during the fifth period p5, the first clock signal CK can be provided to the third input terminal TM3. When the first clock signal CK is provided to the third input terminal TM3, the seventh transistor T7 is turned on. During the fifth period p5, the supply of the second clock signal CB to the second input terminal TM2 is interrupted, and the first transistor T1 and the third transistor T3 are turned off. During the fifth period p5, the start signal STV or the output signal Outp from the output terminal of the previous scan unit is interrupted. In some embodiments, when the first transistor T1 is turned off, the first node N1 maintains the voltage of the previous period. The invalid voltage at the first node N1 turns off the fifth transistor T5. During the fifth period p5, the first clock signal CK is not provided to the output terminal TM4 and is not provided to the n-th stage gate line as a gate driving signal.

[0144] Compare Figure 1 and Figure 2 each of the scan units described in Figure 3 and Figure 4 with each of the scan units described in Figure 3 and Figure 4 The gate driving signals output from each of the scan units described in Figure 1 and Figure 2 are out of phase with the gate driving signals output from each of the scan units described in

[0145] The present disclosure can be implemented in a scan circuit having various types of transistors, including a scan circuit having p-type transistors, a scan circuit having n-type transistors, and a scan circuit having one or more p-type transistors and one or more n-type transistors. For p-type transistors, an effective control signal (e.g., a turn-on control signal) is a low-voltage signal, while an ineffective control signal (e.g., a turn-off control signal) is a high-voltage signal. For n-type transistors, an effective control signal (e.g., a turn-on control signal) is a high-voltage signal, while an ineffective control signal (e.g., a turn-off control signal) is a low-voltage signal. Refer to Figure 1 and Figure 3 , in some embodiments, all the transistors in each scan unit of the scan circuit are p-type transistors, such as polysilicon transistors.

[0146] Various alternative scan circuits can be used in the present disclosure. Figure 5 is a circuit diagram of a corresponding scan unit of a scan circuit according to some embodiments of the present disclosure. Figure 6 is a circuit diagram of a corresponding scan unit of a scan circuit according to some embodiments of the present disclosure. Figure 5 Each scan unit in Figure 1 corresponds to Figure 2 each scan unit in Figure 6 Each scan unit in Figure 3 corresponds to Figure 4 each scan unit in Figure 6 The gate drive signals output from each scan unit shown in Figure 5 are out of phase with the gate drive signals output from each scan unit shown in

[0147] Refer to Figure 5 , in some embodiments, each scan unit includes an input sub-circuit ISC, an output sub-circuit OSC, a first processing sub-circuit PSC1, a second processing sub-circuit PSC2, a third processing sub-circuit PSC3, a first voltage stabilizing sub-circuit SSC1, and a second voltage stabilizing sub-circuit SSC2.

[0148] In some embodiments, the output sub-circuit OSC is configured to provide a voltage of a second power signal VGH or a first power signal VGL to an output terminal TM4 in response to the voltage of a fourth node N4 and the voltage of a first node N1. Optionally, the output sub-circuit OSC includes a ninth transistor T9 and a tenth transistor T10.

[0149] The ninth transistor T9 is coupled between the second power supply signal VGH and the output terminal TM4. The gate of the ninth transistor T9 is coupled to the fourth node N4. The ninth transistor T9 can be turned on or off according to the voltage of the fourth node N4. Optionally, when the ninth transistor T9 is turned on, the voltage of the second power supply signal VGH is supplied to the output terminal TM4, and the one ( Figure 5 labeled as Outc) therein can be transmitted to the nth-stage gate line and used as a gate driving signal having a gate-conducting level.

[0150] The tenth transistor T10 is coupled between the output terminal TM4 and the first power supply signal VGL. The gate of the tenth transistor T10 is coupled to the first node N1. The tenth transistor T10 can be turned on or off according to the voltage of the first node N1. Optionally, when the tenth transistor T10 is turned on, the voltage of the first power supply signal VGL is supplied to the output terminal TM4, and the one ( Figure 5 labeled as Outc) therein can be supplied to the nth-stage gate line and used as a gate driving signal having a gate-cutoff level. In one example, when the gate driving signal has a gate-cutoff level, it can be understood that no gate driving signal is provided.

[0151] In some embodiments, the input sub-circuit ISC is configured to control the voltage of the first node N1 in response to signals respectively provided to the first input terminal TM1 and the second input terminal TM2. Optionally, the input sub-circuit ISC includes a first transistor T1.

[0152] The first transistor T1 is coupled between the first input terminal TM1 and the first node N1. The gate of the first transistor T1 is coupled to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the first transistor T1 is turned on to electrically couple the first input terminal TM1 and the first node N1.

[0153] In some embodiments, the first processing sub-circuit PSC1 is configured to control the voltage of the fourth node N4 in response to the voltage of the first node N1. Optionally, the first processing sub-circuit PSC1 includes an eighth transistor T8 and a second capacitor C2.

[0154] The eighth transistor T8 is coupled between the second power supply signal VGH and the fourth node N4. The gate of the eighth transistor T8 is coupled to the first node N1. The eighth transistor T8 can be turned on or off according to the voltage of the first node N1. Optionally, when the eighth transistor T8 is turned on, the voltage of the second power supply signal VGH can be supplied to the fourth node N4.

[0155] The second capacitor C2 is coupled between the second power supply signal VGH and the fourth node N4. Optionally, the second capacitor C2 is configured to charge the voltage to be applied to the fourth node N4. Optionally, the second capacitor C2 is configured to stably maintain the voltage of the fourth node N4.

[0156] In some embodiments, the second processing sub - circuit PSC2 is coupled to the fifth node N5 and is configured to control the voltage of the fourth node N4 in response to a signal input to the third input terminal TM3. Optionally, the second processing sub - circuit PSC2 includes a sixth transistor T6, a seventh transistor T7, and a first capacitor C1.

[0157] A first terminal of the first capacitor C1 is coupled to the fifth node N5, and a second terminal of the first capacitor C1 is coupled to the third node N3, which is a common node between the sixth transistor T6 and the seventh transistor T7.

[0158] The sixth transistor T6 is coupled between the third node N3 and the fifth node N5. The gate of the sixth transistor T6 is coupled to the fifth node N5. The sixth transistor T6 can be turned on according to the voltage of the fifth node N5. Thus, the voltage corresponding to the second clock signal CB provided to the third input terminal TM3 can be applied to the third node N3.

[0159] The seventh transistor T7 is coupled between the fourth node N4 and the third node N3. The gate of the seventh transistor T7 is coupled to the third input terminal TM3. The seventh transistor T7 can be turned on in response to the second clock signal CB provided to the third input terminal TM3. Thus, the voltage of the second power supply signal VGH is applied to the third node N3.

[0160] In some embodiments, the third processing sub - circuit PSC3 is configured to control the voltage of the second node N2. Optionally, the third processing sub - circuit PSC3 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a third capacitor C3.

[0161] The fifth transistor T5 is coupled between the second power supply signal VGH and the fourth transistor T4. The gate of the fifth transistor T5 is coupled to the second node N2. The fifth transistor T5 can be turned on or off according to the voltage of the second node N2.

[0162] The fourth transistor T4 is coupled between the fifth transistor T5 and the third input terminal TM3. A first electrode of the fourth transistor T4 is configured to be provided with the second clock signal CB provided to the third input terminal TM3. The gate of the fourth transistor T4 is coupled to the gate of the tenth transistor T10. A second electrode of the fourth transistor T4 is coupled to a second electrode of the fifth transistor T5.

[0163] The second transistor T2 is coupled between the second node N2 and the second input terminal TM2. The gate of the second transistor T2 is coupled to the first node N1.

[0164] The third transistor T3 is coupled between the second node N2 and the first power supply signal VGL. The gate of the third transistor T3 is coupled to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the third transistor T3 can be turned on, such that the voltage of the first power supply signal VGL can be provided to the second node N2.

[0165] The third capacitor C3 is coupled between the tenth transistor T10 and the fifth transistor T5. The first capacitor electrode of the third capacitor C3 is coupled to the second electrode of the fifth transistor T5 and the first electrode of the fourth transistor T4. The second capacitor electrode of the third capacitor C3 is coupled to the gate of the fourth transistor T4 and the gate of the tenth transistor T10.

[0166] In some embodiments, the first voltage regulation sub-circuit SSC1 is coupled between the second processing sub-circuit PSC2 and the third processing sub-circuit PSC3. Optionally, the first voltage regulation sub-circuit SSC1 is configured to limit the voltage drop width of the second node N2. Optionally, the first voltage regulation sub-circuit SSC1 includes an eleventh transistor T11.

[0167] The eleventh transistor T11 is coupled between the second node N2 and the fifth node N5. The gate of the eleventh transistor T11 is coupled to the first power supply signal VGL. Since the first power supply signal VGL has a gate conduction level voltage, the eleventh transistor T11 can always remain on. Therefore, the second node N2 and the fifth node N5 can be maintained at the same voltage and operate as substantially the same node. As used herein, the term "substantially the same" means that the difference between two values does not exceed 10% of the base value (e.g., one of the two values), such as not exceeding 8% of the base value, not exceeding 6%, not exceeding 4%, not exceeding 2%, not exceeding 1%, not exceeding 0.5%, not exceeding 0.1%, not exceeding 0.05%, and not exceeding 0.01%.

[0168] In some embodiments, the second voltage regulation sub-circuit SSC2 is coupled between the first node N1 and the output sub-circuit OSC. Optionally, the second voltage regulation sub-circuit SSC2 is configured to limit the voltage drop width of the first node N1. Optionally, the second voltage regulation sub-circuit SSC2 includes a twelfth transistor T12.

[0169] The twelfth transistor T12 is coupled between the first node N1 and the gate of the tenth transistor T10. The gate of the twelfth transistor T12 is coupled to the first power signal VGL. Since the first power signal VGL has a gate-conducting level voltage, the twelfth transistor T12 can always remain conductive. Therefore, the first node N1 and the gate of the tenth transistor T10 can be maintained at the same voltage.

[0170] In some embodiments, referring to Figure 5 , each of the first transistor T1 to the twelfth transistor T12 can be formed by a p-type transistor. In some embodiments, the gate-conducting voltage of the first transistor T1 to the twelfth transistor T12 can be set to a low level, while its gate-cutoff voltage can be set to a high level.

[0171] In alternative embodiments, each of the first transistor T1 to the twelfth transistor T12 can be formed by an n-type transistor. In some embodiments, the gate-conducting voltage of the first transistor T1 to the twelfth transistor T12 can be set to a high level, while its gate-cutoff voltage can be set to a low level.

[0172] Referring to Figure 6 , in some embodiments, each scan unit includes an input sub-circuit ISC, an output sub-circuit OSC, a first processing sub-circuit PSC1, a second processing sub-circuit PSC2, a third processing sub-circuit PSC3, a first voltage stabilizing sub-circuit SSC1, and a second voltage stabilizing sub-circuit SSC2.

[0173] In some embodiments, the output sub-circuit OSC is configured to provide the voltage of the second power signal VGH or the first power signal VGL to the output terminal TM4 in response to the voltage of the fourth node N4. Optionally, the output sub-circuit OSC includes a ninth transistor T9 and a tenth transistor T10.

[0174] The ninth transistor T9 is coupled between the second power signal VGH and the output terminal TM4. The gate of the ninth transistor T9 is coupled to the fourth node N4. The ninth transistor T9 can be turned on or off according to the voltage of the fourth node N4. Optionally, when the ninth transistor T9 is turned on, the voltage of the second power signal VGH is provided to the output terminal TM4, and its ( Figure 6 labeled as Outc) can be transmitted to the nth-stage gate line and used as a gate driving signal having a gate-conducting level.

[0175] The tenth transistor T10 is coupled between the output terminal TM4 and the first power signal VGL. The gate of the tenth transistor T10 is coupled to the first node N1. The tenth transistor T10 can be turned on or off according to the voltage of the first node N1. Optionally, when the tenth transistor T10 is turned on, the voltage of the first power signal VGL is provided to the output terminal TM4, and its (in Figure 6The one marked as Outc) can be provided to the nth-level gate line and used as a gate drive signal having a gate cutoff level. In one example, when the gate drive signal has a gate cutoff level, it can be understood that no gate drive signal is provided.

[0176] In some embodiments, the input sub-circuit ISC is configured to control the voltage of the first node N1 in response to signals respectively provided to the first input terminal TM1 and the second input terminal TM2. Optionally, the input sub-circuit ISC includes a first transistor T1.

[0177] The first transistor T1 is coupled between the first input terminal TM1 and the first node N1. The gate of the first transistor T1 is coupled to the second input terminal TM2. When the second clock signal CB is provided to the second input terminal TM2, the first transistor T1 is turned on to electrically couple the first input terminal TM1 and the first node N1.

[0178] In some embodiments, the first processing sub-circuit PSC1 is configured to control the voltage of the fourth node N4 in response to the voltage of the first node N1. Optionally, the first processing sub-circuit PSC1 includes an eighth transistor T8 and a second capacitor C2.

[0179] The eighth transistor T8 is coupled between the second power supply signal VGH and the fourth node N4. The gate of the eighth transistor T8 is coupled to the first node N1. The eighth transistor T8 can be turned on or off according to the voltage of the first node N1. Optionally, when the eighth transistor T8 is turned on, the voltage of the second power supply signal VGH can be provided to the fourth node N4.

[0180] The second capacitor C2 is coupled between the second power supply signal VGH and the fourth node N4. Optionally, the second capacitor C2 is configured to charge the voltage to be applied to the fourth node N4. Optionally, the second capacitor C2 is configured to stably maintain the voltage of the fourth node N4.

[0181] In some embodiments, the second processing sub-circuit PSC2 is coupled to the fifth node N5 and is configured to control the voltage of the fourth node N4 in response to the signal input to the third input terminal TM3. Optionally, the second processing sub-circuit PSC2 includes a sixth transistor T6, a seventh transistor T7, and a first capacitor C1.

[0182] The first terminal of the first capacitor C1 is coupled to the fifth node N5, and the second terminal of the first capacitor C1 is coupled to the third node N3, which is the common node between the sixth transistor T6 and the seventh transistor T7.

[0183] The sixth transistor T6 is coupled between the third node N3 and the fifth node N5. The gate of the sixth transistor T6 is coupled to the fifth node N5. The sixth transistor T6 can be turned on according to the voltage of the fifth node N5. Therefore, the voltage corresponding to the first clock signal CK provided to the third input terminal TM3 can be applied to the third node N3.

[0184] The seventh transistor T7 is coupled between the fourth node N4 and the third node N3. The gate of the seventh transistor T7 is coupled to the third input terminal TM3. The seventh transistor T7 can be turned on in response to the first clock signal CK provided to the third input terminal TM3, so that the voltage of the second power supply signal VGH is applied to the third node N3.

[0185] In some embodiments, the third processing sub-circuit PSC3 is configured to control the voltage of the second node N2. Optionally, the third processing sub-circuit PSC3 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a third capacitor C3.

[0186] The fifth transistor T5 is coupled between the second power supply signal VGH and the fourth transistor T4. The gate of the fifth transistor T5 is coupled to the second node N2. The fifth transistor T5 can be turned on or off according to the voltage of the second node N2.

[0187] The fourth transistor T4 is coupled between the fifth transistor T5 and the third input terminal TM3. The first electrode of the fourth transistor T4 is configured to be provided with the first clock signal CK provided to the third input terminal TM3. The gate of the fourth transistor T4 is coupled to the gate of the tenth transistor T10. The second electrode of the fourth transistor T4 is coupled to the second electrode of the fifth transistor T5.

[0188] The second transistor T2 is coupled between the second node N2 and the second input terminal TM2. The gate of the second transistor T2 is coupled to the first node N1.

[0189] The third transistor T3 is coupled between the second node N2 and the first power supply signal VGL. The gate of the third transistor T3 is coupled to the second input terminal TM2. When the second clock signal CB is provided to the second input terminal TM2, the third transistor T3 can be turned on, so that the voltage of the first power supply signal VGL can be provided to the second node N2.

[0190] The third capacitor C3 is coupled between the tenth transistor T10 and the fifth transistor T5. The first capacitor electrode of the third capacitor C3 is coupled to the second electrode of the fifth transistor T5 and the second electrode of the fourth transistor T4. The second capacitor electrode of the third capacitor C3 is coupled to the gate of the fourth transistor T4 and the gate of the tenth transistor T10.

[0191] In some embodiments, the first voltage regulator sub - circuit SSC1 is coupled between the second processing sub - circuit PSC2 and the third processing sub - circuit PSC3. Optionally, the first voltage regulator sub - circuit SSC1 is configured to limit the voltage drop width of the second node N2. Optionally, the first voltage regulator sub - circuit SSC1 includes an eleventh transistor T11.

[0192] The eleventh transistor T11 is coupled between the second node N2 and the fifth node N5. The gate of the eleventh transistor T11 is coupled to the first power supply signal VGL. Since the first power supply signal VGL has a gate - conducting level voltage, the eleventh transistor T11 can always remain conductive. Therefore, the second node N2 and the fifth node N5 can be maintained at the same voltage and operate as substantially the same node.

[0193] In some embodiments, the second voltage regulator sub - circuit SSC2 is coupled between the first node N1 and the output sub - circuit OSC. Optionally, the second voltage regulator sub - circuit SSC2 is configured to limit the voltage drop width of the first node N1. Optionally, the second voltage regulator sub - circuit SSC2 includes a twelfth transistor T12.

[0194] The twelfth transistor T12 is coupled between the first node N1 and the gate of the tenth transistor T10. The gate of the twelfth transistor T12 is coupled to the first power supply signal VGL. Since the first power supply signal VGL has a gate - conducting level voltage, the twelfth transistor T12 can always remain conductive. Therefore, the first node N1 and the gate of the tenth transistor T10 can be maintained at the same voltage.

[0195] In some embodiments, refer to Figure 6 , each of the first transistor T1 to the twelfth transistor T12 can be formed by a p - type transistor. In some embodiments, the gate - conducting voltage of the first transistor T1 to the twelfth transistor T12 can be set to a low level, while its gate - cutoff voltage can be set to a high level.

[0196] In an alternative embodiment, each of the first transistor T1 to the twelfth transistor T12 can be formed by an n - type transistor. In some embodiments, the gate - conducting voltage of the first transistor T1 to the twelfth transistor T12 can be set to a high level, while its gate - cutoff voltage can be set to a low level.

[0197] Various alternative scan circuits can be used in the present disclosure. Figure 7 is a circuit diagram of a corresponding scan unit of the scan circuit in some embodiments of the present disclosure. Figure 8 is a circuit diagram of a corresponding scan unit of the scan circuit in some embodiments of the present disclosure. Figure 7 The corresponding scan unit in Figure 1 and Figure 2 corresponds to the corresponding scan unit inFigure 8 The corresponding scan unit in Figure 3 and Figure 4 the corresponding scan unit. From Figure 8 The gate driving signal output from the corresponding scan unit shown is out of phase with the gate driving signal output from Figure 7 the corresponding scan unit shown.

[0198] Refer to Figure 7 , in some embodiments, each scan unit includes an input sub-circuit ISC, an output sub-circuit OSC, a first processing sub-circuit PSC1, a second processing sub-circuit PSC2, a third processing sub-circuit PSC3, a first voltage stabilizing sub-circuit SSC1, and a second voltage stabilizing sub-circuit SSC2.

[0199] In some embodiments, the output sub-circuit OSC is configured to provide the voltage of the second power signal VGH or the first power signal VGL to the output terminal TM4 in response to the voltage of the fourth node N4. Optionally, the output sub-circuit OSC includes a ninth transistor T9 and a tenth transistor T10.

[0200] The ninth transistor T9 is coupled between the second power signal VGH and the output terminal TM4. The gate of the ninth transistor T9 is coupled to the fourth node N4. The ninth transistor T9 can be turned on or off according to the voltage of the fourth node N4. Optionally, when the ninth transistor T9 is turned on, the voltage of the second power signal VGH is provided to the output terminal TM4, and its ( Figure 7 labeled as Outc) can be transmitted to the nth-stage gate line and used as a gate driving signal with a gate conduction level.

[0201] The tenth transistor T10 is coupled between the output terminal TM4 and the first power signal VGL. The gate of the tenth transistor T10 is coupled to the first node N1. The tenth transistor T10 can be turned on or off according to the voltage of the first node N1. Optionally, when the tenth transistor T10 is turned on, the voltage of the first power signal VGL is provided to the output terminal TM4, and its ( Figure 7 labeled as Outc) can be provided to the nth-stage gate line and used as a gate driving signal with a gate cut-off level. In one example, when the gate driving signal has a gate cut-off level, it can be understood that no gate driving signal is provided.

[0202] In some embodiments, the input sub-circuit ISC is configured to control the voltage of the first node N1 in response to signals respectively provided to the first input terminal TM1 and the second input terminal TM2. Optionally, the input sub-circuit ISC includes a first transistor T1.

[0203] The first transistor T1 is coupled between the first input terminal TM1 and the first node N1. The gate of the first transistor T1 is coupled to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the first transistor T1 is turned on to electrically couple the first input terminal TM1 and the first node N1.

[0204] In some embodiments, the first processing sub - circuit PSC1 includes an eighth transistor T8, a thirteenth transistor T13, and a second capacitor C2.

[0205] The eighth transistor T8 is coupled between the second power supply signal VGH and the fourth node N4. The gate of the eighth transistor T8 is coupled to the second electrode of the thirteenth transistor T13. The eighth transistor T8 can be turned on or off according to the voltage of the second electrode of the thirteenth transistor T13. Optionally, when the eighth transistor T8 is turned on, the voltage of the second power supply signal VGH can be provided to the fourth node N4.

[0206] The thirteenth transistor T13 is coupled between the second power supply signal VGH and the eighth transistor T8. The gate of the thirteenth transistor T13 is coupled to the signal terminal ECX. The first electrode of the thirteenth transistor T13 is coupled to the second power supply signal VGH. The second electrode of the thirteenth transistor T13 is coupled to the gate of the eighth transistor T8. The thirteenth transistor T13 can be turned on or off according to the voltage of the signal terminal ECX. Optionally, when the thirteenth transistor T13 is turned on, the voltage of the first power supply VGH can be provided to the gate of the eighth transistor T8.

[0207] The second capacitor C2 is coupled between the second power supply signal VGH and the fourth node N4. Optionally, the second capacitor C2 is configured to charge the voltage to be applied to the fourth node N4. Optionally, the second capacitor C2 is configured to stably maintain the voltage of the fourth node N4.

[0208] In some embodiments, the second processing sub - circuit PSC2 is coupled to the fifth node N5 and is configured to control the voltage of the fourth node N4 in response to a signal input to the third input terminal TM3. Optionally, the second processing sub - circuit PSC2 includes a sixth transistor T6, a seventh transistor T7, and a first capacitor C1.

[0209] The first terminal of the first capacitor C1 is coupled to the fifth node N5, and the second terminal of the first capacitor C1 is coupled to the third node N3, which is a common node between the sixth transistor T6 and the seventh transistor T7.

[0210] The sixth transistor T6 is coupled between the third node N3 and the fifth node N5. The gate of the sixth transistor T6 is coupled to the fifth node N5. The sixth transistor T6 can be turned on according to the voltage of the fifth node N5. Therefore, the voltage corresponding to the second clock signal CB provided to the third input terminal TM3 can be applied to the third node N3.

[0211] The seventh transistor T7 is coupled between the fourth node N4 and the third node N3. The gate of the seventh transistor T7 is coupled to the third input terminal TM3. The seventh transistor T7 can be turned on in response to the second clock signal CB provided to the third input terminal TM3. Therefore, the voltage of the second power supply signal VGH is applied to the third node N3.

[0212] In some embodiments, the third processing sub-circuit PSC3 is configured to control the voltage of the second node N2. Optionally, the third processing sub-circuit PSC3 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a third capacitor C3.

[0213] The fifth transistor T5 is coupled between the second power supply signal VGH and the fourth transistor T4. The gate of the fifth transistor T5 is coupled to the second node N2. The fifth transistor T5 can be turned on or off according to the voltage of the second node N2.

[0214] The fourth transistor T4 is coupled between the fifth transistor T5 and the third input terminal TM3. The first electrode of the fourth transistor T4 is configured to be provided with the second clock signal CB provided to the third input terminal TM3. The gate of the fourth transistor T4 is coupled to the gate of the tenth transistor T10. The second electrode of the fourth transistor T4 is coupled to the second electrode of the fifth transistor T5.

[0215] The second transistor T2 is coupled between the second node N2 and the second input terminal TM2. The gate of the second transistor T2 is coupled to the first node N1.

[0216] The third transistor T3 is coupled between the second node N2 and the first power supply signal VGL. The gate of the third transistor T3 is coupled to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the third transistor T3 can be turned on, so that the voltage of the first power supply signal VGL can be provided to the second node N2.

[0217] The third capacitor C3 is coupled between the tenth transistor T10 and the fifth transistor T5. The first capacitor electrode of the third capacitor C3 is coupled to the second electrode of the fifth transistor T5 and the first electrode of the fourth transistor T4. The second capacitor electrode of the third capacitor C3 is coupled to the gate of the fourth transistor T4 and the gate of the tenth transistor T10.

[0218] In some embodiments, the first voltage regulator sub - circuit SSC1 is coupled between the second processing sub - circuit PSC2 and the third processing sub - circuit PSC3. Optionally, the first voltage regulator sub - circuit SSC1 is configured to limit the voltage drop width of the second node N2. Optionally, the first voltage regulator sub - circuit SSC1 includes an eleventh transistor T11.

[0219] The eleventh transistor T11 is coupled between the second node N2 and the fifth node N5. The gate of the eleventh transistor T11 is coupled to the first power supply signal VGL. Since the first power supply signal VGL has a gate - conducting level voltage, the eleventh transistor T11 can always remain conducting. Thus, the second node N2 and the fifth node N5 can be maintained at the same voltage and operate as substantially the same node. As used herein, the term "substantially the same" means that the difference between two values does not exceed 10% of the base value (e.g., one of the two values), such as not exceeding 8% of the base value, not exceeding 6% of the base value, not exceeding 4% of the base value, not exceeding 2% of the base value, not exceeding 1% of the base value, not exceeding 0.5% of the base value, not exceeding 0.1% of the base value, not exceeding 0.05% of the base value, and not exceeding 0.01% of the base value.

[0220] In some embodiments, the second voltage regulator sub - circuit SSC2 is coupled between the first node N1 and the output sub - circuit OSC. Optionally, the second voltage regulator sub - circuit SSC2 is configured to limit the voltage drop width of the first node N1. Optionally, the second voltage regulator sub - circuit SSC2 includes a twelfth transistor T12.

[0221] The twelfth transistor T12 is coupled between the first node N1 and the gate of the tenth transistor T10. The gate of the twelfth transistor T12 is coupled to the first power supply signal VGL. Since the first power supply signal VGL has a gate - conducting level voltage, the twelfth transistor T12 can always remain conducting. Thus, the first node N1 and the gate of the tenth transistor T10 can be maintained at the same voltage.

[0222] In some embodiments, reference Figure 7 , each of the first transistor T1 to the twelfth transistor T12 can be formed of a p - type transistor. In some embodiments, the gate - conducting voltage of the first transistor T1 to the twelfth transistor T12 can be set to a low level, while its gate - cut - off voltage can be set to a high level.

[0223] In alternative embodiments, each of the first transistor T1 to the twelfth transistor T12 can be formed of an n - type transistor. In some embodiments, the gate - conducting voltage of the first transistor T1 to the twelfth transistor T12 can be set to a high level, while its gate - cut - off voltage can be set to a low level.

[0224] Reference Figure 8, in some embodiments, each scanning unit includes an input sub - circuit ISC, an output sub - circuit OSC, a first processing sub - circuit PSC1, a second processing sub - circuit PSC2, a third processing sub - circuit PSC3, a first voltage - stabilizing sub - circuit SSC1, and a second voltage - stabilizing sub - circuit SSC2.

[0225] In some embodiments, the output sub - circuit OSC is configured to provide the voltage of the second power signal VGH or the first power signal VGL to the output terminal TM4 in response to the voltage of the fourth node N4. Optionally, the output sub - circuit OSC includes a ninth transistor T9 and a tenth transistor T10.

[0226] The ninth transistor T9 is coupled between the second power signal VGH and the output terminal TM4. The gate of the ninth transistor T9 is coupled to the fourth node N4. The ninth transistor T9 can be turned on or off according to the voltage of the fourth node N4. Optionally, when the ninth transistor T9 is turned on, the voltage of the second power signal VGH is provided to the output terminal TM4, and its ( Figure 8 labeled as Outc) can be transmitted to the n - th level gate line and used as a gate driving signal with a gate - conducting level.

[0227] The tenth transistor T10 is coupled between the output terminal TM4 and the first power signal VGL. The gate of the tenth transistor T10 is coupled to the first node N1. The tenth transistor T10 can be turned on or off according to the voltage of the first node N1. Optionally, when the tenth transistor T10 is turned on, the voltage of the first power signal VGL is provided to the output terminal TM4, and its (labeled as Outc in Figure 8 it) can be provided to the n - th level gate line and used as a gate driving signal with a gate - cutoff level. In one example, when the gate driving signal has a gate - cutoff level, it can be understood that no gate driving signal is provided.

[0228] In some embodiments, the input sub - circuit ISC is configured to control the voltage of the first node N1 in response to signals respectively provided to the first input terminal TM1 and the second input terminal TM2. Optionally, the input sub - circuit ISC includes a first transistor T1.

[0229] The first transistor T1 is coupled between the first input terminal TM1 and the first node N1. The gate of the first transistor T1 is coupled to the second input terminal TM2. When the second clock signal CB is provided to the second input terminal TM2, the first transistor T1 is turned on to electrically couple the first input terminal TM1 and the first node N1.

[0230] In some embodiments, the first processing sub - circuit PSC1 includes an eighth transistor T8, a thirteenth transistor T13, and a second capacitor C2.

[0231] The eighth transistor T8 is coupled between the second power supply signal VGH and the fourth node N4. The gate of the eighth transistor T8 is coupled to the second electrode of the thirteenth transistor T13. The eighth transistor T8 can be turned on or off according to the voltage of the second electrode of the thirteenth transistor T13. Optionally, when the eighth transistor T8 is turned on, the voltage of the second power supply signal VGH can be provided to the fourth node N4.

[0232] The thirteenth transistor T13 is coupled between the second power supply signal VGH and the eighth transistor T8. The gate of the thirteenth transistor T13 is coupled to the signal terminal ECX. The first electrode of the thirteenth transistor T13 is coupled to the second power supply signal VGH. The second electrode of the thirteenth transistor T13 is coupled to the gate of the eighth transistor T8. The thirteenth transistor T13 can be turned on or off according to the voltage of the signal terminal ECX. Optionally, when the thirteenth transistor T13 is turned on, the voltage of the first power supply VGH can be provided to the gate of the eighth transistor T8.

[0233] The second capacitor C2 is coupled between the second power supply signal VGH and the fourth node N4. Optionally, the second capacitor C2 is configured to charge the voltage to be applied to the fourth node N4. Optionally, the second capacitor C2 is configured to stably maintain the voltage of the fourth node N4.

[0234] In some embodiments, the second processing sub-circuit PSC2 is coupled to the fifth node N5 and is configured to control the voltage of the fourth node N4 in response to a signal input to the third input terminal TM3. Optionally, the second processing sub-circuit PSC2 includes a sixth transistor T6, a seventh transistor T7, and a first capacitor C1.

[0235] The first terminal of the first capacitor C1 is coupled to the fifth node N5, and the second terminal of the first capacitor C1 is coupled to the third node N3, which is a common node between the sixth transistor T6 and the seventh transistor T7.

[0236] The sixth transistor T6 is coupled between the third node N3 and the fifth node N5. The gate of the sixth transistor T6 is coupled to the fifth node N5. The sixth transistor T6 can be turned on according to the voltage of the fifth node N5. Therefore, the voltage corresponding to the first clock signal CK provided to the third input terminal TM3 can be applied to the third node N3.

[0237] The seventh transistor T7 is coupled between the fourth node N4 and the third node N3. The gate of the seventh transistor T7 is coupled to the third input terminal TM3. The seventh transistor T7 can be turned on in response to the first clock signal CK provided to the third input terminal TM3. Therefore, the voltage of the second power supply signal VGH is applied to the third node N3.

[0238] In some embodiments, the third processing sub-circuit PSC3 is configured to control the voltage of the second node N2. Optionally, the third processing sub-circuit PSC3 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a third capacitor C3.

[0239] The fifth transistor T5 is coupled between the second power supply signal VGH and the fourth transistor T4. The gate of the fifth transistor T5 is coupled to the second node N2. The fifth transistor T5 can be turned on or off according to the voltage of the second node N2.

[0240] The fourth transistor T4 is coupled between the fifth transistor T5 and the third input terminal TM3. The first electrode of the fourth transistor T4 is configured to be provided with a first clock signal CK supplied to the third input terminal TM3. The gate of the fourth transistor T4 is coupled to the gate of the tenth transistor T10. The second electrode of the fourth transistor T4 is coupled to the second electrode of the fifth transistor T5.

[0241] The second transistor T2 is coupled between the second node N2 and the second input terminal TM2. The gate of the second transistor T2 is coupled to the first node N1.

[0242] The third transistor T3 is coupled between the second node N2 and the first power supply signal VGL. The gate of the third transistor T3 is coupled to the second input terminal TM2. When the second clock signal CB is supplied to the second input terminal TM2, the third transistor T3 can be turned on, so that the voltage of the first power supply signal VGL can be supplied to the second node N2.

[0243] The third capacitor C3 is coupled between the tenth transistor T10 and the fifth transistor T5. The first capacitor electrode of the third capacitor C3 is coupled to the second electrode of the fifth transistor T5 and the second electrode of the fourth transistor T4. The second capacitor electrode of the third capacitor C3 is coupled to the gate of the fourth transistor T4 and the gate of the tenth transistor T10.

[0244] In some embodiments, the first voltage stabilizing sub-circuit SSC1 is coupled between the second processing sub-circuit PSC2 and the third processing sub-circuit PSC3. Optionally, the first voltage stabilizing sub-circuit SSC1 is configured to limit the voltage drop width of the second node N2. Optionally, the first voltage stabilizing sub-circuit SSC1 includes an eleventh transistor T11.

[0245] The eleventh transistor T11 is coupled between the second node N2 and the fifth node N5. The gate of the eleventh transistor T11 is coupled to the first power supply signal VGL. Since the first power supply signal VGL has a gate-conducting level voltage, the eleventh transistor T11 can always remain on. Therefore, the second node N2 and the fifth node N5 can be maintained at the same voltage and operate as substantially the same node.

[0246] In some embodiments, the second voltage stabilizing sub - circuit SSC2 is coupled between the first node N1 and the output sub - circuit OSC. Optionally, the second voltage stabilizing sub - circuit SSC2 is configured to limit the voltage drop width of the first node N1. Optionally, the second voltage stabilizing sub - circuit SSC2 includes a twelfth transistor T12.

[0247] The twelfth transistor T12 is coupled between the first node N1 and the gate of the tenth transistor T10. The gate of the twelfth transistor T12 is coupled to the first power supply signal VGL. Since the first power supply signal VGL has a gate - conducting level voltage, the twelfth transistor T12 can always remain conductive. Therefore, the first node N1 and the gate of the tenth transistor T10 can be maintained at the same voltage.

[0248] In some embodiments, referring Figure 8 , each of the first transistor T1 to the twelfth transistor T12 can be formed by a p - type transistor. In some embodiments, the gate - conducting voltage of the first transistor T1 to the twelfth transistor T12 can be set to a low level, while its gate - cutoff voltage can be set to a high level.

[0249] In alternative embodiments, each of the first transistor T1 to the twelfth transistor T12 can be formed by an n - type transistor. In some embodiments, the gate - conducting voltage of the first transistor T1 to the twelfth transistor T12 can be set to a high level, while its gate - cutoff voltage can be set to a low level.

[0250] In some embodiments, the present disclosure provides an array substrate having a plurality of pixel driving circuits and a plurality of light - emitting elements. Each of one or more scanning circuits is configured to provide a plurality of control signals (e.g., gate scanning signals, reset control signals, or light - emitting control signals) to multiple rows of pixel driving circuits. Various suitable pixel driving circuits can be used in this array substrate. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, each of the plurality of pixel driving circuits is an 8T1C driving circuit. Various suitable light - emitting elements can be used in this array substrate. Examples of suitable light - emitting elements include organic light - emitting diodes, quantum dot light - emitting diodes, and micro - light - emitting diodes. Optionally, the light - emitting element is a micro - light - emitting diode. Optionally, the light - emitting element is an organic light - emitting diode including an organic light - emitting layer.

[0251] Figure 9 is a plan view of an array substrate according to some embodiments of the present disclosure. Referring Figure 9, the array substrate includes an array of sub-pixels Sp. Each sub-pixel includes electronic components, for example, including a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes a plurality of first gate lines (for example, each first gate line GL1), a plurality of second gate lines (for example, each second gate line GL2), a plurality of data lines (for example, each data line DL), a plurality of high-voltage supply lines (for example, each high-voltage supply line Vdd), and a plurality of low-voltage supply lines (for example, each low-voltage supply line). Each sub-pixel Sp emits light and is driven by a corresponding pixel driving circuit PDC. In one example, a high-voltage signal (for example, VDD signal) is input to the corresponding pixel driving circuit PDC connected to the anode of the light-emitting element through the corresponding high-voltage supply line Vdd among the plurality of high-voltage supply lines; a low-voltage signal (for example, VSS signal) is input to the cathode of the light-emitting element through the low-voltage supply line. The voltage difference between the high-voltage signal (for example, VDD signal) and the low-voltage signal (for example, VSS signal) is the driving voltage ΔV, which drives the light-emitting element to emit light.

[0252] Figure 10A is a circuit diagram showing the structure of a pixel driving circuit according to some embodiments of the present disclosure. Refer to Figure 10A, in some embodiments, the pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second reset transistor Tr2 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to the second electrode of the driving transistor Td; a first transistor T1 having a gate connected to a corresponding first gate line GL1 among a plurality of first gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to the first electrode of the driving transistor Td; a third reset transistor Tr3 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding third reset signal line Vint3 among a plurality of third reset signal lines, and a second electrode connected to the first electrode of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding second gate line GL2 among a plurality of second gate lines, a first electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td, and a second electrode connected to the second electrode of the driving transistor Td; a third transistor T3 having a gate connected to a corresponding light emission control signal line em among a plurality of light emission control signal lines, a first electrode connected to a corresponding voltage supply line Vdd among a plurality of voltage supply lines, and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the first transistor T1; a fourth transistor T4 having a gate connected to a corresponding light emission control signal line em among a plurality of light emission control signal lines, a first electrode connected to the second electrode of the driving transistor Td and the second electrode of the second transistor T2, and a second electrode connected to the anode of the light emitting element LE; and a first reset transistor Tr1 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding first reset signal line Vint1 among a plurality of first reset signal lines, and a second electrode connected to the second electrode of the fourth transistor T4 and the anode of the light emitting element LE. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the third transistor T3.

[0253] In some embodiments, the pixel driving circuit includes a driving transistor Td, a data writing transistor (e.g., the first transistor T1), a compensation transistor (e.g., the second transistor T2), two light emission control transistors (e.g., the third transistor T3 and the fourth transistor T4), and three reset transistors (e.g., the first reset transistor Tr1, the second reset transistor Tr2, and the third reset transistor Tr3).

[0254] As used herein, the first electrode or the second electrode refers to one of the first terminal and the second terminal of a transistor, and the first terminal and the second terminal are connected to the active layer of the transistor. The direction of the current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Thus, depending on the direction of the current flowing through the transistor, in one example, the first electrode is configured to receive an input signal, and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal, and the first electrode is configured to output an output signal.

[0255] The pixel driving circuit further includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the first electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, the second electrode of the third reset transistor Tr3, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the second transistor T2, the first electrode of the fourth transistor T4, and the second electrode of the second reset transistor Tr2. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light-emitting element LE.

[0256] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels include corresponding first sub-pixels, corresponding second sub-pixels, and corresponding third sub-pixels. Optionally, the corresponding pixels of the array substrate include corresponding first sub-pixels, corresponding second sub-pixels, and corresponding third sub-pixels. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeated array in the S1-S2-S3 format, where S1 represents the corresponding first sub-pixel, S2 represents the corresponding second sub-pixel, and S3 represents the corresponding third sub-pixel. In another example, the S1-S2-S3 format is the C1-C2-C3 format, where C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, and C3 represents the corresponding third sub-pixel of the third color. In another example, the C1-C2-C3 format is the R-G-B format, where the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, and the corresponding third sub-pixel is a blue sub-pixel.

[0257] In another example, the array of multiple sub-pixels includes an array that repeats in the S1-S2-S3-S4 format, where S1 represents the corresponding first sub-pixel, S2 represents the corresponding second sub-pixel, S3 represents the corresponding third sub-pixel, and S4 represents the corresponding fourth sub-pixel. In another example, the S1-S2-S3-S4 format is the C1-C2-C3-C4 format, where C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, C3 represents the corresponding third sub-pixel of the third color, and C4 represents the corresponding fourth sub-pixel of the fourth color. In another example, the S1-S2-S3-S4 format is the C1-C2-C3-C2' format, where C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, C3 represents the corresponding third sub-pixel of the third color, and C2' represents the corresponding fourth sub-pixel of the second color. In another example, the C1-C2-C3-C2' format is the R-G-B-G format, where the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, the corresponding third sub-pixel is a blue sub-pixel, and the corresponding fourth sub-pixel is a green sub-pixel.

[0258] In some embodiments, the minimum repeating unit of the multiple sub-pixels of the array substrate includes the corresponding first sub-pixel, the corresponding second sub-pixel, and the corresponding third sub-pixel. Optionally, each of the respective first sub-pixels, the respective second sub-pixels, and the respective third sub-pixels includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, a driving transistor Td, and a storage capacitor Cst.

[0259] In an alternative embodiment, the minimum repeating unit of the multiple sub-pixels of the array substrate includes the corresponding first sub-pixel, the corresponding second sub-pixel, the corresponding third sub-pixel, and the corresponding fourth sub-pixel. Optionally, each of the respective first sub-pixels, the respective second sub-pixels, the respective third sub-pixels, and the respective fourth sub-pixels includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, a driving transistor Td, and a storage capacitor Cst.

[0260] The present disclosure can be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, and pixel driving circuits having one or more p-type transistors and one or more n-type transistors. Refer to Figure 10A, the second transistor T2 is an n-type transistor, such as a metal oxide transistor, and the other transistors are p-type transistors, such as polysilicon transistors. For p-type transistors, the effective control signal (e.g., the turn-on control signal) is a low voltage signal, while the ineffective control signal (e.g., the turn-off control signal) is a high voltage signal. For n-type transistors, the effective control signal (e.g., the turn-on control signal) is a high voltage signal, while the ineffective control signal (e.g., the turn-off control signal) is a low voltage signal.

[0261] Figure 10B is a timing diagram showing the operation of a pixel driving circuit according to some embodiments of the present disclosure. Refer to Figure 10A and Figure 10B , during one frame period of an image, the operation of the pixel driving circuit includes a reset sub-phase t1, a data writing sub-phase t2, and a light emitting sub-phase t3. In an initial sub-phase t0, a turn-off reset control signal is provided to the gate of the second reset transistor Tr2 through a corresponding second reset control signal line rst2 to turn off the second reset transistor Tr2. A turn-off reset control signal is provided to the gates of the first reset transistor Tr1 and the third reset transistor Tr3 through corresponding first reset control signal lines rst1 to turn off the first reset transistor Tr1 and the third reset transistor Tr3. In the initial sub-phase t0, a turn-off signal is provided to a corresponding first gate line GL1, so the first transistor T1 is turned off.

[0262] In the reset sub-phase t1, a turn-on reset control signal is provided to the gate of the first reset transistor Tr1 through a corresponding first reset control signal line rst1 to turn on the first reset transistor Tr1; an initialization voltage signal from a corresponding first reset signal line Vint1 is allowed to be transferred from the first electrode of the first reset transistor Tr1 to the second electrode of the first reset transistor Tr1, and then transferred to a fourth node N4. The anode of the light emitting element LE is initialized. A turn-on reset control signal is provided to the gate of the third reset transistor Tr3 through a corresponding first reset control signal line rst1 to turn on the third reset transistor Tr3; an initialization voltage signal from a corresponding third reset signal line Vint3 is allowed to be transferred from the first electrode of the third reset transistor Tr3 to the second electrode of the third reset transistor Tr3; and then transferred to a node N2. The node N2 is initialized. In the reset sub-phase t1, a turn-off signal is provided to a corresponding first gate line GL1, so the first transistor T1 is turned off. A high voltage signal is provided to a corresponding light emission control signal line em to turn off the third transistor T3 and the fourth transistor T4.

[0263] In the data writing sub-phase t2, a turn-on reset control signal is provided to the gate of the second reset transistor Tr2 through the second reset control signal line rst2 to turn on the second reset transistor Tr2; an initialization voltage signal from the corresponding second reset signal line Vint2 is allowed to be transferred from the first electrode of the second reset transistor Tr2 to the second electrode of the second reset transistor Tr2, and then transferred to the first capacitor electrode Ce1 and the gate of the driving transistor Td. The gate of the driving transistor Td is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the corresponding voltage supply line Vdd. Since the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 increases, the first capacitor electrode Ce1 is charged in the data writing sub-phase t2.

[0264] In the data writing sub-phase t2, again, a turn-off reset control signal is provided to the gates of the first reset transistor Tr1 and the third reset transistor Tr3 through the corresponding first reset control signal line rst1 to turn off the first reset transistor Tr1 and the third reset transistor Tr3. The corresponding first gate line GL1 and the corresponding second gate line GL2 are respectively provided with turn-on signals, so the first transistor T1 and the second transistor T2 are turned on. The second electrode of the driving transistor Td is connected to the second electrode of the second transistor T2. The gate of the driving transistor Td is electrically connected to the first electrode of the second transistor T2. Since the second transistor T2 is turned on in the data writing sub-phase t2, the gate and the second electrode of the driving transistor Td are connected and short-circuited, and only the PN junction between the gate and the first electrode of the driving transistor Td is effective, so that the driving transistor Td is in the diode-connected mode. The first transistor T1 is turned on in the data writing sub-phase t2. The data voltage signal transmitted through the corresponding data line DL is received by the first electrode of the first transistor T1 and then transmitted to the first electrode of the driving transistor Td, and this first electrode is connected to the second electrode of the first transistor T1. The node N2 connected to the first electrode of the driving transistor Td has the voltage level of the data voltage signal. Since only the PN junction between the gate and the first electrode of the driving transistor Td is effective, in the data writing sub-phase t2, the voltage level of the N1 node gradually rises to (Vdata + Vth), where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 is reduced to a relatively small value, the storage capacitor Cst discharges. The corresponding light emission control signal line em is provided with a high voltage signal to turn off the third transistor T3 and the fourth transistor T4.

[0265] In the light-emitting sub-phase t3, a cut-off reset control signal is provided to the gate of the second reset transistor Tr2 through the corresponding second reset control signal line rst2 to cut off the second reset transistor Tr2. A cut-off reset control signal is provided to the gates of the first reset transistor Tr1 and the third reset transistor Tr3 through the corresponding first reset control signal line rst1 to cut off the first reset transistor Tr1 and the third reset transistor Tr3. The corresponding first gate line GL1 and the corresponding second gate line GL2 are respectively provided with cut-off signals, and the first transistor T1 and the second transistor T2 are cut off. A low-voltage signal is provided to the corresponding light-emitting control signal line em to turn on the third transistor T3 and the fourth transistor T4. In the light-emitting sub-phase t3, the voltage level of the node N1 is maintained at (Vdata + Vth), and the driving transistor Td is turned on by this voltage level and operates in the saturation region. A path is formed from the third transistor T3, through the driving transistor Td, the fourth transistor T4 to the light-emitting element LE. The driving transistor Td generates a driving current for driving the light-emitting element LE to emit light. The voltage level at the node N3 connected to the second electrode of the driving transistor Td is equal to the light-emitting voltage of the light-emitting element LE.

[0266] Figure 11 is a schematic diagram showing one or more scan circuits in a display device according to some embodiments of the present disclosure. Refer to Figure 11 , in some embodiments, the display device includes multiple rows of sub-pixels and one or more scan circuits configured to provide control signals to the multiple rows of sub-pixels. As Figure 11 shown, in some embodiments, the display device includes a first scan circuit SC1 and a second scan circuit SC2.

[0267] In some embodiments, the first scan circuit SC1 includes a multi-stage cascaded scan unit. Optionally, the multi-stage cascaded scan unit of the first scan circuit SC1 is configured to provide multiple control signals (e.g., gate scan signals, reset control signals, or light-emitting control signals) to multiple rows of sub-pixels. Optionally, as Figure 11 shown, each stage of the multi-stage cascaded scan unit of the first scan circuit SC1 is configured to provide a control signal to a single row of sub-pixels. In some embodiments, the first scan circuit SC1 is a first gate scan signal generation circuit configured to generate gate scan signals for the sub-pixels in the array substrate. In one example, the first scan circuit SC1 is a first gate scan signal generation circuit configured to generate gate scan signals for multiple first gate lines ( Figure 10A the corresponding first gate line GL1 is shown in). The multiple first gate lines are configured to provide gate scan signals to the first transistor T1 (e.g., a p-type transistor) in each pixel driving circuit.

[0268] In some embodiments, the first scan circuit SC1 includes scan units on both sides of the display panel. Each stage of the first scan circuit SC1 includes scan units on both sides of the display panel, and the scan units of the same stage on both sides of the display panel are configured to provide control signals to the same row of sub-pixels.

[0269] In some embodiments, the second scan circuit SC2 includes a multi-stage cascaded scan unit. Optionally, the multi-stage cascaded scan units of the second scan circuit SC2 are configured to provide multiple control signals (e.g., gate scan signals, reset control signals, or emission control signals) to multiple rows of sub-pixels. Optionally, as Figure 11 shown, each stage of the multi-stage cascaded scan units of the second scan circuit SC2 is configured to provide control signals to multiple rows (e.g., two rows) of sub-pixels. In some embodiments, the second scan circuit SC2 is a second gate scan signal generation circuit, which is configured to generate gate scan signals for the sub-pixels in the array substrate. In one example, the second scan circuit SC2 is a second gate scan signal generation circuit, which is configured to generate gate scan signals for multiple second gate lines (the corresponding second gate lines GL2 are shown in Figure 10A . The multiple second gate lines are configured to provide gate scan signals to the second transistors T2 (e.g., n-type transistors) in the corresponding pixel driving circuits.

[0270] In some embodiments, the display device further includes a third scan circuit SC3, a fourth scan circuit SC4, and a fifth scan circuit SC5. In some embodiments, the third scan circuit SC3 includes a multi-stage cascaded scan unit. Optionally, the multi-stage cascaded scan units of the third scan circuit SC3 are configured to provide multiple control signals (e.g., gate scan signals, reset control signals, or emission control signals) to multiple rows of sub-pixels. Optionally, as Figure 11 shown, each stage of the multi-stage cascaded scan units of the third scan circuit SC3 is configured to provide control signals to multiple rows (e.g., two rows) of sub-pixels. In some embodiments, the third scan circuit SC3 is a second reset control signal generation circuit, which is configured to generate reset control signals for the sub-pixels in the array substrate. In one example, the third scan circuit SC3 is a second reset control signal generation circuit, which is configured to generate second reset control signals for multiple second reset control signal lines (the corresponding second reset control signal lines rst2 are shown in Figure 10A . The multiple second reset control signal lines are configured to provide second reset control signals to the second reset transistors Tr2 (e.g., p-type transistors) in each pixel driving circuit.

[0271] In some embodiments, the fourth scanning circuit SC4 includes multiple cascaded scanning units. Optionally, the multiple cascaded scanning units of the fourth scanning circuit SC4 are configured to provide multiple control signals (e.g., gate scanning signals, reset control signals, or emission control signals) to multiple rows of sub-pixels. Optionally, as Figure 11 shown, each of the cascaded scanning units in the multiple cascaded scanning units of the fourth scanning circuit SC4 is configured to provide control signals to multiple rows (e.g., two rows) of sub-pixels. In some embodiments, the fourth scanning circuit SC4 is a first reset control signal generation circuit, which is configured to generate a reset control signal for the sub-pixels in the array substrate. In one example, the fourth scanning circuit SC4 is a first reset control signal generation circuit, which is configured to generate a first reset control signal for multiple first reset control signal lines ( Figure 10A the corresponding first reset control signal line rst1 is shown in). The multiple first reset control signal lines are configured to provide the first reset control signal to the first reset transistor Tr1 and the third reset transistor Tr3 (e.g., p-type transistors) in each pixel driving circuit.

[0272] In some embodiments, the fifth scanning circuit SC5 includes multiple cascaded scanning units. Optionally, the multiple cascaded scanning units of the fifth scanning circuit SC5 are configured to provide multiple control signals (e.g., gate scanning signals, reset control signals, or emission control signals) to multiple rows of sub-pixels. Optionally, as Figure 11 shown, each of the cascaded scanning units in the multiple cascaded scanning units of the fifth scanning circuit SC5 is configured to provide control signals to multiple rows (e.g., two rows) of sub-pixels. In some embodiments, the fifth scanning circuit SC5 is an emission control signal generation circuit, which is configured to generate an emission control signal for the sub-pixels in the array substrate. In one example, the fifth scanning circuit SC5 is an emission control signal generation circuit, which is configured to generate an emission control signal for multiple emission control signal lines ( Figure 10A the corresponding emission control signal line em is shown in). The multiple emission control signal lines are configured to provide the emission control signal to the third transistor T3 and the fourth transistor T4 (e.g., p-type transistors) in each pixel driving circuit.

[0273] Figure 12 is a schematic diagram showing a first scanning circuit in a display device according to some embodiments of the present disclosure. Refer to Figure 12, in some embodiments, the first scan circuit includes a plurality of first scan units and a plurality of second scan units. Optionally, the plurality of first scan units and the plurality of second scan units are arranged alternately. Optionally, each first scan unit RSU1 and each second scan unit RSU2 are configured to provide control signals to adjacent two rows of sub-pixels respectively. In one example, each first scan unit RSU1 and each second scan unit RSU2 are configured to provide a first gate scan signal to a data writing transistor in a pixel driving circuit in adjacent two rows of sub-pixels respectively.

[0274] In some embodiments, the control signal output from each first scan unit RSU1 and provided to the first adjacent row of sub-pixels is out of phase with the control signal output from each second scan unit RSU2 and provided to the second adjacent row of sub-pixels. In one example, the first gate scan signal output from each first scan unit RSU1 and provided to the first adjacent row of sub-pixels is out of phase with the first gate scan signal output from each second scan unit RSU2 and provided to the second adjacent row of sub-pixels.

[0275] Figure 13 is a schematic diagram showing a second scan circuit in a display device according to some embodiments of the present disclosure. Refer to Figure 13 , in some embodiments, the second scan circuit SC2 includes a plurality of third scan units. Optionally, each third scan unit RSU3 in the plurality of third scan units is configured to provide a control signal to adjacent two rows of sub-pixels. In one example, each third scan unit RSU3 in the plurality of third scan units is configured to provide a second gate scan signal to a compensation transistor in a pixel driving circuit in adjacent two rows of sub-pixels.

[0276] In some embodiments, the control signal output from each third scan unit RSU3 and provided to the first adjacent row of sub-pixels is in phase with the control signal output from each third scan unit RSU3 and provided to the second adjacent row of sub-pixels. In one example, the second gate scan signal output from each third scan unit RSU3 and provided to the first adjacent row of sub-pixels is in phase with the second gate scan signal output from each third scan unit RSU3 and provided to the second adjacent row of sub-pixels.

[0277] In some embodiments, the display device includes K rows of sub-pixels, where K is an integer greater than 1. The K rows of sub-pixels include the (2k - 1)-th row of sub-pixels and the (2k)-th row of sub-pixels, where 1 ≤ k ≤ K / 2 and k is an integer. Refer to Figure 12 and Figure 13, in some embodiments, the first scanning circuit includes a plurality of first scanning units and a plurality of second scanning units. Optionally, the plurality of first scanning units and the plurality of second scanning units are arranged alternately. Optionally, each first scanning unit RSU1 is configured to provide a control signal to the sub-pixels of the (2k - 1)-th row, and each second scanning unit RSU2 is configured to provide a control signal to the sub-pixels of the (2k)-th row. In one example, each first scanning unit RSU1 is configured to provide a first gate scanning signal to the data writing transistor in the pixel driving circuit of the sub-pixels of the (2k - 1)-th row, and each second scanning unit RSU2 is configured to provide a first gate scanning signal to the data writing transistor in the pixel driving circuit of the sub-pixels of the (2k)-th row.

[0278] In some embodiments, the control signal output from each first scanning unit RSU1 and provided to the sub-pixels of the (2k - 1)-th row is out of phase with the control signal output from each second scanning unit RSU2 and provided to the sub-pixels of the (2k)-th row. In one example, the first gate scanning signal output from each first scanning unit RSU1 and provided to the sub-pixels of the (2k - 1)-th row is out of phase with the first gate scanning signal output from each second scanning unit RSU2 and provided to the sub-pixels of the (2k)-th row.

[0279] In some embodiments, the second scanning circuit SC2 includes a plurality of third scanning units. Optionally, each third scanning unit RSU3 among the plurality of third scanning units is configured to provide a control signal to the sub-pixels of the (2k - 1)-th row and the sub-pixels of the (2k)-th row. In one example, each third scanning unit RSU3 among the plurality of third scanning units is configured to provide a second gate scanning signal to the compensation transistor in the pixel driving circuit of the sub-pixels of the (2k - 1)-th row and the (2k)-th row.

[0280] In some embodiments, the control signal output from each third scanning unit RSU3 and provided to the sub-pixels of the (2k - 1)-th row is in phase with the control signal output from each third scanning unit RSU3 and provided to the sub-pixels of the (2k)-th row. In one example, the second gate scanning signal output from each third scanning unit RSU3 and provided to the sub-pixels of the (2k - 1)-th row is in phase with the second gate scanning signal output from each third scanning unit RSU3 and provided to the sub-pixels of the (2k)-th row.

[0281] As used herein, the terms "the (2k - 1)-th row" and "the (2k)-th row" are used in the context of K rows. The array substrate may or may not include additional rows before the first row among the K rows and / or additional rows after the last row among the K rows. In the context of the array substrate, the term "the (2k - 1)-th row" does not necessarily represent an odd row, and the term "the (2k)-th row" does not necessarily represent an even row. In one example, the (2k - 1)-th row is an odd row in the context of K rows, but may be an even row in the context of the array substrate. In another example, the (2k - 1)-th row is an odd row in the context of K rows and is also an odd row in the context of the array substrate. In one example, the (2k)-th row is an even row in the context of K rows, but may be an odd row in the context of the array substrate. In another example, the (2k)-th row is an even row in the context of K rows and is also an even row in the context of the array substrate.

[0282] Figure 14A is a schematic diagram showing the structure of a plurality of scan units in multiple rows of a scan circuit according to some embodiments of the present disclosure. Figure 14B is showing Figure 14A the structure of the semiconductor material layer in the scan circuit shown. Figure 14C is showing Figure 14A the structure of the first conductive layer in the scan circuit shown. Figure 14D is showing Figure 14A the structure of the second conductive layer in the scan circuit shown. Figure 14E is showing Figure 14A the structure of the first signal line layer in the scan circuit shown.

[0283] Figure 14F is showing Figure 14A the structure of the second signal line layer in the scan circuit shown. Figure 14A are marked with labels indicating transistors (T1, T2, T3, T4, T5, T6, T7, and T8) and capacitors (C1 and C2) in each scan unit, as well as signal lines (CBL, CKL, VGLL, VGHL, STVL, Vint1, Vint2, and Vint3).

[0284] Referring to Figure 14A and Figure 14B , in some embodiments, the semiconductor material layer includes the active layer of the transistors in each scan unit. Figure 14BMarked with marks indicating the active layers of the transistors in respective scan units, e.g., the active layer ACT1 of the first transistor T1, the active layer ACT2 of the second transistor T2, the active layer ACT3 of the third transistor T3, the active layer ACT4 of the fourth transistor T4, the active layer ACT5 of the fifth transistor T5, the active layer ACT6 of the sixth transistor T6, the active layer ACT7 of the seventh transistor T7, and the active layer ACT8 of the eighth transistor T8. Figure 14B Further marked with marks indicating the first and second electrodes of certain transistors in respective scan units. For example, the first transistor T1 includes a first electrode S1 and a second electrode D1, the second transistor T2 includes a first electrode S2 and a second electrode D2, the third transistor T3 includes a first electrode S3 and a second electrode D3, the sixth transistor T6 includes a first electrode S6 and a second electrode D6, the seventh transistor T7 includes a first electrode S7 and a second electrode D7, and the eighth transistor T8 includes a first electrode S8 and a second electrode D8. Various suitable semiconductor materials can be used to fabricate the semiconductor material layer. Examples of semiconductor materials for forming the semiconductor material layer include metal oxide-based semiconductor materials (e.g., indium gallium zinc oxide) and metal oxynitride-based semiconductor materials (e.g., zinc oxide nitride).

[0285] Reference Figure 14A And Figure 14C , in some embodiments, the first conductive layer includes the first capacitor electrode Ce1 of the first capacitor C1, the third capacitor electrode Ce3 of the second capacitor C2, the gate G1 of the first transistor T1, the gate G2 of the second transistor T2, the gate G3 of the third transistor T3, the gate G4 of the fourth transistor T4, the gate G5 of the fifth transistor T5, the gate G6 of the sixth transistor T6, the gate G7 of the seventh transistor T7, and the gate G8 of the eighth transistor T8. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first conductive layer. For example, the conductive material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for fabricating the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum copper alloy, copper molybdenum alloy, molybdenum aluminum alloy, aluminum chromium alloy, copper chromium alloy, molybdenum chromium alloy, copper molybdenum aluminum alloy, etc.

[0286] Reference Figure 14A And Figure 14D, in some embodiments, the second conductive layer includes the first electrode S4 of the fourth transistor T4, the second electrode D4 of the fourth transistor T4, the first electrode S5 of the fifth transistor T5, the second electrode D5 of the fifth transistor T5, and a plurality of connection lines. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the second conductive layer. For example, a conductive material can be deposited on a substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc.

[0287] Reference Figure 14A and Figure 14E , in some embodiments, the first signal line layer includes the second capacitor electrode Ce2 of the first capacitor C1 and the fourth capacitor electrode Ce4 of the second capacitor C2. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the first signal line layer. For example, a conductive material can be deposited on a substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. In some embodiments, the first signal line layer includes a plurality of sub-layers stacked together. In one example, the first signal line layer includes a stacked titanium / aluminum / titanium multi-layer structure. In another example, the first signal line layer includes a stacked molybdenum / aluminum / molybdenum multi-layer structure.

[0288] Reference Figure 14A and Figure 14F, in some embodiments, the second signal line layer includes a first power supply signal line VGLL configured to provide a first power supply signal, a second power supply signal line VGHL configured to provide a second power supply signal, a first clock signal line CKL configured to provide a first clock signal, a second clock signal line CBL configured to provide a second clock signal, a start signal line STVL configured to provide a start signal, a first reset signal supply line Vint1 configured to provide a first reset signal, a second reset signal supply line Vint2 configured to provide a second reset signal, and a third reset signal supply line Vint3 configured to provide a third reset signal. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second signal line layer. For example, the conductive material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the second signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. In some embodiments, the second signal line layer includes a plurality of sub-layers stacked together. In one example, the second signal line layer includes a stacked titanium / aluminum / titanium multi-layer structure. In another example, the second signal line layer includes a stacked molybdenum / aluminum / molybdenum multi-layer structure.

[0289] Reference Figure 14A to Figure 14F , in some embodiments, each scan unit of the scan circuit includes a first pad PAD1 and a second pad PAD2. Optionally, the first pad PAD1 and the second pad PAD2 are located in the first conductive layer. In some embodiments, the first pad PAD1 includes the gate G7 of the seventh transistor T7. In some embodiments, the second pad PAD2 includes the gate G1 of the first transistor T1 and the gate G3 of the third transistor T3. Optionally, the first pad PAD1 is an integral structure. Optionally, the second pad PAD2 is an integral structure.

[0290] In some embodiments, the first pad PAD1 in the scan unit in the (2k - 1)-th row is connected to the first electrode S5 of the fifth transistor T5 in the scan unit in the (2k - 1)-th row. In some embodiments, the first pad PAD1 in the scan unit in the (2k)-th row is connected to the first electrode S5 of the fifth transistor T5 in the scan unit in the (2k)-th row.

[0291] Figure 14G is a schematic diagram showing Figure 14A the connection of the first connection line and the second connection line in the scan circuit shown. Reference Figure 14A to Figure 14G, in some embodiments, the scan circuit includes a plurality of first connection lines CL1. Optionally, the plurality of first connection lines CL1 are located in the second conductive layer. Optionally, each of the plurality of first connection lines CL1 exists in the scan cells of the (2k - 1)-th row and does not exist in the scan cells of the (2k)-th row.

[0292] In some embodiments, each of the plurality of first connection lines CL1 in the scan cells of the (2k - 1)-th row is electrically connected to the gate G7 of the seventh transistor T7 in the scan cells of the (2k - 1)-th row, electrically connected to the first electrode S5 of the fifth transistor T5 in the scan cells of the (2k - 1)-th row, electrically connected to the gate G1 of the first transistor T1 and the gate G3 of the third transistor T3 in the scan cells of the (2k)-th row, electrically connected to the first electrode S2 of the second transistor T2 in the scan cells of the (2k)-th row, and electrically connected to the first clock signal line CKL.

[0293] In some embodiments, each first connection line is connected to the first pad PAD1 in the scan cells of the (2k - 1)-th row, connected to the second pad PAD2 in the scan cells of the (2k)-th row, connected to the first electrode S2 of the second transistor T2 in the scan cells of the (2k)-th row, and connected to the first clock signal line CKL.

[0294] Reference Figure 14A to Figure 14F , in some embodiments, the scan circuit includes a plurality of second connection lines CL2. Optionally, the plurality of second connection lines CL2 are located in the second conductive layer. Optionally, each of the plurality of second connection lines CL2 exists in the scan cells of the (2k)-th row and does not exist in the scan cells of the (2k - 1)-th row.

[0295] In some embodiments, each of the plurality of second connection lines CL2 in the scan cells of the (2k)-th row is electrically connected to the gate G7 of the seventh transistor T7 in the scan cells of the (2k)-th row, electrically connected to the first electrode S5 of the fifth transistor T5 in the scan cells of the (2k)-th row, electrically connected to the gate G1 of the first transistor T1 and the gate G3 of the third transistor T3 in the scan cells of the (2k + 1)-th row, electrically connected to the first electrode S2 of the second transistor T2 in the scan cells of the (2k + 1)-th row, and electrically connected to the second clock signal line CBL.

[0296] In some embodiments, each of the second connection lines is connected to a first pad PAD1 in a scan unit in the (2k)-th row, connected to a second pad PAD2 in a scan unit in the (2k + 1)-th row, connected to a first electrode S2 of a second transistor T2 in a scan unit in the (2k + 1)-th row, and connected to a first clock signal line CBL.

[0297] Figure 14A to Figure 14F The scan units of the scan circuit described in Figure 1 and Figure 3 correspond to the scan units described in Figure 14A to Figure 14F The scan units in the (2k)-th row of the scan circuit described in Figure 1 correspond to the scan units described in Figure 14A to Figure 14F The scan units in the (2k - 1)-th row and the (2k + 1)-th row of the scan circuit described in Figure 3 correspond to the scan units described in

[0298] Figure 15A is a schematic diagram showing the structure of a plurality of scan units in multiple rows of a scan circuit according to some embodiments of the present disclosure. Figure 15B is a schematic diagram showing Figure 15A the structure of a semiconductor material layer in the scan circuit shown in Figure 15C is a schematic diagram showing Figure 15A the structure of a first conductive layer in the scan circuit shown in Figure 15D is a schematic diagram showing Figure 15A the structure of a second conductive layer in the scan circuit shown in Figure 15E is a schematic diagram showing Figure 15A the structure of a first signal line layer in the scan circuit shown in

[0299] Figure 15F is a schematic diagram showing ​ the structure of a second signal line layer in the scan circuit shown in ​ is a schematic diagram showing ​ the structure of a third signal line layer in the scan circuit shown in ​ is marked with marks indicating transistors (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, and T13), capacitors (C1, C2, and C3), and signal lines (CBL, CKL, VGLL, VGHL, and STVL) in each scan unit.

[0300] Referring to ​ and ​ , in some embodiments, the semiconductor material layer includes an active layer of a transistor in each scan unit. ​Marked with marks that indicate the active layers of the transistors in each scanning unit. For example, the active layer ACT1 of the first transistor T1, the active layer ACT2 of the second transistor T2, the active layer ACT3 of the third transistor T3, the active layer ACT4 of the fourth transistor T4, the active layer ACT5 of the fifth transistor T5, the active layer ACT6 of the sixth transistor T6, the active layer ACT7 of the seventh transistor T7, the active layer ACT8 of the eighth transistor T8, the active layer ACT9 of the ninth transistor T9, the active layer ACT10 of the tenth transistor T10, the active layer ACT11 of the eleventh transistor T11, the active layer ACT12 of the twelfth transistor T12, and the active layer ACT13 of the thirteenth transistor T13. ​ Further marked with marks that indicate the first and second electrodes of certain transistors in each scanning unit. For example, the first transistor T1 includes a first electrode S1 and a second electrode D1, the second transistor T2 includes a first electrode S2 and a second electrode D2, the third transistor T3 includes a first electrode S3 and a second electrode D3, the fourth transistor T4 includes a first electrode S4 and a second electrode D4, the fifth transistor T5 includes a first electrode S5 and a second electrode D5, the sixth transistor T6 includes a first electrode S6 and a second electrode D6, the seventh transistor T7 includes a first electrode S7 and a second electrode D7, the eighth transistor T8 includes a first electrode S8 and a second electrode D8, the eleventh transistor T11 includes a first electrode S11 and a second electrode D11, the twelfth transistor T12 includes a first electrode S12 and a second electrode D12, and the thirteenth transistor T13 includes a first electrode S13 and a second electrode D13.

[0301] Reference ​ And ​ , in some embodiments, the first conductive layer includes the first capacitor electrode Ce1 of the first capacitor C1, the third capacitor electrode Ce3 of the second capacitor C2, the fifth capacitor electrode Ce5 of the third capacitor C3, the gate G1 of the first transistor T1, the gate G2 of the second transistor T2, the gate G3 of the third transistor T3, the gate G4 of the fourth transistor T4, the gate G5 of the fifth transistor T5, the gate G6 of the sixth transistor T6, the gate G7 of the seventh transistor T7, the gate G8 of the eighth transistor T8, the gate G9 of the ninth transistor T9, the gate G10 of the tenth transistor T10, the gate G11 of the eleventh transistor T11, the gate G12 of the twelfth transistor T12, and the gate G13 of the thirteenth transistor T13.

[0302] Reference ​ And ​, in some embodiments, the second conductive layer includes the first electrode S9 of the ninth transistor T9, the second electrode D9 of the ninth transistor T9, the first electrode S10 of the tenth transistor T10, the second electrode D10 of the tenth transistor T10, a first power supply signal line VGLL configured to provide a first power supply signal, and a plurality of connection lines.

[0303] Reference Figure 15A and Figure 15E , in some embodiments, the first signal line layer includes the second capacitor electrode Ce2 of the first capacitor C1, the fourth capacitor electrode Ce4 of the second capacitor C2, and the sixth capacitor electrode Ce6 of the third capacitor C3.

[0304] Reference Figure 15A and Figure 15F , in some embodiments, the second signal line layer includes a second power supply signal line VGHL configured to provide a second power supply signal, a first clock signal line CKL configured to provide a first clock signal, a second clock signal line CBL configured to provide a second clock signal, a control signal line CXL configured to provide a control signal to the gate of the thirteenth transistor T13, and a start signal line STVL configured to provide a start signal.

[0305] Reference Figure 15A With Figure 15G , in some embodiments, the third signal line layer includes a plurality of output connection lines OUTCL. Each of the plurality of output connection lines OUTCL is connected to the second electrode of the ninth transistor T9 and is connected to the second electrode of the tenth transistor T10.

[0306] Reference Figures 15A to 15F , in some embodiments, each scanning unit of the scanning circuit includes a first pad PAD1 and a second pad PAD2. Optionally, the first pad PAD1 and the second pad PAD2 are located in the first conductive layer. In some embodiments, the first pad PAD1 includes the gate G7 of the seventh transistor T7. In some embodiments, the second pad PAD2 includes the gate G1 of the first transistor T1 and the gate G3 of the third transistor T3. Optionally, the first pad PAD1 is an integral structure. Optionally, the second pad PAD2 is an integral structure.

[0307] Figure 15H is a schematic diagram showing Figure 15A the connection of the first connection line and the second connection line in the scanning circuit shown. Reference Figures 15A to 15H, in some embodiments, the scan circuit includes a plurality of first connection lines CL1. Optionally, the plurality of first connection lines CL1 are located in the second conductive layer. Optionally, each of the plurality of first connection lines CL1 exists in the scan cells of the (2k - 1)-th row and does not exist in the scan cells of the (2k)-th row.

[0308] In some embodiments, each of the plurality of first connection lines CL1 in the scan cells of the (2k - 1)-th row is electrically connected to the gate G7 of the seventh transistor T7 in the scan cells of the (2k - 1)-th row, electrically connected to the first electrode S4 of the fourth transistor T4 in the scan cells of the (2k - 1)-th row, electrically connected to the first electrode S6 of the sixth transistor T6 in the scan cells of the (2k - 1)-th row, electrically connected to the gates G1 of the first transistor T1 and the gate G3 of the third transistor T3 in the scan cells of the (2k)-th row, and electrically connected to the first clock signal line CBL.

[0309] In some embodiments, each first connection line is connected to the first pad PAD1 in the scan cells of the (2k - 1)-th row, connected to the second pad PAD2 in the scan cells of the (2k)-th row, connected to the first electrode S4 of the fourth transistor T4 in the scan cells of the (2k - 1)-th row, connected to the first electrode S6 of the sixth transistor T6 in the scan cells of the (2k - 1)-th row, and connected to the first clock signal line CBL.

[0310] Reference Figures 15A to 15F , in some embodiments, the scan circuit includes a plurality of second connection lines CL2. Optionally, the plurality of second connection lines CL2 are located in the second conductive layer. Optionally, each of the plurality of second connection lines CL2 exists in the scan cells of the (2k)-th row and does not exist in the scan cells of the (2k - 1)-th row.

[0311] In some embodiments, each of the plurality of second connection lines CL2 in the scan cells of the (2k)-th row is electrically connected to the gate G7 of the seventh transistor T7 in the scan cells of the (2k)-th row, electrically connected to the first electrode S4 of the fourth transistor T4 in the scan cells of the (2k)-th row, electrically connected to the first electrode S6 of the sixth transistor T6 in the scan cells of the (2k)-th row, electrically connected to the gates G1 of the first transistor T1 and the gate G3 of the third transistor T3 in the scan cells of the (2k + 1)-th row, and electrically connected to the second clock signal line CKL.

[0312] In some embodiments, each of the second connection lines is connected to the first pad PAD1 in the scan unit in the (2k)-th row, connected to the second pad PAD2 in the scan unit in the (2k + 1)-th row, connected to the first electrode S4 of the fourth transistor T4 in the scan unit in the (2k)-th row, connected to the first electrode S6 of the sixth transistor T6 in the scan unit in the (2k)-th row, and connected to the first clock signal line CKL.

[0313] Figures 15A to 15G The scan unit in the scan circuit shown in Figure 7 and Figure 8 corresponds to the scan unit shown in Figures 15A to 15F The scan unit in the (2k)-th row in the scan circuit shown in Figure 8 corresponds to the scan unit shown in Figures 15A to 15F The scan units in the (2k - 1)-th row and the (2k + 1)-th row in the scan circuit shown in Figure 7 correspond to the scan unit shown in

[0314] Figure 16A is a schematic diagram showing the structure of multiple scan units in multiple rows of a scan circuit according to some embodiments of the present disclosure. Figure 16B is a schematic diagram showing Figure 16A the structure of the semiconductor material layer in the scan circuit shown in Figure 16C is a schematic diagram showing Figure 16A the structure of the first conductive layer in the scan circuit shown in Figure 16D is a schematic diagram showing Figure 16A the structure of the second conductive layer in the scan circuit shown in Figure 16E is a schematic diagram showing Figure 16A the structure of the first signal line layer in the scan circuit shown in

[0315] Figure 16F is a schematic diagram showing Figure 16A the structure of the second signal line layer in the scan circuit shown in Figure 16G is a schematic diagram showing Figure 16A the structure of the third signal line layer in the scan circuit shown in Figure 16A is marked with labels indicating the transistors (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, and T15) and capacitors (C1, C2, and C3) in each scan unit, as well as the signal lines (CBL, CKL, CXL, VGLL, STVL1, STVL2, VGLL1, VGLL2, VGLL3, VGHL1, VGHL2, and VGHL3).

[0316] Refer to Figure 16A andFigure 16B In some embodiments, the semiconductor material layer includes the active layers of the transistors in each scanning unit. Figure 16B Markings are used to indicate the active layers of the transistors in each scanning unit. For example, the active layer of the first transistor T1 is ACT1, the active layer of the second transistor T2 is ACT2, the active layer of the third transistor T3 is ACT3, the active layer of the fourth transistor T4 is ACT4, the active layer of the fifth transistor T5 is ACT5, the active layer of the sixth transistor T6 is ACT6, the active layer of the seventh transistor T7 is ACT7, the active layer of the eighth transistor T8 is ACT8, the active layer of the ninth transistor T9 is ACT9, the active layer of the tenth transistor T10 is ACT10, the active layer of the eleventh transistor T11 is ACT11, the active layer of the twelfth transistor T12 is ACT12, the active layer of the thirteenth transistor T13 is ACT13, the active layer of the fourteenth transistor T14 is ACT14, the active layer of the fifteenth transistor T15 is ACT15, and the active layer of the sixteenth transistor T16 is ACT16. Figure 16B Further markings are used to indicate the first and second electrodes of certain transistors in each scanning unit. For example, the first transistor T1 includes a first electrode S1 and a second electrode D1, the second transistor T2 includes a first electrode S2 and a second electrode D2, the third transistor T3 includes a first electrode S3 and a second electrode D3, the fourth transistor T4 includes a first electrode S4 and a second electrode D4, the fifth transistor T5 includes a first electrode S5 and a second electrode D5, the sixth transistor T6 includes a first electrode S6 and a second electrode D6, the seventh transistor T7 includes a first electrode S7 and a second electrode D7, the eighth transistor T8 includes a first electrode S8 and a second electrode D8, the eleventh transistor T11 includes a first electrode S11 and a second electrode D11, the twelfth transistor T12 includes a first electrode S12 and a second electrode D12, the thirteenth transistor T13 includes a first electrode S13 and a second electrode D13, the fourteenth transistor T14 includes a first electrode S14 and a second electrode D14, the fifteenth transistor T15 includes a first electrode S15 and a second electrode D15, and the sixteenth transistor T16 includes a first electrode S16 and a second electrode D16.

[0317] Refer to Figure 16A and Figure 16C, in some embodiments, the first conductive layer includes the first capacitor electrode Ce1 of the first capacitor C1, the third capacitor electrode Ce3 of the second capacitor C2, the fifth capacitor electrode Ce5 of the third capacitor C3, the gate G1 of the first transistor T1, the gate G2 of the second transistor T2, the gate G3 of the third transistor T3, the gate G4 of the fourth transistor T4, the gate G5 of the fifth transistor T5, the gate G6 of the sixth transistor T6, the gate G7 of the seventh transistor T7, the gate G8 of the eighth transistor T8, the gate G9 of the ninth transistor T9, the gate G10 of the tenth transistor T10, the gate G11 of the eleventh transistor T11, the gate G12 of the twelfth transistor T12, the gate G13 of the thirteenth transistor T13, the gate G14 of the fourteenth transistor T14, the gate G15 of the fifteenth transistor T15, and the gate G16 of the sixteenth transistor T16.

[0318] Reference Figure 16A With Figure 16D , in some embodiments, the second conductive layer includes the first electrode S9 of the ninth transistor T9, the second electrode D9 of the ninth transistor T9, the first electrode S10 of the tenth transistor T10, and the second electrode D10 of the tenth transistor T10.

[0319] Reference Figure 16A And Figure 16E , in some embodiments, the first signal line layer includes the second capacitor electrode Ce2 of the first capacitor C1, the fourth capacitor electrode Ce4 of the second capacitor C2, and the sixth capacitor electrode Ce6 of the third capacitor C3.

[0320] Reference Figure 16A And Figure 16F , in some embodiments, the second signal line layer includes a first clock signal line CKL configured to provide a first clock signal, a second clock signal line CBL configured to provide a second clock signal, a first start signal line STVL1 configured to provide a start signal, a second start signal line STVL2 configured to provide a start signal, a control signal line CXL configured to provide a control signal to the gate of the thirteenth transistor T13, a plurality of first power signal lines (e.g., VGLL1, VGLL2, and VGLL3) configured to provide a first power signal, and a plurality of second power signal lines (e.g., VGHL1 and VGHL2) configured to provide a second power signal.

[0321] Reference Figure 16A And Figure 16G , in some embodiments, the third signal line layer includes a plurality of first power connection lines VGLCL configured to connect at least two of the plurality of first power lines.

[0322] Reference Figures 16A to 16G, in some embodiments, the scan circuit includes a first pad PAD1. Optionally, the first pad PAD1 is located on the first conductive layer. Optionally, the first pad PAD1 includes the gate G7 of the seventh transistor T7 in the scan units of the (2k)th row. The first pad PAD1 extends from the area having the scan units of the (2k - 1)th row into the area having the scan units of the (2k)th row, and is connected to the second power supply line CKL at this position.

[0323] Figure 17A is a schematic diagram showing the structure of multiple scan units in multiple rows of scan units in the scan circuit and one or more dummy scan units in one or more rows of dummy scan units according to some embodiments of the present disclosure. Figure 17B is a schematic diagram showing Figure 17A the structure of the semiconductor material layer in the scan circuit shown. Figure 17C is a schematic diagram showing Figure 17A the structure of the first conductive layer in the scan circuit shown. Figure 17D is a schematic diagram showing Figure 17A the structure of the second conductive layer in the scan circuit shown. Figure 17E is a schematic diagram showing Figure 17A the structure of the first signal line layer in the scan circuit shown. Figure 17F is a schematic diagram showing Figure 17A the structure of the second signal line layer in the scan circuit shown. Figure 17G is a schematic diagram showing Figure 17A the connection of the first connection line in the scan circuit shown. Figure 17A is marked with labels that indicate the transistors (T1, T2, T3, T4, T5, T6, T7, and T8) and capacitors (C1 and C2) of the scan units, the dummy transistors (DT1, DT2, DT3, DT4, DT5, DT6, DT7, and DT8) and dummy capacitors (DC1 and DC2) of the dummy scan units, and the signal lines (CBL, CKL, VGLL, VGHL, STVL, Vint1, Vint2, and Vint3) in each scan unit.

[0324] As used herein, the term "dummy" refers to a unit having the same or similar structure as a scan unit, but this structure is only for a configuration that exists as a pattern and does not actually perform the functions in the scan circuit. Therefore, an electrical signal may not be applied to the "dummy" scan unit, or even if an electrical signal is applied to the "dummy" scan unit, the "dummy" scan unit may not perform an electrically equivalent function.

[0325] Refer to Figures 17A to 17G, the area circled by the dashed line represents an area having one or more dummy scan units. In some embodiments, the scan circuit includes scan units in the (2k - 1)-th row and scan units in the (2k)-th row, and one or more dummy scan units that separate the scan units in the (2k - 1)-th row and the scan units in the (2k)-th row.

[0326] Reference Figure 17A With Figure 17B , in some embodiments, the semiconductor material layer includes the active layers of the transistors in each scan unit. Figure 17B Marked with a label that indicates the active layer of the transistor in each scan unit. For example, the active layer ACT1 of the first transistor T1, the active layer ACT2 of the second transistor T2, the active layer ACT3 of the third transistor T3, the active layer ACT4 of the fourth transistor T4, the active layer ACT5 of the fifth transistor T5, the active layer ACT6 of the sixth transistor T6, the active layer ACT7 of the seventh transistor T7, and the active layer ACT8 of the eighth transistor T8. Figure 17B Further marked with a label that indicates the dummy active layer of the dummy transistor in each dummy scan unit. For example, the dummy active layer DACT1 of the first dummy transistor DT1, the dummy active layer DACT2 of the second dummy transistor DT2, the dummy active layer DACT3 of the third dummy transistor DT3, the dummy active layer DACT4 of the fourth dummy transistor DT4, the dummy active layer DACT5 of the fifth dummy transistor DT5, the dummy active layer DACT6 of the sixth dummy transistor DT6, the dummy active layer DACT7 of the seventh dummy transistor DT7, and the dummy active layer DACT8 of the eighth dummy transistor DT8. Figure 17B Further marked with a label that indicates the first and second electrodes of certain transistors in each scan unit. For example, the first transistor T1 includes a first electrode S1 and a second electrode D1, the second transistor T2 includes a first electrode S2 and a second electrode D2, the third transistor T3 includes a first electrode S3 and a second electrode D3, the sixth transistor T6 includes a first electrode S6 and a second electrode D6, the seventh transistor T7 includes a first electrode S7 and a second electrode D7, and the eighth transistor T8 includes a first electrode S8 and a second electrode D8. Figure 17BFurther, it is marked with marks that indicate the dummy first electrodes and dummy second electrodes of certain dummy transistors in each scanning unit. For example, the first dummy transistor DT1 includes a dummy first electrode DS1 and a dummy second electrode DD1, the second dummy transistor DT2 includes a dummy first electrode DS2 and a dummy second electrode DD2, the third dummy transistor DT3 includes a dummy first electrode DS3 and a dummy second electrode DD3, the sixth dummy transistor DT6 includes a dummy first electrode DS6 and a dummy second electrode DD6, the seventh dummy transistor DT7 includes a dummy first electrode DS7 and a dummy second electrode DD7, and the eighth dummy transistor DT8 includes a dummy first electrode DS8 and a dummy second electrode DD8.

[0327] Reference Figure 17A and Figure 17C , in some embodiments, with respect to the scanning unit, the first conductive layer includes a first capacitor electrode Ce1 of the first capacitor C1, a third capacitor electrode Ce3 of the second capacitor C2, a gate G1 of the first transistor T1, a gate G2 of the second transistor T2, a gate G3 of the third transistor T3, a gate G4 of the fourth transistor T4, a gate G5 of the fifth transistor T5, a gate G6 of the sixth transistor T6, a gate G7 of the seventh transistor T7, and a gate G8 of the eighth transistor T8. In some embodiments, with respect to the dummy scanning unit, the first conductive layer further includes a dummy first capacitor electrode DCe1 of the first dummy capacitor DC1, a dummy third capacitor electrode DCe3 of the second dummy capacitor DC2, a dummy gate DG1 of the first dummy transistor DT1, a dummy gate DG2 of the second dummy transistor DT2, a dummy gate DG3 of the third dummy transistor DT3, a dummy gate DG4 of the fourth dummy transistor DT4, a dummy gate DG5 of the fifth dummy transistor DT5, a dummy gate DG6 of the sixth dummy transistor DT6, a dummy gate DG7 of the seventh dummy transistor DT7, and a dummy gate DG8 of the eighth dummy transistor DT8.

[0328] Reference Figure 17A With Figure 17D , in some embodiments, with respect to the scanning unit, the second conductive layer includes a first electrode S4 of the fourth transistor T4, a second electrode D4 of the fourth transistor T4, a first electrode S5 of the fifth transistor T5, a second electrode D5 of the fifth transistor T5, and a plurality of connection lines. In some embodiments, with respect to the dummy scanning unit, the second conductive layer further includes a dummy first electrode DS4 of the fourth dummy transistor DT4, a dummy second electrode DD4 of the fourth dummy transistor DT4, a dummy first electrode DS5 of the fifth dummy transistor DT5, and a dummy second electrode DD5 of the fifth dummy transistor DT5.

[0329] Reference Figure 17A and Figure 17E, in some embodiments, regarding the scan unit, the first signal line layer includes the second capacitor electrode Ce2 of the first capacitor C1 and the fourth capacitor electrode Ce4 of the second capacitor C2. In some embodiments, regarding the dummy scan unit, the first signal line layer further includes the dummy second capacitor electrode DCe2 of the first dummy capacitor DC1 and the dummy fourth capacitor electrode DCe4 of the second dummy capacitor DC2.

[0330] Reference Figure 17A and Figure 17F , in some embodiments, the second signal line layer includes a first power supply signal line VGLL configured to provide a first power supply signal, a second power supply signal line VGHL configured to provide a second power supply signal, a first clock signal line CKL configured to provide a first clock signal, a second clock signal line CBL configured to provide a second clock signal, a start signal line STVL configured to provide a start signal, a first reset signal supply line Vint1 configured to provide a first reset signal, a second reset signal supply line Vint2 configured to provide a second reset signal, and a third reset signal supply line Vint3 configured to provide a third reset signal.

[0331] Reference Figures 17A to 17F , in some embodiments, each scan unit of the scan circuit includes a first pad PAD1 and a second pad PAD2. Optionally, the first pad PAD1 and the second pad PAD2 are located in the first conductive layer. In some embodiments, the first pad PAD1 includes the gate G7 of the seventh transistor T7. In some embodiments, the second pad PAD2 includes the gate G1 of the first transistor T1 and the gate G3 of the third transistor T3. Optionally, the first pad PAD1 is an integral structure. Optionally, the second pad PAD2 is an integral structure.

[0332] In some embodiments, the first pad PAD1 in the scan unit in the (2k - 1)-th row is connected to the first electrode S5 of the fifth transistor T5 in the scan unit in the (2k - 1)-th row. In some embodiments, the first pad PAD1 in the scan unit in the (2k)-th row is connected to the first electrode S5 of the fifth transistor T5 in the scan unit in the (2k)-th row.

[0333] Figure 17G is a diagram showing Figure 17A the connection of the first connection line and the second connection line in the scan circuit shown in. Reference Figures 17A to 17G , in some embodiments, the scan circuit includes a plurality of first connection lines CL1. Optionally, the plurality of first connection lines CL1 are located in the second conductive layer.

[0334] In some embodiments, a separate first connection line among a plurality of first connection lines CL1 extends from a scan unit in the (2k - 1)-th row, passes through a region having one or more dummy scan units, and enters a scan unit in the (2k)-th row.

[0335] In some embodiments, each of the plurality of first connection lines CL1 in the scan unit in the (2k - 1)-th row is electrically connected to the gate G7 of the seventh transistor T7 in the scan unit in the (2k - 1)-th row, electrically connected to the first electrode S5 of the fifth transistor T5 in the scan unit in the (2k - 1)-th row, electrically connected to the gate G1 of the first transistor T1 and the gate G3 of the third transistor T3 in the scan unit in the (2k)-th row, electrically connected to the first electrode S2 of the second transistor T2 in the scan unit in the (2k)-th row, and electrically connected to the first clock signal line CKL.

[0336] In some embodiments, a separate first connection line is connected to the first pad PAD1 in the scan unit in the (2k - 1)-th row, extends through a region having one or more dummy scan units, is connected to the second pad PAD2 in the scan unit in the (2k)-th row, is connected to the first electrode S2 of the second transistor T2 in the scan unit in the (2k)-th row, and is connected to the first clock signal line CKL.

[0337] Reference Figures 14A to 14F And Figures 17A to 17F , in some embodiments, the scan circuit includes a plurality of second connection lines CL2. Optionally, the plurality of second connection lines CL2 are located in the second conductive layer.

[0338] In some embodiments, each of the plurality of second connection lines CL2 in the scan unit in the (2k)-th row is electrically connected to the gate G7 of the seventh transistor T7 in the scan unit in the (2k)-th row, electrically connected to the first electrode S5 of the fifth transistor T5 in the scan unit in the (2k)-th row, electrically connected to the gate G1 of the first transistor T1 and the gate G3 of the third transistor T3 in the scan unit in the (2k + 1)-th row, electrically connected to the first electrode S2 of the second transistor T2 in the scan unit in the (2k + 1)-th row, and electrically connected to the second clock signal line CBL.

[0339] In some embodiments, each second connection line is connected to the first pad PAD1 in the scan unit in the (2k)-th row, connected to the second pad PAD2 in the scan unit in the (2k + 1)-th row, connected to the first electrode S2 of the second transistor T2 in the scan unit in the (2k + 1)-th row, and connected to the first clock signal line CBL.

[0340] Figures 17A to 17FThe scan units of the scan circuit described in Figure 1 and Figure 3 the scan units described in Figures 17A to 17F The scan units in the (2k)-th row of the scan circuit described in Figure 1 the scan units described in Figures 17A to 17F The scan units in the (2k - 1)-th row and the (2k + 1)-th row of the scan circuit described in Figure 3 the scan units described in

[0341] In Figures 17A to 17G the shown scan circuit, since a separate first connection line extends through a region having one or more dummy scan units, and the separate first connection line is connected to the first clock signal line CKL. In comparison, each second connection line does not have to extend through a region having one or more dummy scan units, and each second connection line is connected to the second clock signal line CBL. The length of each first connection line is increased compared to each second connection line. This difference results in different loads between the first clock signal line CKL and the second clock signal line CBL. In some embodiments, due to this difference, the load on the first clock signal line CKL is significantly greater than the load on the second clock signal line CBL. As Figure 1 and Figure 3 shown, the output terminal of each scan unit in the (2k - 1)-th row is the second clock signal line CBL, and the output terminal of each scan unit in the (2k)-th row is the first clock signal line CKL. The difference in the load between the first clock signal line CKL and the second clock signal line CBL directly affects the output waveform of the scan circuit. In addition, even in a region far from one or more dummy scan units, due to the difference between the load on the first clock signal line CKL and the load on the second clock signal line CBL, the output signals from the scan units in the odd rows and the scan units in the even rows are different from each other, resulting in Figures 17A to 17G display non-uniformity in the display panel connected to the scan circuit shown in

[0342] Figure 18A is a schematic diagram showing the structure of a plurality of scan units in multiple rows of scan units and one or more dummy scan units in one or more rows of dummy scan units in a scan circuit according to some embodiments of the present disclosure. Figure 18B is a schematic diagram showing Figure 18A the structure of the semiconductor material layer in the scan circuit shown in Figure 18C is a schematic diagram showing Figure 18A the structure of the first conductive layer in the scan circuit shown in Figure 18D is a schematic diagram showing Figure 18A the structure of the second conductive layer in the scan circuit shown in Figure 18Eis a schematic diagram showing Figure 18A the structure of the first signal line layer in the scanning circuit shown. Figure 18F is a schematic diagram showing Figure 18A the structure of the second signal line layer in the scanning circuit shown. Figure 18G is a schematic diagram showing Figure 18A the structure of the third signal line layer in the scanning circuit shown. Figure 18H is a schematic diagram showing Figure 18A the connection of the first connection line in the scanning circuit shown.

[0343] Referring to Figures 18A to 18H , the area circled by the dashed line represents an area having one or more dummy scan units DSU. In some embodiments, the scanning circuit includes scan units in the (2k - 1)th row and scan units in the (2k)th row, and one or more dummy scan units DSU that separate the scan units in the (2k - 1)th row and the scan units in the (2k)th row.

[0344] In some embodiments, the scanning circuit includes a plurality of first connection lines CL1. Optionally, the plurality of first connection lines CL1 are located in the second conductive layer. In some embodiments, an individual first connection line among the plurality of first connection lines CL1 extends from a scan unit in the (2k - 1)th row through an area having one or more dummy scan units DSU and into a scan unit in the (2k)th row.

[0345] In some embodiments, referring to Figures 15A to 15G and Figures 18A to 18H , each of the plurality of first connection lines CL1 in the scan units in the (2k - 1)th row is electrically connected to the gate G7 of the seventh transistor T7 in the scan units in the (2k - 1)th row, electrically connected to the first electrode S4 of the fourth transistor T4 in the scan units in the (2k - 1)th row, electrically connected to the first electrode S6 of the sixth transistor T6 in the scan units in the (2k - 1)th row, electrically connected to the gate G1 of the first transistor T1 and the gate G3 of the third transistor T3 in the scan units in the (2k)th row, and electrically connected to the first clock signal line CBL.

[0346] In some embodiments, referring to Figures 15A to 15G and Figures 18A to 18H, a separate first connection line is connected to the first pad PAD1 in the scan unit in the (2k - 1)th row, connected to the first electrode S4 of the fourth transistor T4 in the scan unit in the (2k - 1)th row, connected to the first electrode S6 of the sixth transistor T6 in the scan unit in the (2k - 1)th row, extends through the area with one or more dummy scan units DSU, connected to the second pad PAD2 in the scan unit in the (2k)th row, and connected to the first clock signal line CBL.

[0347] Reference Figures 15A to 15G And Figures 18A to 18H , in some embodiments, the scan circuit includes a plurality of second connection lines CL2. Optionally, the plurality of second connection lines CL2 are located in the second conductive layer.

[0348] In some embodiments, each of the plurality of second connection lines CL2 in the scan unit in the (2k)th row is electrically connected to the gate G7 of the seventh transistor T7 in the scan unit in the (2k)th row, electrically connected to the first electrode S4 of the fourth transistor T4 in the scan unit in the (2k)th row, electrically connected to the first electrode S6 of the sixth transistor T6 in the scan unit in the (2k)th row, electrically connected to the gates G1 of the first transistor T1 and G3 of the third transistor T3 in the scan unit in the (2k + 1)th row, and electrically connected to the second clock signal line CKL.

[0349] In some embodiments, each second connection line is connected to the first pad PAD1 in the scan unit in the (2k)th row, connected to the second pad PAD2 in the scan unit in the (2k + 1)th row, connected to the first electrode S4 of the fourth transistor T4 in the scan unit in the (2k)th row, connected to the first electrode S6 of the sixth transistor T6 in the (2k)th row, and connected to the first clock signal line CKL.

[0350] Figures 18A to 18H The scan units of the shown scan circuit correspond to Figure 7 And Figure 8 The shown scan units. Figures 18A to 18G The scan units in the (2k)th row in the shown scan circuit correspond to Figure 8 The shown scan units. Figures 18A to 18G The scan units in the (2k - 1)th row in the shown scan circuit correspond to Figure 7 The shown scan units.

[0351] In Figures 18A to 18GIn the scanning circuit shown, since a separate first connection line extends through a region having one or more dummy scan cells and the separate first connection line is connected to a first clock signal line CKL. In comparison, each second connection line does not have to extend through a region having one or more dummy scan cells, and each second connection line is connected to a second clock signal line CBL. The length of each first connection line is increased compared to each second connection line. This difference results in different loads between the first clock signal line CKL and the second clock signal line CBL. In some embodiments, due to this difference, the load on the first clock signal line CKL is significantly greater than the load on the second clock signal line CBL. As Figure 1 and Figure 3 shown, the output terminal of each scan cell in the (2k - 1)-th row is the second clock signal line CBL, and the output terminal of each scan cell in the (2k)-th row is the first clock signal line CKL. The difference in the load between the first clock signal line CKL and the second clock signal line CBL directly affects the output waveform of the scanning circuit. In addition, even in a region far from one or more dummy scan cells, due to the difference in the load between the first clock signal line CKL and the second clock signal line CBL, the output signals from the scan cells in the odd rows and the even rows are different from each other, resulting in Figures 18A to 18G display non-uniformity in the display panel connected to the scanning circuit shown in

[0352] Figure 19A is a schematic diagram showing the structure of a plurality of scan cells in multiple rows of scan cells and one or more dummy scan cells in one or more rows of dummy scan cells in a scanning circuit according to some embodiments of the present disclosure. Figure 19B is a schematic diagram showing Figure 19A the structure of a semiconductor material layer in the scanning circuit shown. Figure 19C is a schematic diagram showing Figure 19A the structure of a first conductive layer in the scanning circuit shown. Figure 19D is a schematic diagram showing Figure 19A the structure of a second conductive layer in the scanning circuit shown. Figure 19E is a schematic diagram showing Figure 19A the structure of a first signal line layer in the scanning circuit shown. Figure 19F is a schematic diagram showing Figure 19A the structure of a second signal line layer in the scanning circuit shown. Figure 19G is a schematic diagram showing Figure 19A the structure of a third signal line layer in the scanning circuit shown.

[0353] Refer to Figures 19A to 19G, the area circled by the dashed line represents the area having one or more dummy scan units DSU. In some embodiments, the scan circuit includes the scan units in the (2k - 1)-th row and the scan units in the (2k)-th row, and one or more dummy scan units DSU that separate the scan units in the (2k - 1)-th row and the scan units in the (2k)-th row.

[0354] Figures 19A to 19G The scan units of the scan circuit shown in Figures 16A to 16G correspond to the scan circuit shown in Figures 19A to 19G The scan units in the (2k)-th row of the scan circuit shown in Figures 16A to 16G correspond to the scan units in the (2k)-th row of the scan circuit shown in Figures 19A to 19G The scan units in the (2k - 1)-th row of the scan circuit shown in Figures 16A to 16G correspond to the scan units in the (2k - 1)-th row of the scan circuit shown in

[0355] Refer to Figures 19A to 19G , in some embodiments, the scan circuit includes a first pad PAD1. Optionally, the first pad PAD1 is located in the first conductive layer. Optionally, the first pad PAD1 includes the gate G7 of the seventh transistor T7 in the scan units of the (2k)-th row. The first pad PAD1 extends in a direction away from the area having the scan units in the (2k - 1)-th row, and is connected to the second power supply line CKL at a position in the area having the scan units in the (2k - 1)-th row.

[0356] In some embodiments, the scan circuit includes a first connection line that connects the first pad PAD1 and the second power supply line CKL at a position in the area having the scan units in the (2k - 1)-th row. In some embodiments, the first connection line extends through the area having one or more dummy scan units DSU. In some embodiments, the first pad PAD1 that is at least partially in the area having the scan units in the (2k)-th row is connected to the second power supply line CKL at a position in the area having the scan units in the (2k - 1)-th row through the first connection line.

[0357] In some embodiments, the first connection line includes a first signal connection line SCL1 and a second signal connection line SCL2. Optionally, the first signal connection line SCL1 is located in the second conductive layer. Optionally, the second signal connection line SCL2 is located in the first conductive layer. In some embodiments, a first pad PAD1 at least partially in the region of the scan units in the (2k)th row is connected to a second power supply line CKL at a position in the region of the scan units in the (2k - 1)th row through the first signal connection line SCL1 and the second signal connection line SCL2. Optionally, the first signal connection line SCL1 extends at least partially in the region having one or more dummy scan units DSU. Optionally, the second signal connection line SCL2 extends at least partially in the region having one or more dummy scan units DSU.

[0358] Figure 20 is a schematic diagram showing a part of the structure of one or more scan circuits according to some embodiments of the present disclosure. Refer to Figure 20 , the scan units in the (2k - 1)th row and the scan units in the (2k)th row are separated by one or more dummy scan units DSU. A separate first connection line ICL1 extends through the region having one or more dummy scan units DSU. The separate first connection line ICL1 is connected to a first clock signal line CKL and is electrically connected to the scan units in the (2k)th row ( Figures 17A to 17G , Figures 18A to 18G ). Optionally, the separate first connection line ICL1 is also connected to the scan units in the (2k - 1)th row ( Figures 17A to 17G , Figures 18A to 18G , and Figures 19A to 19G ). Figure 20 shows a plurality of scan circuits. The inventors of the present disclosure have found that this structure causes a difference between the load on the first clock signal line and the load on the second clock signal line, resulting in display non-uniformity in the display panel connected to the scan circuit.

[0359] Figure 21A is a schematic diagram showing the structure of a plurality of scan units in multiple rows of scan units and one or more dummy scan units in one or more rows of dummy scan units in a scan circuit according to some embodiments of the present disclosure. Figure 21B is a schematic diagram showing Figure 21A the structure of the semiconductor material layer in the scan circuit shown. Figure 21C is a schematic diagram showing Figure 21A the structure of the first conductive layer in the scan circuit shown. Figure 21D is a schematic diagram showing Figure 21A the structure of the second conductive layer in the scan circuit shown. Figure 21E is a schematic diagram showing Figure 21ASchematic diagram of the structure of the first signal line layer in the scanning circuit shown. Figure 21F Shows Figure 21A Schematic diagram of the structure of the second signal line layer in the scanning circuit shown. Figure 21G Shows Figure 21A Schematic diagram of the connection of the first clock signal line and the second clock signal line in the scanning circuit shown.

[0360] Figures 21A to 21G The scanning unit in the scanning circuit shown in corresponds to Figures 17A to 17G The scanning unit in the scanning circuit shown in. Figures 21A to 21G The second scanning unit SU2 in the scanning circuit shown in corresponds to Figures 17A to 17G The scanning unit in the (2k)-th row in the scanning circuit shown in. Figures 21A to 21G The first scanning unit SU1 in the scanning circuit shown in corresponds to Figures 17A to 17G The scanning unit in the (2k - 1)-th row in the scanning circuit shown in. Figures 21A to 21G The first dummy scanning unit DSU1 and the second dummy scanning unit DSU2 shown in correspond to Figures 17A to 17G One or more dummy scanning units DSU shown in.

[0361] Figure 21A Marked with a label that indicates the transistors (T1, T2, T3, T4, T5, T6, T7, and T8) and capacitors (C1 and C2) of the scanning unit, the dummy transistors (DT1, DT3, DT4, DT5, DT7, and DT8) and dummy capacitor (DC1) of the dummy scanning unit, and the signal lines (CBL, CKL, VGLL, VGHL, STVL, Vint1, Vint2, and Vint3) in each scanning unit.

[0362] Refer to Figures 21A to 21G , in some embodiments, the scanning circuit includes a first scanning unit SU1, a first dummy scanning unit DSU1, and a second scanning unit SU2. Optionally, the first scanning unit SU1, the first dummy scanning unit DSU1, and the second scanning unit SU2 are arranged in sequence. Optionally, the first dummy scanning unit DSU1 separates the first scanning unit SU1 and the second scanning unit SU2.

[0363] In some embodiments, the scanning circuit further includes a second dummy scanning unit DSU2. Optionally, the first scanning unit SU1, the second dummy scanning unit DSU2, the first dummy scanning unit DSU1, and the second scanning unit SU2 are arranged in sequence. Optionally, the first dummy scanning unit DSU1 separates the second scanning unit SU2 and the second dummy scanning unit DSU2; and the second dummy scanning unit DSU2 separates the first dummy scanning unit DSU1 and the first scanning unit SU1.

[0364] Reference Figure 21A With Figure 21B , in some embodiments, the semiconductor material layer includes the active layers of the transistors in each scanning unit. Figure 21B Marked with a mark that indicates the active layer of the transistors in each scanning unit. For example, the active layer ACT1 of the first transistor T1, the active layer ACT2 of the second transistor T2, the active layer ACT3 of the third transistor T3, the active layer ACT4 of the fourth transistor T4, the active layer ACT5 of the fifth transistor T5, the active layer ACT6 of the sixth transistor T6, the active layer ACT7 of the seventh transistor T7, and the active layer ACT8 of the eighth transistor T8. Figure 21B Further marked with a mark that indicates the dummy active layer of the dummy transistors in each scanning unit. For example, the dummy active layer DACT1 of the first dummy transistor DT1, the dummy active layer DACT3 of the third dummy transistor DT3, the dummy active layer DACT4 of the fourth dummy transistor DT4, the dummy active layer DACT5 of the fifth dummy transistor DT5, and the dummy active layer DACT8 of the eighth dummy transistor DT8. Figure 21B Further marked with a mark that indicates the first electrode and the second electrode of certain transistors in each scanning unit. For example, the first transistor T1 includes a first electrode S1 and a second electrode D1, the second transistor T2 includes a first electrode S2 and a second electrode D2, the third transistor T3 includes a first electrode S3 and a second electrode D3, the sixth transistor T6 includes a first electrode S6 and a second electrode D6, the seventh transistor T7 includes a first electrode S7 and a second electrode D7, and the eighth transistor T8 includes a first electrode S8 and a second electrode D8. Figure 21B Further marked with a mark that indicates the dummy first electrode and the dummy second electrode of certain dummy transistors in each scanning unit. For example, the first dummy transistor DT1 includes a dummy first electrode DS1 and a dummy second electrode DD1, the third dummy transistor DT3 includes a dummy first electrode DS3 and a dummy second electrode DD3, the sixth dummy transistor DT6 includes a dummy first electrode DS6, and the eighth dummy transistor DT8 includes a dummy first electrode DS8 and a dummy second electrode DD8.

[0365] ReferenceFigure 21A and Figure 21C In some embodiments, with respect to the scan unit, the first conductive layer includes the first capacitor electrode Ce1 of the first capacitor C1, the third capacitor electrode Ce3 of the second capacitor C2, the gate G1 of the first transistor T1, the gate G2 of the second transistor T2, the gate G3 of the third transistor T3, the gate G4 of the fourth transistor T4, the gate G5 of the fifth transistor T5, the gate G6 of the sixth transistor T6, the gate G7 of the seventh transistor T7, and the gate G8 of the eighth transistor T8. In some embodiments, with respect to the dummy scan unit, the first conductive layer further includes the dummy first capacitor electrode DCe1 of the first dummy capacitor DC1, the dummy gate DG4 of the fourth dummy transistor DT4, the dummy gate DG5 of the fifth dummy transistor DT5, the dummy gate DG6 of the sixth dummy transistor DT6, and the dummy gate DG7 of the seventh dummy transistor DT7.

[0366] Reference Figure 21A and Figure 21D In some embodiments, with respect to the scan unit, the second conductive layer includes the first electrode S4 of the fourth transistor T4, the second electrode D4 of the fourth transistor T4, the first electrode S5 of the fifth transistor T5, the second electrode D5 of the fifth transistor T5, and a plurality of connection lines. In some embodiments, with respect to the dummy scan unit, the second conductive layer further includes the dummy first electrode DS4 of the fourth dummy transistor DT4, the dummy second electrode DD4 of the fourth dummy transistor DT4, the dummy first electrode DS5 of the fifth dummy transistor DT5, the dummy second electrode DD5 of the fifth dummy transistor DT5, and a plurality of connection lines.

[0367] Reference Figure 21A and Figure 21E In some embodiments, with respect to the scan unit, the first signal line layer includes the second capacitor electrode Ce2 of the first capacitor C1 and the fourth capacitor electrode Ce4 of the second capacitor C2.

[0368] Reference Figure 21A and Figure 21F In some embodiments, the second signal line layer includes a first power supply signal line VGLL configured to provide a first power supply signal, a second power supply signal line VGHL configured to provide a second power supply signal, a first clock signal line CKL configured to provide a first clock signal, a second clock signal line CBL configured to provide a second clock signal, a start signal line STVL configured to provide a start signal, a first reset signal supply line Vint1 configured to provide a first reset signal, a second reset signal supply line Vint2 configured to provide a second reset signal, and a third reset signal supply line Vint3 configured to provide a third reset signal.

[0369] ReferenceFigures 21A to 21F In some embodiments, each scan unit of the scan circuit includes a first pad PAD1 and a second pad PAD2. Optionally, the first pad PAD1 and the second pad PAD2 are located in the first conductive layer. In some embodiments, the first pad PAD1 includes the gate G7 of the seventh transistor T7. In some embodiments, the second pad PAD2 includes the gate G1 of the first transistor T1 and the gate G3 of the third transistor T3. Optionally, the first pad PAD1 is an integral structure. Optionally, the second pad PAD2 is an integral structure.

[0370] In some embodiments, each dummy scan unit of the scan circuit includes a first dummy pad DPAD1. Optionally, the first dummy pad DPD1 is located in the first conductive layer. In some embodiments, the first dummy pad DPDD1 includes the dummy gate DG7 of the seventh dummy transistor DT7. Optionally, the first dummy pad DPAD1 is an integral structure.

[0371] In some embodiments, the second scan unit SU2 includes a second extension E2 connected to the first pad PAD1 in the second scan unit SU2, and the first pad PAD1 is connected to the first electrode S5 of the fifth transistor T5 in the second scan unit SU2. The second extension E2 in the second scan unit SU2 is electrically connected to the gate G7 of the seventh transistor T7 in the second scan unit SU2. Optionally, the second extension E2 in the second scan unit SU2 is connected to the second clock signal line CBL. Optionally, the second extension E2 is located in the second conductive layer.

[0372] In some embodiments, the first dummy scan unit DSU1 includes a first dummy extension DE1 connected to the first dummy pad DPAD1 in the first dummy scan unit DSU1. Optionally, the first dummy extension DE1 is connected to the first clock signal line CKL. Optionally, the first dummy extension DE1 is located in the second conductive layer.

[0373] In some embodiments, a first dummy extension portion DE1 in a first dummy scan unit DSU1 is connected to a second pad PAD2 in a second scan unit SU2. The first dummy extension portion DE1 in the first dummy scan unit DSU1 is electrically connected to a gate G1 of a first transistor T1 and a gate G3 of a third transistor T3 in the second scan unit SU2. In some embodiments, the first dummy extension portion DE1 in the first dummy scan unit DSU1 is further connected to a first electrode S2 of a second transistor T2 in the second scan unit SU2. Since the first dummy extension portion DE1 in the first dummy scan unit DSU1 is connected to a first clock signal line CKL, the first dummy extension portion DE1 in the first dummy scan unit DSU1 is configured to transmit a first clock signal to the first electrode S2 of the second transistor T2 in the second scan unit SU2, and to the gate G1 of the first transistor T1 and the gate G3 of the third transistor T3 in the second scan unit SU2.

[0374] In some embodiments, the first dummy extension portion DE1 in the first dummy scan unit DSU1 is also connected to a first dummy pad DPAD1 in the first dummy scan unit DSU1.

[0375] In some embodiments, due to the absence of a via connecting the first dummy pad DPAD1 in the first dummy scan unit DSU1 and a dummy first electrode DS5 of a fifth dummy transistor DT5, the first dummy pad DPAD1 in the first dummy scan unit DSU1 is not connected to the dummy first electrode DS5 of the fifth dummy transistor DT5 in the first dummy scan unit DSU1. In one example, the dummy first electrode DS5 and a dummy second electrode DD5 of the fifth dummy transistor DT5 in the first dummy scan unit DSU1 are part of an integral structure. In another example, the dummy first electrode DS5 and the dummy second electrode DD5 of the fifth dummy transistor DT5 in the first dummy scan unit DSU1, and the dummy first electrode DS4 and the dummy second electrode DD4 of a fourth dummy transistor DT4 are part of an integral structure.

[0376] In some embodiments, a first scan unit SU1 includes a first extension portion E1 connected to a first pad PAD1 in the first scan unit SU1, and the first pad PAD1 in the first scan unit SU1 is connected to a first electrode S5 of a fifth transistor T5 in the first scan unit SU1. The first extension portion E1 in the first scan unit SU1 is electrically connected to a gate G7 of a seventh transistor T7 in the first scan unit SU1. Optionally, the first extension portion E1 in the first scan unit SU1 is connected to the first clock signal line CKL. Optionally, the first extension portion E1 is located in a second conductive layer.

[0377] In some embodiments, the first extension E1 in the first scan unit SU1 is electrically isolated from any dummy scan unit. For example, the first extension E1 in the first scan unit SU1 is not connected to any component of a dummy transistor or a dummy capacitor in any dummy scan unit.

[0378] In some embodiments, the first extension E1 in the first scan unit SU1 is not connected to the second scan unit SU2. For example, the first extension E1 in the first scan unit SU1 is not connected to any component of a transistor or a capacitor in the second scan unit SU2.

[0379] In some embodiments, the second dummy scan unit DSU2 includes a second dummy extension DE2 connected to a first dummy pad DPAD1 in the second dummy scan unit DSU2. Optionally, the second dummy scan unit DSU2 is electrically isolated from the first clock signal line CKL and electrically isolated from the second clock signal line CBL. Optionally, the second dummy extension DE2 is located in the second conductive layer.

[0380] In some embodiments, the second dummy extension DE2 in the second dummy scan unit DSU2 is not connected to any component in the first dummy scan unit DSU1. For example, the second dummy extension DE2 in the second dummy scan unit DSU2 is not connected to any component of a dummy transistor or a dummy capacitor in the first dummy scan unit DSU1.

[0381] In some embodiments, the second dummy extension DE2 in the second dummy scan unit DSU2 is not connected to the second scan unit SU2. For example, the second dummy extension DE2 in the second dummy scan unit DSU2 is not connected to any component of a transistor or a capacitor in the second scan unit SU2.

[0382] In some embodiments, the first dummy pad DPAD1 in the second dummy scan unit DSU2 is connected to the dummy first electrode DS5 of the fifth dummy transistor DT5 in the second dummy scan unit DSU2, for example, through a via connecting the first dummy pad DPAD1 in the second dummy scan unit DSU2 and the dummy first electrode DS5 of the fifth dummy transistor DT5. In one example, the dummy first electrode DS5 and the dummy second electrode DD5 of the fifth dummy transistor DT5 in the second dummy scan unit DSU2 are part of an integral structure. In another example, the dummy first electrode DS5 and the dummy second electrode DD5 of the fifth dummy transistor DT5 in the second dummy scan unit DSU2, and the dummy first electrode DS4 and the dummy second electrode DD4 of the fourth dummy transistor DT4 are part of an integral structure. In some embodiments, the dummy first electrode DS4 of the fourth dummy transistor DT4 is connected to a second power supply signal line VGHL configured to provide a second power signal. In some embodiments, the first dummy pad DPAD1, the second dummy extension DE2, the dummy first electrode DS5 and the dummy second electrode DD5 of the fifth dummy transistor DT5, and the dummy first electrode DS4 and the dummy second electrode DD4 of the fourth dummy transistor DT4 in the second dummy scan unit DSU2 are configured to be provided with the second power signal.

[0383] The inventors of the present disclosure have found that, in Figures 21A to 21G the scan circuit shown, since there is no connection line extending through the region having one or more dummy scan units, the difference between the load on the first clock signal line CKL and the load on the second clock signal line CBL can be significantly reduced. The display panel connected to Figures 21A to 21G the scan circuit shown has significantly improved display uniformity.

[0384] Figure 22A is a schematic diagram showing the structure of a plurality of scan units in a plurality of rows of scan units and one or more dummy scan units in one or more rows of dummy scan units in a scan circuit according to some embodiments of the present disclosure. Figure 22B is a schematic diagram showing Figure 22A the structure of a semiconductor material layer in the scan circuit shown. Figure 22C is a schematic diagram showing Figure 22A the structure of a first conductive layer in the scan circuit shown. Figure 22D is a schematic diagram showing Figure 22A the structure of a second conductive layer in the scan circuit shown. Figure 22E is a schematic diagram showing Figure 22A the structure of a first signal line layer in the scan circuit shown. Figure 22F is a schematic diagram showing Figure 22A the structure of a second signal line layer in the scan circuit shown.Figure 22G is a schematic diagram showing Figure 22A the structure of the third signal line layer in the scanning circuit shown. Figure 22H is a schematic diagram showing Figure 22A the connection of the first clock signal line and the second clock signal line in the scanning circuit shown.

[0385] Figures 22A to 22G The scanning unit in the scanning circuit shown in Figures 18A to 18G corresponds to the scanning unit in the scanning circuit shown in Figures 22A to 22G The second scanning unit SU2 in the scanning circuit shown in Figures 18A to 18G corresponds to the scanning unit in the (2k)-th row in the scanning circuit shown in Figures 22A to 22G The first scanning unit SU1 in the scanning circuit shown in Figures 18A to 18G corresponds to the scanning unit in the (2k - 1)-th row in the scanning circuit shown in Figures 22A to 22G The first dummy scanning unit DSU1 and the second dummy scanning unit DSU2 described in Figures 18A to 18G correspond to one or more dummy scanning units DSU described in

[0386] Figure 22A are marked with labels indicating the transistors (T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, and T13) and capacitors (C1, C2, and C3) of the scanning unit, the dummy transistors (DT8, DT9, DT10, and DT13) and dummy capacitors (DC1, DC2, and DC3) of the dummy scanning unit, and the signal lines (CBL, CKL, VGLL, VGHL, and STVL) in each scanning unit.

[0387] Referring to Figures 22A to 22G , in some embodiments, the scanning circuit includes a first scanning unit SU1, a first dummy scanning unit DSU1, and a second scanning unit SU2. Optionally, the first scanning unit SU1, the first dummy scanning unit DSU1, and the second scanning unit SU2 are arranged in sequence. Optionally, the first dummy scanning unit DSU1 separates the first scanning unit SU1 and the second scanning unit SU2.

[0388] In some embodiments, the scanning circuit further includes a second dummy scanning unit DSU2. Optionally, the first scanning unit SU1, the second dummy scanning unit DSU2, the first dummy scanning unit DSU1, and the second scanning unit SU2 are arranged in sequence. Optionally, the first dummy scanning unit DSU1 separates the second scanning unit SU2 and the second dummy scanning unit DSU2; and the second dummy scanning unit DSU2 separates the first dummy scanning unit DSU1 and the first scanning unit SU1.

[0389] Reference Figure 22A And Figure 22B , in some embodiments, the semiconductor material layer includes the active layers of the transistors in each scanning unit. Figure 22B Marked with marks indicating the active layers of the transistors in each scanning unit. For example, the active layer ACT1 of the first transistor T1, the active layer ACT2 of the second transistor T2, the active layer ACT4 of the fourth transistor T4, the active layer ACT5 of the fifth transistor T5, the active layer ACT6 of the sixth transistor T6, the active layer ACT7 of the seventh transistor T7, the active layer ACT8 of the eighth transistor T8, the active layer ACT9 of the ninth transistor T9, the active layer ACT10 of the tenth transistor T10, the active layer ACT11 of the eleventh transistor T11, and the active layer ACT12 of the twelfth transistor T12. In some embodiments, each scanning unit further includes the active layer of the third transistor and the active layer of the thirteenth transistor. Figure 22B Further marked with marks indicating the dummy active layers of the dummy transistors in each dummy scanning unit. For example, the dummy active layer DACT5 of the fifth dummy transistor DT5, the dummy active layer DACT8 of the eighth dummy transistor DT8, the dummy active layer DACT9 of the ninth dummy transistor DT9, the dummy active layer DACT10 of the tenth dummy transistor DT10, and the dummy active layer DACT13 of the thirteenth dummy transistor DT13. Figure 22B Further marked with marks indicating the first and second electrodes of certain transistors in each scanning unit. For example, the first transistor T1 includes a first electrode S1 and a second electrode D1, the second transistor T2 includes a first electrode S2 and a second electrode D2, the third transistor T3 includes a first electrode S3 and a second electrode D3, the fourth transistor T4 includes a first electrode S4 and a second electrode D4, the fifth transistor T5 includes a first electrode S5 and a second electrode D5, the sixth transistor T6 includes a first electrode S6 and a second electrode D6, the seventh transistor T7 includes a first electrode S7 and a second electrode D7, the eighth transistor T8 includes a first electrode S8 and a second electrode D8, the eleventh transistor T11 includes a first electrode S11 and a second electrode D11, the twelfth transistor T12 includes a first electrode S12 and a second electrode D12, and the thirteenth transistor T13 includes a first electrode S13 and a second electrode D13. Figure 22BFurther, markings are used to label the dummy first electrodes and dummy second electrodes of certain dummy transistors in each scan unit. For example, the fourth dummy transistor DT4 includes a dummy first electrode DS4 and a dummy second electrode DD4, the fifth dummy transistor DT5 includes a dummy first electrode DS5 and a dummy second electrode DD5, the sixth dummy transistor DT6 includes a dummy first electrode DS6 and a dummy second electrode DD6, the seventh dummy transistor DT7 includes a dummy first electrode DS7, the eighth dummy transistor DT8 includes a dummy first electrode DS8 and a dummy second electrode DD8, and the thirteenth dummy transistor DT13 includes a dummy first electrode DS13 and a dummy second electrode DD13.

[0390] Reference Figure 22A and Figure 22C , in some embodiments, with respect to the scan unit, the first conductive layer includes the first capacitor electrode Ce1 of the first capacitor C1, the third capacitor electrode Ce3 of the second capacitor C2, the fifth capacitor electrode Ce5 of the third capacitor C3, the gate G1 of the first transistor T1, the gate G2 of the second transistor T2, the gate G4 of the fourth transistor T4, the gate G5 of the fifth transistor T5, the gate G6 of the sixth transistor T6, the gate G7 of the seventh transistor T7, the gate G9 of the ninth transistor T9, the gate G10 of the tenth transistor T10, the gate G11 of the eleventh transistor T11, and the gate G12 of the twelfth transistor T12. In some embodiments, each scan unit further includes the gate of the third transistor and the gate of the thirteenth transistor. In some embodiments, with respect to the dummy scan unit, the first conductive layer further includes the dummy first capacitor electrode DCe1 of the first dummy capacitor DC1, the dummy third capacitor electrode DCe3 of the second dummy capacitor DC2, the dummy fifth capacitor electrode DCe5 of the third dummy capacitor DC3, the dummy gate DG4 of the fourth dummy transistor DT4, the dummy gate DG6 of the sixth dummy transistor DT6, the dummy gate DG7 of the seventh dummy transistor DT7, the dummy gate DG8 of the eighth dummy transistor DT8, the dummy gate DG9 of the ninth dummy transistor DT9, the dummy gate DG10 of the tenth dummy transistor DT10, and the dummy gate DG13 of the thirteenth dummy transistor DT13.

[0391] Reference Figure 22A With Figure 22D, in some embodiments, regarding the scan unit, the second conductive layer includes the first electrode S9 of the ninth transistor T9, the second electrode D9 of the ninth transistor T9, the first electrode S10 of the tenth transistor T10, the second electrode D10 of the tenth transistor T10, the first power supply signal line VGLL configured to provide a first power supply signal, and a plurality of connection lines. In some embodiments, regarding the dummy scan unit, the second conductive layer further includes the dummy first electrode DS9 of the ninth dummy transistor DT9, the dummy second electrode DD9 of the ninth dummy transistor DT9, the dummy first electrode DS10 of the tenth dummy transistor DT10, the dummy second electrode DD10 of the tenth dummy transistor DT10, and a plurality of connection lines.

[0392] Reference Figure 22A and Figure 22E , in some embodiments, regarding the scan unit, the first signal line layer includes the second capacitor electrode Ce2 of the first capacitor C1, the fourth capacitor electrode Ce4 of the second capacitor C2, and the sixth capacitor electrode Ce6 of the third capacitor C3. In some embodiments, regarding the dummy scan unit, the first signal layer further includes the dummy second capacitor electrode DCe2 of the first dummy capacitor DC1, the dummy fourth capacitor electrode DCe4 of the second dummy capacitor DC2, and the dummy sixth capacitor electrode DCe6 of the third dummy capacitor DC3.

[0393] Reference Figure 22A and Figure 22F , in some embodiments, the second signal line layer includes a second power supply signal line VGHL configured to provide a second power supply signal, a first clock signal line CKL configured to provide a first clock signal, a second clock signal line CBL configured to provide a second clock signal, a control signal line CXL configured to provide a control signal to the gate of the thirteenth transistor T13, and a start signal line STVL configured to provide a start signal.

[0394] Reference Figure 22A and Figure 22G , in some embodiments, the third signal line layer includes a plurality of first power supply connection lines VGLCL configured to connect at least two of the plurality of first power supply lines.

[0395] Reference Figures 22A to 22G , in some embodiments, each scan unit of the scan circuit includes a first pad PAD1 and a second pad PAD2. Optionally, the first pad PAD1 and the second pad PAD2 are located in the first conductive layer. In some embodiments, the first pad PAD1 includes the gate G7 of the seventh transistor T7. In some embodiments, the second pad PAD2 includes the gate G1 of the first transistor T1 and the gate of the third transistor. Optionally, the first pad PAD1 is an integral structure. Optionally, the second pad PAD2 is an integral structure.

[0396] In some embodiments, each dummy scan unit of the scan circuit includes a first dummy pad DPAD1. Optionally, the first dummy pad DPD1 is located in the first conductive layer. In some embodiments, the first dummy pad DPDD1 includes a dummy gate DG7 of a seventh dummy transistor DT7.

[0397] In some embodiments, the second scan unit SU2 includes a second extension E2 that is connected to a first pad PAD1 in the second scan unit SU2, connected to a first electrode S4 of a fourth transistor T4 in the second scan unit SU2, and connected to a first electrode S6 of a sixth transistor T6 in the second scan unit SU2. The second extension E2 in the second scan unit SU2 is electrically connected to a gate G7 of a seventh transistor T7 in the second scan unit SU2. Optionally, the second extension E2 in the second scan unit SU2 is connected to a first clock signal line CKL. Optionally, the second extension E2 is located in the second conductive layer.

[0398] In some embodiments, the first dummy scan unit DSU1 includes a first dummy extension DE1 that is connected to the first dummy pad DPAD1 in the first dummy scan unit DSU1. Optionally, the first dummy extension DE1 is connected to a second clock signal line CBL. Optionally, the first dummy extension DE1 is located in the second conductive layer.

[0399] In some embodiments, the first dummy extension DE1 in the first dummy scan unit DSU1 is connected to a second pad PAD2 in the second scan unit SU2. The first dummy extension DE1 in the first dummy scan unit DSU1 is electrically connected to a gate G1 of a first transistor T1 and a gate G3 of a third transistor T3 in the first scan unit SU2. In some embodiments, the first dummy extension DE1 in the first dummy scan unit DSU1 is further connected to a first electrode S2 of a second transistor T2 in the second scan unit SU2. Since the first dummy extension DE1 in the first dummy scan unit DSU1 is connected to the second clock signal line CBL, the first dummy extension DE1 in the first dummy scan unit DSU1 is configured to transmit a second clock signal to the first electrode S2 of the second transistor T2 in the second scan unit SU2, and transmit it to the gate G1 of the first transistor T1 and the gate G3 of the third transistor T3 in the second scan unit SU2.

[0400] In some embodiments, the first dummy extension DE1 in the first dummy scan unit DSU1 is not connected to the dummy second electrode DD9 of the ninth dummy transistor DT9 in the first dummy scan unit DSU1. In one example, the dummy first electrode DS9 and the dummy second electrode DD9 of the ninth dummy transistor DT9 in the first dummy scan unit DSU1 are part of an integral structure.

[0401] In some embodiments, the first scan unit SU1 includes a first extension E1 that is connected to the first pad PAD1 in the first scan unit SU1, connected to the first electrode S4 of the fourth transistor T4 in the first scan unit SU1, and connected to the first electrode S6 of the sixth transistor T6 in the first scan unit SU1. The first extension E1 in the first scan unit SU1 is electrically connected to the gate G7 of the seventh transistor T7 in the first scan unit SU1. Optionally, the first extension E1 in the first scan unit SU1 is connected to the second clock signal line CBL. Optionally, the first extension E1 is located in the second conductive layer.

[0402] In some embodiments, the first extension E1 in the first scan unit SU1 is electrically isolated from any dummy scan unit. For example, the first extension E1 in the first scan unit SU1 is not connected to any component of a dummy transistor or a dummy capacitor in any dummy scan unit.

[0403] In some embodiments, the first extension E1 in the first scan unit SU1 is not connected to the second scan unit SU2. For example, the first extension E1 in the first scan unit SU1 is not connected to any component of a transistor or a capacitor in the second scan unit SU2.

[0404] In some embodiments, the second dummy scan unit DSU2 includes a second dummy extension DE2 connected to the first dummy pad DPAD1 in the second dummy scan unit DSU2. Optionally, the second dummy scan unit DSU2 is electrically isolated from the first clock signal line CKL and electrically isolated from the second clock signal line CBL. Optionally, the second dummy extension DE2 is located in the second conductive layer.

[0405] In some embodiments, the second dummy extension DE2 in the second dummy scan unit DSU2 is not connected to any component in the first dummy scan unit DSU1. For example, the second dummy extension DE2 in the second dummy scan unit DSU2 is not connected to any component of a dummy transistor or a dummy capacitor in the first dummy scan unit DSU1.

[0406] In some embodiments, the second dummy extension DE2 in the second dummy scan unit DSU2 is not connected to the second scan unit SU2. For example, the second dummy extension DE2 in the second dummy scan unit DSU2 is not connected to any component such as a transistor or a capacitor in the second scan unit SU2.

[0407] In some embodiments, the second dummy extension DE2 in the second dummy scan unit DSU2 is connected to the dummy second electrode DD9 of the ninth dummy transistor DT9 in the second dummy scan unit DSU2. In one example, the dummy first electrode DS9 and the dummy second electrode DD9 of the ninth dummy transistor DT9 in the second dummy scan unit DSU2 are part of an integral structure. In some embodiments, the dummy first electrode DS9 and the dummy second electrode DD9 of the ninth dummy transistor DT9 in the second dummy scan unit DSU2 are connected to a second power supply signal line VGHL configured to provide a second power signal. In some embodiments, the first dummy pad DPAD1, the second dummy extension DE2, the dummy first electrode DS9 and the dummy second electrode DD9 of the ninth dummy transistor DT9 in the second dummy scan unit DSU2 are configured to be provided with the second power signal.

[0408] The inventors of the present disclosure have found that Figures 22A to 22H in the scan circuit shown in Figures 22A to 22H , since there is no connection line extending through the region having one or more dummy scan units, the difference between the load on the first clock signal line CKL and the load on the second clock signal line CBL can be significantly reduced.

[0409] Figure 23A is a schematic diagram showing the structure of a plurality of scan units in a plurality of rows of scan units and one or more dummy scan units in one or more rows of dummy scan units in a scan circuit according to some embodiments of the present disclosure. Figure 23B is a schematic diagram showing Figure 23A the structure of a semiconductor material layer in the scan circuit shown in Figure 23C is a schematic diagram showing Figure 23A the structure of a first conductive layer in the scan circuit shown in Figure 23D is a schematic diagram showing Figure 23A the structure of a second conductive layer in the scan circuit shown in Figure 23E is a schematic diagram showing Figure 23A the structure of a first signal line layer in the scan circuit shown in Figure 23F is a schematic diagram showing Figure 23A the structure of a second signal line layer in the scan circuit shown in Figure 23G is a schematic diagram showing Figure 23ASchematic diagram of the structure of the third signal line layer in the scanning circuit shown. Figure 23H Shows Figure 23A Schematic diagram of the connection of the first clock signal line in the scanning circuit shown.

[0410] Figures 23A to 23G The scanning unit of the scanning circuit shown in corresponds to Figures 19A to 19G The scanning unit of the scanning circuit shown in. Figures 23A to 23G The second scanning unit SU2 in the scanning circuit shown in corresponds to Figures 19A to 19G The scanning unit in the (2k)th row in the scanning circuit shown in. Figures 23A to 23G The first scanning unit SU1 in the scanning circuit shown in corresponds to Figures 19A to 19G The scanning unit in the (2k - 1)th row in the scanning circuit shown in. Figures 23A to 23G The first dummy scanning unit DSU1 and the second dummy scanning unit DSU2 shown in correspond to Figures 19A to 19G One or more dummy scanning units DSU shown in.

[0411] Refer to Figures 23A to 23G , in some embodiments, the scanning circuit includes a first scanning unit SU1, a first dummy scanning unit DSU1, and a second scanning unit SU2. Optionally, the first scanning unit SU1, the first dummy scanning unit DSU1, and the second scanning unit SU2 are arranged in sequence. Optionally, the first dummy scanning unit DSU1 separates the first scanning unit SU1 and the second scanning unit SU2.

[0412] In some embodiments, the scanning circuit further includes a second dummy scanning unit DSU2. Optionally, the first scanning unit SU1, the second dummy scanning unit DSU2, the first dummy scanning unit DSU1, and the second scanning unit SU2 are arranged in sequence. Optionally, the first dummy scanning unit DSU1 separates the second scanning unit SU2 and the second dummy scanning unit DSU2; and the second dummy scanning unit DSU2 separates the first dummy scanning unit DSU1 and the first scanning unit SU1.

[0413] Refer to Figures 23A to 23G , in some embodiments, each scanning unit of the scanning circuit includes a first pad PAD1. Optionally, the first pad PAD1 is located in the first conductive layer. In some embodiments, the first pad PAD1 includes the gate G7 of the seventh transistor T7. Optionally, the first pad PAD1 is an integral structure.

[0414] In some embodiments, the scan circuit includes a second extension E2 connected to a first pad PAD1 in the second scan unit SU2. The second extension E2 in the second scan unit SU2 is electrically connected to the gate G7 of a seventh transistor T7 in the second scan unit SU2. Optionally, the second extension E2 is located in the first conductive layer. Optionally, the second extension E2 and the first pad PAD1 are part of an integral structure.

[0415] In some embodiments, the second extension E2 is connected to the first clock signal line CKL, for example, at a position in an area having a first dummy scan unit DSU1. In some embodiments, the second extension E2 in the second scan unit SU2 is connected to the first clock signal line CKL at a position in an area having a first dummy scan unit DSU1.

[0416] In some embodiments, the second extension E2 is not connected to any components in the first dummy scan unit DSU1. For example, the second extension E2 is not connected to any components of a dummy transistor or a dummy capacitor in the first dummy scan unit DSU1.

[0417] In some embodiments, the second extension E2 is not connected to the first scan unit SU1. For example, the second extension E2 is not connected to any components of a transistor or a capacitor in the first scan unit SU1.

[0418] In some embodiments, the scan circuit includes a dummy first extension DE1 connected to one or more signal lines in the second dummy scan unit DSU2, which is in turn connected to a second power supply line (such as VGHL2).

[0419] The inventors of the present disclosure have found that in Figures 23A to 23H the scan circuit shown, since there is no connection line extending through an area having one or more dummy scan units, the difference between the load on the first clock signal line CKL and the load on the second clock signal line CBL can be significantly reduced. Figures 23A to 23H The display panel connected to the scan circuit shown has significantly improved display uniformity.

[0420] In some embodiments, referring to Figures 21A to 21G 、 Figures 22A to 22H and Figures 23A to 23H , the orthographic projection of the dummy first extension DE1 on the substrate substantially overlaps at least one of the orthographic projection of the first clock signal line CKL on the substrate and the orthographic projection of the second clock signal line CBL on the substrate.

[0421] In another aspect, the present invention provides a display device including a scanning circuit described herein or manufactured by the methods described herein, and a display panel having a plurality of light-emitting elements. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode display device. Optionally, the display device is a micro light-emitting diode display device. Optionally, the display device is a mini light-emitting diode display device. Optionally, the display device is a quantum dot display device.

[0422] For purposes of illustration and description, the foregoing description of embodiments of the present invention has been given. It is not exhaustive and is not intended to limit the present invention to the precise forms or exemplary embodiments disclosed. Accordingly, the foregoing description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the present invention and its best mode of practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the present invention is intended to be defined by the appended claims and their equivalents, where all terms are meant in their broadest reasonable sense unless otherwise specified. Thus, terms such as "the invention," "the present invention," etc. do not necessarily limit the scope of the claims to a particular embodiment, and references to exemplary embodiments of the present invention do not imply a limitation of the present invention and should not be inferred as such. The present invention is limited only by the spirit and scope of the appended claims. Additionally, these claims may refer to the use of "first," "second," etc., followed by a noun or element. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by such nomenclature unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. Furthermore, no element or component in this disclosure is intended to be dedicated to the public, whether or not the element or component is expressly recited in the appended claims.

Claims

1. A scanning circuit, comprising: A first clock signal line; A second clock signal line; And A first scanning unit, a first dummy scanning unit, and a second scanning unit, which are arranged in sequence in a region including a plurality of scanning units and one or more dummy scanning units; Wherein each scanning unit includes a first pad and a second pad; The first pad includes the gate of a seventh transistor; The second pad includes the gates of a first transistor and a third transistor; The first dummy scanning unit includes a first dummy extension; The first dummy extension is connected to the second pad in the second scanning unit and is configured to transmit one of the first clock signal or the second clock signal to the gates of the first transistor and the third transistor in the second scanning unit; And The orthographic projection of the first dummy extension on the substrate at least partially overlaps at least one of the orthographic projection of the first clock signal line on the substrate or the orthographic projection of the second clock signal line on the substrate.

2. The scanning circuit according to claim 1, wherein, The first dummy extension is connected to one of the first clock signal line or the second clock signal line at a position in the region having the first dummy scanning unit.

3. The scanning circuit according to claim 2, wherein, The first dummy extension in the first dummy scanning unit is further connected to the first electrode of a second transistor in the second scanning unit and is configured to transmit one of the first clock signal or the second clock signal to the first electrode of the second transistor in the second scanning unit.

4. The scanning circuit according to claim 1, wherein, The second scanning unit includes a second extension connected to the first pad in the second scanning unit; Wherein the first pad in the second scanning unit includes the gate of the seventh transistor in the second scanning unit; and The second extension in the second scanning unit is connected to the other of the first clock signal line or the second clock signal line and is configured to transmit the other of the first clock signal or the second clock signal to the gate of the seventh transistor in the second scanning unit.

5. The scanning circuit according to claim 4, wherein, The first pad in the second scanning unit is connected to the first electrode of a fifth transistor in the second scanning unit; And The second extension in the second scanning unit is configured to transmit the other of the first clock signal or the second clock signal to the first electrode of the fifth transistor in the second scanning unit through the first pad in the second scanning unit.

6. The scanning circuit according to claim 4, wherein, The second extension in the second scanning unit is connected to the first electrodes of a fourth transistor and a sixth transistor in the second scanning unit and is configured to transmit the other of the first clock signal or the second clock signal to the first electrodes of the fourth transistor and the sixth transistor in the second scanning unit.

7. The scanning circuit according to claim 1, wherein The first scanning unit includes a first extension connected to the first pad in the first scanning unit; Among them, the first pad in the first scanning unit includes the gate of the seventh transistor in the first scanning unit; The first pad in the first scanning unit is connected to the first electrode of the fifth transistor in the first scanning unit; and The first extension in the first scanning unit is connected to one of the first clock signal line or the second clock signal line, and is configured to transmit one of the first clock signal or the second clock signal to the gate of the seventh transistor and the first electrode of the fifth transistor in the first scanning unit.

8. The scanning circuit according to claim 7, wherein, The first pad in the first scanning unit is connected to the first electrode of the fifth transistor in the first scanning unit; And The first extension in the first scanning unit is configured to transmit one of the first clock signal or the second clock signal to the first electrode of the fifth transistor in the first scanning unit through the first pad in the first scanning unit.

9. The scanning circuit according to claim 7, wherein, The first extension in the first scanning unit is connected to the first electrode of the fourth transistor and the first electrode of the sixth transistor in the first scanning unit, and is configured to transmit the other of the first clock signal or the second clock signal to the first electrode of the fourth transistor and the first electrode of the sixth transistor in the first scanning unit.

10. The scanning circuit according to claim 1, wherein, The first dummy scanning unit further includes a first dummy pad; The first dummy pad in the first dummy scanning unit includes the dummy gate of the seventh dummy transistor; and The first dummy extension is connected to the first dummy pad.

11. The scanning circuit according to claim 10, wherein, The first dummy pad in the first dummy scanning unit is not connected to the dummy first electrode of the fifth dummy transistor in the first dummy scanning unit; The dummy first electrode and the dummy second electrode of the fifth dummy transistor and the dummy first electrode and the dummy second electrode of the fourth dummy transistor in the first dummy scanning unit are part of an integral structure; And The integral structure is configured to be provided with a second power signal.

12. The scanning circuit according to claim 1, wherein, The first dummy extension in the first dummy scanning unit is not connected to the dummy second electrode of the ninth dummy transistor in the first dummy scanning unit; The dummy first electrode and the dummy second electrode of the ninth dummy transistor in the first dummy scanning unit are part of an integral structure; And The integral structure is configured to be provided with a second power signal.

13. The scanning circuit according to claim 7, wherein, The first extension in the first scanning unit is not connected to any component of the dummy transistor or the dummy capacitor in any dummy scanning unit; and The first extension in the first scanning unit is not connected to any component of the transistor or the capacitor in the second scanning unit.

14. The scanning circuit according to claim 1, further comprising a second dummy scanning unit in the area including a plurality of scanning units and one or more dummy scanning units; Among them, The first scanning unit, the second dummy scanning unit, the first dummy scanning unit, and the second scanning unit are arranged in sequence.

15. The scanning circuit according to claim 14, wherein, The second dummy scan unit is electrically isolated from the first clock signal line and is also electrically isolated from the second clock signal line.

16. The scanning circuit according to claim 14, wherein, The second dummy scan unit includes a second dummy extension portion in the second dummy scan unit; and The second dummy extension portion in the second dummy scan unit is electrically isolated from the first clock signal line and is also electrically isolated from the second clock signal line.

17. The scanning circuit according to claim 16, wherein, The second dummy scan unit further includes a first dummy pad connected to the second dummy extension portion in the second dummy scan unit; and The first dummy pad and the second dummy extension portion in the second dummy scan unit are electrically isolated from the first clock signal line and are also electrically isolated from the second clock signal line.

18. The scanning circuit according to claim 16, wherein, The second dummy extension portion in the second dummy scan unit is not connected to any component of the dummy transistor or the dummy capacitor in the first dummy scan unit; and The second dummy extension portion in the second dummy scan unit is not connected to any component of the transistor or the capacitor in the first scan unit or the second scan unit.

19. The scanning circuit according to claim 17, wherein, The first dummy pad in the second dummy scan unit is connected to the dummy first electrode of a fifth dummy transistor in the second dummy scan unit; The dummy first electrode and the dummy second electrode of the fifth dummy transistor and the dummy first electrode and the dummy second electrode of a fourth dummy transistor in the second dummy scan unit are part of an integral structure; and The integral structure is configured to be supplied with a second power signal.

20. A scan circuit, comprising: A first clock signal line; A second clock signal line; and A first scan unit, a first dummy scan unit, and a second scan unit, where the first scan unit, the first dummy scan unit, and the second scan unit are arranged in sequence in a region including a plurality of scan units and one or more dummy scan units; wherein each scan unit includes a first pad; The first pad includes the gate of a seventh transistor; The scan circuit further includes a second extension portion; The second extension portion is connected to one of the first clock signal line or the second clock signal line at a position in the region having the first dummy scan unit; and The second extension portion is connected to the first pad in the second scan circuit and is configured to transmit one of the first clock signal or the second clock signal to the gate of the seventh transistor.

21. A display device, comprising the scan circuit according to any one of claims 1 to 20, and a display panel connected to the scan circuit.

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