An electronic paper panel architecture

Abstract

The present invention relates to an electronic paper panel architecture, comprising a display panel, a source driver chip for driving the display panel, and a plurality of scan lines. In addition, it also comprises a gate row scanning circuit for driving the plurality of scan lines. The gate row scanning circuit comprises a plurality of driving units, each driving unit is provided with an input end, a first output end, and a second output end. Each input end is electrically connected to a clock signal pin in the source driver chip, each first output end is electrically connected to a scan line, the second output end in the first driving unit is electrically connected to the start signal pin in the source driver chip, the first output end in the last driving unit is also electrically connected to the end signal pin in the source driver chip, and the first output ends in all driving units except the last are also electrically connected to the second output end in the next driving unit. The present invention solves the technical problem of needing to adopt multiple scan line driving circuits, thereby reducing the module manufacturing cost.

Description

Technical Field

[0001] The present invention relates to the field of electronic paper display, and in particular to an electronic paper panel architecture. Background Art

[0002] Electronic paper ink screen display has the characteristics of ultra-low power consumption, low-frequency display and power saving, and has a wide range of application markets in price tags, advertising signs and bus stops.

[0003] Typically, the driver integrated circuits used in electronic paper are scan line driver circuits and data line driver circuits. Both circuits include multiple driver units, each of which drives one or more corresponding scan lines or data lines.

[0004] However, the driving circuits used in this driving method often require a relatively large space, making it particularly unsuitable for narrow-framed electronic paper structures. Furthermore, the aforementioned driving method uses a relatively large number of driving circuits, thereby increasing manufacturing costs. Summary of the Invention

[0005] The purpose of the present invention is to overcome the defects of the prior art and provide an electronic paper panel architecture.

[0006] The present invention provides an electronic paper panel architecture, and its technical solution is as follows:

[0007] An electronic paper panel architecture includes a display panel, a source driver chip for driving the display panel, and a plurality of scan lines, and also includes a gate row scanning circuit for driving the plurality of scan lines, the gate row scanning circuit including a plurality of drive units, each of the drive units having an input end, a first output end, and a second output end, each of the input ends being electrically connected to a clock signal pin in the source driver chip, each of the first output ends being electrically connected to one of the scan lines, the second output end of the first drive unit being electrically connected to a start signal pin in the source driver chip, the first output end of the last drive unit being also electrically connected to an end signal pin in the source driver chip, and the first output ends of the remaining drive units, except for the last drive unit, are all also electrically connected to the second output end of the next drive unit.

[0008] By adopting the above technical solution, compared with the prior art, the technical solution provided by the present invention application can at least bring the following beneficial effects: by setting a gate row scanning circuit (GOA circuit), because it is composed of many driving units and this type of circuit occupies a small space area, it is very suitable for use in narrow-frame electronic paper. Moreover, the second output end of the first driving unit is electrically connected to the start signal (STV) pin in the source driver chip, and each driving unit has two output ends, one can be used to drive the scan line, and the other is used to connect each driving unit. Once the STV signal is given at the second output end of the first driving unit, each clock is cyclically turned on in turn, and the scanning signal is turned on row by row from top to bottom or from bottom to top in the display area through the GOA circuit unit, and finally the picture is displayed, so there is no need to use multiple scan line driving circuits, thereby saving cost.

[0009] Preferably, the driving unit includes a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9 and a capacitor Cst, wherein the source and gate of the transistor T1 are electrically connected to the second output terminal, the drain of the transistor T1 is electrically connected to the gate of the transistor T2, the source of the transistor T3, the gate of the transistor T4, the drain of the transistor T7, and the positive plate of the capacitor Cst, and the negative plate of the capacitor Cst is electrically connected to the first output terminal, the source of the transistor T2 is electrically connected to the gate and drain of the transistor T3, the gate of the transistor T5, and the drain of the transistor T6. , the source of the transistor T7 is electrically connected, the drain of the transistor T4 is electrically connected to the input terminal, the source of the transistor T4 is electrically connected to the first output terminal, the source of the transistor T5 is electrically connected to the source of the transistor T6, the drain of the transistor T8, and the source of the transistor T9, the drain of the transistor T5 is electrically connected to the first output terminal, the gate of the transistor T6 is electrically connected to the second output terminal, the gate of the transistor T7 is electrically connected to the gate of the transistor T8, and the source of the transistor T8 is electrically connected to the drain of the transistor T9; since the transistor is small in size and can output multiple circuit signals, orderly and reasonable driving of the scan lines is achieved.

[0010] Preferably, each of the driving units is provided with a first control end, a second control end and a third control end, the first control end is electrically connected to the drain of the transistor T2, the second control end is electrically connected to the source of the transistor T7, and the third control end is electrically connected to the gate and drain of the transistor T9 at the same time; in this way, when control signals are input to these control ends, with the cooperation of multiple transistors in the GOA circuit, multiple driving operations of the pixel units controlled in the scan line can be achieved.

[0011] Preferably, the gate row scanning circuit is arranged at the left edge, right edge or upper edge of the display panel and is located in the peripheral area of ​​the electronic paper display; this will not affect the normal operation of pixels in the display area.

[0012] Preferably, the topological distance between the circuit area where the gate row scanning circuit is located and the area covered by the electronic paper film is greater than 50 microns, and the topological distance between the circuit area where the gate row scanning circuit is located and the area where the electronic paper glass frame is located is greater than 100 microns; in this way, the GOA circuit will not be damaged during frame sealing.

[0013] Preferably, a wire-changing hole is provided on the surface or frame of the display panel; thus, wiring or wire-changing can be performed through the wire-changing hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a schematic diagram of the electronic paper panel architecture structure according to an embodiment of the present invention;

[0015] Figure 2 Schematic diagram of the structure of the first driving unit in the gate row scanning circuit according to an embodiment of the present invention;

[0016] Figure 3 Schematic diagram of the structure of the last driving unit in the gate row scanning circuit according to an embodiment of the present invention;

[0017] Figure 4 Schematic diagram of the structure of two adjacent driving units in the middle part of the gate row scanning circuit according to an embodiment of the present invention;

[0018] Figure 5 This is a cross-sectional view of a frame of an electronic paper panel structure according to an embodiment of the present invention;

[0019] Figure 6 FIG. 2 is a schematic diagram of another electronic paper panel structure according to an embodiment of the present invention.

[0020] Among them, the numbers marked in the figure represent: 1. Display panel; 2. Source driver chip; 3. Pixel unit; 4. Scan line; 5. Data line; 6. Gate row scanning circuit; 61. Drive unit; 62. Line change hole; 71. Input end; 72. First output end; 73. Second output end; 74. First control end; 75. Second control end; 76. Third control end. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0022] An embodiment of the present invention provides an electronic paper panel architecture, including a display panel 1 and a source driver chip 2 for driving the display panel 1. The display panel 1 is provided with a pixel array composed of pixel units 3, and a plurality of scan lines 4 and a plurality of data lines 5 for controlling the pixel units 3. In addition, the display panel 1 also includes a gate row scanning circuit 6 for driving the plurality of scan lines 4. The gate row scanning circuit 6 includes a plurality of driving units 61. Each driving unit 61 is provided with an input terminal 71, a first output terminal 72, and a second output terminal 73. Each input terminal 71 is electrically connected to a clock signal pin CK in the source driver chip 2, and each first output terminal 72 is electrically connected to a scan line 4. The second output terminal 73 of the first driving unit 61 is electrically connected to the start signal pin STV of the source driver chip 2, and the first output terminal 72 of the last driving unit 61 is also electrically connected to the end signal pin END of the source driver chip 2. Except for the last driving unit 61, the first output terminal 72 of the remaining driving units 61 is also electrically connected to the second output terminal 73 of the next driving unit 61.

[0023] The driving unit 61 of this embodiment includes a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9 and a capacitor Cst. The source and gate of the transistor T1 are both electrically connected to the second output terminal 73. The drain of the transistor T1 is also electrically connected to the gate of the transistor T2, the source of the transistor T3, the gate of the transistor T4, the drain of the transistor T7 and the positive plate of the capacitor Cst. The negative plate of the capacitor Cst is electrically connected to the first output terminal (72). The source of the transistor T2 is also electrically connected to the gate of the transistor T2, the source of the transistor T3, the gate of the transistor T4, the drain of the transistor T7 and the positive plate of the capacitor Cst. The gate and drain of transistor T3, the gate of transistor T5, the drain of transistor T6, and the source of transistor T7 are electrically connected. The drain of transistor T4 is electrically connected to the input terminal 71. The source of transistor T4 is electrically connected to the first output terminal 72. The source of transistor T5 is electrically connected to the source of transistor T6, the drain of transistor T8, and the source of transistor T9. The drain of transistor T5 is electrically connected to the first output terminal 72. The gate of transistor T6 is electrically connected to the second output terminal 73. The gate of transistor T7 is electrically connected to the gate of transistor T8. The source of transistor T8 is electrically connected to the drain of transistor T9.

[0024] In this embodiment, each driving unit 61 is provided with a first control terminal 74, a second control terminal 75 and a third control terminal 76, the first control terminal 74 is electrically connected to the drain of the transistor T2, the second control terminal 75 is electrically connected to the source of the transistor T7, and the third control terminal 76 is electrically connected to the gate and drain of the transistor T9 at the same time.

[0025] In this embodiment, the gate row scanning circuit 6 is disposed on the left and right edges of the display panel 1, located in the peripheral area of ​​the electronic paper display. A line switching hole 62 is provided on the surface or frame of the display panel 1. The topological distance A between the wiring area where the gate row scanning circuit 6 resides and the area covered by the electronic paper film is greater than 50 microns, and the topological distance between the wiring area where the gate row scanning circuit 6 resides and the area where the electronic paper glass frame resides is greater than 100 microns.

[0026] Specifically, the regional topological distance used in this embodiment can be defined as follows:

[0027] Let A and B be two two-dimensional regions. The topological distance d(A, B) between region A and region B is defined as;

[0028]

[0029] , where d(x, y) is the two-dimensional Euclidean distance between point y and point y (e.g. Figure 5 shown).

[0030] Of course, the GOA circuit can also be set at the top (upper edge) of the display surface, such as Figure 6 As shown, it can be set only on the left edge, or only on the right edge, or on the left edge and the upper edge, or on the right edge and the upper edge. Of course, it can also be set on the left edge, the right edge and the upper edge at the same time.

[0031] Although the embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the invention, and the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. An electronic paper panel architecture, comprising a display panel (1), a source driver chip (2) for driving the display panel (1), and a plurality of scan lines (4), characterized in that: It also includes a gate row scanning circuit (6) for driving the plurality of scanning lines (4), the gate row scanning circuit (6) including a plurality of driving units (61), each of the driving units (61) being provided with an input terminal (71), a first output terminal (72) and a second output terminal (73), each of the input terminals (71) being electrically connected to a clock signal pin in the source driving chip (2), each of the first output terminals (72) being electrically connected to a scanning line (4), the second output terminal (73) in the first driving unit (61) being electrically connected to a start signal pin in the source driving chip (2), the first output terminal (72) in the last driving unit (61) being also electrically connected to an end signal pin in the source driving chip (2), and the first output terminals (72) in the remaining driving units (61) except the last driving unit (61) being also electrically connected to the second output terminal (73) in the next driving unit (61); The driving unit (61) includes a transistor T1, a transistor T2, a transistor T3, a transistor T4, a transistor T5, a transistor T6, a transistor T7, a transistor T8, a transistor T9 and a capacitor Cst, wherein the source and gate of the transistor T1 are both electrically connected to the second output terminal (73), the drain of the transistor T1 is simultaneously electrically connected to the gate of the transistor T2, the source of the transistor T3, the gate of the transistor T4, the drain of the transistor T7, and the positive plate of the capacitor Cst, the negative plate of the capacitor Cst is electrically connected to the first output terminal (72), the source of the transistor T2 is simultaneously electrically connected to the gate and drain of the transistor T3, the The gate of transistor T5, the drain of transistor T6, and the source of transistor T7 are electrically connected, the drain of transistor T4 is electrically connected to the input terminal (71), the source of transistor T4 is electrically connected to the first output terminal (72), the source of transistor T5 is electrically connected to the source of transistor T6, the drain of transistor T8, and the source of transistor T9 at the same time, the drain of transistor T5 is electrically connected to the first output terminal (72), the gate of transistor T6 is electrically connected to the second output terminal (73), the gate of transistor T7 is electrically connected to the gate of transistor T8, and the source of transistor T8 is electrically connected to the drain of transistor T9.

2. The electronic paper panel structure according to claim 1, wherein: Each of the driving units (61) is provided with a first control terminal (74), a second control terminal (75) and a third control terminal (76), wherein the first control terminal (74) is electrically connected to the drain of the transistor T2, the second control terminal (75) is electrically connected to the source of the transistor T7, and the third control terminal (76) is electrically connected to both the gate and the drain of the transistor T9.

3. The electronic paper panel structure according to claim 2, wherein: The gate row scanning circuit (6) is arranged on the left edge, right edge or upper edge of the display panel (1), and is located in the peripheral area of ​​the electronic paper display.

4. The electronic paper panel structure according to claim 3, wherein: The topological distance between the circuit area where the gate row scanning circuit (6) is located and the area covered by the electronic paper film is greater than 50 microns, and the topological distance between the circuit area where the gate row scanning circuit (6) is located and the area where the electronic paper glass frame is located is greater than 100 microns.

5. The electronic paper panel structure according to claim 4, wherein: A line-changing hole (62) is provided on the surface of the display panel (1) or on the frame.

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