Real-time task WCET optimization method based on instruction and data cache static locking

Abstract

The invention discloses a real-time task WCET optimization method based on instruction and data cache static locking, and relates to the field of task WCET optimization in a real-time system, and the method comprises the following steps: carrying out offline program control flow diagram construction and WCET analysis on a to-be-operated program task; constructing a Petri net graph-based semantic flow model at an instruction-data level; extracting a feasible path of a program task by utilizing loop detection based on a depth-first search algorithm according to the Petri net graph semantic flow model; performing memory arrangement and cache mapping according to instructions and data information in the feasible path; constructing a WCET optimization problem of a single executable path; and solving the optimization problem, and comparing the WCET of all the paths to obtain the WCET of the program task. According to the method, the program running path is obtained through the instruction-data level control flow diagram, static locking is carried out on the memory block where the hotspot instruction and data are located, the search scale of the large-scale program WCET problem is reduced, the solving feasibility and speed are increased, and the algorithm practicability is improved.

Description

Technical Field

[0001] The present invention relates to the field of task WCET optimization in real-time systems, and particularly to a method for optimizing the WCET of real-time tasks based on static locking of instruction and data caches. Background Art

[0002] An edge programmable controller is a new type of controller that integrates the functions of device edge, router edge, and computing edge. It has high computing power, versatility, and flexible communication characteristics, and is an important direction for the transformation of programmable logic controllers (PLCs) towards intelligent manufacturing.

[0003] Similar to the program execution part in the traditional PLC scan cycle (0.5 to 100 milliseconds), the execution time of real-time program tasks in an edge programmable controller (abbreviated as edge PLC) also has a great impact on the overall time consumption. Therefore, the execution time of these tasks must be strictly controlled to ensure that they are completed within the specified cycle and to avoid potential serious consequences caused by timeouts or delays. Usually, system performance and task execution time are analyzed and optimized based on the worst case execution time (WCET) to ensure their safety and reliability in various operating environments. Therefore, accurately predicting and optimizing the WCET is of great significance for the design and verification of the system. A "real-time program task" is defined as a real-time task composed of a complete program and running in the form of an independent process. In edge PLCs, IEC 61131-3 standard languages, such as ladder diagrams and structured text programs, are mainly used to write real-time program tasks. Ladder diagram programs are simpler than structured text and can be converted into structured text programs. Therefore, the research object in the present invention is the real-time task constructed by structured text programs.

[0004] The prediction of the worst case execution time (WCET) in the offline state is a widely used analysis method. Its core steps include: obtaining the control flow graph of the program, conducting low-level analysis and modeling in combination with the specific operating environment, and finally achieving the accurate calculation of the WCET. The main innovation of the present invention lies in how to accurately model the WCET of the program to improve its prediction accuracy and optimization effect in the edge PLC operating environment.

[0005] In an edge PLC, when the processor executes a program, it needs to read data such as the user program from memory for instruction analysis and execution. This process is similar to the way the processor in a traditional PLC obtains program data from the working storage area. In both cases, the data transfer speed between the processor and the storage medium is relatively slow. Therefore, a cache mechanism is usually introduced to improve system performance. The processor's level-1 cache (L1 cache) is typically divided into an instruction cache and a data cache, which are used to store instructions and data respectively. When the instruction or data accessed by the program already exists in the cache, it is called a cache hit, and the access speed is relatively fast. If the corresponding data is not in the cache, it is a cache miss, and in this case, the processor must access the main memory, resulting in a significant access delay. Therefore, adopting a reasonable cache management strategy can effectively optimize the WCET of the program. Among them, cache static locking is a common optimization method, which pre-determines at compile time which instructions and data are locked in a cache of limited size and remains unchanged during program execution. This method can provide higher determinacy and make the WCET analysis more accurate. In contrast, dynamic cache locking allows the program to dynamically select cache content for locking during runtime, which can theoretically utilize cache resources more efficiently. However, the complexity and runtime overhead of dynamic cache locking make WCET modeling more difficult, which is not conducive to the analysis and verification of real-time systems.

[0006] After retrieving existing literature, the closest implementation scheme is as follows: Chinese Patent 201310118037.X, titled: An Instruction Prefetch Content Selection Method for Optimizing WCET of Real-Time Tasks, which adds a hardware structure of an instruction information table (BBIT) to the instruction cache, statically analyzes the set of basic program blocks, and locks a specified number of instruction information according to the execution frequency. However, this method only focuses on instruction cache optimization, does not consider the impact of data access time, and its basic block selection strategy based on the greedy algorithm may not guarantee the WCET optimization effect. Chinese Patent Application 202210421822.1, titled: A Dynamic Cache Locking WCET Analysis Method Based on Memory Block Lifecycle, obtains the cache state of the program through abstract interpretation technology and calculates the memory block lifecycle and locking set on the worst-case path. Additionally, Chinese Patent 201710996826.1, titled: A Multicore Cache WCET Analysis Method Supporting Instruction Prefetch, introduces a classification method for cache early access to better understand and predict the impact of instruction prefetch on cache behavior, and then replaces and places subsequent partial instructions into the cache when reading a single instruction of the program, reducing the program WCET by dynamically switching cache content.

[0007] However, when these methods perform dynamic lock modeling, they only add different dynamic cache replacement policies on the basis of static cache locking. On the one hand, they do not fully consider the time overhead and cache consistency issues brought about by cache replacement. On the other hand, they also do not consider the impact of data cache on access time, resulting in limited accuracy of WCET analysis.

[0008] Therefore, those skilled in the art are committed to developing a WCET optimization method for real-time tasks based on static locking of instruction and data caches. Summary of the Invention

[0009] In view of the above-mentioned defects of the prior art, the technical problem to be solved by the present invention is that in the static cache locking optimization method adopted by existing real-time systems, only instruction cache or data cache is usually considered, ignoring the interactive influence between the two in the L1 cache, resulting in a significant deviation between the predicted WCET value and the actual execution time, thus affecting the accuracy of the control algorithm and the real-time performance of the system, and further affecting the final task scheduling and system performance.

[0010] To achieve the above object, the present invention provides a WCET optimization method for real-time tasks based on static locking of instruction and data caches, and the method includes the following steps:

[0011] S101: For the program task to be run, perform offline construction of the program control flow graph and WCET analysis;

[0012] S103: Construct a Petri net graph semantic flow model at the instruction-data level, and the Petri net graph semantic flow model includes program instructions and variable data;

[0013] S105: According to the Petri net graph semantic flow model, use loop detection based on the depth-first search algorithm to extract the feasible paths of the program task;

[0014] S107: According to the instruction and data information in the feasible paths, perform memory layout and cache mapping;

[0015] S109: Construct the WCET optimization problem of a single executable path;

[0016] S111: Solve the optimization problem and compare the WCETs of all paths to obtain the WCET of the program task.

[0017] Further, in the step S103, the Petri net graph semantic flow model includes transition nodes and place nodes, the transition nodes are configured to be that the program instruction is reading an instruction, and the place nodes are configured to be that variables need to be operated in the current instruction;

[0018] The transition nodes and the place nodes are configured as basic units, and a combined graph structure is constructed through the basic units and the syntax of structured text. In the combined graph structure, the operation semantics of the program are continuously switched between the transition nodes and the place nodes.

[0019] Further, the step S103 includes the following sub-steps:

[0020] S1031: Input the structured text source program, and generate a basic unit structure after processing each line of code. The basic unit structure includes program command nodes and their subsequent variable nodes;

[0021] S1032: Connect the generated basic unit structure with the context nodes;

[0022] S1033: Generate the complete Petri net graph semantic flow model, and the model contains all program instructions and variable data.

[0023] Further, in the step S105, the loop detection of the depth-first search algorithm is to explore along each feasible path of the Petri net until it cannot continue, and then backtrack to the previous branch point until the entire Petri net graph is traversed. Specifically, it includes the following sub-steps:

[0024] S1051: Mark the current node as visited and add the current node to the current path stack;

[0025] S1052: For each unvisited subsequent node of the current node, recursively call the depth-first search to continue exploring the subsequent node;

[0026] S1053: For the subsequent node that has been visited and is in the recursive stack, find the part of the loop in the current path and record it;

[0027] S1054: According to the loop condition or the pre-configured condition, given the execution times information of the nodes in the loop;

[0028] S1055: For an acyclic graph, use the depth-first search algorithm to obtain all feasible paths and the instruction and data information on the paths.

[0029] Further, in the step S107, the greedy algorithm is used to arrange the memory of instructions and data. Select the memory blocks where the hot instructions and data in the program are located for static locking under limited caching, and the cache mapping method is restricted by direct mapping or fully associative mapping.

[0030] Further, when arranging the memory of the instructions and the data using the greedy algorithm, the instructions and the data in a single feasible path are respectively allocated to different memory blocks. The instructions are stored in sequence, and for the data, there is no requirement for order, but data integrity and memory alignment must be ensured.

[0031] Further, in the direct mapping, only one memory block mapped to the same cache line can be selected to be locked into the corresponding cache line, and the cache hit of each instruction and data is checked; in the fully associative mapping, the total number of main memory blocks locked into the cache cannot exceed the number of cache lines. In WCET analysis, the query time is proportional to the number of cache lines.

[0032] Further, step S107 includes the following sub-steps:

[0033] S1071: Follow the rule of sequential placement and put the assembly instructions obtained by transforming a single instruction into the main memory in sequence, and a single source program cannot be split and placed;

[0034] S1072: Use the greedy algorithm to put the hot data together and try to fill each memory block with data as much as possible;

[0035] S1073: Use the direct mapping and fully associative mapping methods to map the instructions and data from the memory to the cache.

[0036] Further, in step S109, the WCET optimization problem is:

[0037]

[0038] s.t.

[0039]

[0040] C2: s(t ij ) = a · num(p ijk ) + b

[0041] C3: α(t) ∈ {0, 1}

[0042] C4: β(p) ∈ {0, 1}

[0043] C5: Block I →InCache = α(t x1 ) = … = α(t xq ), t x · ∈ Block I [i], i ∈ {0, 1, …, len(Block I ) - 1}

[0044] C6: Block D →InCache = β(t y1 ) = … = β(t yq ), t x · ∈ block D [i], i ∈ {0, 1, …, len(Block D ) - 1}

[0045] For direct mapping:

[0046]

[0047] For fully associative mapping:

[0048]

[0049] Wherein, the objective function represents minimizing the execution time of a single feasible path l i , C1, C2, …, C8 are constraint conditions, l i is the i-th feasible path, α(t ij ) represents whether the instruction is in the cache, W0(t ij ) represents the execution time required for the instruction in the cache, W1(t ij ) represents the execution time required for the instruction in the memory, Search(t ij ) represents the query time of the instruction in the instruction cache, times(t ij ) represents the number of times the instruction will be executed in the path; Call z is the call execution time, β(p ijk ) represents whether the variable is in the cache, W D0 (p ijk ) represents the execution time required for the variable in the cache, W D1 (p ijk ) represents the execution time required for the variable in the memory, Search(p ijk ) represents the query time of the variable in the data cache, s(t ij ) represents the number of variables in the instruction, num(p ijk ) represents the number of variables contained, n is the number of instructions in the path, m is the number of variables in the path, Block I , Block D are memory blocks, Block I [i] → InCache represents the variable indicating whether the current memory block will be placed in the cache, a, b, k, z are variables, t ij is a program instruction, p ijkP is a program variable, Lc is the number of cache lines, and I_Cache and D_Cache are the number of cache lines.

[0050] Further, in the step S111, an optimizer is used to solve the optimization problem. The optimizer introduces the idea of genetic mutation to improve the optimizer, introduces mutation in the genetic algorithm in the transformation part, uses heuristic thinking to solve the optimization problem, converts the decision variables from the instructions and the data into memory blocks, and obtains the minimum WCET of the program.

[0051] In a preferred embodiment of the present invention, compared with the prior art, the present invention has the following beneficial effects:

[0052] 1. The present invention proposes a more accurate program WCET analysis method for the program tasks running on the edge PLC, breaking through the limitation of only considering instructions or data in the traditional program WCET analysis, reducing the scale of searching for the WCET problem of large-scale programs, accelerating the feasibility and speed of solution, and improving the practicability of the algorithm.

[0053] 2. The present invention ensures the WCET of the program task, obtains all feasible paths of the program. The optimization problem and constraint conditions proposed by the present invention are more accurate and have better effects for offline estimating the program WCET. Compared with traditional algorithms, such as the genetic algorithm, it can converge to a better result and give the best instruction and data cache locking scheme.

[0054] 3. The method of the present invention can be seamlessly integrated into the existing edge PLC, has good compatibility and adaptability, is easy to implement and popularize, has high technical feasibility, requires lower hardware and software resources, and has a relatively economical implementation cost.

[0055] The following will further illustrate the concept, specific structure and technical effects of the present invention with reference to the drawings, so as to fully understand the purpose, features and effects of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 is a schematic diagram of the steps of the real-time task WCET optimization method according to a preferred embodiment of the present invention;

[0057] Figure 2 is an overall framework diagram of the program task WCET prediction and optimization according to a preferred embodiment of the present invention;

[0058] Figure 3 is a flowchart of constructing a program flow graph at the instruction-data level according to a preferred embodiment of the present invention;

[0059] Figure 4 is an example of constructing a Petri semantic model for a structured text program according to a preferred embodiment of the present invention;

[0060] Figure 5 It is a flowchart for obtaining the executable path and path information of a preferred embodiment of the present invention;

[0061] Figure 6 It is a schematic diagram of the memory layout for instructions and data of a preferred embodiment of the present invention;

[0062] Figure 7 It is a flowchart for solving the optimization problem of a preferred embodiment of the present invention. Detailed implementation manners

[0063] The following introduces multiple preferred embodiments of the present invention with reference to the accompanying drawings of the specification, making its technical content clearer and easier to understand. The present invention can be embodied in many different forms of embodiments, and the protection scope of the present invention is not limited to the embodiments mentioned in the text.

[0064] In the drawings, components with the same structure are denoted by the same numerical labels, and components with similar structures or functions everywhere are denoted by similar numerical labels. The size and thickness of each component shown in the drawings are arbitrarily shown, and the present invention does not limit the size and thickness of each component. In order to make the illustration clearer, the thickness of some components in the drawings is appropriately exaggerated.

[0065] In the existing static cache locking optimization method adopted by real-time systems, usually only the instruction cache or the data cache is considered, ignoring the interactive influence between the two in the L1-level cache. However, in an actual edge PLC, the L1 cache of the processor is divided into an instruction cache and a data cache, and both have an important impact on the task execution time during the WCET modeling process. If only one cache type is considered, it may lead to a significant deviation between the predicted value of WCET and the actual execution time, thus affecting the accuracy of the control algorithm and the real-time performance of the system, and further affecting the final task scheduling and system performance. For the WCET optimization of real-time program tasks in edge PLCs, the present invention provides a new method that comprehensively considers the static locking of instruction and data caches. By obtaining the running path of the program through an instruction-data level control flow graph, and comprehensively considering the arrangement and mapping methods of instructions and data in the cache and memory, the memory blocks where the hot instructions and data in the program are located are selected for static locking under limited caching, which can greatly reduce the estimated WCET of the program and make it closer to the actual execution time.

[0066] As Figure 1 shown, a real-time task WCET optimization method based on static locking of instruction and data caches provided by an embodiment of the present invention takes a structured text program as a research example, models the WCET of a single feasible path of the program as a 0-1 integer programming problem, and quantitatively analyzes the impact of whether each instruction and each variable are respectively cache-hit on the WCET of the entire program mathematically.

[0067] The real-time task WCET optimization method provided in this embodiment includes the following steps:

[0068] S101: For the program tasks to be run, perform offline construction of the program control flow graph and WCET analysis.

[0069] For multiple structured text program tasks to be run on a single-core computer system, perform offline construction of the program flow graph and WCET analysis respectively. The optimized program execution time will be used for scheduling design later, so that each program task meets the real-time requirements.

[0070] S103: Construct a Petri net graph semantic flow model at the instruction-data level. The Petri net graph semantic flow model includes program instructions and variable data.

[0071] To represent the program flow at the instruction-data level, a new program flow graph is constructed based on Petri nets. All feasible paths are obtained through path search. The execution time of each feasible path is used as the objective function, and which instructions and data to put into the limited cache size is selected. By defining two 0-1 vectors α and β with different dimensions as decision variables, which represent whether n instructions are cache hits (1 for hit and 0 for miss, and the running time of the instruction will be reduced when it is a hit) and whether m variable data are cache hits (1 for hit and 0 for miss) respectively, the minimum WCET of a single feasible path is obtained by controlling the values of each dimension of α and β.

[0072] The Petri net graph semantic flow model constructed at the instruction-data level includes transition nodes and place nodes. The transition nodes are configured as program instructions that are reading instructions, and the place nodes are configured as variables that need to be operated on in the current instruction;

[0073] The transition nodes and place nodes are configured as basic units, and a combined graph structure is constructed through the basic units and the syntax of structured text. The continuous switching between the transition nodes and place nodes in the combined graph structure represents the operation semantics of the program.

[0074] This step includes the following sub-steps:

[0075] S1031: Input the structured text source program, and generate a basic unit structure after processing each line of code. The basic unit structure includes program command nodes and their subsequent variable nodes;

[0076] S1032: Connect the generated basic unit structure with the context nodes;

[0077] S1033: Generate a complete Petri net graph semantic flow model, and the model contains all program instructions and variable data.

[0078] S105: According to the semantic flow model of the Petri net diagram, use loop detection based on the depth-first search algorithm to extract the feasible paths of the program tasks.

[0079] When performing loop detection through the depth-first search algorithm, explore along each feasible path of the Petri net until it can no longer continue, then backtrack to the previous branch point until the entire Petri net diagram is traversed.

[0080] Specifically, it includes the following sub-steps:

[0081] S1051: Mark the current node as visited and add the current node to the current path stack;

[0082] S1052: For each unvisited successor node of the current node, recursively call the depth-first search to continue exploring the successor node;

[0083] S1053: For the successor nodes that have been visited and are in the recursive stack, find the loop part in the current path and record it;

[0084] S1054: According to the loop condition or pre-configured conditions, give the execution times information of the nodes in the loop;

[0085] S1055: For an acyclic graph, use the depth-first search algorithm to obtain all feasible paths and the instruction and data information on the paths.

[0086] S107: According to the instruction and data information in the feasible paths, perform memory layout and cache mapping.

[0087] Through the fine layout design of the instructions and data generated by the transformation of the structured text program in the memory of the edge PLC, to better represent the actual data storage, mapping, and access situations.

[0088] In this embodiment, use the greedy algorithm to layout the memory of the instructions and data, select the memory blocks where the hot instructions and data in the program are located for static locking under limited caching, and the cache mapping method is restricted by direct mapping or fully associative mapping.

[0089] When using the greedy algorithm to layout the memory of the instructions and data, allocate the instructions and data in a single feasible path to different memory blocks respectively. For instructions, store them in order, and for data, there is no requirement for order, but data integrity and memory alignment must be ensured.

[0090] In the memory layout design, two cache mapping strategies are analyzed: direct mapping and fully associative mapping. By constructing different constraint conditions through these two mapping methods, the accuracy and universality of the program WCET model are further improved. Specifically, for edge PLCs with different L1 cache sizes, this innovative design can provide a choice of cache mapping strategies, enabling the present invention to be more widely adapted to different edge PLCs and obtaining the optimal WCET prediction results.

[0091] Direct mapping can quickly locate the cache line and determine whether there is a hit by performing a modulo operation on the memory block position, and the query speed is relatively fast. However, since multiple memory blocks may be mapped to the same cache line, this may lead to conflicts. Therefore, the mathematical constraint form of direct mapping in the main innovation point is: only one of the memory blocks mapped to the same cache line can be selected to be locked into the corresponding cache line, and for WCET analysis, cache hit checks for each instruction and data must be introduced.

[0092] Fully associative mapping allows the main memory block to be locked into the cache line as long as there is free space in the cache line, providing higher flexibility. However, as the number of cache lines increases, the query time will also increase. Therefore, the mathematical constraint form of fully associative mapping in the main innovation point is: the total number of main memory blocks locked into the cache cannot exceed the number of cache lines, and in WCET analysis, a query time proportional to the number of cache lines needs to be introduced.

[0093] In this embodiment, this step includes the following sub-steps:

[0094] S1071: Follow the rule of sequential placement, and place the assembly instructions obtained by converting a single instruction into the main memory in sequence, and a single source program cannot be split and placed;

[0095] S1072: Use the greedy algorithm to put the hot data together and try to fill each memory block with data as much as possible;

[0096] S1073: Use the direct mapping and fully associative mapping methods to map the instructions and data from the memory to the cache.

[0097] By considering the memory layout and cache mapping methods, the WCET cache locking analysis based on memory blocks or program blocks is further explained and improved. Meanwhile, the constraints and impacts of different mapping methods on WCET modeling are analyzed. Through experiments, how to select the mapping method when the cache line size is different for direct mapping and fully associative mapping is quantitatively obtained, verifying the qualitative theory. According to the optimization problem, it is solved in combination with the memory layout. The decision variable is changed to whether the memory block is mapped to the cache line, where 1 represents a hit and 0 represents a miss. The hits of instructions and data in the memory block are consistent with the memory block. For larger-scale programs, this solution method will greatly reduce the dimension of the decision variable and improve the feasibility and efficiency of solving the WCET optimization problem for large-scale programs.

[0098] S109: Construct the WCET optimization problem for a single executable path.

[0099] In this embodiment, the WCET prediction and optimization problem is transformed into a mathematical problem, and the solution of the mathematical problem will directly guide how to statically lock instructions and data into a cache with a limited size to ensure the shortest execution time for a single executable path and achieve the prediction and optimization of WCET.

[0100] The WCET optimization problem is as follows:

[0101]

[0102] s.t.

[0103]

[0104] C2: s(t ij ) = a · num(p ijk ) + b

[0105] C3: α(t) ∈ {0, 1}

[0106] C4: β(p) ∈ {0, 1}

[0107] C5: Block I →InCache = α(t x1 ) = … = α(t xq ), t x · ∈ Block I [i], i ∈ {0, 1, …, len(Block I ) - 1}

[0108] C6: Block D →InCache = β(t y1 ) = … = β(t yq ), t x· ∈ Block D[i], i ∈ {0, 1, …, len(Block D ) - 1}

[0109] For direct mapping:

[0110]

[0111] For fully associative mapping:

[0112]

[0113] Wherein, the objective function represents minimizing the execution time of a single feasible path l i , C1, C2, …, C8 are constraints, l i is the i-th feasible path, α(t ij ) represents whether the instruction is in the cache, W0(t ij ) represents the execution time required for the instruction in the cache, W1(t ij ) represents the execution time required for the instruction in the memory, Search(t ij ) represents the query time of the instruction in the instruction cache, times(t ij ) represents the number of times the instruction will be executed in the path; Call z is the call execution time, β(p ijk ) represents whether the variable is in the cache, W D0 (p ijk ) represents the execution time required for the variable in the cache, W D1 (p ijk ) represents the execution time required for the variable in the memory, Search(p ijk ) represents the query time of the variable in the data cache, s(t ij ) represents the number of variables in the instruction, num(p ijk ) represents the number of contained variables, n is the number of instructions in the path, m is the number of variables in the path, Block I , Block D are memory blocks, Block I [i] → InCache represents the variable indicating whether the current memory block will be placed in the cache, a, b, k, z are variables, t ij is a program instruction, p ijk is a program variable, Lc is the number of cache lines, I_Cache, D_Cache are the number of cache lines.

[0114] S111: Solve the optimization problem, compare the WCETs of all paths, and obtain the WCET of the program task.

[0115] In this embodiment, by comparing the WCETs of all feasible paths and taking the maximum value among them as the WCET of the entire program task. By introducing the idea of genetic variation to improve the optimizer, the optimizer adopts the PO optimizer, which can ensure the effect of heuristic optimization to the greatest extent. Finally, the optimal strategy is obtained to lock some instructions and data into the cache offline and obtain the minimum WCET of the program.

[0116] The improved PO optimizer is used to solve the optimization problem. The idea of genetic variation is introduced to improve the PO optimizer. Mutation in the genetic algorithm is introduced in the transformation part. The heuristic idea is used to solve the optimization problem. The decision variables are transformed from instructions and data into memory blocks to obtain the minimum WCET of the program.

[0117] Compared with the prior art, the real-time task WCET optimization method based on static locking of instruction and data caches provided by the present invention has the following characteristics:

[0118] 1. In the existing static cache locking optimization methods adopted by real-time systems, only instruction caches or data caches are usually considered, ignoring the interactive effects between the two in the L1 cache. However, in actual edge PLCs, the L1 cache of the processor is divided into an instruction cache and a data cache, and both have an important impact on the task execution time during the WCET modeling process. If only one cache type is considered, it may lead to a significant deviation between the predicted WCET value and the actual execution time, thus affecting the accuracy of the control algorithm and the real-time performance of the system, and further affecting the final task scheduling and system performance. The present invention proposes a new method that comprehensively considers the static locking of instructions and data caches for WCET optimization of real-time program tasks in edge PLCs. By obtaining the program's execution path through an instruction-data level control flow graph, and comprehensively considering the arrangement and mapping methods of instructions and data in the cache and memory, the memory blocks where hot instructions and data in the program are located are selected for static locking under limited caching, which can greatly reduce the estimated WCET of the program and make it closer to the actual execution time. Taking a structured text program as a research example, the WCET of a single feasible path of the program is modeled as a 0-1 integer programming problem, and the impact of whether each instruction and each variable is cached hit on the WCET of the entire program is quantitatively analyzed mathematically. Specifically, two 0-1 vectors α and β with different dimensions are defined as decision variables, representing whether n instructions are cached hit (1 for hit and 0 for miss, and the running time of the instruction will be reduced when hit) and whether m variable data are cached hit (1 for hit and 0 for miss), respectively. To represent the program flow at the instruction-data level, a new program flow graph is constructed based on Petri nets, and all feasible paths are obtained through path search. The execution time of each feasible path is used as the objective function, and under the condition of limited cache size, it is selected which instructions and data are placed in it, that is, the minimum WCET of a single feasible path is obtained by controlling the values of each dimension of α and β. By transforming the WCET prediction and optimization problem into a mathematical problem, the solution of the mathematical problem will directly guide how to statically lock instructions and data into a cache with a limited size to ensure the shortest execution time for a single executable path and achieve the prediction and optimization of WCET. Further, by comparing the WCETs of all feasible paths, the maximum value is taken as the WCET of the entire program task. By introducing the idea of genetic mutation to improve the PO optimizer, the effect of heuristic optimization can be ensured to the greatest extent, and finally the optimal strategy is obtained to offline lock some instructions and data into the cache and obtain the minimum WCET of the program.

[0119] 2. Existing program WCET cache locking strategies mainly rely on memory block graphs or program block graphs for analysis. Specifically, the program is divided into multiple independent blocks through the program control flow graph, and based on this structure, specific program blocks are directly selected to be locked in the cache. However, these methods have significant limitations: on the one hand, they do not fully consider the actual arrangement of source program instructions and data in memory and their interaction with the cache; on the other hand, for different memory block-to-cache mapping strategies, such as direct mapping and fully associative mapping, their profound impact on cache hit rate and access latency has not been systematically studied. This omission causes the current methods to be unable to comprehensively reflect the actual characteristics of cache behavior when predicting WCET, limiting the accuracy and generality of the prediction results. The present invention conducts a fine layout design of the instructions and data generated by the transformation of structured text programs in the memory of the edge PLC to better represent the actual data storage, mapping, and access situations. In the memory layout design, two cache mapping strategies are analyzed: direct mapping and fully associative mapping. By constructing different constraint conditions through these two mapping methods, the accuracy and generality of the program WCET model are further improved. Specifically, for edge PLCs with different L1 cache sizes, this innovative design can give the choice of cache mapping strategy, enabling the present invention to be more widely adapted to different edge PLCs and obtaining the optimal WCET prediction results. The greedy algorithm is used to allocate the instructions and data in a single feasible path to different memory blocks respectively. The instructions are stored in sequence, while for the data, there is no requirement for sequence, but data integrity and memory alignment must be ensured. Direct mapping can quickly locate the cache line and determine whether there is a hit through modulo operation on the memory block position, and the query speed is relatively fast. However, since multiple memory blocks may map to the same cache line, this may lead to conflicts. Therefore, the mathematical constraint form of direct mapping in the main innovation points is: only one of the memory blocks mapped to the same cache line can be selected to be locked into the corresponding cache line, and for WCET analysis, a cache hit check for each instruction and data must be introduced. Fully associative mapping allows the main memory block to be locked into the cache line as long as there is free space in the cache line, providing higher flexibility, but as the number of cache lines increases, the query time will also increase. Therefore, the mathematical constraint form of fully associative mapping in the main innovation points is: the total number of main memory blocks locked into the cache cannot exceed the number of cache lines, and in WCET analysis, a query time proportional to the number of cache lines needs to be introduced. The present invention further explains and improves the WCET cache locking analysis based on memory blocks or program blocks by considering memory layout and cache mapping methods. At the same time, the constraints and impacts of different mapping methods on WCET modeling are analyzed, and through experiments, it is quantitatively obtained how to select the mapping method when the cache line size is different for direct mapping and fully associative mapping, verifying the qualitative theory.Solve according to the optimization problem in combination with the memory layout. Change the decision variables to whether the memory blocks are mapped to the cache lines, where 1 indicates a hit and 0 indicates a miss. The hits of the instructions and data in the memory blocks are consistent with the memory blocks. For larger-scale programs, this solution method will greatly reduce the dimension of the decision variables and improve the feasibility and efficiency of solving the WCET optimization problem for large-scale programs.

[0120] The present invention will be described in detail below in conjunction with the preferred embodiments of the present invention.

[0121] The real-time task WCET optimization method based on static locking of instruction and data caches provided in this embodiment includes the following steps:

[0122] Step 1. Consider an Figure 2 application scenario as follows. For multiple structured text program tasks that are about to run on a single-core computer system, perform offline program flow graph construction and WCET analysis respectively.

[0123] Among them, structured text is a text-based programming language for programmable logic controllers, similar to the C language, with many syntax elements. The optimized program execution time will be used for scheduling design later, so that each program task meets the real-time requirements, that is, all tasks are completed within their absolute deadlines.

[0124] Step 2. In order to select specific source program instructions and programs for latching, it is necessary to construct a program flow graph at the instruction-data level to obtain information, as Figure 3 shown.

[0125] Traditional control flow graphs, such as the ControlFlow Graph using program blocks as nodes, cannot meet this requirement. Therefore, the present invention selects Petri nets as the basis to construct a new graph semantic model: Since the program operation semantic flow can be divided into two types: reading / executing instructions and reading / writing variables, and the transition and place elements in Petri nets are similar in meaning to them, the transition node can be represented as the program instruction is reading an instruction, and the subsequent place node can be represented as certain variables need to be operated on in the current instruction. Further, the transition node and its subsequent place node are used as basic units, and a combined graph structure is constructed through the grammar of basic units and structured text. In this graph structure, the continuous switching between transition nodes and place nodes represents the change of the system state, that is, it represents the operation semantics of the program. To implement the automatic conversion function, an algorithm is designed to achieve the following functions: input the structured text source program, process each line of code. If it is a basic assignment / calculation statement, directly generate the basic unit structure (i.e., the program command node and its subsequent variable node). If it is a complex syntax structure, iteratively analyze its internal program statements. The iteration termination condition is that the current statement is a basic assignment / calculation statement, and then connect the generated unit with the context node. Finally, a complete Petri net graph semantic flow model is generated, which contains the specific information of all program instructions and variable data.

[0126] Step 3, according to the semantic flow model obtained in Step 2, use loop detection based on the depth-first search algorithm, that is, explore along each feasible path of the Petri net until it cannot continue, and then backtrack to the previous branch point until the entire Petri net graph is traversed, as Figure 4 , Figure 5 shown.

[0127] Among them, a judgment for detecting loops is added. The key lies in distinguishing between two states: "whether the node has been visited" and "whether the node is currently in the recursive stack", so as to effectively detect the loops in the graph.

[0128] The data variables used by the program are:

[0129] currentPath, the current path, used to record the nodes on the path;

[0130] allPath, the set of all found paths;

[0131] visitedEdges, record whether the edge has been visited to prevent repeated access;

[0132] visitedNodes, record the access status of the node (true means visited);

[0133] onStack, which records whether the current node is on the recursive stack (for loop detection). onStack[node] = true indicates that the node is on the current recursive path;

[0134] cycles, which stores all detected loops.

[0135] A loop can only be formed when the node is on the current path and has not been visited yet.

[0136] During depth - first search traversal, first mark the current node as visited and add it to the current path stack. For each successor node of the current node, perform the following operations: If the successor node has not been visited, recursively call depth - first search to continue exploring the successor node. If the successor node has been visited and it is still on the recursive stack currently (i.e., onStack[nextNode] = true), it means that a loop has been formed by returning to a previous node. At this time, the part of the loop can be found from the current path and recorded, and information about the number of executions of the nodes in the loop can be given according to loop conditions or user - set conditions. For an acyclic graph, the depth - first search algorithm can also be used to obtain all feasible paths and the instruction and data information on the paths.

[0137] Step 4: Perform memory layout and cache mapping according to the instruction and data information in the single path obtained in Step 3, specifically as follows:

[0138] Step 4.1: Memory layout of instructions and data. Assume that the size of the memory block where the instruction is located is 4Bytes × 8 = 32Bytes. According to the principle of program compilation into assembly code, assume that the number of assembly instructions that can be obtained by converting a single source program instruction is proportional to the number of variables it contains, and the memory size occupied by a single assembly instruction is fixed, which can be considered as 4Bytes. Therefore, at most 8 assembly instructions can be placed in one instruction memory block. In this experiment, assume that the number of assembly instructions obtained by converting a single source program does not exceed 8. Following the rule of sequential placement, place the assembly instructions obtained by converting a single instruction in sequence in the main memory, and a single source program cannot be split and placed. Only in this way can the latch strategy be ensured at the source program level. The data memory block is similar, but since a single data may be relatively small, such as the integer type size is 4Bytes, so the size of the data memory block is generally smaller than the instruction memory block, and the data does not need to be stored in order. Therefore, use the greedy algorithm to put the hot data together and try to fill each memory block with data as much as possible to make the space utilization rate higher, but also need to meet rules such as memory alignment and data integrity. For array data, it is continuous in memory. After the above two layouts, the instructions and data obtained in a path can be placed in different memory spaces in a better way, as Figure 6 shown.

[0139] Step 4.2: Further use different mapping methods to map instructions and data from memory to cache.

[0140] The size of each memory block is always equal to the size of each cache line. Mapping means putting a memory block into a cache line. Two different basic mapping methods are mainly introduced, namely direct mapping and fully associative mapping. These two methods are significantly different. For direct mapping, the memory blocks are numbered starting from 0. Let the main memory block number be Mi and the number of cache lines be Lc. Then the cache line number to which the main memory block is mapped is Mi % Lc. It is not difficult to see that the disadvantage of direct mapping is that every Lc memory blocks will try to be put into the same cache line, so conflicts will occur. Correspondingly, the advantage of direct mapping is that when querying whether an instruction or data is cached, since the address and cache line number are uniquely determined, the query time in the cache is shorter. In summary, direct mapping is more suitable for scenarios with a larger number of cache lines. For fully associative mapping, each memory block can be put into any cache line as long as the cache line is empty. Therefore, fully associative mapping is more flexible. However, relatively speaking, since it is not certain whether the data is in the cache and where it is in the cache, when encountering an instruction or data, the query time in the cache will be longer. For WCET, a conservative estimate needs to be made. Therefore, it is assumed that the query time is always proportional to the number of cache lines and fixed. In summary, fully associative mapping is more suitable for scenarios with a smaller number of cache lines. These two mapping methods are transformed into different mathematical expressions to constrain the number of main memory blocks put into the cache, and further to constrain the optimal selection of instructions and data.

[0141] Step 5: Construct the following optimization problem to represent the WCET optimization problem of a single executable path.

[0142] Specifically:

[0143]

[0144] s.t.

[0145]

[0146] C2: s(t ij ) = a · num(p ijk ) + b

[0147] C3: α(t) ∈ {0, 1}

[0148] C4: β(p) ∈ {0, 1}

[0149] C5: Block I →InCache = α(t x1 ) = … = α(t xq ), t x· ∈ Block I[i], i ∈ {0, 1, …, len(Block I ) - 1}

[0150] C6: Block D →InCache = β(t y1 ) = … = β(t yq ), t x· ∈ Block D [i], i ∈ {0, 1, …, len(Block D ) - 1}

[0151] For direct mapping:

[0152]

[0153] For fully associative mapping:

[0154]

[0155] Among them, the objective function represents minimizing the execution time of a single feasible path l i The execution time of α(t ij ) indicates whether the instruction is in the cache. W0(t ij ), W1(t ij ) represent the execution time required for the instruction in the cache and the execution time required in the memory. Search(t ij ) represents the query time of the instruction in the instruction cache, and the size of this time is related to the memory mapping method; times(t ij ) represents the number of times the instruction will be executed in the path, which is determined by loops and repeated commands in the program.

[0156] The constraint condition C1 represents the execution time constraint of the instruction in or not in the cache, which is determined by the call execution time Call z (proportional to the instruction size) and the total call time of the variables contained in the instruction. Among them, whether the variable is in the data cache also needs to be considered, represented by β(p ijk ), and Search(p ijk ) represents the query time of the variable in the data cache.

[0157] The constraint condition C2 assumes that the instruction size is proportional to the number of variables num(p ijk ).

[0158] The constraint condition C3 represents that α(t ij ) is an n-dimensional 0 - 1 integer variable, 1 indicates the instruction is in the cache, and n is the number of instructions in this path.

[0159] The constraint condition C4 represents β(p ijkis an m-dimensional 0-1 variable, where 1 indicates that the variable is in the cache, and m is the number of variables in this path.

[0160] Constraint C5 means that whether the instructions in the same memory block Block I are hit needs to be consistent, because mapping instructions to the cache is a mapping of the entire memory block.

[0161] Constraint C6 means that whether the variable data in the same memory block Block D are hit needs to be consistent.

[0162] In direct mapping, every time the j + k·Lc-th main memory block is placed in the cache, it will conflict with other main memory blocks mapped to the j-th cache line. Therefore, constraints C7 and C8 are needed to ensure that there is only one instruction or data memory block placed in a cache line, Block I [i] → InCache. indicates whether the current memory block will be placed in the cache, which is also a 0-1 variable. In fully associative mapping, it is necessary to ensure that the number of main memory blocks placed in the cache does not exceed the number of cache lines. Therefore, constraints C7 and C8 are also used to ensure that the solution found by the optimizer can meet the capacity limit.

[0163] Step 6, Solving the optimization problem. The PO optimizer is a rare heuristic algorithm with a relatively complex structure. To further expand the exploration area, mutation in the genetic algorithm is introduced in the transformation part to generate more feasible solutions, which is very important for heuristic algorithms and is more likely to explore and obtain better solutions. Finally, by comparing the improved PO optimizer with traditional heuristic algorithms, the genetic algorithm, it can be obtained that the former has better optimization effect. To further reduce the solution complexity, consider changing the original decision variables α(t) and β(p) representing whether a single instruction and data are in the cache to whether a single instruction memory block and data memory block are in the cache, while the optimization objective still uses whether a single instruction and data are in the cache to calculate, but it needs to be determined by the variable indicating whether the memory block is in the cache whether all instructions or variables in the memory block are in the cache. This way is equivalent to reducing the dimensions of α(t) and β(p) and reducing the solution complexity, as Figure 7 shown.

[0164] Step 7, Jump to Step 2, select a new path, construct an optimization problem and use the PO optimizer to solve for the solution closest to the optimal solution, and obtain the minimum WCET of this path, and stop until there are no unprocessed new paths. Finally, compare the WCETs of all paths, and use the largest one as the WCET of the entire program.

[0165] For the program tasks running on edge PLCs, the present invention proposes a method for analyzing the WCET of programs with more accurate modeling, breaking through the limitation of only considering instructions or data in traditional WCET analysis of programs, and having significant technical advantages. By constructing a program flow graph at the instruction-data level, more fine-grained feasible path information can be obtained, thus providing a modeling closer to the underlying architecture of the operating environment for the construction of WCET estimation and optimization problems. At the same time, the memory of instructions and data is arranged using a greedy algorithm, and constraints are constructed based on two different cache mapping methods. The WCET of a single executable path is modeled as a 0-1 integer programming problem, quantifying the WCET of the program and the influence of specific instructions and data on it, and providing a mathematically rigorous optimization solution. By introducing the idea of genetic mutation to improve the PO optimizer, using heuristic ideas to solve the optimization problem, and at the same time transforming the decision variables from instructions to memory blocks, the scale of searching for the WCET problem of large-scale programs is reduced, the feasibility and speed of solution are accelerated, and the practicality of the algorithm is improved.

[0166] In terms of performance metrics, the present invention ensures the WCET of program tasks, obtains all feasible paths of the program, and further takes the above WCET modeling as the objective function to obtain the optimal execution time of a single executable path. By comparing the results of all paths, the maximum value of the WCET of all single paths is selected as the WCET of the program task, which not only ensures the worst-case premise but also optimizes the execution time in this case through the selection of decision variables. Compared with some classical methods, the optimization problems and constraint conditions proposed by the present invention are more accurate and have better effects for offline estimation of program WCET. Compared with traditional algorithms such as genetic algorithms, it can converge to a better result and give the best instruction and data cache locking scheme.

[0167] In terms of production implementation, the method of the present invention can be seamlessly integrated into existing edge PLCs, with good compatibility and adaptability, easy to implement and promote, and high technical feasibility. The required hardware and software resources are relatively low, and the implementation cost is economical. Only need to optimize the program through software offline algorithms, and use software system commands to lock the instructions and data in the optimal solution into the cache, without large-scale hardware transformation. This method has good scalability and is applicable to various types of burst tasks and multiple control systems, and can be effectively applied. The algorithm optimizes the arrangement of memory resources, gives different mapping method selections according to the cache sizes of different systems, further improves the system operation efficiency, and reduces the overall production cost. With the wide application of industrial automation and complex intelligent control systems, the demand for program WCET prediction and optimization is increasing continuously. The present invention can meet the market demand and has broad application prospects and potential economic benefits. In complex industrial automation control systems, the WCET prediction and optimization algorithm proposed by the present invention can effectively and accurately analyze real-time program tasks and provide reference data for control means such as scheduling. In an automated manufacturing system, it can accurately control the execution timing of key production tasks, thus avoiding conflicts and delays between devices, ensuring that the worst-case execution time of each production task during execution is minimized, improving production efficiency, reducing machine downtime, and ensuring high-yield and high-precision manufacturing requirements. In an industrial robot control system, the edge PLC is responsible for real-time processing of tasks of multiple sensors and actuators, and performs path planning and motion control. Through accurate WCET analysis and optimization, it is ensured that the robot can strictly comply with real-time task requirements when performing complex operations, avoiding control delays or instability caused by improper task scheduling.

[0168] The preferred specific embodiments of the present invention have been described in detail above. It should be understood that those of ordinary skill in the art can make many modifications and variations based on the concept of the present invention without creative labor. Therefore, all technical solutions that can be obtained by those skilled in the art in the technical field of the present invention based on the concept of the present invention through logical analysis, reasoning or limited experiments on the basis of the prior art should be within the protection scope determined by the claims.

Claims

1. A WCET optimization method for real-time tasks based on static locking of instruction and data caches, characterized in that, The method includes the following steps: S101: For the program task to be run, construct an offline program control flow graph and perform WCET analysis; S103: Construct a Petri net graph semantic flow model at the instruction-data level, where the Petri net graph semantic flow model includes program instructions and variable data; S105: According to the Petri net graph semantic flow model, use loop detection based on the depth-first search algorithm to extract the feasible paths of the program task; S107: According to the instruction and data information in the feasible paths, perform memory layout and cache mapping; S109: Construct the WCET optimization problem for a single executable path; S111: Solve the optimization problem and compare the WCETs of all paths to obtain the WCET of the program task.

2. The method according to claim 1, wherein In the step S103, the Petri net graph semantic flow model includes transition nodes and place nodes. The transition nodes are configured such that the program instructions are reading instructions, and the place nodes are configured such that variables need to be operated on in the current instruction; The transition nodes and the place nodes are configured as basic units, and a combined graph structure is constructed through the basic units and the syntax of structured text. In the combined graph structure, the continuous switching between the transition nodes and the place nodes represents the operation semantics of the program.

3. The method according to claim 2, wherein The step S103 includes the following sub-steps: S1031: Input the structured text source program, and generate a basic unit structure after processing each line of code. The basic unit structure includes program command nodes and their subsequent variable nodes; S1032: Connect the generated basic unit structure with the context nodes; S1033: Generate the complete Petri net graph semantic flow model, which contains all program instructions and variable data.

4. The method according to claim 3, wherein In the step S105, for the loop detection of the depth-first search algorithm, explore along each feasible path of the Petri net until it cannot continue, and then backtrack to the previous branch point until the entire Petri net graph is traversed. Specifically, it includes the following sub-steps: S1051: Mark the current node as visited and add the current node to the current path stack; S1052: For each unvisited subsequent node of the current node, recursively call the depth-first search to continue exploring the subsequent node; S1053: For the subsequent node that has been visited and is in the recursive stack, find the part of the loop in the current path and record it; S1054: According to the loop condition or pre-configured conditions, give the execution times information of the nodes in the loop; S1055: For an acyclic graph, use the depth-first search algorithm to obtain all feasible paths and the instruction and data information on the paths.

5. The method according to claim 4, wherein In the step S107, use the greedy algorithm to arrange the memory of instructions and data, select the memory blocks where the hot instructions and data in the program are located for static locking under limited caching, and the cache mapping method is restricted by direct mapping or fully associative mapping.

6. The method according to claim 5, wherein When arranging the memory of the instructions and the data using the greedy algorithm, the instructions and the data in a single feasible path are respectively allocated to different memory blocks. The instructions are stored in sequence, while for the data, there is no requirement for sequence, but data integrity and memory alignment must be ensured.

7. The method according to claim 6, wherein In the direct mapping, only one of the memory blocks mapped to the same cache line can be selected and locked into the corresponding cache line, and the cache hits for each instruction and data are checked; in the fully associative mapping, the total number of main memory blocks locked into the cache cannot exceed the number of cache lines. In WCET analysis, the query time is proportional to the number of cache lines.

8. The method according to claim 7, wherein The step S107 includes the following sub-steps: S1071: Follow the rule of sequential placement, and place the assembly instructions obtained by converting a single instruction into the main memory in sequence, and a single source program cannot be split and placed. S1072: Use the greedy algorithm to put the hot data together and try to fill each memory block with data as much as possible. S1073: Use the direct mapping and fully associative mapping methods to map the instructions and data from the memory to the cache.

9. The method according to claim 8, wherein In the step S109, the WCET optimization problem is: s.t. C2:s(t ij ) = a·num(p ijk ) + b C3: α(t) ∈ {0, 1} C4: β(p) ∈ {0, 1} C5:Block I →InCache = α(t x1 ) = … = α(t xq ), t x· ∈Block I [i], i ∈ {0, 1, …, len(Block I ) - 1} C6:Block D →InCache = β(t y1 ) = … = β(t yq ), t x· ∈ Block D [i], i ∈ {0, 1, …, len(Block D ) - 1} For direct mapping: For fully associative mapping: Among them, the objective function represents minimizing the execution time of a single feasible path l i , C1, C2, …, C8 are constraint conditions, and l i is the i-th feasible path, α(t ij ) indicates whether the instruction is in the cache, W0(t ij ) represents the execution time required for the instruction in the cache, W1(t ij ) represents the execution time required for the instruction in the memory, Search(t ij ) represents the query time of the instruction in the instruction cache, times(t ij ) represents the number of times the instruction will be executed in the path; Call z is the call execution time, β(p ijk ) indicates whether the variable is in the cache, W D0 (p ijk ) represents the execution time required for the variable in the cache, W D1 (p ijk ) represents the execution time required for the variable in the memory, Search(p ijk ) represents the query time of the variable in the data cache, s(t ij ) represents the number of variables in the instruction, num(p ijk ) represents the number of contained variables, n is the number of instructions in the path, m is the number of variables in the path, Block I , Block D are memory blocks, Block I [i] → InCache represents the variable indicating whether the current memory block will be put into the cache, a, b, k, z are variables, t ij is a program instruction, p ijk is a program variable, Lc is the number of cache lines, and I_Cache, D_Cache are the number of cache lines.

10. The method according to claim 9, characterized in that, In the step S111, an optimizer is used to solve the optimization problem. The optimizer introduces the idea of genetic mutation to improve the optimizer, introduces mutation in the genetic algorithm in the conversion part, and uses heuristic ideas to solve the optimization problem. The decision variables are converted from instructions and data to memory blocks to obtain the minimum WCET of the program.

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