ZYNQ-based motor simulation method

Abstract

According to the ZYNQ platform-based motor simulation method provided by the invention, the ARM + FPGA heterogeneous architecture characteristic of ZYNQ is fully utilized, a motor simulation model is intelligently segmented and deployed, and a set of complete solution from model design to code generation, deployment and debugging is constructed based on a real-time Linux system. The method has the advantages of being high in universality, easy and convenient to use and low in cost, the motor model can be rapidly built according to the electrical characteristics of the motor, codes suitable for different computing resources are generated through the code generation technology, and efficient hardware-in-the-loop simulation is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of hardware-in-the-loop simulation, and specifically to a motor simulation method based on ZYNQ. Background Art

[0002] With the rapid development of power electronics technology and control theory, motor control systems are increasingly widely used in the fields of industrial automation, new energy vehicles, robots, etc. At present, there are mainly the following implementation schemes for motor simulation technology: 1. Pure software simulation scheme based on general-purpose processors This method uses a general-purpose processor platform such as x86 to run the motor mathematical model. Although such a method is convenient for development, its real-time performance is poor, and it is difficult to meet the simulation requirements of high-precision motor control systems.

[0003] 2. Real-time simulation scheme based on dedicated DSP processors This scheme uses a high-performance DSP processor to achieve real-time calculation of the motor model. Although the real-time performance is improved, the computing resources are limited, and it is difficult to achieve high-precision simulation of complex motor models.

[0004] 3. Hardware simulation scheme based on FPGA This scheme fully implements the motor model on the FPGA. Although the real-time performance is high, the development difficulty is large, the parameter adjustment is inconvenient, and the flexibility is lacking.

[0005] 4. Traditional X86 CPU + FPGA heterogeneous simulation scheme This scheme distributes the computing tasks to the CPU and the FPGA, but such systems usually need to communicate through complex interfaces such as PCIe and Ethernet, with large development difficulty and long cycle.

[0006] The above existing technologies generally have the contradiction that it is difficult to balance the lack of real-time performance or large development difficulty; lack flexible parameter adjustment and model deployment methods; the system structure is complex and the cost is high; the development cycle is long, which is not conducive to rapid iterative verification and difficult to meet the simulation requirements. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a motor simulation method based on ZYNQ, which can effectively solve the problems proposed in the above background art.

[0008] To solve the above problems, the technical solution adopted by the present invention is: A motor simulation method based on ZYNQ, including the following steps: S1. Hardware interface development: Build input and output interfaces including ADC and DAC on the PL side of ZYNQ, and write low-level driver code. The driver code includes ADC / DAC controller logic on the FPGA side, data acquisition and conversion logic, and PS side - PL side control mechanism; S2. Board Support Package development: Create an HDL Coder board support package for the ZYNQ platform, including hardware interface definitions, Simulink code generation templates, and optimization configurations; S3. Motor model construction: Establish the electrical and mechanical models of the motor in Simulink; S4. Model intelligent segmentation: Divide the model into non-real-time modules deployed on the PS side and real-time modules deployed on the PL side according to real-time requirements; S5. Code automatic generation: Generate PS side C code through Simulink Coder and call the board support package in step S2; Generate PL side HDL code through HDL Coder; S6. FPGA logic implementation: Use the Xilinx Vivado IDE to complete the timing optimization, synthesis, and routing of the HDL code, and optimize the execution logic and timing to generate a bitstream; S7. Real-time Linux system customization: Integrate the Xenomai real-time kernel on the basis of the Linux kernel based on the Petalinux tool, configure the device tree, and generate a boot image; S8. System deployment and testing: Burn the boot image into the memory card, verify the startup and hardware recognition of the Petalinux system on the ZYNQ platform, and test the communication function between the PS side and the PL side; S9. Hardware connection: Connect the motor controller to the ZYNQ platform through the input and output interfaces developed in step S1; S10. Software deployment and operation: After compiling the C code generated in step S5, transfer the executable file to the PS side and run it; S11. Parameter adjustment and data monitoring: Connect to the PS side through the external mode of Simulink using the XCP protocol, adjust the motor model parameters in real time, and monitor the simulation data; S12. Controller debugging and optimization: Adjust the controller parameters according to the simulation data, evaluate the control performance, and iteratively optimize the control strategy. Record the optimized parameter configuration for actual motor deployment.

[0009] As a further preferred solution of the present invention, the hardware interface development in step S1 further includes: designing ADC / DAC controller logic supporting SPI / I2C interfaces; developing a driver program and a register mapping mechanism to implement the control of the PL side hardware interface by the PS side.

[0010] As a further preferred embodiment of the present invention, the criteria for intelligent segmentation of the model in step S4 include: allocating modules with a calculation frequency higher than 10 kHz to the PL side; deploying algorithms with parallel computing characteristics to the PL side; and allocating modules that require online parameter adjustment to the PS side.

[0011] As a further preferred embodiment of the present invention, the customization of the real-time Linux system in step S7 includes: tailoring the Linux kernel according to actual requirements and removing unnecessary components; configuring the device tree to ensure correct hardware recognition; and creating a boot image, including the kernel, device tree, and file system.

[0012] As a further preferred embodiment of the present invention, step S9 includes configuring the PWM output, ADC interface, DAC output, and signal conditioning circuit.

[0013] As a further preferred embodiment of the present invention, step S10 includes configuring the compilation environment and cross-compilation toolchain, generating an executable file for the ARM architecture and transferring it to the ZYNQ platform, and configuring the XCP daemon to achieve self-start of the simulation software.

[0014] Compared with the prior art, the present invention provides a motor simulation method based on ZYNQ, having the following beneficial effects: The present invention provides a motor simulation method based on the ZYNQ platform. This method makes full use of the ARM+FPGA heterogeneous architecture characteristics of ZYNQ, intelligently segments and deploys the motor simulation model, and constructs a complete solution from model design to code generation, deployment, and debugging based on the real-time Linux system. This method has the characteristics of strong versatility, easy use, and low cost. It can quickly build a motor model according to the electrical characteristics of the motor, and generate code suitable for different computing resources through code generation technology to achieve efficient hardware-in-the-loop simulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic diagram of the implementation framework of the present invention; Figure 2 is a schematic diagram of the embodiment framework of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] If there are descriptions involving "first", "second", etc. in the embodiments of the present invention, such descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features.

[0017] If "and / or" or "and / or" appears throughout the text, its meaning includes three parallel solutions. Taking "A and / or B" as an example, it includes solution A, solution B, or a solution that satisfies both A and B simultaneously.

[0018] In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0019] Explanation of key terms: 1. Hardware-in-the-Loop Simulation (HIL) A real-time simulation technology that combines actual hardware (such as a controller) with a simulation model to verify the performance of the hardware in a virtual environment. It is commonly used for testing and verifying complex systems and can verify the performance of a control system without using the actual controlled object.

[0020] 2. FPGA (Field-Programmable Gate Array) A programmable logic device that users can configure its internal logic circuit according to requirements and is suitable for scenarios such as parallel computing and signal processing.

[0021] 3. ZYNQ An SoC (System on Chip) launched by Xilinx, integrating an ARM processor and an FPGA, suitable for high-performance embedded systems. The ZYNQ platform provides two parts: PS (Processing System, based on the ARM processor) and PL (Programmable Logic, based on the FPGA), which are interconnected through a high-performance AXI4 bus.

[0022] 4. Xilinx A globally leading supplier of FPGAs and programmable logic devices, providing a variety of hardware and software solutions, including the ZYNQ series of SoC platforms.

[0023] 5. Xilinx Vivado IDE An integrated development environment developed by Xilinx for the design, simulation, and debugging of FPGAs and SoCs, supporting the complete development process from RTL design to bitstream generation.

[0024] 6. Verilog A hardware description language (HDL) used for designing and simulating digital circuits and is one of the main languages for implementing FPGA logic.

[0025] 7. XCP (Universal Measurement and Calibration Protocol) A communication protocol for automotive electronic systems, which supports real-time data acquisition and parameter calibration, and is used in the present invention to implement the communication between Simulink external mode and ZYNQ platform.

[0026] 8.Petalinux An embedded Linux development tool provided by Xilinx, which supports building and customizing Linux systems on platforms such as ZYNQ, and simplifies the development process of embedded Linux systems.

[0027] 9.Xenomai A real-time Linux extension framework that provides hard real-time performance, is suitable for scenarios with high real-time requirements such as industrial control, and supports microsecond-level response of real-time tasks.

[0028] 10.Simulink Coder A MATLAB tool for converting Simulink models into C code, suitable for embedded system development, and capable of generating code optimized for specific hardware platforms.

[0029] 11.Simulink HDL Coder A MATLAB tool for converting Simulink models into hardware description languages (such as Verilog or VHDL), suitable for FPGA and ASIC designs, and supports the rapid implementation of hardware-accelerated algorithms.

[0030] 12.AXI4 bus A high-performance bus protocol defined by ARM, which is part of the AMBA (Advanced Microcontroller Bus Architecture) specification, and is used for efficient data transfer between PS and PL in the ZYNQ platform.

[0031] Refer to Figure 1-2 , the present invention realizes motor simulation based on ZYNQ through the following steps: Step 1: Hardware interface development According to the requirements of the input and output signals of the simulation object motor, build input and output hardware interfaces including ADC (Analog to Digital Converter) and DAC (Digital to Analog Converter) on the PL side of ZYNQ, and write the underlying driver code. Specifically, it includes: 1.1 Design the ADC / DAC controller logic on the FPGA side, supporting standard interfaces such as SPI / I2C; 1.2 Implement data acquisition and conversion logic to ensure that the signal conversion accuracy and rate meet the simulation requirements; 1.3 Develop driver programs and register mapping mechanisms to achieve the control of the hardware interface on the PS side to the PL side.

[0032] Step 2: Develop the board support package Develop the HDL Coder board support package for the ZYNQ platform by combining software and hardware resources. Specifically include: 2.1 Define the hardware interface and board-level configuration information; 2.2 Develop the Simulink board-level custom code generation template; 2.3 Configure the code generation options and optimization strategies; 2.4 Complete the testing and verification of the board support package.

[0033] Step 3: Establish the motor model Build a Simulink model according to the mathematical model of the motor, the simulation object. Specifically include: 3.1 Establish the electrical model of the motor, including the stator, rotor circuits, and electromagnetic relationships; 3.2 Establish the mechanical model, including the moment of inertia, frictional torque, etc.

[0034] Step 4: Intelligent model segmentation Divide the model into two parts according to the real-time requirements: Parts with relatively low real-time requirements (such as the motor parameter input interface, data monitoring module, etc.) will be deployed on the PS side; parts with high real-time requirements (such as the core electromagnetic and mechanical models of the motor, high-frequency PWM signal processing, etc.) will be deployed on the PL side.

[0035] The specific criteria for model segmentation include: 4.1 Calculate the frequency requirements: Computational tasks higher than 10 kHz are preferentially assigned to the PL side; 4.2 Parallel computing characteristics: Algorithms with high parallelism are preferentially assigned to the PL side; 4.3 Data interaction frequency: The data interaction frequency between the PS and the PL should be minimized to reduce communication overhead; 4.4 Parameter adjustment requirements: Parameter modules that need to be frequently adjusted online are preferentially assigned to the PS side.

[0036] Step 5: Automatic code generation 5.1 Use Simulink Coder to generate C code for the PS side, calling the board support package in Step 2; 5.2 Use HDL Coder to generate optimized HDL code for the PL side; Step 6: FPGA logic implementation Implement the synthesis and implementation of the generated HDL code using the Xilinx Vivado IDE: 6.1 Import the HDL code and configure the constraint file; 6.2 Execute logic synthesis and optimization; 6.3 Conduct timing analysis and constraints to ensure that the design meets the real-time requirements; 6.4 Generate the bitstream and export the hardware description file including the bitstream.

[0037] Step Seven: Customize the Real-Time Linux System Use the Petalinux toolkit provided by Xilinx to customize the Linux system according to the actual hardware configuration of the ZYNQ hardware platform: 7.1 Create a Petalinux project based on the hardware description file; 7.2 Trim the Linux kernel according to the application requirements to reduce unnecessary components; 7.3 Import the Xenomai real-time kernel patch and configure the real-time related parameters; 7.4 Configure the device tree to ensure correct hardware recognition; 7.5 Create a boot image including the kernel, device tree and file system.

[0038] Step Eight: System Deployment and Testing Burn the boot image into the TF card and test whether the Petalinux system can run normally on the simulation platform: 8.1 Verify system startup and hardware recognition; 8.2 Test the real-time performance and confirm that the Xenomai kernel works properly; 8.3 Verify the I / O interface function; 8.4 Test the communication between the PS and the PL.

[0039] Step Nine: Hardware Connection Connect the motor controller to the simulation platform through the input / output interface developed in Step One: 9.1 Connect the PWM output of the controller to the ADC interface of the simulation platform; 9.2 Connect the DAC output of the simulation platform to the feedback signal input of the controller; 9.3 Configure the signal conditioning circuit to ensure signal level and timing matching.

[0040] Step Ten: Software Deployment and Operation After compiling the C code generated in Step Five, transfer the executable file to the PS side and run it: 10.1 Configure the compilation environment and the cross-compilation toolchain; 10.2 Compile and generate an executable file suitable for the ARM architecture; 10.3 Transmit the executable file to the ZYNQ platform through the network or storage device; 10.4 Configure the XCP daemon to achieve self - startup of the simulation software.

[0041] Step Eleven: Parameter Adjustment and Data Monitoring Connect to the PS side through the external mode of Simulink using the XCP protocol: 11.1 Establish a network connection between the host and the simulation platform; 11.2 Configure the Simulink external mode parameters, specifying the XCP protocol and communication ports; 11.3 Establish a connection and verify the communication status; 11.4 Real - time change the motor model parameters through the Simulink interface; 11.5 Read and display the key data during the simulation process.

[0042] Step Twelve: Controller Debugging and Optimization Adjust the motor controller parameters according to the data read in Step Eleven: 12.1 Analyze the simulation data and evaluate the control performance; 12.2 Adjust the controller parameters according to the analysis results; 12.3 Observe the adjustment results in real - time and iteratively optimize the control strategy; Record the optimal parameter configuration for actual system deployment.

[0043] As a specific embodiment of the present invention: Take the simulation of a permanent magnet synchronous motor (PMSM) as an example Hardware platform: Xilinx ZYNQ - 7020 SoC; Interface configuration: 8 - channel 16 - bit ADC and 8 - channel 16 - bit DAC; Motor model: Parameterized PMSM model, supporting parameter configurations such as different pole pairs, stator resistance / inductance, permanent magnet flux linkage, etc.; Simulation step size: The simulation step size of the core model on the PL side is 100 μs, and the update period of the parameter interface on the PS side is 1 ms.

[0044] The implementation principle is as follows: 1. Optimization of the heterogeneous computing architecture based on the ZYNQ platform Using the ARM+FPGA heterogeneous architecture of ZYNQ, the motor simulation model is segmented according to real-time requirements. The parameter transfer and data monitoring module with low real-time requirements is deployed on the PS side, and the core computing model with high real-time requirements is deployed on the PL side, giving full play to the flexibility of the ARM processor and the parallel computing power of the FPGA.

[0045] 2. Model-based Automatic Code Generation and Deployment Method Combining Simulink Coder and HDL Coder technologies with the ZYNQ platform, the automatic generation and deployment from the unified motor model to the C code on the PS side and the HDL code on the PL side are realized, significantly improving the development efficiency and reducing the development difficulty.

[0046] 3. Construction Method of Embedded Linux Platform with Enhanced Real-time Performance A technical solution of tailoring the Linux kernel based on the Petalinux toolkit and integrating the Xenomai real-time kernel is proposed to construct an embedded Linux platform with both versatility and real-time performance, solving the problem of inconvenient development and debugging of traditional bare-metal development.

[0047] 4. High-efficiency Data Interaction Mechanism for Hardware and Software Collaboration Utilizing the AXI4 bus of the ZYNQ platform to achieve high-efficiency data interaction between the PS side and the PL side, avoiding the complex high-speed interface development in the traditional X86 CPU + FPGA architecture, reducing the system complexity and cost, and realizing the tight coupling of hardware and software collaboration.

[0048] 5. Real-time Parameter Adjustment and Monitoring Method Based on XCP Protocol Applying the XCP protocol in combination with the Simulink external mode to the field of motor simulation, the real-time adjustment of model parameters and data monitoring are realized, providing a friendly user interface and interaction method, and significantly improving the debugging efficiency.

[0049] The method provided by the present invention is applicable to various motor types and control algorithms, can quickly build a simulation model according to the electrical characteristics of the motor, and supports the general simulation of different types of motors such as permanent magnet synchronous motors, induction motors, and DC motors.

[0050] High real-time performance: Through the heterogeneous computing architecture of the ZYNQ platform, combined with the Xenomai real-time kernel and FPGA hardware acceleration, the present invention can achieve a simulation step size and response delay in the microsecond level, meet the strict real-time requirements of high-precision motor control systems, and is applicable to industrial control scenarios with strict real-time requirements.

[0051] High development efficiency: Based on model-based design and automatic code generation technology, the present invention significantly shortens the development cycle and reduces the development difficulty, enabling users to focus on the motor model itself without having to pay excessive attention to the underlying implementation details.

[0052] Low cost: Adopting the ZYNQ single-chip solution avoids the high cost and complex interface development of the traditional X86 CPU + FPGA architecture, and is suitable for small and medium-sized enterprises and research institutions.

[0053] Convenient debugging: Connected to the PS side of the ZYNQ simulation platform through the XCP protocol in Simulink external mode, it can adjust parameters in real time and monitor simulation data, significantly improving the debugging efficiency.

[0054] Good scalability: The modular design and standardized interfaces make the system easy to expand and upgrade, and support the rapid integration of motor models and control algorithms.

[0055] High integration: Integrating functions such as motor models, data acquisition, signal processing, and human-machine interaction on a single ZYNQ chip reduces the system volume, improves reliability, and is convenient for laboratory and field applications.

[0056] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention accordingly. Any equivalent structural transformation made under the inventive concept of the present invention by using the content of the specification and drawings of the present invention, or direct / indirect application in other related technical fields, is included in the patent protection scope of the present invention.

Claims

1. A motor simulation method based on ZYNQ, characterized in that It includes the following steps: S1. Hardware interface development: Build input and output interfaces including ADC and DAC on the PL side of ZYNQ, and write low-level driver code. The driver code includes ADC / DAC controller logic on the FPGA side, data acquisition and conversion logic, and PS side - PL side control mechanism; S2. Board Support Package development: Create an HDL Coder board support package for the ZYNQ platform, including hardware interface definitions, Simulink code generation templates, and optimization configurations; S3. Motor model construction: Establish the electrical model and mechanical model of the motor in Simulink; S4. Model intelligent segmentation: Divide the model into non-real-time modules deployed on the PS side and real-time modules deployed on the PL side according to real-time requirements; S5. Automatic code generation: Generate PS side C code through Simulink Coder and call the board support package in step S2; Generate PL side HDL code through HDL Coder; S6. FPGA logic implementation: Use the Xilinx Vivado IDE to complete the timing optimization, synthesis, and routing of the HDL code, and optimize the execution logic and timing to generate the bitstream; S7. Real-time Linux system customization: Integrate the Xenomai real-time kernel on the basis of the Linux kernel based on the Petalinux tool, configure the device tree, and generate the boot image; S8. System deployment and testing: Burn the boot image into the memory card, verify the startup and hardware recognition of the Petalinux system on the ZYNQ platform, and test the communication function between the PS side and the PL side; S9. Hardware connection: Connect the motor controller to the ZYNQ platform through the input and output interfaces developed in step S1; S10. Software deployment and operation: After compiling the C code generated in step S5, transfer the executable file to the PS side and run it; S11. Parameter adjustment and data monitoring: Connect to the PS side through the external mode of Simulink with the XCP protocol, adjust the motor model parameters in real time, and monitor the simulation data; S12. Controller debugging and optimization: Adjust the controller parameters according to the simulation data, evaluate the control performance, and iteratively optimize the control strategy, and record the optimized parameter configuration for actual motor deployment.

2. The ZYNQ-based motor simulation method according to claim 1, wherein The hardware interface development in step S1 further includes: Designing ADC / DAC controller logic that supports SPI / I2C interfaces; Developing driver programs and register mapping mechanisms to achieve the control of the PL side hardware interface by the PS side.

3. The ZYNQ-based motor simulation method according to claim 1, wherein The criteria for model intelligent segmentation in step S4 include: Allocating modules with a computing frequency higher than 10 kHz to the PL side; Deploying algorithms with parallel computing characteristics to the PL side; Allocating modules that require online parameter adjustment to the PS side.

4. The ZYNQ-based motor simulation method according to claim 1, wherein The real-time Linux system customization in step S7 includes: Tailoring the Linux kernel according to actual needs and removing unnecessary components; Importing the Xenomai real-time kernel patch and configuring real-time parameters; Configuring the device tree to ensure correct hardware recognition; Creating a boot image including the kernel, device tree, and file system.

5. The ZYNQ-based motor simulation method according to claim 1, wherein The step S9 includes configuring PWM output, ADC interface, DAC output and signal conditioning circuit.

6. The ZYNQ-based motor simulation method according to claim 1, wherein The step S10 includes configuring the compilation environment and cross-compilation tool chain, generating an executable file for the ARM architecture and transmitting it to the ZYNQ platform, and configuring the XCP daemon process to achieve self-start of the simulation software.

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