Underwater wireless optical communication system based on pulse position modulation technology

Abstract

The invention discloses an underwater wireless optical communication system based on a pulse position modulation technology, and a transmitting module of the underwater wireless optical communication system comprises a transmitting end FPGA used for modulating target data into digital pulse signals; the driving modulation circuit is used for converting the digital pulse signal into a modulation current signal for controlling a light source; the light source module is used for generating a light signal based on the modulation current signal; the receiving module comprises an optical module used for performing power attenuation and stray light filtering on an optical signal; the photoelectric detector is used for performing photoelectric conversion and amplification on the optical signal to obtain an analog electric signal; the analog-to-digital conversion and pulse shaping circuit is used for performing analog-to-digital conversion and pulse shaping on the analog electric signal to obtain a digital signal; and the receiving end FPGA is used for performing bit synchronization, frame synchronization and demodulation on the digital signal to obtain demodulation data. By adopting the pulse position modulation technology, the FPGA design and the compact modular structure, the purposes of low power consumption, miniaturization and real-time information transmission are achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of underwater wireless optical communication, and particularly relates to an underwater wireless optical communication system based on pulse position modulation technology. Background Art

[0002] With the exploration of the ocean environment by humans, the demands in the fields of ocean resource development, environmental detection, and national defense security have grown rapidly, generating more requirements for underwater environmental information interaction technologies. In particular, the construction of underwater sensor networks and autonomous underwater vehicle devices rely heavily on real-time information interaction.

[0003] Currently, there are three relatively mature underwater information interaction methods: underwater acoustic communication, electromagnetic wave communication, and underwater optical cables. Underwater acoustic communication has high device power consumption, large volume, low transmission rate, poor security, and can affect marine mammals. The transmission distance of electromagnetic wave communication underwater is only a few meters, and the huge cost and inflexibility of underwater optical cables limit their applicable scenarios. Underwater wireless optical communication (UWOC) technology has become a popular research direction for underwater real-time information interaction methods. The deployment and application of UWOC networks require practical optical transmitter and receiver solutions with high performance, low cost, and high reliability.

[0004] However, water has strong absorption and scattering characteristics for light. This results in a significant decrease in optical power as the communication distance increases, even in the blue-green light band, and the communication range usually does not exceed 200 meters. Therefore, existing research has made various attempts in aspects such as light sources, photodetectors, and modulation and coding methods, attempting to increase the communication distance and rate while reducing the communication error rate, optical power, and cost.

[0005] Light sources are a current research hotspot in underwater optical communication, and their performance determines the transmission rate and distance of UWOC systems. Light-emitting diodes (LEDs) and laser diodes (LDs) are the most widely used light sources. Photoelectric detectors are the core devices of receivers, and their sensitivity and photosensitive area affect the transmission rate and alignment difficulty of the system. Existing research on the improvement of photoelectric detectors allows for more types of light source selections and hardware solutions. Existing research selects LD as the light source and photomultiplier tubes (PMTs) as the photoelectric detector, and constructs a communication system with a communication distance of up to 120 m, a bit error rate of 6.31×10-4, and a communication rate of 0.06 Mbps in a water environment with an attenuation length of 35.88. Existing research uses a self-designed LED as the light source, which has a larger bandwidth than ordinary LEDs. While reducing the alignment difficulty, it also has a modulation bandwidth as high as 500 MHz comparable to that of LD, achieving 2 m of underwater data transmission with a communication rate of 3.8 Gbit / s. Existing research verifies the possibility of short pulses in optical communication in a 7 m water tank. Using pulse position modulation (PPM), a 64PPM / 150 Mbps UWOC system is achieved, with a bit error rate of 2.8×10-4, an average optical power of the transmitter of 4.483 dBm, and a 3dB pulse width of 200 ps. Existing research uses a method based on photon counting and discriminator, with a 15 mW blue LD as the light source and a high-sensitivity PMT as the photon counting device, demonstrating 35.64 m of 32-PPM modulated medium and long-distance underwater communication, with an average number of received photons per bit of only 0.34, verifying the feasibility of a low-power optical communication scheme.

[0006] As can be seen from the above existing research, the implementation methods of underwater wireless optical communication systems show diversity, and their overall performance is significantly affected by the collaborative design of each module from the optical transmitter to the receiver. However, the applicant has found that existing technologies and theoretical verifications mostly rely on arbitrary waveform generators and computer-aided platforms, and there are generally problems such as too high a proportion of offline operations and strong hardware dependence (such as high-cost modulation equipment) in the signal processing link, and there are still deficiencies in low-power real-time processing, miniaturized system integration, and engineering practicality. Summary of the Invention

[0007] Aiming at the deficiencies of the above-mentioned existing technologies, the technical problem to be solved by the present invention is: how to provide an underwater wireless optical communication system based on pulse position modulation technology, which realizes the goals of low power consumption, miniaturization and real-time information transmission by adopting pulse position modulation technology, FPGA design and a compact modular structure, and provides a new solution idea for the field of underwater wireless communication.

[0008] To solve the above technical problems, the present invention adopts the following technical solutions:

[0009] An underwater wireless optical communication system based on pulse position modulation technology, comprising a transmitting module and a receiving module;

[0010] The transmitting module includes:

[0011] A transmitting end FPGA, configured to receive target data to be transmitted and modulate the target data into a digital pulse signal based on pulse position modulation;

[0012] A driving and modulating circuit, configured to convert the digital pulse signal output by the transmitting end FPGA into a modulating current signal for controlling a light source and drive the light source to emit light;

[0013] A light source module, configured to generate a corresponding optical signal based on the modulating current signal generated by the driving and modulating circuit to complete electro-optical conversion, and collimate and focus the optical signal and then transmit it to an underwater channel;

[0014] The receiving module includes:

[0015] An optical module, configured to receive the optical signal transmitted through the underwater channel and perform power attenuation and stray light filtering on the optical signal;

[0016] A photodetector, configured to perform photoelectric conversion and amplification on the optical signal output by the optical module to obtain an analog electrical signal;

[0017] An analog-to-digital conversion and pulse shaping circuit, configured to perform analog-to-digital conversion and pulse shaping on the analog electrical signal output by the photodetector to obtain a digital signal;

[0018] A receiving end FPGA, configured to perform bit synchronization, frame synchronization and demodulation on the digital signal output by the analog-to-digital conversion and pulse shaping circuit based on clock data recovery, frame detection and pulse position demodulation to obtain demodulated data, and send it to a terminal device through a serial port.

[0019] Preferably, the transmitting end FPGA includes:

[0020] A transmitting end top-level module, configured to switch the states of the top-level module state machine and the coding module state machine;

[0021] Wherein:

[0022] The states of the top-level module state machine include an idle state, a storage state, a transmission state, and a termination state;

[0023] The states of the encoding module state machine include IDEL, SOF, DATA, and EOF;

[0024] A serial-to-parallel conversion module is used to convert the target data of serial eight-bit binary into parallel data and temporarily store it in a register;

[0025] Where:

[0026] When the data conversion is completed, the top-level module state machine is converted from the idle state to the storage state, and order is set to SOF; otherwise, order is set to IDEL, where order is used to control the generation of data frames;

[0027] A data storage module is used to write the parallel data temporarily stored in the register into the memory when the top-level module state machine is converted from the idle state to the storage state;

[0028] Where:

[0029] A counter is used to count the writes to the memory. When the value of the counter reaches the set value, it indicates that the data storage is completed, the writing stops, the top-level module state machine is converted from the storage state to the transmission state, and the data in the memory is sent to the input end of the PPM modulation module; order is set to DATA;

[0030] When the data transmission is completed, the top-level module state machine is converted from the transmission state to the termination state; order is set to EOF;

[0031] A PPM modulation and data framing module is used to perform PPM modulation on the received data and generate and send a PPM data frame to obtain a digital pulse signal including a frame header, a data segment, and a frame tail.

[0032] Preferably, the processing steps of the PPM modulation and data framing module include:

[0033] S01: When the data sent by the memory is read at the input end of the PPM modulation module, a right shift mask operation is used to sequentially extract two-bit data selected_data from the low bit to the high bit;

[0034] S02: Define two pulse transition times, namely data_0 and data_1, where data_0 is used to represent the position where the pulse is generated, and data_1 is used to represent the duration and recovery time of the pulse;

[0035] S03: Calculate the positions data_0 and data_1 of the two pulses according to the extracted two-bit data selected_data;

[0036] S04: Output data frames according to the states of the encoding module state machine, count based on the counter Clk_cnt, and set the high and low levels of the data frames according to the value of Clk_cnt:

[0037] 1) When order = IDLE, set the output result to 1, keep it at a high level, without pulse signals, and wait for the generation of the frame header;

[0038] 2) When order = SOF, according to the count value of Clk_cnt, set the output to 1 or 0 at specific positions to generate a specific frame header sequence;

[0039] 3) When order = DATA, compare the count value of Clk_cnt with data_0 and data_1. When Clk_cnt = data_0, set the output to 0 and start generating data pulses. When Clk_cnt = data_1, stop generating data pulses and set the output to 1, thus completing the pulse position mapping and generating a data segment sequence;

[0040] 4) When order = EOF, according to the count value of Clk_cnt, set the output to 1 or 0 at specific positions to generate a specific frame tail sequence;

[0041] S05: Combine the generated frame header sequence, data segment sequence, and frame tail sequence to obtain a digital pulse signal containing all the information of one frame of data.

[0042] Preferably, the receiving - end FPGA includes:

[0043] The receiving - end top - level module, which is used to coordinate the work of each module;

[0044] The clock data recovery module, which is used to sample the input digital signal at different clock edges, determine the edge positions of the data, and recover the synchronous clock signal and data signal;

[0045] The PPM decoding module, which is used to convert the data signal recovered by the clock data recovery module into eight - bit parallel data, and perform frame synchronization and demodulation on the eight - bit parallel data to obtain the demodulated data;

[0046] The serial port sending module, which is used to send the demodulated data through the UART.

[0047] Preferably, the processing steps of the receiving - end FPGA include:

[0048] S11: After the top-level module at the receiving end converts the digital signal output by the analog-to-digital conversion and pulse shaping circuit into a single-ended signal OUT, it uses this as the input ser_in of the clock and data recovery module. At the same time, it uses a phase-locked loop IP core to generate two clock signals clk_0 and clk_90 with the same frequency but different phases, and uses these as the sampling clocks of the clock and data recovery module;

[0049] S12: The clock and data recovery module processes ser_in using the rising and falling edges of clk_0 and clk_90, and outputs the recovered synchronous clock signal ser_clk and data signal ser_out, which are used as the clock signal clk and input data Din of the PPM decoding module;

[0050] S13: Define three states of the decoding state machine: IDEL, WAIT, DECODE;

[0051] S14: The PPM decoding module performs frame header detection and PPM decoding on Din under the drive of clk:

[0052] 1) In the IDEL state, detect whether there is a falling edge in the input data Din data stream. When a falling edge is detected, switch from the idle state to the WAIT state;

[0053] 2) In the WAIT state, accurately detect the frame start signal through the frame detection flag bit, and make a detailed judgment in different clock cycles according to the input level to ensure correct detection of the frame header generation state. After detecting the frame header generation state, switch from the WAIT state to the DECODE state, otherwise return to IDEL;

[0054] 3) In the DECODE state, divide 128 clock cycles into 8 time slots, each time slot contains 1 low level and 7 high levels, and perform the inverse operation of encoding on the detected data to recover the eight-bit parallel data;

[0055] S14: Use the recovered eight-bit parallel data as the demodulated data.

[0056] Preferably, the serial port sending module uses the demodulated data and enable signal output by the PPM decoding module as the input data and data enable signal; when the data enable signal is valid, send the input data through the UART and output the UART sending signal.

[0057] Preferably, the light source module includes a blue laser diode as the light source, a collimating lens for collimating the optical signal emitted by the blue laser diode, and a heat dissipation module for ensuring the stable operation of the blue laser diode.

[0058] Preferably, the optical module includes a blue light band filter and a Fresnel lens that sequentially process the received optical signal, and a cassette is used to cover the blue light band filter and the Fresnel lens to achieve light shielding; wherein, the blue light band filter is used to filter out stray light; the Fresnel lens is used to increase the signal receiving area while achieving a light concentrating effect.

[0059] Preferably, the photodetector is a multi-photon counter, and a cassette is used to cover the multi-photon counter to achieve light shielding;

[0060] The pixel unit of the multi-photon counter receives the optical signal transmitted by the optical module, and performs photoelectric conversion and amplification on the optical signal to obtain an analog electrical signal.

[0061] Preferably, the analog-to-digital conversion and pulse shaping circuit uses two-stage comparators to perform analog-to-digital conversion and pulse shaping on the analog electrical signal;

[0062] The analog electrical signal output by the photodetector is input to the non-inverting input terminal of the first-stage comparator, and a comparison voltage is set at the inverting input terminal. A low-voltage differential signal is output through the first-stage comparator; the low-voltage differential signal output by the first-stage comparator is input to the non-inverting input terminal of the second-stage comparator, and a threshold voltage is connected to the inverting input terminal. A digital signal that meets the electrical standard of the low-voltage differential signal is output through the second-stage comparator.

[0063] Compared with the prior art, the underwater wireless optical communication system based on pulse position modulation technology in the present invention has the following beneficial effects:

[0064] In response to the urgent needs of underwater wireless optical communication for low power consumption, miniaturized devices, and real-time information transmission, the present invention proposes an underwater real-time wireless optical communication solution that combines pulse position modulation and synchronization technology based on a field programmable gate array (FPGA), and designs a low-cost, miniaturized, and low-power underwater blue light wireless communication system.

[0065] The FPGA at the transmitting end of the transmitting module uses Pulse Position Modulation (PPM) technology to modulate data. It can significantly reduce energy consumption while maintaining a high data transmission rate. The PPM technology represents different data information by adjusting the position of pulses on the time axis. Compared with other modulation methods, it has higher energy efficiency. Especially in the underwater environment where the optical signal attenuation is large, it can effectively extend the battery life of the device. The generated high-frequency modulation signal is loaded onto a 450nm semiconductor laser through a high-frequency laser drive circuit. The light source in this band has relatively good penetrability and a small volume, making it suitable for the application of miniaturized devices. Combined with the design of a heat dissipation module and a collimating lens, the working time and communication distance of the system are effectively extended. The receiving module of the system uses an attenuation sheet to simulate the far-distance optical power attenuation. The optoelectronic conversion module selects a Multi pixel photon counter (MPPC) to complete optoelectronic conversion and achieve high-sensitivity detection. The analog-to-digital conversion and pulse shaping circuit digitally processes and shapes the rising and falling edges of the analog signal output by the MPPC through a dual-channel high-speed rail-to-rail input comparator. Both the transmitting end and the receiving end of the system are designed using Field Programmable Gate Arrays (FPGA). The high integration and programmability of the FPGA enable the system to be flexibly configured, optimize power management according to actual needs, and further reduce the overall energy consumption.

[0066] Meanwhile, the FPGA at the transmitting end completes data preprocessing through protocol parsing, serial-to-parallel conversion, and caching mechanisms, and generates digital pulse signals using a fourth-order pulse position modulation algorithm, ensuring the fast processing and accurate modulation of data, providing a basis for real-time transmission. The FPGA at the receiving end performs bit synchronization, frame synchronization, and data demodulation on the received digital signals through a clock data recovery algorithm based on the oversampling principle, effectively improving the accuracy and stability of data demodulation, and ensuring the real-time and reliability of information. The overall design of the system takes into account the characteristics of the underwater channel, such as power attenuation and stray light interference. Through the power attenuation and stray light filtering functions of the optical module, as well as the optoelectronic conversion and amplification functions of the photodetector, the effective reception and conversion of optical signals are ensured, further guaranteeing the quality of real-time information transmission. The experimental results show that the system of the present invention can achieve real-time communication with a low bit error rate (<10 -1 to 0.85m -1 ) under the condition of a high-loss cross-media link with a transmission power of 36.32mW, a rate of 512Kbps, and a transmission distance of 25 meters. -4 ) BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to make the objectives, technical solutions, and advantages of the invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings, where:

[0068] Figure 1It is the system block diagram of an underwater wireless optical communication system.

[0069] Figure 2 It is the symbol diagram of pulse position modulation.

[0070] Figure 3 It is the state machine of the transmitting module: Figure 3 (a) is the state machine of the top-level module, Figure 3 (b) is the state machine of the encoding module.

[0071] Figure 4 It is the frame structure diagram of pulse position modulation.

[0072] Figure 5 It is the timing diagram of bit synchronization simulation.

[0073] Figure 6 It is the characteristic diagram of the laser: Figure 6 (a) is the LIV curve of the laser, Figure 6 (b) is the spectral curve.

[0074] Figure 7 It is the design and spot test of the transmitter: Figure 7 (a) is the laser and the heat dissipation metal column, Figure 7 (b) is the adjustable focusing lens, Figure 7 (c) is the heat dissipation structure of the laser, Figure 7 (d) is the unfocused spot of the laser, Figure 7 (e) is the focusing effect diagram of the laser, Figure 7 (f) is the schematic diagram of the peripheral circuit of IC-HK.

[0075] Figure 8 It is the output waveform diagram of the FPGA and MPPC modules: Figure 8 (a) is the modulated signal output by the FPGA, Figure 8 (b) is the signal output by the MPPC module.

[0076] Figure 9 It is the schematic diagram and PCB of the analog-to-digital conversion and pulse shaping circuit: Figure 9 (a) is the schematic diagram of the analog-to-digital conversion and pulse shaping circuit, Figure 9 (b) is the physical diagram of the analog-to-digital conversion and pulse shaping circuit.

[0077] Figure 10 It is the waveform diagram of the analog-to-digital conversion and pulse shaping module: Figure 10 (a) is the output voltage of the MPPC module, Figure 10 (b) is the output signal of the analog-to-digital conversion module, Figure 10 (c) is the output signal of the pulse shaping module, Figure 10 (d) is the voltage amplification of the MPPC module, Figure 10(e) Amplify the output signal of the analog-to-digital conversion module, Figure 10 (f) Amplify the output signal of the pulse shaping module.

[0078] Figure 11 Build an optical power test and experimental platform: Figure 11 (a) The system experimental test platform, Figure 11 (b) The propagation diagram of light in the underwater channel, Figure 11 (c) The attenuation of the 450nm blue light power with the underwater distance.

[0079] Figure 12 (a) The change of the bit error rate of the UWOC system with distance under different modulation widths; Figure 12 (b) The bit error rate of the UWOC system at 25 meters under different counting widths. Specific implementation manners

[0080] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. Usually, the components of the embodiments of the present invention described and illustrated herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0081] It should be noted that similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the inventive product is usually placed during use. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention. In addition, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and cannot be construed as indicating or implying relative importance. In addition, terms such as "horizontal" and "vertical" do not mean that the components are required to be absolutely horizontal or hanging vertically, but can be slightly inclined. For example, "horizontal" only means that its direction is more horizontal relative to "vertical", and does not mean that the structure must be completely horizontal, but can be slightly inclined. In the description of the present invention, it should also be noted that unless otherwise clearly specified and limited, the terms "set", "installed", "connected", "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0082] The following will be further described in detail through specific embodiments:

[0083] Embodiment:

[0084] In this embodiment, an underwater wireless optical communication system based on pulse position modulation technology is disclosed.

[0085] As Figure 1 shown, an underwater wireless optical communication system based on pulse position modulation technology includes a transmitting module, a receiving module, and a terminal device;

[0086] The transmitting module includes:

[0087] A transmitting end FPGA, configured to receive target data to be transmitted and modulate the target data into a digital pulse signal based on pulse position modulation (PPM);

[0088] In this embodiment, the transmitting - end FPGA is designed based on the Field Programmable Gate Array (FPGA). The transmitting - end FPGA completes data pre - processing through protocol parsing, serial - to - parallel conversion, and caching mechanisms, and then generates a digital pulse signal (pulse width 320 ns) using a fourth - order pulse - position modulation algorithm.

[0089] The driving and modulation circuit is used to convert the digital pulse signal output by the transmitting - end FPGA into a modulation current signal for controlling the light source and drive the light source to emit light. The digital signal output by the transmitting - end FPGA is transmitted to the driving and modulation circuit through a 3.3V TTL - level IO port via an SMA interface to drive the LD in the 450 - nm band to achieve stable optical power output in the milliwatt range.

[0090] The light - source module is used to generate a corresponding optical signal based on the modulation current signal generated by the driving and modulation circuit to complete electro - optical conversion, and collimate and focus the optical signal and then transmit it to the underwater channel.

[0091] The receiving module includes:

[0092] The optical module is used to receive the optical signal transmitted through the underwater channel and attenuate the power of the optical signal and filter out stray light.

[0093] The photodetector is used to perform photoelectric conversion and amplification on the optical signal output by the optical module to obtain an analog electrical signal.

[0094] The analog - to - digital conversion and pulse - shaping circuit is used to perform analog - to - digital conversion and pulse - shaping on the analog electrical signal output by the photodetector to obtain a digital signal.

[0095] The receiving - end FPGA is used to perform bit synchronization, frame synchronization, and demodulation on the digital signal output by the analog - to - digital conversion and pulse - shaping circuit based on clock data recovery, frame detection, and pulse - position demodulation to obtain demodulated data, and send it to the terminal device through a serial port. In this embodiment, the receiving - end FPGA is designed based on the Field Programmable Gate Array (FPGA).

[0096] The terminal device is used to receive the demodulated data output by the receiving - end FPGA.

[0097] In view of the urgent need for low - power, miniaturized devices, and real - time information transmission in underwater wireless optical communication, the present invention proposes an underwater real - time wireless optical communication scheme combining pulse - position modulation and synchronization technology based on the Field Programmable Gate Array (FPGA), and designs a low - cost, miniaturized, and low - power underwater blue - light wireless communication system.

[0098] The transmitting - end FPGA of the transmitting module uses pulse - position modulation (PPM) technology to modulate data. It can significantly reduce energy consumption while maintaining a high data - transmission rate. The PPM technology represents different data information by adjusting the position of pulses on the time axis. Compared with other modulation methods, it has higher energy efficiency. Especially in the underwater environment where the optical signal attenuation is large, it can effectively extend the battery life of the device. The generated high - frequency modulation signal is loaded onto a 450 - nm semiconductor laser through a high - frequency laser driving circuit. The light source in this wavelength band has relatively good penetrability and a small volume, which is suitable for the application of miniaturized devices. Combined with the design of a heat - dissipation module and a collimating lens, it effectively extends the system working time and communication distance. The receiving module of the system uses an attenuation sheet to simulate the far - distance optical - power attenuation. The optoelectronic conversion module selects a multi - pixel photon counter (MPPC) to complete optoelectronic conversion and achieve high - sensitivity detection. The analog - to - digital conversion and pulse - shaping circuit digitizes and shapes the analog signal output by the MPPC through a dual - channel high - speed rail - to - rail input comparator. Both the transmitting end and the receiving end of the system are designed with field - programmable gate arrays (FPGA). The high integration and programmability of the FPGA enable the system to be flexibly configured, optimize power management according to actual needs, and further reduce the overall energy consumption.

[0099] Meanwhile, the transmitting - end FPGA completes data pre - processing through protocol parsing, serial - to - parallel conversion, and caching mechanisms, and generates digital pulse signals using a fourth - order pulse - position modulation algorithm, ensuring fast data processing and accurate modulation, providing a basis for real - time transmission. The receiving - end FPGA performs bit synchronization, frame synchronization, and data demodulation on the received digital signals through a clock - data recovery algorithm based on the oversampling principle, effectively improving the accuracy and stability of data demodulation, and ensuring the real - time and reliability of information. The overall design of the system takes into account the characteristics of the underwater channel, such as power attenuation and stray - light interference. Through the power - attenuation and stray - light filtering functions of the optical module, as well as the optoelectronic conversion and amplification functions of the photodetector, it ensures the effective reception and conversion of optical signals, further guaranteeing the quality of real - time information transmission. Experimental results show that the system of the present invention can achieve real - time communication with a low bit - error rate (<10 -1 to 0.85 m -1 under the condition of a high - loss cross - medium link with a transmitting power of 36.32 mW, a rate of 512 Kbps, and a transmission distance of 25 m. -4 )

[0100] To better introduce the technical solution of the present invention, this embodiment is described through the following several parts.

[0101] I. PPM Modulation, Demodulation, and Synchronization Design

[0102] Pulse Position Modulation (PPM) is a unique modulation technique that achieves information transmission by changing the relative position of pulses. Different from traditional On / Off Key (OOK) and Pulse Width Modulation (PWM), during information transmission, PPM does not need to adjust the pulse width but only changes the pulse position. This characteristic enables an optical transmitter based on PPM modulation to transmit more information under the same energy consumption. In a power-limited system, PPM has a higher energy utilization rate. A lower radiation power is of great significance for extending the working life of the emission light source, thereby effectively increasing the usage duration of the entire system. The basic working principle of PPM is to convert an n-bit binary array into a single-pulse signal on a specific set of time slots within a time period composed of multiple time slots. During this process, the position of the single pulse carries the data information, thus completing the representation and transmission of data.

[0103] In this embodiment, Verilog HDL hardware description language is used in combination with the Vivado 2018.3 platform for FPGA development and design. As can be seen from the above discussion, PPM modulation based on FPGA is essentially a counting process, and corresponding levels are output according to different states and counting situations. First, it should be clear that compared with OOK modulation, PPM modulation has more stringent synchronization requirements. Therefore, the data frame needs to be divided into three parts (frame header, eight-bit data segment, frame tail) for design. Research shows that the higher the order of PPM modulation, the lower the average optical power of the system, but this is at the cost of sacrificing the bandwidth utilization rate. Considering comprehensively, this embodiment adopts a 4-PPM modulation method, that is, a period of time is divided into 4 time slots, and there is only one pulse signal in every 4 time slots to represent the data content, representing 00, 01, 10, 11 respectively. The specific implementation method is as Figure 2 shown.

[0104] The input from the host computer at the transmitting end to the FPGA via the serial port is an 8-bit binary signal. It is grouped into sets of 2 bits each using a right-shift masking operation, and data is extracted from the lowest two bits. This is achieved through a bit counter (bit_cnt), which gradually traverses each 2-bit segment in the eight-bit data. Since the system uses the UART protocol to communicate with the host computer, unlike previous PPM modulation, the high level of the PPM signal in this embodiment is the idle state, and the low level is the data pulse. Next is the calculation of the pulse position. First, two pulse transition times are defined, namely data_0 and data_1. Data_0 is used to represent the position where the pulse is generated, and data_1 is used to represent the duration and recovery time of the pulse. The clock counter (Clk_cnt) is used for time counting and synchronization. Based on a clock frequency of 50 MHz, it counts once every 20 ns. To avoid inter-symbol interference, the 4 time slots are further divided into 8 time slots, and the data obtained by multiplying data_0×2 + 1 by 16 is used to map the position of the pulse within a suitable time range, as Figure 2 shown. Such a design can map the possible results of the 2-bit input data into a suitable time window, thereby achieving PPM modulation. At the same time, according to the clock frequency and data transmission rate requirements of the system, the pulse position can also be conveniently adjusted and controlled to adapt to different communication needs. It helps to optimize the performance of data transmission, make full use of time resources, and at the same time meet the timing requirements of the system and the characteristics of PPM modulation.

[0105] In this embodiment, the transmitting-end FPGA includes a transmitting-end top module, a serial-to-parallel conversion module, a data storage module, and a PPM modulation module. In Figure 3 (a), the data flow in different states can be seen, and the state switching command (Order) of the encoding state machine is generated according to its state.

[0106] The transmitting-end top module is used to switch the states of the top-module state machine and the encoding-module state machine according to the states of other modules; among them:

[0107] The states of the top-module state machine include the idle state (S_IDEL), the storage state (SDRAM), the sending state (SEND), and the termination state (END);

[0108] The states of the encoding-module state machine include the idle state (IDEL), the start-of-frame generation state (SOF), the data generation state (DATA), and the end-of-frame generation state (EOF);

[0109] The serial-to-parallel conversion module (uart_rx module) is used to convert the serial eight-bit binary target data into parallel data and temporarily store it in a register;

[0110] Among them:

[0111] When the data conversion is completed, the data_ready signal is issued, the top-level module state machine is switched from the idle state to the storage state, order is set to the start-of-frame generation state (SOF), otherwise order is set to the idle state (IDEL), where order is used to control the generation of data frames.

[0112] The data storage module (ppm_memory module) is used to write the parallel data temporarily stored in the register into the memory when the top-level module state machine is switched from the idle state to the storage state.

[0113] Where:

[0114] A counter is used to count the writes to the memory. When the value of the counter reaches the set value, it indicates that the data storage is completed, the writing stops, the top-level module state machine is switched from the storage state to the transmission state, and the data in the memory is sent to the input end of the PPM modulation module from the specified address; order is set to the data generation state (DATA).

[0115] When the data transmission is completed, the top-level module state machine is switched from the transmission state to the termination state; order is set to EOF.

[0116] The PPM modulation and data framing module is used to perform PPM modulation on the received data and generate and send PPM data frames to obtain a digital pulse signal including a frame header, a data segment, and a frame tail.

[0117] The encoding state machine is as Figure 3 shown in (b). This state machine is divided into four states: idle state (IDEL), start-of-frame generation state (SOF), data generation state (DATA), and end-of-frame generation state (EOF). In the IDEL state, the output is set to 1; in the SOF state, according to the count value of Clk_cnt, the output is set to 1 or 0 to generate a specific frame header sequence; in the DATA state, the count value of Clk_cnt is compared with data_0 and data_1. When Clk_cnt = data_0, the output is set to 0 and the data pulse starts to be generated. When Clk_cnt = data_1, the data pulse stops being generated and the output is set to 1, thus completing the pulse position mapping; in the EOF state, according to the count value of Clk_cnt, the output is set to 1 or 0 to generate a specific frame tail sequence. To sum up, the PPM modulation pulse width is 320 ns, each frame of data contains 44 time slots, which are in turn the frame header (8 time slots), data (32 time slots), and frame tail (4 time slots). Its data frame structure is as Figure 4 shown.

[0118] Specifically, the processing steps of the PPM modulation and data framing module include:

[0119] S01: When the input end of the PPM modulation module reads the data sent by the memory, a right shift mask operation is adopted to sequentially extract two-bit data selected_data from the low bit to the high bit;

[0120] S02: Define two pulse transition times, namely data_0 and data_1, where data_0 is used to represent the position where the pulse is generated, and data_1 is used to represent the duration and recovery time of the pulse;

[0121] S03: Calculate the positions data_0 and data_1 of the two pulses according to the extracted two-bit data selected_data;

[0122] The calculation process is as follows: perform bit recombination on selected_data, multiply by 2 and add 1, then multiply by 16 to expand it within a time window of 128 clock cycles, and data_1 is 16 more than data_0;

[0123] S04: Output the data frame according to the state of the encoding module state machine. At the same time, a counter Clk_cnt based on a 50MHz clock frequency is used for counting, and the high and low levels of the data frame are set according to the value of Clk_cnt:

[0124] 1) When order = IDLE, set the output result to 1, keep it at a high level, there is no pulse signal, and wait for the generation of the frame header;

[0125] 2) When order = SOF, according to the count value of Clk_cnt, set the output to 1 or 0 at a specific position to generate a specific frame header sequence;

[0126] 3) When order = DATA, compare the count value of Clk_cnt with data_0 and data_1. When Clk_cnt = data_0, set the output to 0, and the data pulse starts to be generated. When Clk_cnt = data_1, the data pulse stops being generated, and the output is set to 1, thus completing the pulse position mapping and generating the data segment sequence;

[0127] 4) When order = EOF, according to the count value of Clk_cnt, set the output to 1 or 0 at a specific position to generate a specific frame tail sequence;

[0128] S05: Combine the generated frame header sequence, data segment sequence, and frame tail sequence to obtain a digital pulse signal containing all the information of a frame of data.

[0129] In this embodiment, the receiving end FPGA includes a receiving end top module, a clock data recovery module, a PPM decoding module, and a serial port sending module.

[0130] The receiving - end top - level module is used to coordinate the work of each module; and uses the IBUFDS primitive to convert the differential input signals DinI and DinIB of the PPM demodulator into a single - ended signal OUT, facilitating subsequent data processing.

[0131] The clock and data recovery module (CDR module) is used to sample the input digital signal (serial data) at different clock edges, determine the edge position of the data, and recover the synchronous clock signal and data signal;

[0132] Where:

[0133] Use the IP core to generate two clock signals clk_0 and clk_90 with a 90 - degree phase difference;

[0134] Use four different clock edges of clk_0 and clk_90: posedge clk_0, posedge clk_90, negedge clk_0, negedge clk_90. The clock edges are used to sample the input data to obtain data values at different times;

[0135] Determine the edge position of the data according to the sampled data and update the pos_neg signal;

[0136] Select appropriate clock signals and data signals for output according to the pos_neg signal;

[0137] The PPM decoding module (ppm_decoder module) is used to convert the data signal recovered by the clock and data recovery module into eight - bit parallel data, and perform frame synchronization and demodulation on the eight - bit parallel data to obtain the demodulated data;

[0138] Define three states: idle state (IDEL), waiting state (WAIT), and decoding state (DECODE);

[0139] In the idle state (IDEL), wait for the falling edge of the input signal. After detection, enter the waiting state (WAIT);

[0140] In the waiting state (WAIT), detect the start - of - frame signal (SOF) through clock counting and the state of the input signal. After detecting the SOF, enter the decoding state (DECODE);

[0141] In the decoding state (DECODE), control the reception of bits through clock counting, combine the received two - bit data into eight - bit parallel data in sequence. After receiving one byte, set the enable signal D_en to high, indicating that the data is ready;

[0142] The serial port transmission module (uart_tx module) is used to transmit the input 8-bit parallel data through UART.

[0143] When the D_en signal is valid, the transmission process is started;

[0144] The baud rate counter baud_cnt is used to control the transmission time of each bit;

[0145] The bit counter bit_cnt is used to control the number of bits transmitted, and the start bit, data bit, and stop bit are transmitted in sequence;

[0146] After the transmission is completed, the Tx_done signal is set high.

[0147] Before PPM demodulation, it is necessary to perform synchronous recovery on the clock data. Due to the strict requirements of PPM modulation for frame synchronization and detection, it is crucial to implement an accurate synchronization technology. Clock and Data Recovery (CDR) is generally used for the recovery of serial data. Since this embodiment uses LVDS differential signals for data transmission and eliminates the clock line at the same time, the data received at the receiving end needs to be recovered for both clock and data. This embodiment adopts a fully digital CDR design based on the principle of co-frequency multi-phase clock sampling of FPGA. The phase-locked loop ip core of FPGA is used to generate two clocks with the same frequency (f = 50MHz) and phases of 0° and 90° respectively. Each clock is sampled at the rising edge and falling edge respectively, so as to achieve four-fold sampling. Then, the discriminator judges the four sampling points to obtain the position of the data signal transition edge, and then selects the best sampling point to recover the data and clock, so as to achieve bit synchronization. The simulation results shown by the built-in simulator of VIVADO are as Figure 5 shown, the data and the clock transition edges are synchronized, and the next step can be entered to perform frame synchronization and demodulation on the signal.

[0148] The clock signal and data signal after bit synchronization are connected to the frame synchronization and demodulation module, and the frame header detection and data demodulation are carried out based on the principle of counting using a state machine. The three states of the state machine are defined as: idle state (IDEL), waiting state (WAIT), and decoding state (DECODE). In the WAIT state, the frame start signal is accurately detected through the frame detection flag bit, and detailed judgments are made at different clock cycles according to the input level to ensure the correct detection of the SOF, improving the reliability and anti-interference ability of the system. In the DECODE state, 128 clock cycles are divided into 8 time slots, each time slot contains 1 low level and 7 high levels, and the data in the PPM signal can be accurately decoded into parallel data to achieve efficient data conversion.

[0149] Specifically, the processing steps of the receiving end FPGA include:

[0150] S11: After the top-level module at the receiving end converts the digital signal output by the analog-to-digital conversion and pulse shaping circuit into a single-ended signal OUT, it uses it as the input ser_in of the clock data recovery module. At the same time, it uses the PLL IP core to generate two clock signals clk_0 and clk_90 with the same frequency but different phases, and uses them as the sampling clocks of the clock data recovery module;

[0151] S12: The clock data recovery module processes ser_in using the rising and falling edges of clk_0 and clk_90, and outputs the recovered synchronous clock signal ser_clk and data signal ser_out, which are used as the clock signal clk and input data Din of the PPM decoding module;

[0152] S13: Define three states of the decoding state machine: idle state (IDEL), waiting state (WAIT), and decoding state (DECODE);

[0153] S14: The PPM decoding module performs frame header detection and PPM decoding on Din under the drive of clk:

[0154] 1) In the idle state (IDEL), detect whether there is a falling edge in the input data Din data stream. When a falling edge is detected, switch from the idle state to the WAIT state;

[0155] 2) In the waiting state (WAIT), accurately detect the frame start signal through the frame detection flag bit, and make a detailed judgment in different clock cycles according to the input level to ensure correct detection of the frame header generation state. After detecting the frame header generation state, switch from the WAIT state to the DECODE state, otherwise return to the idle state (IDEL);

[0156] 3) In the decoding state (DECODE), divide 128 clock cycles into 8 time slots, each time slot contains 1 low level and 7 high levels, and perform the inverse operation of the encoding on the detected data to recover the eight-bit parallel data and the enable signal;

[0157] S14: Use the recovered eight-bit parallel data as the demodulated data.

[0158] The serial port sending module uses the demodulated data Dout and the enable signal D_en output by the PPM decoding module as the input data uart_din and the data enable signal uart_din_en respectively. When the uart_din_en signal is valid, send the uart_din data through the UART and output the UART sending signal uart_txd.

[0159] II. Optical Transmitter Design

[0160] The optical transmitter includes a driving modulation circuit and a light source module.

[0161] In this embodiment, the light source module includes a blue laser diode (Laser diodes, LD) as the light source, a collimating lens for collimating the optical signal emitted by the blue laser diode, and a heat dissipation module for ensuring the stable operation of the blue laser diode.

[0162] The PPM enable signal modulated by the FPGA is input into the optical transmitter, and the optical transmitter completes the electro-optical signal conversion. For the UWOC (Underwater Wireless Optical Communication) system, the performance of the transmitter determines the communication quality of the system. To reduce costs and design complexity, the transmitter in this embodiment consists only of a driving modulation circuit based on a high-frequency switching chip and a light source module. A blue LD is selected as the light source, which can obtain a higher modulation bandwidth and a longer transmission distance compared with ordinary LEDs. The schematic design of the hardware part is carried out around the high-frequency laser driver chip IC-HK integrated chip.

[0163] In this embodiment, the laser diode selects a 450nm semiconductor laser, which is packaged in TO18. The typical vertical beam divergence angle is 20°, and the horizontal beam divergence angle is 8°. Its spectral characteristic curve and LIV characteristic curve are as Figure 6 shown. The peak wavelength is 450.89nm, the peak power can reach 140mW, the laser threshold current is 50mA, the driving current is lower than 120mA, and the driving voltage is less than 6.5V.

[0164] The core of the driving modulation circuit is the design of the peripheral circuit of the IC-HK chip. IC-HK is a fast-switching chip dedicated to laser diode driving released by the German semiconductor chip manufacturer IC-Haus. The modulation frequency can reach 155Mhz, meeting the system design requirements. Its internal consists of two field-effect transistor control circuits, with two enable pins EN1 and EN2. Each path can control the LDK pin to deliver a maximum current of 700mA to the cathode of the laser. As Figure 7 (f) shows, to ensure the stability of the laser operation, this embodiment adopts the method of the common action of two enable pins. The EN2 pin is voltage-divided by a resistor and cooperates with the resistor of the AGND2 pin to achieve an output current of 0 - 70mA at the LDK pin; the EN1 pin receives the 3.3V standard TTL level from the FPGA through SMA and cooperates with the resistor of the AGND1 pin to achieve a current output of 0 - 155mA. This driving circuit can output a maximum current of 225mA, which is sufficient to drive the mainstream low-power blue-green semiconductor laser diodes on the market. An output voltage adjustable power supply chip LM317 is used, in cooperation with an adjustable potentiometer, to generate the voltage of the CI pin of the IC-HK, thereby realizing the adjustability of the cathode current of the laser from 0 to 225mA.

[0165] The PCB circuit board of the drive modulation circuit has a size of only 3 cm × 4 cm. The heat dissipation copper posts and the TEC semiconductor refrigeration sheet can ensure the long-term stable operation of the laser. The integrated adjustable collimating lens can adjust the spot size and has the advantages of high integration at the same time. The laser heat dissipation metal posts are as Figure 7 (a) shown, the structure of the collimating lens group is as Figure 7 (b) shown, the structure of the laser heat sink is as Figure 7 (c) shown, a TEC refrigeration sheet is attached to its lower end. The spot effect of the laser without collimation is as Figure 7 (d) shown. At this time, the laser beam diverges severely. Figure 7 (e) is the collimation effect diagram of the laser at 10 meters, and its spot diameter is less than 3 mm.

[0166] III. Optical Receiver Design

[0167] The optical receiver includes an optical module, a photodetector module, and an analog-to-digital conversion and pulse shaping module.

[0168] After the optical signal is transmitted through the underwater channel, it first passes through the optical module for power attenuation and stray light filtering. At this time, the relatively weak optical signal (in the microampere level) irradiates on the pixel unit of the photodetector module. The MPPC is responsible for completing the conversion and amplification of the optical signal into an electrical signal. The output analog signal is transmitted to the backend analog-to-digital conversion and pulse shaping circuit. After adjusting the threshold voltage, the analog-to-digital signal conversion work is completed. Finally, the digital signal is transmitted to the IO port of the receiver FPGA, and the FPGA independently completes the synchronization, frame header detection, decoding, and transmission work of the digital signal.

[0169] 1. Optical Module

[0170] In this embodiment, the optical module includes an optical attenuation sheet, a blue light band filter, and a Fresnel lens that sequentially process the received optical signal, and a dark box is used to cover the optical attenuation sheet, the blue light band filter, and the Fresnel lens to achieve light shielding treatment;

[0171] Among them, the optical attenuation sheet is used to simulate the underwater channel and the dark deep water environment (only required in the experimental environment); the blue light band filter is used to filter out stray light and enhance the signal-to-noise ratio; the Fresnel lens is used to increase the signal reception area while achieving a light condensing effect and reduce the difficulty of optical alignment.

[0172] The optical module is crucial for the light receiving part. A Fresnel lens with a diameter of 13 mm is selected to achieve the effect of light concentration, increase the signal receiving area, and reduce the difficulty of optical alignment. Due to the high sensitivity of the MPPC and the interference of stray light signals, in order to simulate a sufficiently long underwater channel and a dark deep - water environment, a 0.01% light attenuation sheet and a blue - band filter are needed. At the same time, a dark box is used to shield the MPPC module from light.

[0173] 2. Photoelectric detector

[0174] In this embodiment, the photoelectric detector is a multi - pixel photon counter (MPPC), and a dark box is used to cover the multi - pixel photon counter to achieve light shielding; the pixel unit of the multi - pixel photon counter receives the optical signal transmitted by the optical module, and performs photoelectric conversion and amplification on the optical signal to obtain an analog electrical signal.

[0175] The detector selects an MPPC with short - wavelength response. It is a new type of photon - counting device composed of multiple Geiger - mode avalanche photodiode pixels, with excellent photon - counting ability, low operating voltage, and not affected by magnetic fields. The C13365SA series MPPC module of Hamamatsu is composed of an MPPC, a signal amplification circuit, a high - voltage power supply circuit, and a temperature compensation circuit. The photosensitive area size is 1.3×1.3 mm, and the output type is an analog signal. The module is powered by ±5v. The spectral response range of the C13365 series is 320 nm - 900 nm, the peak sensitivity wavelength is 500 nm, with high sensitivity in the short - wavelength range, very suitable for detecting optical information in the blue - green light band (450 - 570 nm) of underwater communication. The photoelectric sensitivity reaches 1.0×109 V / W, the - 3dB bandwidth is DC - 5MHz, and the output rise time is only 5 ns. It can meet the design requirements of the communication system of the present invention.

[0176] Covering the optical module and the detector module with a dark box can effectively avoid the irradiation of stray light and improve the signal - to - noise ratio of the system. The optical signal passes through the underwater channel and the optical module and then reaches the MPPC. The MPPC completes photoelectric conversion and amplifies the signal. Figure 8 (a) The yellow waveform is the FPGA enable signal, and the blue waveform is the analog signal waveform output by the MPPC module. Figure 8 (b) is the waveform of the amplified analog signal output by the MPPC module.

[0177] 3. Analog - to - digital conversion and pulse shaping circuit

[0178] In this embodiment, the analog-to-digital conversion and pulse shaping circuit uses a two-stage comparator to realize analog-to-digital conversion and pulse shaping of the analog electrical signal; the analog electrical signal output by the photodetector is input to the non-inverting input terminal of the first-stage comparator, and a comparison voltage is set at the inverting input terminal, and a low voltage differential signal (Low Voltage Differential Signaling, LVDS) is output through the first-stage comparator; the low voltage differential signal output by the first-stage comparator is input to the non-inverting input terminal of the second-stage comparator, and a threshold voltage is connected to the inverting input terminal, and a digital signal that meets the electrical standard of the low voltage differential signal is output through the second-stage comparator.

[0179] The analog-to-digital conversion and pulse shaping circuit is designed based on the Texas Instruments TLV3605 series comparator. This is a high-speed rail-to-rail input comparator with LVDS output, low propagation delay of 800ps, bandwidth of 1.5GHz, steep transition edge, and can detect pulse signals with a minimum pulse width of 600ps. A 4-layer PCB is used to design the pulse shaping module based on TLV3605. When designing, the LVDS signal design guidelines are followed, and the trace lengths of the differential lines should be as equal as possible. SMA terminals are welded to the input and output ends of the first-stage TLV3605 comparator, so that the oscilloscope can observe the signal quality of each level of input and output in real time. The circuit schematic and physical picture are as follows: Figure 9 shown.

[0180] This embodiment uses a two-stage comparator to realize analog-to-digital signal conversion and pulse shaping. The analog electrical signal output by the MPPC is connected to the non-inverting input terminal of the first-stage TLV3605, and a comparison voltage is set at the inverting input terminal. The high-level fluctuation range of the output voltage of the MPPC is 2-3.5V, and the low-level fluctuation range is 0-0.8V. After experimental testing, when the threshold voltage of the comparator is set to 1.78V, the output LVDS signal jump edge is steeper and the data is stable. However, by observing the LVDS signal waveform, it can be seen that the falling edge of the LVDS+ signal and the rising edge of the -LVDS signal are still not steep enough, fluctuating between 5ns-20ns, such as Figure 10 As shown in (e), this is very disadvantageous for the bit synchronization and frame synchronization modules based on the counter at the back end, and it is easy to cause data loss. Therefore, it is necessary to add a secondary comparator circuit to further shape the signal. The LVDS+ signal at the output of the first-stage comparator is connected to the non-inverting input of the secondary comparator, and the inverting input is connected to the threshold voltage. The output signal amplitude of the first-stage comparator is 350mv. After experimental testing, when the comparison voltage of the secondary comparator is set to 0.038v, the LVDS signal output has an extremely narrow jump edge, and its rise and fall time is less than 5ns, as shown in Figure 1. Figure 10As shown in (f). The LVDS signal generated by the analog-to-digital conversion and pulse shaping circuit is connected to the IO port of the receiving-end FPGA through an equal-length RF connecting wire. The built-in primitive IBUFDS of the FPGA is used to convert the differential signal into a single-ended signal for the next CDR, frame detection, and demodulation operations.

[0181] IV. Experiment Description

[0182] 1. Experimental Environment Testing and Platform Building

[0183] The experimental platform is as Figure 11 shown in (a). The black MPPC cassette contains the MPPC module and the optical module. Two FPGAs are responsible for signal processing at the transmitting and receiving ends. The baud rate of data transmission between the FPGA and the computer through the serial port is set to 512000 bps. The parameters of the drive modulation circuit are adjusted so that the anode voltage of the LD is set to 5.5 V and the enable control voltage is set to 2.81 V. At this time, the output optical power of the transmitter is measured to be 36.32 mW; an optical K9 mirror is used for multiple optical path reflections in the experimental water tank to extend the underwater channel distance, as Figure 11 shown in (b); the weak optical signal after passing through the underwater channel is captured by the MPPC module after passing through the attenuation sheet and the optical bandpass filter.

[0184] The signal quality received by the UWOC system receiver is affected by parameters such as the optical power of the transmitter, the receiver sensitivity, and the attenuation coefficient of the transmission medium for light of a specific wavelength. Among them, the optical power of the transmitter and the receiver sensitivity are both determined when the UWOC system is designed. In the PPM modulation communication system, the optical power of the transmitter is affected by the modulation pulse width and the communication rate; in order to measure the performance of the UWOC system of this embodiment, it is necessary to measure the attenuation coefficient of the laboratory underwater channel. Under the conditions of a pulse width of 320 ns and a communication rate of 512 Kbps, the parameters of the drive modulation circuit are adjusted to make the output optical power constant, so as to measure the total attenuation coefficient of the laboratory underwater channel. Figure 11 (c) shows the power change of the optical signal with a wavelength of 450 nm after passing through air, the underwater channel, the acrylic plate, and the mirror. According to the Beer-Lambert law, from the incident optical power and the output optical power, it can be calculated that the total attenuation degree of the medium in the experimental environment is about 0.47 m -1 -0.85 m -1 , research shows that the attenuation coefficient of light of this wavelength in clear water is 0.15 m -1 , the attenuation coefficient in coastal waters is 0.39 m -1 , and the attenuation coefficient in turbid waters is 2.17 m -1 . It can be seen that the medium environment of this experiment is between coastal water and turbid water. According to the Beer-Lambert law, a laser with an optical power of 36 mW passes through 25 meters with an attenuation degree of 0.47 m -1-0.85 m -1 The underwater channel attenuation is approximately 19.6 pW - 316 nW after attenuation.

[0185] 2. Communication Performance Test

[0186] To optimize communication performance under hardware cost constraints, this experiment carried out research on optimizing the key parameters of pulse position modulation. Based on the timing constraints of the 512 kbps serial communication protocol (each frame takes 19.5 μs), the upper limit of the modulation pulse width was determined to be 320 ns (corresponding to a frame period of 14.08 μs) through theoretical derivation to avoid the risk of data overflow. Figure 12 The parameter analysis shown indicates that when the PPM modulation pulse width is set to 320 ns and the demodulation end uses a counting width of 80 ns (corresponding to a sampling frequency of 12.5 MHz), the system exhibits optimal transmission performance. Experimental data confirms that under this configuration, the system successfully achieves an effective communication distance of 25 meters under high-loss conditions of the cross-media channel of 0.47 - 0.85 m -1 The bit error rate (BER) is stably maintained at 10 -4 order of magnitude, meeting the high-reliability transmission requirements of the UWOC system.

[0187] 3. Conclusion

[0188] The experimental results show that the optical signal power emitted by the optical transmitter of the low-cost UWOC system based on PPM modulation in the present invention is 36.32 mW. Under a high-loss environment with a total link attenuation of 0.47 m -1 -0.85 m -1 stable real-time communication at 512 kbps with a bit error rate below 10-4 can be achieved over a distance of 25 m. And experiments were carried out to test the influence of the PPM modulation width and decoding counting width on the PPM modulation and demodulation system. The bit error rate performance of the UWOC system was tested when the modulation pulse widths were 20 ns, 40 ns, 80 ns, and 320 ns respectively, as well as the influence of the change in the demodulation counting pulse width (10 ns, 20 ns, 80 ns, 320) on the bit error rate. It is concluded that when the overall machine hardware, structural cost, and parameters of this UWOC system are fixed, when the modulation pulse width is 320 ns and the counting pulse width is 80 ns, the communication rate of the system is the highest and the communication distance is the farthest.

[0189] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit the technical solutions. Those of ordinary skill in the art should understand that any modifications or equivalent replacements made to the technical solutions of the present invention without departing from the purpose and scope of the present technical solution shall be covered by the scope of the claims of the present invention.

Claims

1. An underwater wireless optical communication system based on pulse position modulation technology, comprising a transmitting module and a receiving module; characterized in that: The transmitting module includes: A transmitting - end FPGA, configured to receive target data to be transmitted and modulate the target data into a digital pulse signal based on pulse position modulation; A driving and modulating circuit, configured to convert the digital pulse signal output by the transmitting - end FPGA into a modulating current signal for controlling a light source and drive the light source to emit light; A light - source module, configured to generate a corresponding optical signal based on the modulating current signal generated by the driving and modulating circuit to complete electro - optical conversion, and collimate and focus the optical signal and then transmit it to an underwater channel; The receiving module includes: An optical module, configured to receive the optical signal transmitted through the underwater channel and attenuate the power of the optical signal and filter out stray light; A photodetector, configured to perform photoelectric conversion and amplification on the optical signal output by the optical module to obtain an analog electrical signal; An analog - to - digital conversion and pulse - shaping circuit, configured to perform analog - to - digital conversion and pulse - shaping on the analog electrical signal output by the photodetector to obtain a digital signal; A receiving - end FPGA, configured to perform bit synchronization, frame synchronization, and demodulation on the digital signal output by the analog - to - digital conversion and pulse - shaping circuit based on clock data recovery, frame detection, and pulse - position demodulation to obtain demodulated data, and send it to a terminal device through a serial port.

2. The underwater wireless optical communication system based on pulse position modulation technology according to claim 1, characterized in that: The transmitting - end FPGA includes: A transmitting - end top - level module, configured to switch the states of the top - level module state machine and the encoding module state machine; Wherein: The states of the top - level module state machine include an idle state, a storage state, a transmission state, and a termination state; The states of the encoding module state machine include IDEL, SOF, DATA, EOF; A serial - to - parallel conversion module, configured to convert the serial eight - bit binary target data into parallel data and temporarily store it in a register; Wherein: When the data conversion is completed, the top - level module state machine is switched from the idle state to the storage state, and order is set to SOF; otherwise, order is set to IDEL, where order is used to control the generation of data frames; A data storage module, configured to write the parallel data temporarily stored in the register into a memory when the top - level module state machine is switched from the idle state to the storage state; Wherein: A counter is used for writing - counting the memory. When the value of the counter reaches a set value, it indicates that the data storage is completed, the writing stops, the top - level module state machine is switched from the storage state to the transmission state, and the data in the memory is sent to the input end of the PPM modulation module; order is set to DATA; When the data transmission is completed, the top - level module state machine is switched from the transmission state to the termination state; order is set to EOF; A PPM modulation and data - framing module, configured to perform PPM modulation on the received data and generate and send a PPM data frame to obtain a digital pulse signal including a frame header, a data segment, and a frame tail.

3. The underwater wireless optical communication system based on pulse position modulation technology according to claim 2, characterized in that: The processing steps of the PPM modulation and data - framing module include: S01: When the data sent by the memory is read at the input end of the PPM modulation module, a right - shift mask operation is used to sequentially extract two - bit data selected_data from the low - order bit to the high - order bit; S02: Define two pulse transition times, namely data_0 and data_1 respectively, where data_0 is used to represent the position where the pulse is generated, and data_1 is used to represent the duration and recovery time of the pulse; S03: Calculate the positions data_0 and data_1 of the two pulses according to the extracted two-bit data selected_data; S04: Output the data frame according to the state pair of the encoding module state machine. Count based on the counter Clk_cnt, and set the high and low levels of the data frame according to the value of Clk_cnt: 1) When order = IDLE, set the output result to 1, keep the high level continuously, there is no pulse signal, and wait for the frame header to be generated; 2) When order = SOF, according to the count value of Clk_cnt, set the output to 1 or 0 at a specific position to generate a specific frame header sequence; 3) When order = DATA, compare the count value of Clk_cnt with data_0 and data_1. When Clk_cnt = data_0, set the output to 0, and the data pulse starts to be generated. When Clk_cnt = data_1, the data pulse stops being generated, and the output is set to 1, thus completing the pulse position mapping and generating the data segment sequence; 4) When order = EOF, according to the count value of Clk_cnt, set the output to 1 or 0 at a specific position to generate a specific frame tail sequence; S05: Combine the generated frame header sequence, data segment sequence, and frame tail sequence to obtain a digital pulse signal containing all the information of one frame of data.

4. The underwater wireless optical communication system based on pulse position modulation technology according to claim 3, wherein: The receiving-end FPGA includes: The receiving-end top-level module is used to coordinate the work of each module; The clock data recovery module is used to sample the input digital signal at different clock edges, determine the edge position of the data, and recover the synchronous clock signal and data signal; The PPM decoding module is used to convert the data signal recovered by the clock data recovery module into eight-bit parallel data, and perform frame synchronization and demodulation on the eight-bit parallel data to obtain the demodulated data; The serial port sending module is used to send the demodulated data through the UART.

5. The underwater wireless optical communication system based on pulse position modulation technology according to claim 4, characterized in that: The processing steps of the receiving-end FPGA include: S11: After the receiving-end top-level module converts the digital signal output by the analog-to-digital conversion and pulse shaping circuit into a single-ended signal OUT, it takes it as the input ser_in of the clock data recovery module. At the same time, use the phase-locked loop IP core to generate two clock signals clk_0 and clk_90 with the same frequency but different phases, and take them as the sampling clocks of the clock data recovery module; S12: The clock data recovery module processes ser_in using the rising edge and falling edge of clk_0 and clk_90, and outputs the recovered synchronous clock signal ser_clk and data signal ser_out, which are used as the clock signal clk and input data Din of the PPM decoding module; S13: Define three states of the decoding state machine: IDEL, WAIT, DECODE; S14: The PPM decoding module performs frame header detection and PPM decoding on Din under the drive of clk: 1) Under IDEL, detect whether there is a falling edge in the input data Din data stream. When a falling edge is detected, switch from the idle state to the WAIT state; 2) In the WAIT state, accurately detect the frame start signal through the frame detection flag bit, and make a detailed judgment in different clock cycles according to the input level to ensure correct detection of the frame header generation state. After detecting the frame header generation state, switch from the WAIT state to the DECODE state, otherwise return to IDEL; 3) In the DECODE state, divide 128 clock cycles into 8 time slots, each time slot contains 1 low level and 7 high levels, perform the inverse operation of encoding on the detected data, and restore the eight-bit parallel data; S14: Use the restored eight-bit parallel data as the demodulated data.

6. The underwater wireless optical communication system based on pulse position modulation technology according to claim 5, characterized in that: The serial port transmission module uses the demodulated data and the enable signal output by the PPM decoding module as the input data and the data enable signal; when the data enable signal is valid, send the input data through the UART and output the UART transmission signal.

7. The underwater wireless optical communication system based on pulse position modulation technology according to claim 1, characterized in that: The light source module includes a blue laser diode as the light source, a collimating lens for collimating the optical signal emitted by the blue laser diode, and a heat dissipation module for ensuring the stable operation of the blue laser diode.

8. The underwater wireless optical communication system based on pulse position modulation technology according to claim 1, characterized in that: The optical module includes a blue light band filter and a Fresnel lens that sequentially process the received optical signal, and uses a dark box to cover the blue light band filter and the Fresnel lens to achieve light shielding; among them, the blue light band filter is used to filter out stray light; the Fresnel lens is used to increase the signal receiving area while achieving the effect of light concentration.

9. The underwater wireless optical communication system based on pulse position modulation technology according to claim 1, characterized in that: The photodetector is a multi-photon counter, and a dark box is used to cover the multi-photon counter to achieve light shielding; Receive the optical signal transmitted by the optical module through the pixel unit of the multi-photon counter, and perform photoelectric conversion and amplification on the optical signal to obtain an analog electrical signal.

10. The underwater wireless optical communication system based on pulse position modulation technology according to claim 1, characterized in that: The analog-to-digital conversion and pulse shaping circuit uses two-stage comparators to achieve analog-to-digital conversion and pulse shaping of the analog electrical signal; Input the analog electrical signal output by the photodetector into the non-inverting input terminal of the first-stage comparator, and set the comparison voltage at the inverting input terminal. Output a low-voltage differential signal through the first-stage comparator; input the low-voltage differential signal output by the first-stage comparator into the non-inverting input terminal of the second-stage comparator, and connect the threshold voltage at the inverting input terminal. Output a digital signal that meets the electrical standard of the low-voltage differential signal through the second-stage comparator.

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