Multi-path Switch Board test system and test method

Abstract

The invention relates to the technical field of Switch Board testing, in particular to a multi-path Switch Board testing system and method, and the method comprises the following steps: 1, testing preparation: collecting the technical specification of a tested board, and building a power supply system and a network testing environment; the collected technical specifications comprise port configuration, supported protocols, power supply requirements and a working temperature range; the voltage and frequency of the power supply system meet the requirements of Switch Board, and the provided power meets the maximum load requirement in the test process; according to the invention, the quality of the Switch Board can be comprehensively evaluated, it is ensured that the Switch Board can stably and reliably operate under various working conditions, and potential defects and problems, such as design defects, manufacturing process problems, component faults and the like, existing in the Switch Board can be found in time in the testing process, so that manufacturers can improve the problems, and the testing efficiency is improved. The quality and reliability of products are improved, and the probability that the products break down in the using process is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of Switch Board testing, and specifically provides a multi-path Switch Board testing system and a testing method. Background Art

[0002] In a GPU server, the "Switch Board" usually refers to a hardware component used to connect and manage the communication and data exchange between multiple GPU devices. This board can play several key roles:

[0003] Interconnect multiple GPUs: The Switch Board can provide additional interconnection channels, enabling more efficient communication between multiple GPUs. This is very important for applications that require highly parallel processing, such as deep learning training, scientific computing, or graphics rendering;

[0004] The conventional testing method is as follows: Assemble the main board and the Switch Board, along with other testing peripherals, power on and enter the system, and start the hardware initialization test;

[0005] During the testing process, it is difficult to fully test all the performance indicators of the Switch Board, and it is also difficult to detect potential defects and problems in the Switch Board during the testing process, resulting in a relatively high probability of failures during product use. Therefore, a multi-path Switch Board testing system and a testing method are proposed to address the above problems. Summary of the Invention

[0006] The purpose of the present invention is to provide a multi-path Switch Board testing system and a testing method to solve the problems that it is difficult to fully test all the performance indicators of the Switch Board during the testing process, and it is also difficult to detect potential defects and problems in the Switch Board during the testing process, resulting in a relatively high probability of failures during product use.

[0007] To achieve the above purpose, the present invention provides the following technical solutions:

[0008] A multi-path Switch Board testing system and a testing method include the following steps:

[0009] Step 1: Test preparation: Collect the technical specifications of the board under test, and build a power supply system and a network testing environment;

[0010] The collected technical specifications include port configuration, supported protocols, power requirements, and operating temperature range;

[0011] The voltage and frequency of the power supply system meet the requirements of the Switch Board, and the power provided satisfies the maximum load demand during the test process;

[0012] For the network test environment, servers, client computers, and router network devices are configured according to the test purpose, and the data transmission performance of the Switch Board is tested with good connection link quality between the network devices;

[0013] Step 2: Power supply test: Verify the input voltage and current of the board under test through the power supply test module, and monitor the power consumption;

[0014] Step 3: IIC interface test: Read the parameter information of each IIC device through the IIC interface test module and perform verification;

[0015] Step 4: Boundary scan test: Use the boundary scan test device to detect the signal integrity and electrical performance of the board under test;

[0016] Step 5: High-speed signal differential test: Use the high-speed signal differential test module to test the high-speed signal transmission quality of the board under test;

[0017] Step 6: JTAG control test: Control the FPGA and power chip through the JTAG interface to detect the high and low level signal states;

[0018] Step 7: Hot plug test: Simulate the plugging and unplugging behavior of the device and observe the system's response under different load conditions;

[0019] Step 8: Data collection and analysis: Record the log information during the test process, perform fault analysis, and judge the test results of the board under test.

[0020] As a further optimized content of the present invention, wherein: in the said Step 3, the IIC interface test includes:

[0021] Read FRU data, parse SN, Checksum, and manufacturing time;

[0022] Detect the temperature sensor to ensure that the temperature data is within the preset range;

[0023] Detect the voltage sampling value to ensure that the voltage parameter meets the design requirements.

[0024] As a further optimized content of the present invention, wherein: in the said Step 4, the boundary scan test adopts a multi-link boundary scan method, including:

[0025] Individually scan the U35 boundary scan device;

[0026] Series scan the U1, U2, U3, and U4 boundary scan devices;

[0027] Connect the Slim-74PIN-J25 Dummy card to conduct IIC link testing.

[0028] As a further optimized content of the present invention, wherein: in the sixth step, the JTAG control test includes:

[0029] Control the power-on and power-off of the power chip and monitor the power output signal;

[0030] Test the general IO signals and conduct interconnectivity testing using the 1149.1 standard;

[0031] Test the differential signals and conduct differential signal loopback testing using the 1149.6 standard.

[0032] As a further optimized content of the present invention, wherein: in the eighth step, the data collection and analysis include:

[0033] Collect test logs, including error logs, warning logs, and debugging information;

[0034] Analyze the test results, identify potential faults through an automatic log analysis system, and improve the test accuracy.

[0035] As a further optimized content of the present invention, including: a device under test, which has multiple data transmission channels and multiple interfaces;

[0036] A boundary scan test device for conducting boundary scan testing on the device under test to detect signal integrity, data transmission rate, and electrical performance;

[0037] An IIC interface test module for reading parameter information of each IIC device on the device under test, including FRU value, temperature data, power status, etc.;

[0038] A JTAG control module for controlling the power supply of the device under test and the start and stop of each functional module, and supporting the on-off test of the power management chip;

[0039] A high-speed signal differential test module for testing the differential signal network of the device under test and detecting the signal transmission quality using the 1149.6 standard;

[0040] A power supply test module for monitoring the power input status of the device under test and detecting power consumption and power stability;

[0041] A hot plug detection unit for detecting the working state of the device under test under different load conditions, simulating device plugging and unplugging, and recording the system response;

[0042] A data recording and analysis system for collecting test logs, including error reports, warning messages, and debugging data, and conducting analysis to determine the test results of the device under test.

[0043] As a further optimized content of the present invention, wherein: the boundary scan test device includes a plurality of serially connected boundary scan links, wherein:

[0044] The first link is connected to the U35 boundary scan device;

[0045] The second link is connected to the U1, U2, U3, U4 boundary scan devices;

[0046] The third link is connected to the BF06-U2-D-ALL tool board and the Slim-74PIN-J25 Dummy card to complete the test of all IIC devices and connectors.

[0047] As a further optimized content of the present invention, wherein: the IIC interface test module further includes:

[0048] The IIC data acquisition unit is used to read the CPLD version information, FRU value, temperature data, and power supply status;

[0049] The IIC communication module is used to connect to the host computer through the USB to IIC interface to control the read and write operations of the IIC device.

[0050] As a further optimized content of the present invention, wherein: the JTAG control module can control the power chip through the JTAG interface to perform high and low level signal tests and read the FPGA register information through JTAG.

[0051] As a further optimized content of the present invention, wherein: the data recording and analysis system can automatically collect the log files generated during the test process, perform intelligent analysis, and identify potential faults.

[0052] Compared with the prior art, the beneficial effects of the present invention are:

[0053] In the present invention, the tests of BSI cover various performance indicators of the Switch Board, including electrical performance, signal integrity, data transmission rate, reliability, etc. Through strict tests, the quality of the Switch Board can be comprehensively evaluated to ensure that it can operate stably and reliably under various working conditions. Moreover, during the test process, potential defects and problems existing in the Switch Board can be detected in a timely manner, such as design defects, manufacturing process problems, component failures, etc., enabling the manufacturer to improve these problems, enhance the quality and reliability of the product, and reduce the probability of product failures during use. Description of the Drawings

[0054] Figure 1 It is the test flow chart of the host computer software of the present invention;

[0055] Figure 2 Schematic diagram of the operation flow chart of the fixture of the present invention;

[0056] Figure 3 Power supply input diagram of the present invention;

[0057] Figure 4 Test connection diagram of IIC and U25 of the present invention;

[0058] Figure 5 Test connection diagram of IIC and U31 of the present invention;

[0059] Figure 6 Test connection diagram of IIC and U13 of the present invention;

[0060] Figure 7 Test connection diagram of IIC and PU23 of the present invention;

[0061] Figure 8 Test connection diagram of IO and J25 of the present invention;

[0062] Figure 9 Differential signal test diagram of the present invention. Detailed implementation manners

[0063] Please refer to Figures 1-9 , the present invention provides a technical solution:

[0064] Among them, Figure 3 The signal of the boxed part is to input a 12V / 10A power supply to the DUT from the J187 / J186 / J88 / J87 connectors of the DUT;

[0065] Figure 4 The test points of the boxed part are connected to the IIC module, which drives the IIC module to read the heat data of U25. If the read temperature value is within the range of 10° to 40°, it will be judged as PASS, otherwise it will be judged as FAIL;

[0066] Figure 5 The test points of the boxed part are connected to the IIC module, which drives the IIC module to read the FRU value of U31, parse and verify the SN, Checksum and manufacturing time of the DUT. If the SN, Checksum and manufacturing time of the DUT are verified correctly during the test, it will be judged as PASS, otherwise it will be judged as FAIL;

[0067] Figure 6The test points in the selected part are connected to the IIC module, which drives the IIC module to write the address 0x09 into the U13 register. If 0x09 can be read at the read address, it will be judged as PASS; otherwise, it will be judged as FAIL. At the same time, by enabling the SCn / SDn channels (the network in the blue square), the SDA and SCL of each channel are connected to it. The network of the Dummy card is tested by the 1149.1 method for network interconnection;

[0068] Figure 7 The test points in the selected part are connected to the IIC module, which drives the IIC module to read the current, voltage, and power in the PU23 register and judge them. If the voltage is 12V and the current is within the Imax range, the test result is PASS; otherwise, it is FAIL;

[0069] Figure 8 The J25 connector inserts the Slim-74PIN-J25 Dummy card. The ordinary IO signals in the red square part of the inserted test Dummy card are tested by the 1149.1 method (the JTAG controls the master chip (U35) of the DUT to drive high and low levels. If the corresponding levels are read through the JTAG control and the Slim-74PIN-J25 Dummy card connected to J25, it will be judged as PASS; otherwise, it will be judged as FAIL);

[0070] Figure 9 The differential signal network in the selected part is tested by the 1149.6 differential loopback (the JTAG controls the master chip U4 of the DUT to send a high-speed digital stream. If the corresponding data stream is read by the Slim-74PIN-ALL Dummy card connected to the MCIOx8 connector (J16) through the JTAG control, it will be judged as PASS; otherwise, it will be judged as FAIL).

[0071] For a part of the selected network, if the low level is read by the Slim-74PIN-ALL Dummy card connected to the MCIOx8 connector (J16) through the JTAG control, it will be judged as PASS; otherwise, it will be judged as FAIL.

[0072] A multi-path Switch Board test system and test method include the following steps:

[0073] Step 1: Test preparation: Collect the technical specifications of the DUT, and build a power supply system and a network test environment;

[0074] The collected technical specifications include port configuration, supported protocols, power requirements, and operating temperature range;

[0075] The voltage and frequency of the power supply system meet the requirements of the Switch Board, and the power provided satisfies the maximum load demand during the test process;

[0076] For the network test environment, configure server, client computer, and router network devices according to the test purpose, and test the data transmission performance of the Switch Board. The connection links between network devices are of good quality;

[0077] Step 2: Power supply test: Verify the input voltage and current of the board under test through the power supply test module, and monitor the power consumption;

[0078] Step 3: IIC interface test: Read the parameter information of each IIC device through the IIC interface test module and perform verification;

[0079] Step 4: Boundary scan test: Use the boundary scan test device to detect the signal integrity and electrical performance of the board under test;

[0080] Step 5: High-speed signal differential test: Use the high-speed signal differential test module to test the high-speed signal transmission quality of the board under test;

[0081] Step 6: JTAG control test: Control the FPGA and power chip through the JTAG interface and detect the high and low level signal states;

[0082] Step 7: Hot plug test: Simulate the plugging and unplugging behavior of the device and observe the system's response under different load conditions;

[0083] Step 8: Data collection and analysis: Record the log information during the test process, perform fault analysis, and judge the test results of the board under test. Through comprehensive preparation and step-by-step testing, ensure that all aspects from power supply, signal, interface to data analysis are effectively verified, thereby improving the accuracy and reliability of the test and providing a strong basis for subsequent product quality improvement.

[0084] As a technical solution for further implementation of this scheme, in Step 3, the IIC interface test includes:

[0085] Read FRU data, parse SN, Checksum, and manufacturing time;

[0086] Detect the temperature sensor to ensure that the temperature data is within the preset range;

[0087] Detect the voltage sampling value to ensure that the voltage parameter meets the design requirements. By refining the content of the IIC interface test, not only can the device identity information and manufacturing data be verified, but also key parameters such as temperature and voltage can be monitored in real time, thereby ensuring the stable operation of the Switch Board in various environments;

[0088] As a further technical solution for the implementation of this solution, in step four, the boundary scan test adopts a multi-link boundary scan method, including:

[0089] Individually scan the U35 boundary scan device;

[0090] Series-scan the U1, U2, U3, and U4 boundary scan devices;

[0091] Connect the Slim-74PIN-J25 Dummy card to conduct IIC link tests. The multi-link boundary scan test can cover different test points on the Switch Board. By conducting segmented tests, the signal integrity and electrical performance of each part can be fully verified, improving the overall test efficiency and the accuracy of fault location;

[0092] As a further technical solution for the implementation of this solution, in step six, the JTAG control test includes:

[0093] Control the power-on and power-off of the power chip and monitor the power output signal;

[0094] Test the general IO signals and conduct interconnectivity tests using the 1149.1 standard;

[0095] Test the differential signals and conduct differential signal loopback tests using the 1149.6 standard. The precise control of the power supply and signals is achieved through JTAG control, which can not only verify the accuracy of the board-level functions but also achieve high-standard tests in high-speed data transmission and differential signal loopback, ensuring the stability of the product in complex environments;

[0096] As a further technical solution for the implementation of this solution, in step eight, the data collection and analysis include:

[0097] Collect test logs, including error logs, warning logs, and debugging information;

[0098] Analyze the test results, identify potential faults through the automatic log analysis system, and improve the test accuracy. Data collection and automatic analysis can not only quickly feedback the test results but also discover potential problems in advance, providing data support for subsequent fault troubleshooting and product optimization, thereby effectively reducing the product failure rate;

[0099] As a further technical solution for the implementation of this solution, it includes: a board under test, which has multiple data transmission channels and multiple interfaces;

[0100] A boundary scan test device for conducting boundary scan tests on the board under test to detect signal integrity, data transmission rate, and electrical performance;

[0101] The IIC interface test module is used to read the parameter information of each IIC device on the board under test, including FRU values, temperature data, power supply status, etc.;

[0102] The JTAG control module is used to control the power supply of the board under test and the start and stop of each functional module, and supports the on-off test of the power management chip;

[0103] The high-speed signal differential test module is used to test the differential signal network of the board under test and detect the signal transmission quality using the 1149.6 standard;

[0104] The power supply test module is used to monitor the power input status of the board under test and detect power consumption and power supply stability;

[0105] The hot plug detection unit is used to detect the working status of the board under test under different loads, simulate device plugging and unplugging and record the system response;

[0106] The data recording and analysis system is used to collect test logs, including error reports, warning messages and debugging data, and perform analysis to determine the test results of the board under test. The test system integrates multiple test modules, covering multiple aspects from power management to signal transmission, from static parameter collection to dynamic response test, ensuring a comprehensive and integrated performance evaluation of the Switch Board, and helping to quickly locate and solve potential defects;

[0107] As a further implementation technical solution of this scheme, the boundary scan test device includes multiple series-connected boundary scan links, where:

[0108] The first link is connected to the U35 boundary scan device;

[0109] The second link is connected to the U1, U2, U3, U4 boundary scan devices;

[0110] The third link is connected to the BF06-U2-D-ALL tool board and the Slim-74PIN-J25 Dummy card to complete the test of all IIC devices and connectors. The multi-link design enables the boundary scan test to achieve specialized detection for different devices and connection points, ensuring the independence and complementarity of each test link, thereby improving the overall test coverage and accuracy;

[0111] As a further implementation technical solution of this scheme, the IIC interface test module further includes:

[0112] The IIC data acquisition unit is used to read the CPLD version information, FRU value, temperature data, and power supply status;

[0113] The IIC communication module is used to connect to the host computer through the USB-to-IIC interface to control the read and write operations of IIC devices. By integrating data acquisition and communication functions, this module not only achieves accurate acquisition of key parameters but also enables real-time interaction with the host computer, providing technical support for rapid diagnosis and remote monitoring;

[0114] As a further technical solution of this scheme, the JTAG control module can control the power chip through the JTAG interface to perform high and low level signal tests, and read the FPGA register information through JTAG. Using the JTAG interface for precise control and signal acquisition, it can monitor the status of key chips in the board in real time, ensure the coordinated operation of each module of the Switch Board, and provide accurate data for subsequent system debugging and optimization;

[0115] As a further technical solution of this scheme, the data recording and analysis system can automatically collect the log files generated during the test process, perform intelligent analysis, and identify potential faults. The automatic log collection and intelligent analysis system greatly shortens the fault diagnosis time, can early warn of potential problems, thereby improving the overall test efficiency and product reliability, and providing strong quality assurance for the production process.

[0116] In this article, specific examples are used to elaborate on the principle and implementation manner of the present invention. The description of the above examples is only used to help understand the method and its core idea of the present invention. The above is only the preferred implementation manner of the present invention. It should be noted that due to the limited nature of written expression and objectively existing infinite specific structures, for those of ordinary skill in the art in this technical field, without departing from the principle of the present invention, several improvements, retouches or changes can be made, or the above technical features can be combined in an appropriate manner; these improvements, retouches, changes or combinations, or directly applying the concept and technical solution of the invention to other occasions without improvement, should all be regarded as the protection scope of the present invention.

Claims

1. A testing method for a multi-path Switch Board testing system, characterized in that, It includes the following steps: Step 1: Test preparation: Collect the technical specifications of the board under test, and build a power supply system and a network test environment; The collected technical specifications include port configuration, supported protocols, power requirements, and operating temperature range; The voltage and frequency of the power system meet the requirements of the Switch Board, and the provided power satisfies the maximum load demand during the test; For the network test environment, configure server, client computer, and router network devices according to the test purpose, and test the data transmission performance of the Switch Board. The connection links between network devices are of good quality; Step 2: Power supply test: Verify the input voltage and current of the board under test through the power supply test module, and monitor the power consumption; Step 3: IIC interface test: Read the parameter information of each IIC device through the IIC interface test module and perform verification; Step 4: Boundary scan test: Use the boundary scan test device to detect the signal integrity and electrical performance of the board under test; Step 5: High-speed signal differential test: Use the high-speed signal differential test module to test the high-speed signal transmission quality of the board under test; Step 6: JTAG control test: Control the FPGA and power chip through the JTAG interface to detect the high and low level signal states; Step 7: Hot plug test: Simulate the plugging and unplugging behavior of the device and observe the system's response under different load conditions; Step 8: Data collection and analysis: Record the log information during the test process, and perform fault analysis to judge the test results of the board under test.

2. The testing method of a multi-path Switch Board testing system according to claim 1, wherein: In the said Step 3, the IIC interface test includes: Read FRU data, parse SN, Checksum, and manufacturing time; Detect the temperature sensor to ensure that the temperature data is within the preset range; Detect the voltage sampling value to ensure that the voltage parameters meet the design requirements.

3. The test method of a multi-path Switch Board test system according to claim 1, characterized in that: In the said Step 4, the boundary scan test adopts the multi-link boundary scan method, including: Individually scan the U35 boundary scan device; Series scan the U1, U2, U3, U4 boundary scan devices; Connect the Slim-74PIN-J25 Dummy card for IIC link test.

4. The testing method of a multi-path Switch Board testing system according to claim 1, characterized in that: In the said Step 6, the JTAG control test includes: Control the power on and off of the power chip and monitor the power output signal; Test the general IO signal and perform the interconnectivity test according to the 1149.1 standard; Test the differential signal and perform the differential signal loopback test according to the 1149.6 standard.

5. The testing method of a multi-path Switch Board testing system according to claim 1, characterized in that: In the said Step 8, the data collection and analysis includes: Collect test logs, including error logs, warning logs, and debug information; Analyze the test results, identify potential faults through the automatic log analysis system, and improve the test accuracy.

6. A multi-path Switch Board test system according to any one of claims 1-5, characterized in that: It includes: The board under test, which has multiple data transmission channels and multiple interfaces; The boundary scan test device, which is used to perform the boundary scan test on the board under test to detect signal integrity, data transmission rate, and electrical performance; The IIC interface test module, which is used to read the parameter information of each IIC device on the board under test, including FRU value, temperature data, power status, etc.; JTAG control module, which is used to control the power supply of the board under test and the start and stop of each functional module, and supports the on-off test of the power management chip; High-speed signal differential test module, which is used to test the differential signal network of the board under test and detect the signal transmission quality according to the 1149.6 standard; Power supply test module, which is used to monitor the power input status of the board under test and detect the power consumption and power supply stability; Hot plug detection unit, which is used to detect the working status of the board under test under different load conditions, simulate device plugging and unplugging and record the system response; Data recording and analysis system, which is used to collect test logs, including error reports, warning messages and debugging data, and perform analysis to determine the test results of the board under test.

7. A multi-path Switch Board test system according to claim 6, characterized in that: The boundary scan test device includes a plurality of serially connected boundary scan links, where: The first link is connected to the U35 boundary scan device; The second link is connected to the U1, U2, U3, U4 boundary scan devices; The third link is connected to the BF06-U2-D-ALL tool board and the Slim-74PIN-J25 Dummy card to complete the test of all IIC devices and connectors.

8. A multi-path Switch Board test system according to claim 6, characterized in that: The IIC interface test module further includes: IIC data acquisition unit, which is used to read the CPLD version information, FRU value, temperature data, power supply status; IIC communication module, which is used to connect to the host computer through the USB to IIC interface to control the read and write operations of the IIC device.

9. A multi-path Switch Board test system according to claim 6, characterized in that: The JTAG control module can control the power chip through the JTAG interface to perform high and low level signal tests, and read the FPGA register information through JTAG.

10. A multi-path Switch Board test system according to claim 6, characterized in that: The data recording and analysis system can automatically collect the log files generated during the test process and perform intelligent analysis to identify potential faults.

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