Scalable architecture for error capture with single recorder method for automotive systems

Abstract

Various embodiments include methods and devices for error capture implemented in a computing device. Embodiments may include receiving, at an error recorder, a plurality of error data for a plurality of memories of a plurality of processors, the plurality of error data including error data for a memory of a processor, the error data having an identification of at least one fail bit of the memory. Embodiments may include receiving, at an error selection module for the processor, a plurality of requests from a plurality of error capture modules for the processor, and in response to a request from an error capture module being ranked prior to another request from another error capture module, determining an error selection module for the processor, the error selection module extracts error data from the error capture module. Embodiments may include transmitting the error data to the error recorder, and storing the error data at the error recorder in an order relative to another error data.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. Non - Provisional Application No. 18 / 145,925, filed on December 23, 2022, the entire content of which is hereby incorporated by reference for all purposes. Background Art

[0003] Computing systems use error - correcting codes (ECCs) to guard against memory failures, to correct single - bit failures or detect and report double - bit failures. Memory failures are reported as interrupts to a security monitoring circuit (referred to herein as the "security monitor") and trigger corrective actions. The security monitor requires information about the memory failure, such as the type of failure (single or double - bit), the failed memory address, and the failed memory ID. An ECC logger is used to store this error information. Summary of the Invention

[0004] Various disclosed aspects include apparatus and methods for error capture implemented in a computing device, the method including receiving, at an error logger, multiple error data for multiple memories of multiple processors, where the multiple memories of the multiple processors include a first memory of a first processor, and the multiple error data includes first error data for the first memory of the first processor, the first error data including an identification of at least one failed bit of the first memory. Some aspects may also include receiving, at multiple error - capture modules, the multiple error data for the multiple memories of the multiple processors, including receiving the first error data at an error - capture module among the multiple error - capture modules.

[0005] Some aspects may also include receiving, at an error selection module for the first processor, a plurality of requests from a plurality of error capture modules for the first processor, wherein each request of the plurality of requests is configured to indicate to the error selection module that at least one error data of the plurality of error data is stored at an error capture module of the plurality of error capture modules; and in response to a first request from a first error capture module of the plurality of error capture modules among the plurality of requests taking precedence over a second request from a second error capture module of the plurality of error capture modules among the plurality of requests, extracting, by the error selection module, the first error data from the first error capture module. Some aspects may also include transmitting the first error data to the error logger; and storing the first error data at the error logger in an order relative to stored error data of the memory among the plurality of memories of the plurality of processors, wherein the plurality of error data includes the stored error data. Some aspects may also include transmitting, from the error logger to the error selection module, a first acknowledgment signal configured to indicate receipt of the first error data; and in response to the second request and the first acknowledgment signal, extracting, by the error selection module, second error data from the second error capture module. In some aspects, the second request may take precedence over a third request from a third error capture module of the plurality of error capture modules among the plurality of requests, and the method may further include transmitting, from the error logger to the error selection module, a second acknowledgment signal configured to indicate receipt of the second error data; and in response to the third request and the second acknowledgment signal, extracting, by the error selection module, third error data from the third error capture module.

[0006] Some aspects may also include receiving, at the error logger, the first error data for the first memory of the first processor, wherein the first error data includes an identification of a number of fault bits; in response to the identification of the number of fault bits being one bit, generating a first interrupt signal configured as a unit fault indicator; and in response to the identification of the number of fault bits being two bits, generating a second interrupt signal configured as a double-bit fault indicator. Some aspects may also include receiving, at a functional safety unit, a third interrupt signal from the error logger; in response to the third interrupt signal being the first interrupt signal, generating, by the functional safety unit, a first safety signal; and in response to the third interrupt signal being the second interrupt signal, generating, by the functional safety unit, a second safety signal.

[0007] In some aspects, the plurality of error data may be configured with information identifying at least one faulty fault bit cell location of the memory. In some aspects, the error logger may be a single error logger for the plurality of memories of the plurality of processors.

[0008] Additional aspects include a computing device having a processor configured to perform the operations of any of the methods outlined above. Additional aspects include a computing device having components for performing the functions of any of the methods outlined above. Additional aspects include a non-transitory processor-readable medium having processor-executable instructions stored thereon, the processor-executable instructions being configured to cause a processor and other components of a computing device to perform the operations of any of the methods outlined above. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The drawings incorporated herein and forming a part of this specification illustrate example embodiments in various implementations and, together with the general description given above and the detailed description given below, serve to explain the features of the claims.

[0010] Figure 1 is a block diagram of components of an example computing device suitable for implementing various implementations.

[0011] Figure 2 is a block diagram of components of a scalable architecture for error capture using a single error logger suitable for implementing various implementations.

[0012] Figure 3 is a block diagram of components of a scalable architecture for error capture using a single error logger suitable for implementing various implementations.

[0013] Figure 4 is a process flow diagram of a method for capturing errors using a scalable architecture for error capture using a single error logger according to some implementations.

[0014] Figure 5 is a process flow diagram of a method for selecting errors using a scalable architecture for error capture using a single error logger according to some implementations.

[0015] Figure 6 is a process flow diagram of a method for logging errors using a scalable architecture for error capture using a single error logger according to some implementations.

[0016] Figure 7 is a process flow diagram of a method for notifying errors using a scalable architecture for error capture using a single error logger according to some implementations.

[0017] Figure 8 is a block diagram of components of an example mobile computing device suitable for implementing various implementations.

[0018] Figure 9is a component block diagram of an example mobile computing device suitable for implementing various embodiments.

[0019] Figure 10 is a component block diagram of an example server suitable for implementing various embodiments.

[0020] Figures 11A to 11C is a component block diagram of an example embedded vehicle computing system suitable for implementing various embodiments. Detailed Description

[0021] Various embodiments will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts. References to specific examples and specific implementations are for illustrative purposes and are not intended to limit the scope of the claims.

[0022] Various embodiments include methods and computing devices that utilize a scalable architecture to implement error capture, the scalable architecture being for error capture using a single error logger. The error logger may be configured to receive error data from multiple memories of multiple processors of the computing device. Each of the multiple processors may have an error selection module and multiple error capture modules associated with or coupled to the multiple memories, the error selection module being configured to select error data from the error capture modules for transmission to the error logger based on the priority of the error data relative to other error data. The error data may include information indicating to the error logger the number of failed bits of the memory associated with the error data, and the error logger may generate an interrupt signal specific to or indicating the number of failed bits.

[0023] The term "computing device" may refer to fixed computing devices, including personal computers, desktop computers, monolithic computers, workstations, supercomputers, mainframe computers, embedded computers (such as in vehicles and other larger systems), computerized vehicles (e.g., partially or fully autonomous ground, air, and / or water vehicles, such as passenger vehicles, commercial vehicles, recreational vehicles, etc.), servers, multimedia computers, and game consoles. The terms "computing device" and "mobile computing device" may be used interchangeably herein to refer to any one or all of the following: cellular phones, smart phones, personal or mobile multimedia players, personal digital assistants (PDAs), laptop computers, tablet computers, convertible laptop / tablet computers (2-in-1 computers), smartbooks, ultrabooks, netbooks, palmtop computers, wireless email receivers, Internet-enabled multimedia cellular phones, mobile game consoles, wireless game controllers, and similar personal electronic devices including memory and programmable processors.

[0024] For purposes of explanation and clarity, although the various embodiments are described in terms of code (e.g., processor-executable instructions), they are similarly applicable to any data, such as code stored in memory, program data, or other information. The terms "code," "data," and "information" are used interchangeably herein to refer to similar elements and are not intended to limit the scope of the claims and the specification to the type of code, data, or information used as examples in describing the various embodiments.

[0025] The computing system uses an Error Correction Code (ECC) to guard against memory faults to correct single-bit faults or detect and report double-bit faults. Memory faults are reported as interrupts to a security monitor. The interrupts can also trigger corrective actions. The security monitor requires information about the memory faults, such as the fault type (single or double-bit), the faulty memory address, and the faulty memory ID. An ECC logger is used to store this error information.

[0026] Traditionally, a computing system with multiple processors or subsystems would employ at least one ECC logger per processor or subsystem to store error information. In known systems, each ECC logger is associated with a limited number of memories per processor or subsystem (e.g., one ECC logger for every 4, 8, or 16 memories for a processor or subsystem). As the number of memories increases and the memory layout spans multiple design hierarchies, the cost of the ECC logger increases in terms of area, pin count, routability, scalability, and the maximum frequency of the subsystem, thereby reducing power, performance, and area metrics. Additionally, security software that needs to read error information from multiple ECC loggers to correctly identify errors incurs significant software overhead.

[0027] The various embodiments described herein address and overcome the aforementioned problems of multiple ECC loggers by reducing the number of ECC loggers or error loggers implemented in a computing system to as few as a single error logger. The various embodiments include a scalable architecture for error capture using a single error logger that is implemented for multiple processors and / or multiple subsystems of a subsystem. As few as one error logger can be implemented to store error information for multiple memories of multiple processors and / or multiple subsystems across subsystems. The scalable architecture for error capture using a single error logger can be scalable for any computing system design, independent of memory count and / or the hierarchy of memories. As few as a single error logger can be implemented, without being limited to the number of memories. The scalable architecture can include an error selection module configured to control the sequential transfer of error information from multiple memories to the error logger.

[0028] Implementing as few as one error logger for multiple processors and / or multiple subsystems of a subsystem reduces the number of error loggers in a computing system, thereby reducing the area required to implement the error logger. An error selection module that controls the sending of error messages from multiple memories to the error logger reduces the pin count required to implement the error logger by decoupling the number of pins required from the number of memories associated with the error logger, rather than using a specified number of pins for all memories associated with the error logger. Implementing as few as one error logger for multiple processors and / or multiple subsystems of a subsystem reduces software overhead by reducing the number of times error information needs to be read for the ECC error logger to correctly identify an error.

[0029] In some embodiments, the design of a computing system may include an error logger that uses a slower clock than the multiple processors and / or multiple subsystems of the subsystem associated with the error logger. The separation of the time domains of the error logger and the multiple processors and / or multiple subsystems of the subsystem associated with the error logger reduces (or even eliminates) the impact of the error logger on the maximum frequency of the multiple processors and / or multiple subsystems of the subsystem. Reducing the number of error loggers reduces the software overhead of reading error information by reducing the number of locations that need to be read by software.

[0030] Figure 1 Illustrated is a system that includes a computing device 100 suitable for use with various embodiments. The computing device 100 may include an SoC 102 that has a processor 104, a memory 106, a communication interface 108, a memory interface 110, a peripheral interface 120, and an error manager 124. The computing device 100 may also include a communication component 112 (such as a wired or wireless modem), a memory 114, an antenna 116 for establishing a wireless communication link, and / or a peripheral 122. The processor 104 may include any one of a variety of processing devices (such as multiple processor cores).

[0031] The term "system on a chip" or "SoC" is used herein to refer to a set of interconnected electronic circuits, typically but not exclusively including processing devices, memory, and communication interfaces. The processing device may include a variety of different types of processors 104 and / or processor cores, such as general-purpose processors, central processing units (CPUs), digital signal processors (DSPs), graphics processing units (GPUs), accelerated processing units (APUs), security processing units (SPUs), neural processing units (NPUs), intellectual property units (IPUs), subsystem processors of specific components of a computing device (such as an image processor of an imaging subsystem, a display processor of a display subsystem, a modem processor of a communication system, a vehicle control processor of a vehicle navigation system), auxiliary processors, peripheral processors, single-core processors, multi-core processors, controllers, and / or microcontrollers. The processing device may further implement other hardware and hardware combinations, such as field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), other programmable logic devices, discrete gate logic, transistor logic, performance monitoring hardware, watchdog hardware, and / or time references. The integrated circuit may be configured such that the components of the integrated circuit reside on a single piece of semiconductor material, such as silicon.

[0032] The SoC 102 may include one or more processors 104. The computing device 100 may include more than one SoC 102, thereby increasing the number of processors 104. The computing device 100 may also include processors 104 that are not associated with the SoC 102. The individual processors 104 may be multi-core processors. Each processor 104 may be configured for a specific purpose that may be the same as or different from other processors 104 of the computing device 100. One or more of the processors 104 with the same or different configurations may be grouped together. A group of processors 104 may be referred to as a multiprocessor cluster.

[0033] The memory 106 of the SoC 102 can be a volatile or non-volatile memory configured to store data and processor-executable code accessible by the processor 104 or one or more of the other components of the SoC 102. The computing device 100 and / or the SoC 102 can include one or more memories 106 configured for various purposes. The one or more memories 106 can include volatile memories such as random access memory (RAM) or main memory, or cache memory. These memories 106 can be configured to temporarily hold a limited amount of data received from data sensors or subsystems, data and / or processor-executable code instructions that are requested from volatile and / or non-volatile memories and loaded into the memory 106 based on various factors for anticipated future access, and / or intermediate processing data and / or processor-executable code instructions generated by the processor 104 and temporarily stored for future quick access without being stored in non-volatile memory. The memory 106 can be configured to at least temporarily store data and processor-executable code loaded into the memory 106 from another memory device, such as another memory 106 or the memory 114, for access by the processor 104 or one or more of the other components of the SoC 102. In some embodiments, any number and combination of the memories 106 can include one-time programmable or read-only memories.

[0034] The memory interface 110 and the memory 114 can work together to allow the computing device 100 to store data and processor-executable code on volatile and / or non-volatile storage media and retrieve data and processor-executable code from the volatile and / or non-volatile storage media. The memory 114 can be configured very similarly to the embodiments of the memory 106, where the memory 114 can store data or processor-executable code for access by the processor 104 or one or more of the other components of the SoC 102. In some embodiments, the non-volatile memory 114 can retain information after the computing device 100 has been powered off. When powered on again and the computing device 100 restarts, the information stored on the memory 114 can be used by the computing device 100. In some embodiments, the volatile memory 114 can not retain information after the computing device 100 has been powered off. The memory interface 110 can control access to the memory 114 and allow the processor 104 or one or more of the other components of the SoC 12 to read data from the memory 114 and write data to the memory.

[0035] The error manager 124 can be a component of the computing device 100 configured to store error data received from components of multiple processors 104 and / or subsystems of the SoC 102. The error manager 124 can analyze the error data to determine how many bits of the memory 106 are faulty (such as a single bit or multiple bits, including two bits), and generate a signal associated with the number of faulty bits. The error manager can send the generated signal to a system (not shown) of the computing device 100 configured to respond to an indication of the faulty memory based on the signal, such as a security monitor configured to maintain the safe operation of the computing device in the case of a faulty memory. Implementations of the error manager 124 are further described herein.

[0036] Some or all of the components of the computing device 100 and / or the SoC 102 can be arranged and / or combined differently and still provide the functionality of the various implementations. The computing device 100 is not limited to one component in each component, and multiple instances of each component can be included in various configurations of the computing device 100.

[0037] Figure 2 An extensible architecture for error capture using a single error logger suitable for implementing various implementations is illustrated. Refer to Figure 1 and Figure 2 , the extensible architecture 200 can include multiple hard macros 202a, 202b (e.g., Figure 1 the error manager 124 in Figure 1 connected to an error logger 212 (e.g., Figure 1 the processors 104 in Figure 1 and the subsystems discussed herein with reference to

[0038] In some implementations, the extensible architecture 200 can include a synchronizer 218 connected between the multiple hard macros 202a, 202b and the error logger 212. In some implementations, the extensible architecture 200 can include a functional safety unit 214 (e.g., Figure 1 Figure 1 the error manager 124 in

[0038] connected to the error logger 212. Various components of the extensible architecture 200 can be electrically connected via any number and combination of cables 216a, 216b, 216c, 216d, 216e, 216f (such as communication lines and / or buses).

[0038] The hard macros 202a, 202b can include multiple memory wrappers 204a, 204b, such as two or more memory wrappers. Any one of the hard macros 202a, 202b can include the same and / or different numbers of memory wrappers 204a, 204b. Each memory wrapper 204a, 204b can include a memory 206 (e.g., Figure 1in the memory 106). Each error capture module 208 can be connected to the error selection module 210.

[0039] One or more faulty bits may occur in the memory, resulting in an error that can be identified by an error correction code (ECC), which is implemented in the memory 206 (such as in a memory controller (not shown)). The memory 206 can generate a memory fault interrupt and a memory fault signature, which can be referred to herein independently and / or cumulatively, in whole and / or in part, as error data. The memory fault signature can include information about the memory fault, such as a hard macro identifier (ID), a memory ID, a memory address, and an ECC status. The hard macro ID can be configured to identify the hard macro 202a, 202b to which the memory 206 experiencing the fault belongs. The memory ID can be configured to identify the memory 206 of the hard macro 202a, 202b that is experiencing the fault. The memory ID can also be configured to identify one or more bit cell locations of the memory 206 that are experiencing the fault. The memory address can be configured to identify the location in the memory 206 that is experiencing the fault. The ECC status can be configured to indicate the number of bits at the location in the memory 206 that is experiencing the fault. The number of bits can be any number, such as one bit or more bits, including two bits. The ECC status can indicate a single-bit fault of one faulty bit at the location in the memory 206 experiencing the fault. The ECC status can indicate a double-bit fault of two faulty bits at the location in the memory 206 experiencing the fault. The error data can identify one or more faulty bits of the memory 206. For example, one or more bit cell locations in the memory address in the memory 206 of the hard macro 202a, 202b can be used to identify one or more faulty bits of the memory.

[0040] The memory 206 can transfer the error data to the error capture module 208. The error capture module 208 can receive the error data from the memory 206, store the error data, and generate and transfer a request to send the error data to the error selection module 210. For example, the error capture module 208 can include a memory (e.g., Figure 1 the memory 106) in (not shown) having a suitable size to store at least one instance of the memory fault signature, such as a register.

[0041] The error selection module 210 can receive requests from multiple error capture modules 208, prioritize the requests, extract error data from the capture module 208 in response to receiving a request, and transmit the error data to the error logger 212. For example, the error selection module 210 can prioritize requests based on the error capture module 208 from which it receives the requests. In some embodiments, the error capture module 208 can be associated with a priority. In some embodiments, the priority of the error capture module 208 can change based on the time of receiving a request from the error capture module 208 relative to the time of receiving requests from other error capture modules 208. In some embodiments, changing the priority can involve managing the priority of the error capture modules 208 in a polling manner, in which the priority rotates among a group of error capture modules 208 based on which error capture modules 208 can request and when. In some embodiments, the error selection module 210 can prioritize requests based on the order or time of receiving the requests. The error selection module 210 can extract error data from the capture module 208 based on the priority of the request in response to receiving the request. The error selection module 210 can transmit the error data extracted from one error capture module 208 to the error logger 212 before extracting additional error data from the error capture module 208.

[0042] A simplified polling example may include four error capture modules 208, each error capture module being assigned a different priority from 1 to 4, where 1 is the highest priority and 4 is the lowest priority. For example, error capture module 1 may have priority 1, error capture module 2 may have priority 2, error capture module 3 may have priority 3, and error capture module 4 may have priority 4. In this example, a request may be received first from error capture module 2 having priority 2, and error selection module 210 may extract error data from error capture module 2 and transmit the error data to error logger 212. Thus, the priorities of error capture modules 1 to 4 may be rotated such that error capture module 1 having priority 1 becomes priority 3, error capture module 2 having priority 2 becomes priority 4, error capture module 3 having priority 3 becomes priority 1, and error capture module 4 having priority 4 becomes priority 2. Extending this example, requests may be received from error capture module 1 having priority 3 and error capture module 3 having priority 1. Error selection module 210 may first extract error data from error capture module 3 and transmit the error data to error logger 212, and then extract error data from error capture module 1 and transmit the error data to error logger 212. The priorities of error capture modules 1 to 4 may be rotated such that error capture module 1 having priority 3 becomes priority 4, error capture module 2 having priority 4 becomes priority 1, error capture module 3 having priority 1 becomes priority 2, and error capture module 4 having priority 2 becomes priority 3.

[0043] Error logger 212 may store error data received from error selection module 210 of multiple hard macros 202a, 202b. Error logger 212 may analyze the stored error data to determine how many fault bits are associated with the error data. For example, error logger 212 may analyze the ECC status of the error data to determine how many fault bits are associated with the error data. For the ECC status of a single-bit error, error logger 212 may determine that one fault bit is associated with the error data. For the ECC status of a double-bit error, error logger 212 may determine that two fault bits are associated with the error data. Based on the number of fault bits associated with the error data, error logger 212 may generate different interrupt signals, where the interrupt signals are configured to indicate the number of fault bits associated with the error data. For example, error logger 212 may generate an interrupt signal configured as a single-fault indicator and an interrupt signal configured as a double-fault indicator. The interrupt signals may be transmitted by error logger 212 to functional safety unit 214. The error data may also be transmitted by error logger 212 to functional safety unit 214.

[0044] The functional safety unit 214 can receive interrupt and error data from the error logger 212 and store the error data. The functional safety unit 214 can analyze the interrupts and generate additional signals for the safety monitor, as further described herein. The functional safety unit 214 can also make the error data available to the safety monitor.

[0045] In some embodiments, multiple hard macros 202a, 202b can operate at different frequencies, different clock speeds than the error logger 212. For example, multiple hard macros 202a, 202b can operate at a higher frequency, faster clock speed than the error logger 212. Communication between the hard macros 202a, 202b operating at different frequencies and the error logger 212 can be synchronized by a synchronizer 218, which is configured to maintain data transmitted between the hard macros 202a, 202b and the error logger 212 in a stable state for the hard macros 202a, 202b and / or the error logger 212 to receive data based on their respective operating frequencies. For example, the synchronizer 218 can maintain error data transmitted from the hard macros 202a, 202b in a stable state for the error logger 212 to receive. For example, the synchronizer 218 can maintain an acknowledgement signal transmitted from the error logger 212 in a stable state for the hard macros 202a, 202b to receive. In some embodiments, the synchronizer 218 can be a stand-alone component of the scalable architecture 200. In some embodiments, the synchronizer 218 can include components integrated with other components of the scalable architecture 200, the hard macros 202a, 202b, and / or the error logger 212. In some embodiments, the synchronizer 218 and / or components of the synchronizer 218 can be implemented for individual hard macros 202a, 202b.

[0046] For purposes of explanation and clarity, Figure 2 the example illustrated in shows two hard macros 202a, 202b connected to the error logger 212 and does not limit the number of hard macros that can be connected to the error logger 212 in the claims and specification. For purposes of explanation and clarity, Figure 2 the example illustrated in shows two memory wrappers 204a, 204b for each hard macro 202a; however, any number of hard macros greater than 2 can be connected to the error logger 212. Further, any number of memory wrappers greater than 2 can be included as part of a hard macro. Figure 2 The example illustrated in is not intended to limit the number of memory wrappers for each hard macro in the claims and specification.

[0047] Figure 3 illustrates a scalable architecture for error capture using a single error logger suitable for implementing various embodiments. Referring to Figures 1 to 3 , a scalable architecture 300 (e.g., Figure 2The scalable architecture 200) in may include a plurality of hard macros 302 (e.g., Figure 1 the processor 104 in, as referenced herein Figure 1 the subsystems discussed, Figure 2 the hard macros 202a, 202b in), and an error logger 212 (e.g., Figure 1 the error manager 124 in). In some embodiments, the scalable architecture 300 may include a synchronizer 218. In some embodiments, the scalable architecture 300 may include a functional safety unit 214 (e.g., Figure 1 the error manager 124 in). The hard macro 302 may include a plurality of memory wrappers 204a, 204b, such as two or more memory wrappers. Any one of the hard macros in the hard macro 302 may include the same and / or different numbers of memory wrappers 204a, 204b. Each memory wrapper 204a, 204b may include a memory 206 (e.g., Figure 1 the memory 106 in) and an error capture module 208. The structures and functions of the memory wrappers 204a, 204b, the memory 206, the error capture module 208, the error logger 212, the synchronizer 218, and the functional safety unit 214 may be referenced in Figure 2 described, and further described with reference to Figure 3 as follows.

[0048] As described herein, the memory 206 may transfer error data 318 to the error capture module 208, which error data includes a memory fault interrupt and a memory fault signature. The error capture module 208 may transfer a request to send error data 320a including the memory fault signature to the error selection module 210. Similarly, the error capture module (not shown) of the memory wrapper 204b may transfer a request to send error data 320b including the memory fault signature to the error selection module 210. The error selection module 210 may extract error data from the error capture module 208 based on the priority and / or request of the error capture module 208 (such as via a polling method).

[0049] The error selection module 210 may transfer the error data 322, 326, 328 extracted from the error capture module 208 to the error logger 212. The error data 322, 326, 328 may be stored by the error logger 212 in a memory 310 (e.g., Figure 1in the memory 106). In response to receiving error data 322, 326, 328, the error logger 212 may transmit acknowledgement signals 330a, 330b, 330c, 330d to the error selection module 210. The acknowledgement signals 330a, 330b, 330c, 330d may indicate to the error selection module 210 that subsequent requests to send error data may be satisfied.

[0050] The synchronizer 218 may include any number and combination of components of the scalable architecture 300. In some embodiments, the synchronizer 218 may include various sequences of flip-flop memories 304a, 304b, 304c, 306a, 306b, 306cm and / or AND gates 308 as exemplified in Figure 3 The synchronizer 218 may be configured to synchronously send data between the error selection module 210 and the error logger 212 operating at different frequencies or clock cycles. For example, the synchronizer 218 may be configured to synchronously send error data 322, 326, 328 from the error selection module 210 to the error logger 212 and acknowledgement signals 330a, 330b, 330c, 330d from the error logger 212 to the error selection module 210.

[0051] In a non-limiting example of the synchronizer 218, the error data 322 extracted from the error capture module 208 and transmitted from the error selection module 210 may be received at the flip-flop memory 304a of the hard macro 302. The flip-flop memory 304a may hold the error data 322 and set the error data enable signal 324a in response to receiving the error data. The flip-flop memory 304a may hold the error data 322 until a fast clock signal (not shown) is received, and output the error data enable signal 324a to another flip-flop memory 304b and output the error data 326 including an error signature to the AND gate 308. The flip-flop memory 304b may forward the error data enable signal 324b to another flip-flop memory 304c, which may wait for a slow clock signal (not shown) before forwarding the error data enable signal 324c to the AND gate 308. The AND gate 308 may transmit the error data 328 to the error logger 212. The error data 328 may be the same signal as the error data 326 resulting from combining the error data 326 with the error data enable signal 324c.

[0052] The error data enable signals 324a, 324ab, 324c can be implemented to enable an asynchronous transfer protocol in which the error data 326 should be stable before the error data 328 is captured at the error logger 212. The enable signal 324a generated from the flip-flop memory 304a can be synchronized by the flip-flop memories 304b, 304c, and the synchronized error data enable signal 324c can be used as a qualifying signal for transferring the error data 326, 328 to the error logger 212. The AND gate 308 can control the transfer of the error data 328 to the error logger 212 based on the reception of the error data enable signal 324c or before the enable signal 324c is synchronized with the slow clock. In other words, before receiving the error data enable signal 324c, the AND gate 308 can output only a low-level signal or a zero (0) value signal to the error logger 212. After receiving the error data enable signal 324c, the logical AND operation of the error data enable signal 324c and the error data 326 at the AND gate 308 can output the error data 328 to the error logger 212.

[0053] The error data 328 can be stored in the memory 310 (e.g., the memory 106 in Figure 1 ) by the error logger 212 in an order relative to other error data received by the error logger. In response to receiving the error data 328, the error logger 212 can sequentially transmit the acknowledgment signals 330a, 330b, 330c, 330d to the error selection module 210 via various flip-flop memories 306a, 306b, 306c. The error logger 212 can transmit the acknowledgment signal 330a to the flip-flop memory 306a. The flip-flop memory 304a can hold the acknowledgment signal 330a until receiving a slow clock signal (not shown) and output the acknowledgment signal 330b to another flip-flop memory 306b. The flip-flop memory 306b can forward the acknowledgment signal 330c to another flip-flop memory 306c, which can wait for a fast clock signal (not shown) before forwarding the acknowledgment signal 330d to the error selection module 210. The acknowledgment signals 330a, 330b, 330c, 330d can indicate to the error selection module 210 that subsequent requests to send error data can be satisfied.

[0054] The error logger 212 can analyze the error data stored at the memory 310 and generate error data 334 and at least one interrupt signal 336, 338 and transmit them to the functional safety unit 214. Based on the number of fault bits associated with the error data stored in the memory 310, the error logger 212 can generate an interrupt signal 336 configured as a single fault indicator and / or an interrupt signal 338 configured as a double fault indicator.

[0055] The functional safety unit 214 can receive error data and store it in a memory 314 (e.g., Figure 1 the memory 106 in). The fault aggregator 316 of the functional safety unit can receive and analyze the interrupt signals 336, 338 from the error logger 212. The fault aggregator 316 can determine whether the interrupt signals 336, 338 are configured as single-bit fault indicators or as double-bit fault indicators. The fault aggregator 316 can transmit an interrupt signal 340 to a safety monitor (not shown), and transmit an error signal 342 in response to determining that the interrupt signal 338 is configured as a single-bit fault indicator, or transmit a warning signal 344 in response to determining that the interrupt signal 336 is configured as a double-bit fault indicator. The safety monitor can respond to the error signal 342 and the warning signal 344 in different ways.

[0056] In some embodiments, the functional safety unit 214 can include a trigger 312 that is configured to transmit an enable signal 332 to the error logger 212. The enable signal 332 can be configured to indicate to the error logger 212 whether the functional safety unit 214 is enabled and available to receive error data 334 and interrupt signals 336, 338 from the error logger 212.

[0057] For ease of explanation and clarity, Figure 3 the example illustrated in shows one hard macro 302 connected to the error logger 212 via a set of connection components that includes synchronizers 218, trigger memories 304a to 304c, 306a to 306c, and AND gates 308, and does not limit the number of hard macros and sets of connection components that can be connected to the error logger 212 in the claims and the specification. Those skilled in the art will understand that any number (two or more) of hard macros and associated sets of connection components can be connected to the error logger 212. For example, the error logger 212 can be a multi-channel interface, and multiple channels can be configured to support multiple hard macros and receive error data from any number of hard macros in parallel. For ease of explanation and clarity, Figure 3 the example illustrated in shows two memory wrappers 204a, 204b for each hard macro 302, and does not limit the number of memory wrappers for each hard macro in the claims and the specification. As described, any number greater than 2 of memory wrappers can be included as part of a hard macro.

[0058] Figure 4 Illustrated is a method 400 for capturing errors by a scalable architecture for error capture using a single error logger according to some embodiments. Referring to Figures 1 to 4 , the method 400 can be implemented in a computing device (e.g., computing device 100), in hardware (e.g., Figure 2 andFigure 3 in the error capture module 208), in software executed in a processor, or in a combination of a software-configured processor and dedicated hardware (e.g., Figure 1 processor 104 in Figure 2 and Figure 3 hard macros 202a, 202b in ), the dedicated hardware including other individual components such as various memories / caches (e.g., Figure 1 memory 106 in Figure 2 and Figure 3 memory 206 in ) and various memory / cache controllers. To cover alternative configurations implemented in various embodiments, the hardware implementing method 400 is referred to herein as an "error handling device". Method 400 may be implemented in parallel by multiple processing devices.

[0059] In block 402, the error handling device may receive error data from a memory (e.g., Figure 1 memory 106 in Figure 2 and Figure 3 memory 206 in ). One or more faulty bits may occur in the memory, resulting in an error, and error data may be generated, including a memory fault interrupt and a memory fault signature for the error at the memory. The memory fault signature may include information about the memory fault, such as a hard macro ID, a memory ID, a memory address, and the hard macro (e.g., Figure 2 and Figure 3 hard macros 202a, 202b in ) and the ECC status of the memory where the fault occurred. The ECC status may be configured to indicate the number of bits at the location where the memory is experiencing a fault. The number of bits may be any number, such as one bit or more bits, including two bits. The ECC status may indicate a single-bit fault of one faulty bit at the location of the memory experiencing the fault. The ECC status may indicate a double-bit fault of two faulty bits at the location of the memory experiencing the fault. In some embodiments, the error handling device that receives error data from the memory in block 402 may be an error capture module (e.g., Figure 2 and Figure 3 error capture module 208 in ).

[0060] In block 404, the error handling device may store the error data. The error handling device may include a memory (e.g., Figure 1 memory 106 in ) such as a register having a sufficient size to store instances of error data from the memory experiencing a memory fault. The error handling device may store the memory fault signature. In some embodiments, the error handling device that stores the error data in block 404 may be an error capture module.

[0061] In block 406, an error handling device may generate a request for sending error data to an error selection module (e.g., Figure 2 and Figure 3 the error selection module 210 therein). Receiving error data from a memory experiencing a memory fault and / or storing the error data may trigger the error handling device to generate a signal as a request for sending the error data to the error selection module. In some embodiments, the signal may include an identifier of the error handling device such that the error selection module may identify the request and / or the priority of the error handling device. In some embodiments, the error handling device that generates a request for sending error data to the error selection module in block 406 may be an error capture module.

[0062] In block 408, the error handling device may transmit the request for sending error data to the error selection module. The error handling device may transmit the generated signal as a request for sending error data to the error selection module. In some embodiments, the signal may include an identifier of the error handling device such that the error selection module may identify the request and / or the priority of the error handling device. In some embodiments, the error handling device that transmits the request for sending error data to the error selection module in block 408 may be an error capture module.

[0063] Figure 5 Illustrated is a method 500 for selecting errors by an extensible architecture for error capture using a single error logger according to some embodiments. Referring to Figures 1 to 5 , method 500 may be implemented in a computing device (e.g., computing device 100), in hardware (e.g., Figure 2 and Figure 3 the error selection module 210 therein), in software executed in a processor, or in a combination of a software-configured processor and dedicated hardware (e.g., Figure 1 processor 104 therein, Figure 2 and Figure 3 hard macros 202a, 202b therein), the dedicated hardware including other individual components such as various memories / caches (e.g., Figure 1 memory 106 therein, Figure 2 and Figure 3 memory 206 therein) and various memory / cache controllers. To cover alternative configurations implemented in various embodiments, the hardware implementing method 500 is referred to herein as an "error handling device". Method 500 may be implemented in parallel by multiple processing devices.

[0064] In block 502, the error handling device may receive from an error capture device (e.g., Figure 2 and Figure 3The error capture device 208) in receives a request to send error data to the error handling device. The error handling device can receive, as a signal for the request to send error data, from the error capture module. In some embodiments, the signal can include an identifier of the error capture module such that the error handling device can identify the request and / or the priority of the error capture module. In some embodiments, the request to send error data can be a request to send error data transmitted in block 408 of method 400 described herein with reference to Figure 4 The error handling device that receives, in block 502, a request from the error capture module to send error data to the error handling device can be an error selection module (e.g., Figure 2 and Figure 3 the error selection module 210) in.

[0065] In decision block 504, the error handling device can determine whether the request to send error data has priority over other requests to send error data. In some embodiments, before extracting error data from the error capture module, the error handling device can receive multiple requests to send error data, such as in block 502. The error handling device can prioritize the outstanding requests to send error data. In some embodiments, the request to send error data can include an identifier of the error capture module that transmitted the request. The error handling device can maintain the priorities of the error capture modules and match the error capture module from which it received the request to send error data with the corresponding priority. The error handling device can compare the priorities of the requests to send error data to determine which request to send error data has priority, and the priority of the request to send error data can be based on the priority of the associated error capture module. In some embodiments, the error handling module that determines in decision block 504 whether the request to send error data has priority over other requests to send error data can be an error selection module.

[0066] In response to determining that the request to send error data does not have priority (i.e., decision block 504 = "no"), the error handling device can again determine in decision block 504 whether the request to send error data has priority over other requests to send error data. In response to determining that the request to send error data has priority (i.e., decision block 504 = "yes"), in optional block 506, the error handling device can retrieve from the error logger (e.g., Figure 2 and Figure 3The error logger 212) in receives an acknowledgment signal for the receipt of error data. The error handling device may be configured to handle a limited amount of error data, such as processing several error data from the error capture module at a time. When the error handling device is processing error data, the error handling device may not be able to process other error data. Once the error handling device receives an acknowledgment of the receipt of error data, the error handling device may no longer need to process that error data and may transition to processing another error data. In some embodiments, receiving an acknowledgment signal for the receipt of error data from the error logger may be optional, since such an acknowledgment may not be required before the error handling device has processed any error data, such as for a particular error management session of the error handling device. For example, an error management session may begin in a computing device (e.g., Figure 1 the computing device 100 in), after which the error handling device resides in the computing device. In this case, the error handling device has not transmitted error data to the error logger during the session. In another example, receiving an acknowledgment signal for the receipt of error data from the error logger may be optional, since other boxes of method 500 (such as optional decision box 506) may be executed whether or not the optional box 506 is implemented. In some embodiments, the error handling device that receives an acknowledgment signal for the receipt of error data in optional box 506 may be the error selection module.

[0067] In optional decision box 508, the error handling device may determine whether an acknowledgment of the receipt of error data has been received. As discussed herein, the error handling device may not process additional error data until the processing of the current error data is complete (which may be signaled by receiving an acknowledgment of the receipt of error data). In some embodiments, the error handling device that determines whether an acknowledgment of the receipt of error data has been received in optional decision box 508 may be the error selection module.

[0068] In response to determining that an acknowledgment of the receipt of error data has not been received (i.e., optional decision box 508 = "no"), in optional box 506, the error handling device may receive again from the error logger an acknowledgment signal for the receipt of error data.

[0069] In response to determining that an acknowledgment of the receipt of error data has been received (i.e., optional decision box 508 = "yes"); in response to determining that the request to send error data has priority (i.e., decision box 504 = "yes"), in box 510, the error handling device may extract error data from the error capture module. The error handling device may extract error data for a request to send error data that is prior to other requests for sending error data. The error data extracted from the error capture module may include for the memory (e.g., Figure 1 the memory 106 in,Figure 2 and Figure 3 In some embodiments, the error handling device that extracts the error data from the error capture module in block 510 may be an error selection module.

[0070] In block 512, the error handling device may transmit the error data to the error logger. The error data transmitted to the error logger may include a memory failure signature. In some embodiments, the error handling device that transmits the error data to the error logger in block 512 may be an error selection module.

[0071] In box 514, the error handling device can update the priority of the error capture module. In some embodiments, the error capture module can be associated with a priority (e.g., assigned a priority). The error handling device can change the priority of the error capture module based on the time of receiving a request from the error capture module relative to the time of receiving a request from other error capture modules, the error data of the transmission error capture module, and / or the confirmation of receiving the error data. In some embodiments, changing the priority can involve managing the priority of the error capture module in a polling manner, in which the priority rotates between a group of error capture modules based on one of the aforementioned standards. In some embodiments, the error handling device that updates the priority of the error capture module in box 514 can be an error selection module.

[0072] Figure 6 A method 600 for logging errors using a scalable architecture for error capture utilizing a single error logger is illustrated according to some embodiments. Figures 1 to 6 The method 600 may be implemented in a computing device (eg, computing device 100), in hardware (eg, Figure 2 and Figure 3 212 in the error logger), in software executed in a processor, or in a software-configured processor and dedicated hardware (e.g., Figure 1 104), the dedicated hardware includes other separate components, such as various memories / caches (e.g., Figure 1 Memory 106 in Figure 2 and Figure 3 To encompass alternative configurations implemented in various embodiments, the hardware implementing method 600 is referred to herein as an "error handling device."

[0073] In block 602, the error handling device may select an error from an error selection module (e.g., Figure 2 and Figure 3The error selection module 210) in receives error data. The error data may include a memory fault signature for an error at a memory (e.g., Figure 1 memory 106 in Figure 2 and Figure 3 memory 206 in). For example, the error data may be the error data transmitted in block 512 of method 500 described herein. In some embodiments, the error handling device that receives the error data from the selection module in block 602 may be an error logger (e.g., Figure 5 and Figure 2 and Figure 3 error logger 212 in).

[0074] In block 604, the error handling device may store the error data at the error logger. The error data may be stored by the error handling device in a memory (e.g., Figure 1 memory 106 in Figure 3 memory 310 in) in an order relative to other error data received by the error handling device. In some embodiments, the error handling device that stores the error data at the error logger in block 604 may be the error logger.

[0075] In block 606, the error handling device may transmit an acknowledgement of the receipt of the error data to the error selection module. The acknowledgement may indicate to the error selection module that the error selection module does not need to continue holding the error data for the error handling device and that subsequent requests for the error data may be satisfied. In some embodiments, the error handling device that transmits the acknowledgement of the receipt of the error data to the error selection module in block 606 may be the error logger.

[0076] In block 608, the error handling device may analyze the error data stored at the error logger. The error data may include information indicating the number of faulty bits in a location of the memory to the error handling device, such as an ECC statistic value. For example, the error handling device may parse an indication of the number of faulty bits from the error data. In some embodiments, the error handling device that analyzes the error data stored at the error logger in block 608 may be the error logger.

[0077] In decision block 610, the error handling device may determine whether the error data indicates a single-bit fault or a double-bit fault. The error handling device may obtain information from the analysis of the error data in block 608 regarding the error data indicating the number of faulty bits in a location of the memory. Based on the information derived from the analysis of the error data, the error handling device may determine whether the error data indicates a single-bit fault or a double-bit fault. In some embodiments, the error handling device that determines whether the error data indicates a single-bit fault or a double-bit fault in decision block 610 may be the error logger.

[0078] In response to determining that the error data indicates a single-bit error (i.e., determining that box 610 = "single"), at box 612, the error handling device may generate a single-bit fault interrupt. The interrupt may be a signal configured to indicate to a functional safety unit (e.g., Figure 2 and Figure 3 the functional safety unit 214 in

[0079] that the error at the location in the memory is caused by a single-bit fault. In some embodiments, the error handling device that generates the single-bit fault interrupt at box 612 may be an error logger.

[0080] In response to determining that the error data indicates a double-bit error (i.e., determining that box 610 = "double"), at box 614, the error handling device may generate a double-bit fault interrupt. The interrupt may be a signal configured to indicate to the functional safety unit that the error at the location in the memory is caused by a double-bit fault. In some embodiments, the error handling device that generates the double-bit fault interrupt at box 614 may be an error logger.

[0081] At box 616, the error handling device may transmit the interrupt to the functional safety unit. Depending on the result of determining box 610, the error handling device may make the single-bit fault interrupt generated at box 612 or the double-bit fault interrupt generated at box 614 available for transmission. Whether the single-bit fault interrupt or the double-bit fault interrupt is available for transmission, the error handling device may transmit the generated available interrupt to the functional safety unit. In some embodiments, the error handling device that transmits the interrupt to the functional safety unit at box 616 may be an error logger.

[0081] At box 618, the error handling device may transmit the error data to the functional safety unit. The error data may be at least one of the error data stored at the error logger (the error data that is analyzed at box 608 to determine which interrupt to generate). In other words, the error data is associated with the generated interrupt and is transmitted to the functional safety unit. The error data may include a memory fault signature. In some embodiments, the error handling device that transmits the error data to the functional safety unit at box 618 may be an error logger.

[0082] Figure 7 Illustrated is a method 700 for notifying of errors by a scalable architecture for error capture using a single error logger according to some embodiments. Referring to Figures 1 to 7 , method 700 may be in a computing device (e.g., computing device 100), in hardware (e.g., Figure 2 and Figure 3 the functional safety unit 214 in Figure 1implemented in combination with the processor 104), and the dedicated hardware includes other individual components such as various memories / caches (e.g., Figure 1 the memory 106 in Figure 2 and Figure 3 the memory 206 in

[0083] In block 702, the error handling device may receive an interrupt from an error logger (e.g., Figure 2 and Figure 3 the error logger 212 in Figure 6 The interrupt may be the interrupt transmitted in block 616 of method 600 described herein. The interrupt may be a single-bit fault interrupt configured to indicate to the error handling device that an error at the location of a memory (e.g., Figure 1 the memory 106 in Figure 2 and Figure 3 the memory 206 in Figure 2 and Figure 3 the functional safety unit 214 in

[0084] In block 704, the error handling device may receive error data from the error logger. The error data may be the error data transmitted in block 618 of method 600 described herein. The error data may include a memory fault signature for the error at the memory. In some embodiments, the error handling device that receives the interrupt from the error logger in block 704 may be a functional safety unit (e.g., Figure 6 Figure 2 and Figure 3 the functional safety unit 214 in

[0085] In block 706, the error handling device may store the error data at the functional safety unit. The error data may be stored by the error handling device in a memory (e.g., Figure 1 the memory 106 in Figure 3 the memory 314 in

[0086] ​In block 708, the error handling device may analyze the received interrupt. The interrupt may be a single-bit fault interrupt or a double-bit fault interrupt. Based on the received interrupt, the error handling device may know how many bits in the memory location are faulty. For example, the error handling device may determine the number of faulty bits according to the indication provided by such interrupt. In some embodiments, the error handling device that analyzes the received interrupt in block 708 may be a functional safety unit.

[0087] In determination block 710, the error handling device may determine whether the interrupt indicates a single-bit fault or a double-bit fault. The error handling device may know the number of faulty bits in the memory location from the analysis of the interrupt in block 708. Based on the analysis of the interrupt, the error handling device may determine whether the interrupt indicates a single-bit fault or a double-bit fault. In some embodiments, the error handling device that determines whether the interrupt indicates a single-bit fault or a double-bit fault in determination block 710 may be a functional safety unit.

[0088] In response to determining that the interrupt indicates a single-bit error (i.e., determination block 710 = "single"), in block 712, the error handling device may generate an error signal. The error signal may be a signal configured to indicate to the safety monitor that the error at the location in the memory is caused by a single-bit fault so that the safety monitor may process the error according to the procedure for single-bit faults. In some embodiments, the error handling device that generates the error signal in block 712 may be a functional safety unit.

[0089] In response to determining that the interrupt indicates a double-bit error (i.e., determination block 710 = "double"), in block 714, the error handling device may generate a warning signal. The warning signal may be a signal configured to indicate to the safety monitor that the error at the location in the memory is caused by a double-bit fault so that the safety monitor may process the error according to the procedure for double-bit faults. In some embodiments, the error handling device that generates the warning signal in block 714 may be a functional safety unit.

[0090] In block 716, the error handling device may generate an interrupt to the safety monitor. The interrupt may be a signal configured to notify the safety monitor of the error that has occurred in the memory and extract the error data stored at the functional safety unit so that the safety monitor may use the error data for the error at the memory to process the error. In some embodiments, the error handling device that generates the interrupt to the safety monitor in block 716 may be a functional safety unit.

[0091] In block 718, the error handling device may transfer interrupts and signals to the safety monitor. Based on the result of determining block 710, the error handling device may make the error signal generated in block 712 or the warning signal generated in block 614 available for transfer. Whether the error signal or the warning signal is available for transfer, the error handling device may transfer the generated available signals and interrupts to the safety monitor. In some embodiments, the error handling device that transfers interrupts and signals to the safety monitor in block 718 may be a functional safety unit.

[0092] Systems according to various embodiments, including but not limited to the embodiments referenced above Figures 1 to 7 and described herein, may be implemented in a wide variety of computing systems including mobile computing devices, examples of which are illustrated in Figure 8 FIG. The mobile computing device 800 may include a processor 802 that is coupled to a touchscreen controller 804 and an internal memory 806. The processor 802 may be one or more multi-core integrated circuits designated for general or specific processing tasks. The internal memory 806 may be volatile or non-volatile memory and may also be secure and / or encrypted memory, or non-secure and / or unencrypted memory, or any combination thereof. Examples of memory types that may be utilized include but are not limited to DDR, LPDDR, GDDR, WIDEIO, RAM, SRAM, DRAM, P-RAM, R-RAM, M-RAM, STT-RAM, and embedded DRAM. The touchscreen controller 804 and the processor 802 may also be coupled to a touchscreen panel 812, such as a resistive sensing touchscreen, a capacitive sensing touchscreen, an infrared sensing touchscreen, etc. Additionally, the display of the mobile computing device 800 need not have touchscreen capabilities.

[0093] The mobile computing device 800 may have one or more radio signal transceivers 808 (e.g., Peanut, Bluetooth, ZigBee, Wi-Fi, RF radio) and antennas 810 that are coupled to each other and / or coupled to the processor 802 for transmitting and receiving communications. The transceivers 808 and the antennas 810 may be used with the circuitry mentioned above to implement various wireless transmission protocol stacks and interfaces. The mobile computing device 800 may include a cellular network wireless modem chip 816 that enables communication via a cellular network and is coupled to the processor.

[0094] The mobile computing device 800 may include a peripheral device connection interface 818 coupled to a processor 802. The peripheral device connection interface 818 may be configured to accept a single type of connection, or may be configured to accept various types of physical and communication connections, such as Universal Serial Bus (USB), FireWire, Thunderbolt, or PCIe, whether common or proprietary. The peripheral device connection interface 818 may also be coupled to a similarly configured peripheral device connection port (not shown).

[0095] The mobile computing device 800 may also include a speaker 814 for providing audio output. The mobile computing device 800 may also include a housing 820 for housing all or some of the components described herein, the housing being constructed of plastic, metal, or a combination of materials. The mobile computing device 800 may include a power supply 822 coupled to the processor 802, such as a disposable or rechargeable battery. The rechargeable battery may also be coupled to the peripheral device connection port to receive a charging current from a source external to the mobile computing device 800. The mobile computing device 800 may also include physical buttons 824 for receiving user input. The mobile computing device 800 may also include a power button 824 for turning the mobile computing device 800 on and off.

[0096] Systems according to various embodiments, including but not limited to the embodiments referenced above Figures 1 to 7 may be implemented in a wide variety of computing systems, including a laptop computer 900, an example of which is illustrated in Figure 9 Many laptop computers include a touchpad touch surface 917 that serves as a pointing device for the computer and may thus receive gestures similar to drag, scroll, and tap gestures implemented on a computing device equipped with a touchscreen display and as described above. The laptop computer 900 will typically include a processor 902 coupled to volatile memory 912 and a mass non-volatile memory, such as a disk drive 913 of flash memory. Additionally, the computer 900 may have one or more antennas 908 for transmitting and receiving electromagnetic radiation, connectable to a wireless data link, and / or a cellular phone transceiver 916 coupled to the processor 902. The computer 900 may also include a floppy disk drive 914 and a compact disc (CD) drive 915 coupled to the processor 902. In a notebook configuration, the computer housing includes a touchpad 917, a keyboard 918, and a display 919, all of which are coupled to the processor 902. Other configurations of computing devices may include a computer mouse or trackball, well known to be coupled to a processor (e.g., via a USB input), which may also be used in conjunction with various embodiments.

[0097] According to various embodiments, including but not limited to those referenced above Figures 1 to 7The systems (such as those described in the embodiments) can also be implemented in a fixed computing system, such as any one of a variety of commercially available servers. Figure 10 An example server 1000 is illustrated in Figure 10 . Such a server 1000 generally includes one or more multi-core processor assemblies 1001 coupled to volatile memory 1002 and a large-capacity non-volatile memory, such as a disk drive 1004. As Figure 10 illustrated, the multi-core processor assembly 1001 can be added to the server 1000 by inserting it into a rack of the assembly. The server 1000 can also include a floppy disk drive, a compact disk (CD) or digital versatile disk (DVD) drive 1006 coupled to the processor 1001. The server 1000 can also include a network access port 1003 coupled to the multi-core processor assembly 1001 for establishing a network interface connection to a network 1005, such as a local area network, the Internet, a public switched telephone network, and / or a cellular data network (e.g., CDMA, TDMA, GSM, PCS, 3G, 4G, LTE, 5G, or any other type of cellular data network) coupled to other broadcast system computers and servers.

[0098] According to various embodiments, including but not limited to the embodiments described above with reference to Figures 1 to 7 the methods and devices for implementing such methods can be implemented in a variety of computing systems, including an embedded vehicle computing system 1100, an example of which is illustrated in Figures 11A to 11C The embedded vehicle computing system 1100 can include a vehicle control unit 1140, such as an ECU, which can include a processor, such as a CPU, an AI processor, etc. The embedded vehicle computing system 1100 can include a plurality of sensors 1142 to 1170, including a satellite geolocation system receiver 1142, an accelerometer 1144, occupancy sensors 1146, 1148, 1150, 1152, tire pressure sensors 1154, 1156, cameras 1158, 1160, microphones 1162, 1164, impact sensors 1166, and object detection and ranging sensors 1168, 1170.

[0099] A plurality of sensors 1142 to 1170 disposed in or on a vehicle can be used for various purposes, such as autonomous and semi-autonomous navigation and control, collision avoidance, position determination, etc., and to provide sensor data about objects and people in or on the vehicle. Sensors 1142 to 1170 can include one or more sensors from a variety of sensors capable of detecting various information useful for navigation and collision avoidance. Each of sensors 1142 to 1170 can communicate wired or wirelessly with control unit 1140 and with each other. Specifically, the sensors can include one or more cameras 1158, 1160 or other optical or optoelectronic sensors. The sensors can also include other types of object detection and ranging sensors 1168, 1170 (e.g., IR sensors and ultrasonic sensors). The sensors can also include tire pressure sensors 1154, 1156, humidity sensors, temperature sensors, satellite geolocation sensors 1142, control input sensors 1145, accelerometers 1144, vibration sensors, gyroscopes, gravimeters, impact sensors 1166, dynamometers, stress gauges, strain sensors, fluid sensors, chemical sensors, gas content analyzers, pH sensors, radiation sensors, Geiger counters, neutron detectors, biomaterial sensors, microphones 1162, 1164, occupancy sensors 1146, 1148, 1150, 1152, proximity sensors and other sensors.

[0100] The vehicle control unit 1140 can include one or more processors configured with processor-executable instructions to perform navigation and collision avoidance operations using information received from various sensors, particularly cameras 1158, 1160. In some embodiments, the control unit 1140 can use the distances and relative positions (e.g., relative azimuth angles) obtainable from object and ranging sensors 1168, 1170 to supplement the processing of camera images. The control unit 1140 can also be configured to use information about other vehicles determined using various embodiments to control steering, braking, and speed when the vehicle is operating in autonomous or semi-autonomous mode. The vehicle control unit 1140 can include one or more processors configured with processor-executable instructions to receive information from sensors 1142 to 1170 and use such information to perform operations as further described herein. In various embodiments, the vehicle control unit 1140 can include the vehicle's V2X on-board equipment, can be a component of the vehicle's V2X on-board equipment, or can communicate with the vehicle's V2X on-board equipment.

[0101] Figure 11CFIG. 0 is a block diagram of components of an embedded vehicle computing system 1100 that is illustrative of components and support systems suitable for implementing various embodiments. The embedded vehicle computing system 1100 can include a control unit 1140, which can include various circuits and devices for controlling the operation of a vehicle. The control unit 1140 can include a processor 1140a (such as a CPU, an AI processor, etc.), a memory 1140b, an input module 1140c, an output module 1140d, and a radio module 1140e. The control unit 1140 can be coupled to a drive control component 1172a, a navigation component 1172b, and one or more sensors 1172c of the embedded vehicle computing system 1100 and is configured to control the drive control component, the navigation component, and the one or more sensors. The control unit 1140 can communicate with V2X on-board equipment 1140f. The processor 1140a can be configured with processor-executable instructions to control the maneuvering, navigation, and / or other operations of the vehicle, including operations of various embodiments, including collecting and analyzing real-world autonomous vehicle operation data collected from the sensors 1172c. The processor 1140a can be coupled to the memory 1140b. The V2X on-board equipment 1140f can include one or more processors 1140g, which are configured with processor-executable instructions to perform various operations of various embodiments, including communicating real-world autonomous vehicle operation data collected from the sensors 1172c between the embedded vehicle computing system 1200 and a computing device on a wireless communication device 1112 and / or a communication network (e.g., a core network 1132) via the radio module 1140e.

[0102] The radio module 1140e can be configured for wireless communication. The radio module 1140e can exchange signals (such as command signals for controlling maneuvering, signals from a navigation facility, data signals, etc.) with a network transceiver (e.g., a base station 1110) via a communication link 1122 and can provide these signals to the processors 1140a, 1140g, and / or the navigation unit 1172b. In some embodiments, the radio module 1140e can enable the embedded vehicle computing system 1100 to communicate with the wireless communication device 1112 via a wireless communication link 1124. The wireless communication link 1124 can be a bi-directional or uni-directional communication link and can use one or more communication protocols.

[0103] The input module 1140c can receive sensor data from one or more vehicle sensors 1172c and electronic signals from other components, including the drive control component 1172a and the navigation component 1172b. The output module 1140d can communicate with or activate various components of the embedded vehicle computing system 1100, including the drive control component 1172a, the navigation component 1172b, and the sensors 1172c.

[0104] The control unit 1140 can be coupled to the drive control component 1172a to control physical elements of the vehicle related to the vehicle's maneuvering and navigation, such as engines, motors, throttles, steering elements, flight control elements, braking or decelerating elements, etc. The drive control component 1172a can also include components for controlling other devices of the vehicle, and these other devices include internal environment controls (e.g., air conditioning and heating), external and / or internal lighting, internal and / or external information displays (which can include display screens or other devices for displaying information), safety devices (e.g., tactile devices, audible alarms, etc.), and other similar devices.

[0105] The control unit 1140 can be coupled to the navigation component 1172b, and can receive data from the navigation component 1172b and be configured to use such data to determine the current position and orientation of the vehicle, as well as an appropriate route to a destination. The navigation component 1172b can include or be coupled to a GNSS receiver system (e.g., one or more Global Positioning System (GPS) receivers) that enables the embedded vehicle computing system 800 to determine its current position using Global Navigation Satellite System (GNSS) signals. Alternatively or in addition, the navigation component 1172b can include a radio navigation receiver for receiving navigation beacons or other signals from radio nodes, such as Wi-Fi access points, cellular network sites, radio stations, remote computing devices, other vehicles, etc. By controlling the drive control element 1172a, the processor 1140a can control the vehicle to navigate and maneuver. The processor 1140a, 1140g, and / or the navigation component 1172b can be configured to communicate with network elements, such as servers in a communication network (e.g., the core network 1132), via wireless communication links 1122, 1126 to receive commands for controlling maneuvers, receive data useful for navigation, provide real-time position reports, etc.

[0106] The control unit 1140 can be coupled to one or more sensors 1172c. The sensors 1172c can include the sensors 1142 to 1170 as described, and can be configured to provide various data to the processors 1140a, 1140g.

[0107] Although the control unit 1140 is described as including separate components, in some embodiments, some or all of the components (e.g., processor 1140a, memory 1140b, input module 1140c, output module 1140d, and radio module 1140e) may be integrated in a single device or module (such as a SoC processing device). Such a SoC processing device may be configured for use in a vehicle and be configured with, for example, processor-executable instructions executed in processor 1140a to perform operations for navigation and collision avoidance.

[0108] Specific implementation examples are described in the following paragraphs. Although some of the specific implementation examples in the following are described according to example methods, additional example implementations may include: example methods implemented by a computing device discussed in the following paragraphs, the computing device including a processor configured with processor-executable instructions for performing the operations of the example methods; example methods implemented by a computing device discussed in the following paragraphs, the computing device including components for performing the functions of the example methods; and example methods implemented as a non-transitory processor-readable storage medium storing processor-executable instructions thereon, the processor-executable instructions configured to cause a processor of the computing device to perform the operations of the example methods.

[0109] Example 1. A method for error capture implemented in a computing device, the method comprising: receiving, at an error logger, multiple error data for multiple memories of multiple processors, wherein the multiple memories of the multiple processors include a first memory of a first processor, and the multiple error data includes first error data for the first memory of the first processor, the first error data including an identification of at least one faulty bit of the first memory.

[0110] Example 2. The method according to claim 1, the method further comprising receiving, at multiple error capture modules, the multiple error data for the multiple memories of the multiple processors, including receiving the first error data at an error capture module among the multiple error capture modules.

[0111] Example 3. The method according to claim 1, the method further comprising: receiving, at an error selection module for the first processor, a plurality of requests from a plurality of error capture modules for the first processor, wherein each request of the plurality of requests is configured to indicate to the error selection module that at least one error data of the plurality of error data is stored at an error capture module of the plurality of error capture modules; and in response to a first request from a first error capture module of the plurality of error capture modules among the plurality of requests taking precedence over a second request from a second error capture module of the plurality of error capture modules among the plurality of requests, extracting, by the error selection module, the first error data from the first error capture module.

[0112] Example 4. The method according to claim 3, the method further comprising: transmitting the first error data to the error logger; and storing the first error data at the error logger in an order relative to stored error data in a memory of the plurality of memories of the plurality of processors, wherein the plurality of error data includes the stored error data.

[0113] Example 5. The method according to claim 3, the method further comprising: transmitting, from the error logger to the error selection module, a first acknowledgment signal, the first acknowledgment signal being configured to indicate receipt of the first error data; and in response to the second request and the first acknowledgment signal, extracting, by the error selection module, second error data from the second error capture module.

[0114] Example 6. The method according to claim 5, wherein the second request takes precedence over a third request from a third error capture module of the plurality of error capture modules among the plurality of requests, the method further comprising: transmitting, from the error logger to the error selection module, a second acknowledgment signal, the second acknowledgment signal being configured to indicate receipt of the second error data; and in response to the third request and the second acknowledgment signal, extracting, by the error selection module, third error data from the third error capture module.

[0115] Example 7. The method according to claim 1, the method further comprising: receiving, at the error logger, the first error data for the first memory of the first processor, wherein the first error data includes an identification of a number of fault bits; in response to the identification of the number of fault bits being one bit, generating a first interrupt signal configured as a single fault indicator; and in response to the identification of the number of fault bits being two bits, generating a second interrupt signal configured as a double fault indicator.

[0116] Example 8. The method according to claim 7, the method further comprising: receiving, at the functional safety unit, a third interrupt signal from the error logger; generating, by the functional safety unit, a first safety signal in response to the third interrupt signal being the first interrupt signal; and generating, by the functional safety unit, a second safety signal in response to the third interrupt signal being the second interrupt signal.

[0117] Example 9. The method according to claim 1, wherein the plurality of error data is configured with information identifying at least one faulty bit cell location of the memory.

[0118] Example 10. The method according to claim 1, wherein the error logger is a single error logger for the plurality of memories of the plurality of processors.

[0119] Computer program code, or "program code", for execution on a programmable processor to perform the operations of the various implementations can be written in a high-level programming language such as C, C++, C#, Smalltalk, Java, JavaScript, Visual Basic, Structured Query Language (e.g., Transact-SQL), Perl, or in various other programming languages. As used in this application, program code or a program stored on a computer-readable storage medium can refer to machine language code (such as, object code) in a format understandable by a processor.

[0120] The foregoing method descriptions and process flow diagrams are provided only as illustrative examples and are not intended to require or imply that the operations of the various implementations must be performed in the order presented. As will be appreciated by those skilled in the art, the order of the operations in the foregoing implementations can be performed in any order. Words such as "thereafter", "then", "next", etc. are not intended to limit the order of the operations; these words are only used to guide the reader through the description of the method. Additionally, any reference to an element of a claim in the singular form (e.g., a reference using the articles "a", "an", or "the") should not be construed as limiting the element to the singular.

[0121] The various illustrative logical blocks, modules, circuits, and algorithm operations described in connection with the various implementations can be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, the various illustrative components, blocks, modules, circuits, and operations have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. While those skilled in the art may implement the described functionality in different ways for each particular application, such specific implementation decisions should not be interpreted as causing a departure from the scope of the claims.

[0122] The hardware for implementing the various illustrative logics, logic blocks, modules, and circuits described in connection with the embodiments disclosed herein can be implemented or executed using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof that is designed to perform the functions described herein. While a general-purpose processor may be a microprocessor, in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Alternatively, some operations or methods may be performed by circuitry specific to a given function.

[0123] In one or more embodiments, the described functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more instructions or code on a non-transitory computer-readable medium or a non-transitory processor-readable medium. The operations of the methods or algorithms disclosed herein may be implemented in a processor-executable software module that may reside on a non-transitory computer-readable or processor-readable storage medium. A non-transitory computer-readable or processor-readable storage medium may be any storage medium that can be accessed by a computer or a processor. By way of example and not limitation, such non-transitory computer-readable or processor-readable media may include RAM, ROM, EEPROM, flash memory, CD-ROM or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired program code in the form of instructions or data structures and that can be accessed by a computer. As used herein, disk and optical disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks generally reproduce data magnetically, while optical discs reproduce data optically with lasers. Combinations of the above are also included within the scope of non-transitory computer-readable and processor-readable media. Additionally, the operations of a method or algorithm may reside as one code and / or instruction or any combination or collection of codes and / or instructions on a non-transitory processor-readable medium and / or a computer-readable medium that can be incorporated into a computer program product.

[0124] The foregoing description of the disclosed embodiments is provided to enable any person skilled in the art to practice or use the claims. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and implementations without departing from the scope of the claims. Thus, the present disclosure is not intended to be limited to the embodiments and implementations described herein, but rather should be accorded the broadest scope consistent with the appended claims and the principles and novel features disclosed herein.

Claims

1. A method for error capture implemented in a computing device, the method comprising: Receiving, at an error logger, multiple error data for multiple memories of multiple processors, wherein the multiple memories of the multiple processors include a first memory of a first processor, and the multiple error data includes first error data for the first memory of the first processor, the first error data including an identification of at least one faulty bit of the first memory.

2. The method according to claim 1, the method further comprising: Receiving, at multiple error capture modules, the multiple error data for the multiple memories of the multiple processors, including receiving the first error data at an error capture module among the multiple error capture modules.

3. The method according to claim 1, the method further comprising: Receiving, at an error selection module for the first processor, multiple requests from multiple error capture modules for the first processor, wherein each request among the multiple requests is configured to indicate to the error selection module that at least one error data among the multiple error data is stored at an error capture module among the multiple error capture modules; And In response to a first request from a first error capture module among the multiple error capture modules being prior to a second request from a second error capture module among the multiple error capture modules among the multiple requests, extracting, by the error selection module, the first error data from the first error capture module.

4. The method according to claim 3, the method further comprising: Transmitting the first error data to the error logger; And Storing, at the error logger, the first error data in an order relative to stored error data of memories among the multiple memories of the multiple processors, wherein the multiple error data includes the stored error data.

5. The method according to claim 3, the method further comprising: Transmitting, from the error logger to the error selection module, a first acknowledgment signal, the first acknowledgment signal being configured to indicate receipt of the first error data; And In response to the second request and the first acknowledgment signal, extracting, by the error selection module, second error data from the second error capture module.

6. The method according to claim 5, wherein the second request is prior to a third request from a third error capture module among the multiple error capture modules among the multiple requests, The method further comprising: Transmitting, from the error logger to the error selection module, a second acknowledgment signal, the second acknowledgment signal being configured to indicate receipt of the second error data; And In response to the third request and the second acknowledgment signal, extracting, by the error selection module, third error data from the third error capture module.

7. The method according to claim 1, the method further comprising: Receiving, at the error logger, the first error data for the first memory of the first processor, wherein the first error data includes an identification of the number of faulty bits; In response to the identification of the number of fault bits being one bit, generate a first interrupt signal configured as a unit fault indicator; and In response to the identification of the number of fault bits being two bits, generate a second interrupt signal configured as a double-bit fault indicator.

8. The method according to claim 7, the method further comprising: Receiving, at the functional safety unit, a third interrupt signal from the error logger; In response to the third interrupt signal being the first interrupt signal, generating, by the functional safety unit, a first safety signal; and In response to the third interrupt signal being the second interrupt signal, generating, by the functional safety unit, a second safety signal.

9. The method according to claim 1, wherein the plurality of error data is configured with information identifying at least one faulty bit cell location of the memory.

10. The method according to claim 1, wherein the error logger is a single error logger for the plurality of memories of the plurality of processors.

11. A computing device, the computing device comprising: A plurality of memories; A plurality of processors, the plurality of processors being coupled to the plurality of memories; and An error logger, the error logger being coupled to the plurality of memories and configured to receive, at the error logger, a plurality of error data for the plurality of memories of the plurality of processors, wherein the plurality of memories of the plurality of processors includes a first memory of a first processor, and the plurality of error data includes first error data for the first memory of the first processor, the first error data including an identification of at least one faulty bit of the first memory.

12. The computing device according to claim 11, the computing device further comprising a plurality of error capture modules, the plurality of error capture modules being configured to receive the plurality of error data for the plurality of memories of the plurality of processors, including receiving the first error data at an error capture module among the plurality of error capture modules.

13. The computing device according to claim 12, the computing device further comprising an error selection module for the first processor, wherein the error selection module is configured to: Receive a plurality of requests from the plurality of error capture modules for the first processor, wherein each request among the plurality of requests is configured to indicate to the error selection module that at least one error data among the plurality of error data is stored at an error capture module among the plurality of error capture modules; and In response to a first request from a first error capture module among the plurality of error capture modules being prior to a second request from a second error capture module among the plurality of error capture modules in the plurality of requests, extract the first error data from the first error capture module.

14. The computing device according to claim 13, wherein the error logger is further configured to: Store the first error data in an order relative to stored error data of the memories among the multiple memories for the multiple processors, where the multiple error data includes the stored error data.

15. The computing device according to claim 13, wherein: The error recorder is further configured to transmit a first acknowledgement signal to the error selection module, the first acknowledgement signal being configured to indicate receipt of the first error data; and The error selection module is further configured to extract second error data from the second error capture module in response to the second request and the first acknowledgement signal.

16. The computing device according to claim 15, wherein: The second request has priority over a third request from a third error capture module among the multiple error capture modules in the multiple requests; The error recorder is further configured to transmit a second acknowledgement signal to the error selection module, the second acknowledgement signal being configured to indicate receipt of the second error data; and The error selection module is further configured to extract third error data from the third error capture module in response to the third request and the second acknowledgement signal.

17. The computing device according to claim 11, wherein the error recorder is further configured to: Receive the first error data for the first memory of the first processor, where the first error data includes an identification of a number of faulty bits; Generate a first interrupt signal configured as a single-bit fault indicator in response to the identification of the number of faulty bits being one bit; and Generate a second interrupt signal configured as a two-bit fault indicator in response to the identification of the number of faulty bits being two bits.

18. The computing device according to claim 17, the computing device further comprising a functional safety unit, the functional safety unit communicating with the error recorder and being configured to: Receive a third interrupt signal from the error recorder; Generate a first safety signal unit in response to the third interrupt signal being the first interrupt signal; And Generate a second safety signal in response to the third interrupt signal being the second interrupt signal.

19. The computing device according to claim 11, wherein the multiple error data is configured with information identifying at least one faulty bit cell location of the memory.

20. The computing device according to claim 11, wherein the error recorder is a single error recorder for the multiple memories of the multiple processors.

21. A computing device, the computing device comprising: Multiple memories; Multiple processors, the multiple processors being coupled to the multiple memories; An error recorder, the error recorder being coupled to the multiple memories; And Means for receiving, at the error recorder, multiple error data for the multiple memories of the multiple processors The multiple memories of the multiple processors include a first memory of a first processor, and the multiple error data includes first error data for the first memory of the first processor, the first error data including an identification of at least one faulty bit of the first memory.

22. The computing device according to claim 21, the computing device further comprising: a plurality of error capture modules; and means for: receiving, at the plurality of error capture modules, the multiple error data for the multiple memories of the multiple processors, including receiving the first error data at an error capture module among the plurality of error capture modules.

23. The computing device according to claim 21, the computing device further comprising: a plurality of error capture modules; an error selection module for the first processor; means for receiving, at the error selection module for the first processor, a plurality of requests from the plurality of error capture modules for the first processor, wherein each request of the plurality of requests is configured to indicate to the error selection module that at least one error data of the multiple error data is stored at an error capture module among the plurality of error capture modules; and means for the error selection module to extract the first error data from the first error capture module in response to a first request from a first error capture module among the plurality of error capture modules taking precedence over a second request from a second error capture module among the plurality of error capture modules in the plurality of requests.

24. The computing device according to claim 23, the computing device further comprising: means for transferring the first error data to the error logger; and means for storing the first error data at the error logger in an order relative to stored error data of the memories in the multiple memories of the multiple processors, wherein the multiple error data includes the stored error data.

25. The computing device according to claim 23, the computing device further comprising: means for transferring a first acknowledgement signal from the error logger to the error selection module, the first acknowledgement signal being configured to indicate receipt of the first error data; and means for the error selection module to extract second error data from the second error capture module in response to the second request and the first acknowledgement signal.

26. The computing device according to claim 25, wherein the second request takes precedence over a third request from a third error capture module among the plurality of error capture modules, the computing device further comprising: means for transferring a second acknowledgement signal from the error logger to the error selection module, the second acknowledgement signal being configured to indicate receipt of the second error data; and means for the error selection module to extract third error data from the third error capture module in response to the third request and the second acknowledgement signal.

27. The computing device according to claim 21, the computing device further comprising: means for receiving at the error logger the first error data for the first memory of the first processor, wherein the first error data includes an identification of the number of fault bits; means for generating a first interrupt signal configured as a single fault indicator in response to the identification of the number of fault bits being one bit; and means for generating a second interrupt signal configured as a double-bit fault indicator in response to the identification of the number of fault bits being two bits.

28. The computing device according to claim 27, the computing device further comprising: a functional safety unit; means for receiving at the functional safety unit a third interrupt signal from the error logger; means for generating a first safety signal by the functional safety unit in response to the third interrupt signal being the first interrupt signal; and means for generating a second safety signal by the functional safety unit in response to the third interrupt signal being the second interrupt signal.

29. The computing device according to claim 21, wherein: the plurality of error data is configured with information identifying at least one faulty fault bit cell location of the memory; and the error logger is a single error logger for the plurality of memories of the plurality of processors.

30. A non-transitory processor-readable medium having processor-executable instructions stored thereon, the processor-executable instructions being configured to cause a processor of a computing device to perform operations, the operations including: receiving at an error logger a plurality of error data for a plurality of memories of a plurality of processors, wherein the plurality of memories of the plurality of processors includes a first memory of a first processor, and the plurality of error data includes first error data for the first memory of the first processor, the first error data including an identification of at least one fault bit of the first memory.

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