PLC system control method and device based on dynamic address allocation and storage medium

Abstract

The invention relates to the technical field of industrial automation, in particular to a PLC system control method and device based on dynamic address allocation and a storage medium, and the method comprises the steps that S1, a CPU module obtains a physical ID of an IO module; s2, generating a unique logic address for each physical ID, and establishing a mapping database; s3, the CPU module carries out handshake by taking the physical ID of the IO module as a communication identifier, and allocates the corresponding logic address to the corresponding IO module as a dynamic address; and S4, in the running process, the CPU module monitors the online state of the IO module through a heartbeat detection mechanism, releases the dynamic logic address of the offline IO module and updates the mapping database, and if a new IO module is online, the CPU module allocates the unoccupied logic address according to the physical ID number of the new IO module. According to the method, the unique logic address is generated for the physical ID, the security of the IO module is improved, the dynamic address is reallocated after the new IO module is online, the address allocation flexibility is improved, the physical ID and the dynamic address of the offline IO module are released, and limited address resources are saved.

Description

Technical Field

[0001] The present invention relates to the technical field of industrial automation, and particularly to a PLC system control method, device and storage medium based on dynamic address allocation. Background Art

[0002] The PLC (Programmable Logic Controller) is an industrial control device that has developed rapidly and been widely used since the 1960s. It is one of the three major pillars of modern industrial automation. It uses a programmable memory to store user instructions and completes certain logical, sequential, timing, counting, arithmetic and certain defined functions through digital or analog input / output to control various types of mechanical equipment or production processes. In a PLC system, each functional module adopts a modular design, and communication between the CPU and the IO module is carried out through a backplane bus. The module address needs to be assigned to the IO module through the backplane bus communication method to realize data communication between the CPU module and the IO module.

[0003] In the prior art, many attempts have been made on PLC address allocation. In the patent application publication number CN114935909A, titled "A PLC System and Daisy Chain Configuration Method", the controller and the IO module are configured in a daisy chain through an IO. After receiving the message sent by the previous IO module, the IO module accumulates the address. However, this method requires additional configuration of IO lines in hardware, and the address allocation adopts a sequential accumulation method, and the address allocation is fixed. When a certain IO module fails, the address allocation of all subsequent IO modules fails.

[0004] In the patent application publication number CN108897277B, titled "An Independent IO Module Address Automatic Allocation Method and Structure for a PLC", each slot on the backplane has a fixed address, and the address is allocated to each IO module through a hardware method. This method limits the flexibility of backplane communication. Summary of the Invention

[0005] The purpose of the present invention is to solve the disadvantages existing in the prior art, and provides a PLC system control method based on dynamic address allocation, including the following steps: S1: After the PLC system is powered on, the CPU module obtains the unique physical ID of the ARM chip of the IO module through the communication bus and stores the physical ID in the central database; S2: The CPU module calls a true random number generator to generate a unique logical address for each physical ID, establishes a mapping database between the physical ID and the logical address, and records information including the address status, the last communication timestamp, and the unresponsive count counter; S3: The CPU module performs handshake via the communication bus using the physical ID of the IO module as the communication identifier, and allocates the corresponding logical address as a dynamic address to the corresponding IO module, thereby completing address binding and communication handshake; S4: During the operation of the system, the CPU module monitors the online status of the IO module through the heartbeat detection mechanism. If the IO module is offline, the dynamic logical address of the offline IO module is released and the mapping database is updated. If a new IO module is online, the CPU module allocates an unoccupied logical address according to its physical ID number, and updates the central database, the mapping database and the communication binding.

[0006] Preferably, in step S2, the CPU module calls a true random number generator to generate a unique logical address for each physical ID, further comprising: The CPU module calls a true random number generator to generate a random number for each physical ID; The CPU module verifies whether the newly generated random number has been allocated by traversing the mapping database, and allocates it if it has not been allocated, and processes it through the exception handling mechanism if it has been allocated; When the generated random number meets the uniqueness requirement, the physical ID is associated with the corresponding logical address, the mapping database is updated, and the address status is recorded as allocated and the current last communication timestamp.

[0007] Preferably, in step S4, the CPU module monitors the online status of the IO module through a heartbeat detection mechanism, including: The CPU module periodically sends heartbeat requests to the IO modules. If an IO module returns a response within the specified time, the CPU module resets the non-response counter of the IO module to 0 and updates the last communication timestamp of the module in the database. If an IO module does not return a response within the specified time, the CPU module adds 1 to the non-response counter of the module. The CPU module checks the counter value of the number of consecutive unresponsive times of the IO module. If the counter value of the unresponsive times exceeds the preset threshold, it is determined to be offline. When a new IO module is connected to the system, the IO module sends a registration request for its physical ID to the CPU module through the communication bus. After the CPU module receives the registration request, the CPU verifies the legitimacy of the ID and determines it to be a new IO module.

[0008] Preferably, in step S4, releasing the dynamic address of the offline IO module and updating the database includes: The CPU module queries the mapping database according to the physical ID number of the offline IO module to find the corresponding logical address and related records; Update the address status flag of the record to the recyclable status, and after a preset delay period, if the IO module still fails to resume online, the CPU module deletes the entry from the mapping database, releases the corresponding logical address resources, so as to be reallocated to newly connected IO modules subsequently.

[0009] Preferably, in step S4, when a new IO module goes online, the CPU module allocates an unoccupied logical address according to its physical ID number, and updates the central database, the mapping database and communication binding, including: First, reuse an unoccupied random number from the released address pool, that is, if the address pool is not empty, select an unoccupied logical address from the released address pool, update the status of the logical address from the recyclable status to the allocated status, associate the physical ID of the new IO module with the logical address, record the current time as the last communication timestamp, and initialize the unresponsive count counter to 0; If the address pool is empty, call the hardware true random number generator to generate a new 32-bit random number as a candidate logical address, and perform uniqueness verification; The CPU module sends the allocated logical address to the corresponding IO module through the communication bus. After receiving the logical address, the IO module completes the communication binding with the CPU module based on the logical address, and the two parties can perform data interaction through this logical address subsequently.

[0010] Preferably, the exception handling mechanism includes: Detect the status of the random number generator. If the random number generator fails or the output does not conform to the random characteristics, perform random number generator processing; During the process of generating a random number, if an address conflict is detected, perform address conflict handling; After the address is allocated, when the CPU module sends the logical address to the IO module, if the communication times out or the data verification fails, perform communication failure handling; Among them, the communication failure handling includes recording the communication failure event in the system log. The communication failure event information includes information such as the physical ID of the target IO module, the allocated logical address, the timestamp and the failure reason, mark the logical address as a temporary conflict state, suspend using the address, and reallocate a new logical address for the IO module. If the communication fails multiple times, determine that the IO module is abnormal, trigger the disconnection handling process, and release the address resources.

[0011] Preferably, the random number generator processing includes: When the CPU module calls the hardware true random number generator, it monitors its working status in real time. If a hardware failure, an irrecoverable error or the generated random number does not conform to the true random characteristics is detected, it is determined that the random number generator fails; The CPU module triggers the exception handling mechanism, extracts the physical ID of the IO module to be allocated, performs a hashing operation on the physical ID using a preset hash function to generate a hash value of a fixed length as the candidate logical address, and verifies the uniqueness of the hash value by traversing the database or Bloom filter. If there is an address conflict, the address conflict handling is performed. If the logical address is unique, the CPU module binds it to the physical ID of the IO module and updates the information such as the address status and the last communication timestamp in the mapping database.

[0012] Preferably, the address conflict handling includes: During the process of generating a random number, if it is found that the newly generated random number already exists in the database, there is an address conflict. When an address conflict is detected, the conflict event is recorded in the system log, and the information including the conflict address, the physical ID of the involved IO module, and the timestamp is recorded. The CPU module will re - call the true random number generator to generate a new random number as the logical address, and traverse the mapping database again to perform a uniqueness check on the newly generated random number. This process of re - generation and verification will be repeated until the generated random number meets the uniqueness requirement or reaches the preset maximum number of retries. If no unique random number is found after reaching the maximum number of retries, the address allocation failure event is recorded in the system log, and exception handling measures such as issuing an alarm and suspending address allocation are taken.

[0013] Based on the same concept, the present invention also provides a computer device, including a memory and a processor. Computer - readable instructions are stored in the memory. When the computer - readable instructions are executed by the processor, the processor executes the steps of the PLC system control method based on dynamic address allocation as described in any one of the embodiments.

[0014] Based on the same concept, the present invention also provides a storage medium storing computer - readable instructions. When the computer - readable instructions are executed by one or more processors, one or more processors execute the steps of the PLC system control method based on dynamic address allocation as described in any one of the embodiments.

[0015] Compared with the prior art, the beneficial effects of the present invention are: The CPU module of the present invention obtains the unique physical ID of the ARM chip of the IO module through the communication bus, realizes the uniqueness of the physical address of the IO module, and then uses the true random number generator to generate a unique logical address for each physical ID, and establishes a mapping database between the physical ID and the logical address, improving the security of the IO module.

[0016] The present invention performs a handshake through a communication bus using the physical ID of the IO module as the communication identifier, and assigns the corresponding logical address as a dynamic address to the corresponding IO module, improving the flexibility of IO module address allocation.

[0017] The present invention monitors the online status of the IO module through a heartbeat detection mechanism. If the IO module goes offline, the dynamic logical address of the offline IO module is released and the mapping database is updated. When a new IO module goes online, the CPU module allocates an unoccupied logical address according to its physical ID number, and updates the central database, the mapping database, and the communication binding, realizing that the CPU module reallocates the dynamic address after the IO module goes online, and the CPU module releases the module ID and the dynamic address after the IO module goes offline, saving limited address resources and effectively solving the flexibility problem of PLC address allocation. Brief Description of the Drawings

[0018] By reading the detailed description of the preferred embodiments below, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention.

[0019] Figure 1 It is a flowchart of the PLC system control method based on dynamic address allocation of the present invention; Figure 2 It is a flowchart of the address allocation of the power-on IO module of the PLC system of the present invention; Figure 3 It is a block diagram of the dynamic address allocation of the PLC system of the present invention; Figure 4 It is a flowchart of the dynamic address release of the offline IO module of the present invention; Figure 5 It is a flowchart of the dynamic address allocation when the IO module goes online of the present invention. Detailed Description of the Preferred Embodiments

[0020] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts fall within the scope of protection of the present application.

[0021] Those skilled in the art will appreciate that, unless otherwise stated, the singular forms "a", "an", and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present invention refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0022] First embodiment See also Figure 1 , Figure 2 and Figure 3 As shown, the PLC system control method based on dynamic address allocation provided in this embodiment includes the following steps: S1: After the PLC system is powered on, the CPU module obtains the unique physical ID of the ARM chip of the IO module through the communication bus, and stores the physical ID in the central database. Specifically, in this embodiment, the unique physical ID of IO module 1 is the chip-specific identification ID1, the unique physical ID of IO module 2 is the chip-specific identification ID2, the unique physical ID of IO module 3 is the chip-specific identification ID3, and the unique physical ID of IO module 4 is the chip-specific identification ID4.

[0023] Furthermore, when the PLC system is powered on, the CPU module first completes its own initialization and activates the backplane communication bus. At this time, the CPU module begins to scan all IO modules on the bus and establishes communication connections with each IO module; The CPU module sends a physical ID query command to each IO module through the bus. After receiving the command, the ARM chip of each IO module reads its own built-in unique physical ID (usually the serial number or exclusive hardware identification solidified when the ARM chip leaves the factory), and feeds the physical ID back to the CPU module through the bus. After receiving the physical IDs of all IO modules, the CPU module aggregates and organizes these unique identification information and stores them in the system's central database.

[0024] S2: The CPU module calls the ARM true random number generator to generate a unique logical address for each physical ID. For example, for any device (physical ID: 0x123456789), the TRNG generates a 32-bit random number (assumed to be 0x4861598754679431) as its logical address, establishes a mapping database between the physical ID and the logical address, and records information including the address status, the last communication timestamp, and the unresponsive count counter (i.e., relevant record information). Specifically, in this embodiment, the ARM true random number generator is a hardware random number generator built into the ARM, which obtains a 32-bit random number based on random noise, and the mapping database is a storage unit established inside the CPU for storing the correspondence between the random number (i.e., the logical address) and the physical ID number. The ARM true random number generates ID1 based on TRNG1, ID2 based on TRNG2, ID3 based on TRNG3, and ID4 based on TRNG4.

[0025] Preferably, in step S2, when the CPU module calls the ARM true random number generator to generate a unique logical address for each physical ID, it further includes: The CPU module calls the ARM true random number generator to generate a random number for each physical ID. For example, after starting the ARM true random number generator TRNG, a 32-bit random number can be obtained by accessing the data register TRNG_DATA. Specifically, in this embodiment, based on the ARM true random number generator, the addresses assigned by the CPU to each IO module have true randomness; The CPU module checks whether the newly generated random number has been assigned by traversing the mapping database. If it has not been assigned, it is assigned. If it has been assigned, it is processed through an exception handling mechanism; When the generated random number meets the uniqueness requirement, the physical ID is associated with the corresponding logical address, the mapping database is updated, and at the same time, the address status is recorded as assigned and the current last communication timestamp.

[0026] S3: The CPU module performs a handshake through the communication bus using the physical ID of the IO module as the communication identifier, and assigns the corresponding logical address as the dynamic address to the corresponding IO module, completing the address binding and communication handshake.

[0027] Furthermore, first, the CPU module traverses all the physical IDs of the IO modules stored in the central database, and for each physical ID, it performs the following operations - selects an unoccupied logical address from the dynamic address pool, and then sends an address assignment instruction containing the logical address to be assigned and communication parameters to the IO module with the corresponding physical ID through the communication bus; After the IO module receives the instruction, it performs response verification using its own physical ID. After confirming that the target object of the instruction is the same as itself, it writes the allocated logical address into the internal register and returns a handshake success signal to the CPU through the bus. After receiving the confirmation signal, the CPU immediately establishes the binding relationship between the physical ID and the logical address in the mapping database, thus completing the address allocation and the establishment of the communication link. Among them, throughout the process, the physical ID ensures the accurate delivery of the instruction to the target module as the only communication identifier, and the dynamic address allocation realizes the flexible configuration independent of the hardware, enabling the system to automatically complete the reallocation and binding of the address by repeating the above process when the module is hot-plugged or replaced due to a fault, ensuring the continuous and stable operation of industrial control.

[0028] S4: During the system operation, the CPU module monitors the online status of the IO module through the heartbeat detection mechanism. If the IO module goes offline, it releases the dynamic logical address of the offline IO module and updates the mapping database. When a new IO module comes online, the CPU module allocates an unoccupied logical address according to its physical ID number and updates the central database, the mapping database, and the communication binding.

[0029] Preferably, in step S4, the CPU module monitors the online status of the IO module through the heartbeat detection mechanism, including: The CPU module periodically sends a heartbeat request to the IO module. If an IO module returns a response within the specified time, the CPU module resets the unresponsive count counter of the IO module to 0 and updates the last communication timestamp of the module in the database. If an IO module does not return a response within the specified time, the CPU module increments the unresponsive count counter of the module by 1; The CPU module checks the value of the unresponsive count counter of the IO module continuously. If the value of the unresponsive count counter exceeds the preset threshold, it is determined to be offline. When a new IO module accesses the system, the IO module sends a registration request of its physical ID to the CPU module through the communication bus. After the CPU module receives the registration request, it determines the new IO module after verifying the legality of the ID.

[0030] Please refer to Figure 4 As shown, in step S4, releasing the dynamic address of the offline IO module and updating the database includes: The CPU module queries the mapping database according to the physical ID number of the offline IO module to find the corresponding logical address and related records. Specifically, in this embodiment, the related records are physical id, logical address, address status, last communication timestamp, and unresponsive count counter (recording the number of consecutive heartbeat timeouts); Update the address status flag of the record to the recyclable status. After a preset delay period, if the IO module still fails to recover online, the CPU module deletes the entry from the mapping database and releases the corresponding logical address resources for subsequent reallocation to newly connected IO modules.

[0031] Please refer to Figure 5 As shown, in step S4, when a new IO module goes online, the CPU module allocates an unoccupied logical address according to its physical ID number and updates the central database, mapping database, and communication binding, including: First, reuse an unoccupied random number from the released address pool. That is, if the address pool is not empty, select an unoccupied logical address from the released address pool, update the status of the logical address from the recyclable status to the allocated status, associate the physical ID of the new IO module with the logical address, record the current time as the last communication timestamp, and initialize the unresponsive count counter to 0. Specifically, in this embodiment, the method of selecting an unoccupied logical address can be in the release order or other strategies such as random selection; If the address pool is empty, call the hardware ARM true random number generator to generate a new 32-bit random number as a candidate logical address and perform a uniqueness check. Specifically, in this embodiment, the uniqueness check is to verify whether the newly generated random number has been allocated to other IO modules by traversing the mapping database or using a Bloom filter, etc.; The CPU module sends the allocated logical address to the corresponding IO module through the communication bus. After receiving the logical address, the IO module completes the communication binding with the CPU module based on this logical address, and then the two parties can perform data interaction through this logical address.

[0032] Preferably, the exception handling mechanism includes: Detect the status of the random number generator. If the random number generator fails or the output does not conform to the random characteristics, perform random number generator processing; During the process of generating a random number, if an address conflict is detected, perform address conflict handling; After the address is allocated, when the CPU module sends the logical address to the IO module, if there is a communication timeout or data verification failure, perform communication failure handling; Among them, communication failure handling includes recording the communication failure event in the system log. The communication failure event information includes information such as the physical ID of the target IO module, the allocated logical address, the timestamp, and the failure reason, marking the logical address as a temporary conflict status, suspending the use of the address, and reallocating a new logical address for the IO module. If there are multiple communication failures, determine that the IO module is abnormal and trigger the disconnection handling process to release the address resources.

[0033] Preferably, the random number generator processing includes: When the CPU module calls the hardware ARM true random number generator, it monitors its working status in real time. If a hardware failure, an irrecoverable error, or the generated random number does not conform to the true random characteristics is detected, it is determined that the random number generator has failed. The CPU module triggers an exception handling mechanism, extracts the physical ID of the IO module to be allocated, performs a hash operation on the physical ID using a preset hash function to generate a hash value of a fixed length as the candidate logical address, and verifies the uniqueness of the hash value by traversing the database or Bloom filter. If an address conflict exists, address conflict handling is performed. If the logical address is unique, the CPU module binds it to the physical ID of the IO module and updates the information including the address status and the last communication timestamp in the mapping database.

[0034] Preferably, the address conflict handling includes: During the process of generating a random number, if it is found that the newly generated random number already exists in the database, an address conflict exists. When an address conflict is detected, the conflict event is recorded in the system log, and the information including the conflict address, the physical ID of the involved IO module, and the timestamp is recorded. The CPU module will re - call the ARM true random number generator to generate a new random number as the logical address, and traverse the mapping database again to perform a uniqueness check on the newly generated random number. This process of re - generation and verification will be repeated until the generated random number meets the uniqueness requirement or reaches the preset maximum retry count. If a unique random number is still not found after reaching the maximum retry count, the address allocation failure event is recorded in the system log, and exception handling measures such as issuing an alarm and suspending address allocation are taken.

[0035] Second Embodiment In some embodiments of the present application, a computer device is further provided, including a memory and a processor. Computer - readable instructions are stored in the memory. When the computer - readable instructions are executed by the processor, the processor executes the steps of the PLC system control method based on dynamic address allocation in the first embodiment of the present invention.

[0036] The present invention further provides a storage medium storing computer - readable instructions. When the computer - readable instructions are executed by one or more processors, the one or more processors execute the steps of the PLC system control method based on dynamic address allocation in the first embodiment of the present invention.

[0037] It can be understood that for the aforementioned PLC system control method based on dynamic address allocation, when it is implemented in the form of software function modules and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer server, or a network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present invention. And the aforementioned storage medium includes: USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs, etc., all kinds of media that can store program codes.

[0038] A computer-readable storage medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries the readable program code. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The readable storage medium can also be any readable medium other than the readable storage medium, and this readable medium can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium can be transmitted using any appropriate medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination of the above.

[0039] The above description is only the preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions falling within the idea of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, several improvements and refinements made without departing from the principle of the present invention should also be regarded as within the protection scope of the present invention.

Claims

1. A control method for a PLC system based on dynamic address allocation, characterized in that, It includes the following steps: S1: After the PLC system is powered on, the CPU module obtains the unique physical ID of the ARM chip of the IO module through the communication bus, and stores the physical ID in the central database; S2: The CPU module calls a true random number generator to generate a unique logical address for each physical ID, establishes a mapping database between the physical ID and the logical address, and records information including the address status, the last communication timestamp, and the unresponsive count counter; S3: The CPU module performs a handshake through the communication bus using the physical ID of the IO module as the communication identifier, and assigns the corresponding logical address as the dynamic address to the corresponding IO module to complete address binding and communication handshake; S4: During the operation of the system, the CPU module monitors the online status of the IO module through a heartbeat detection mechanism. If an IO module goes offline, the dynamic logical address of the offline IO module is released and the mapping database is updated. When a new IO module comes online, the CPU module assigns an unoccupied logical address according to its physical ID number, and updates the central database, the mapping database, and the communication binding.

2. The PLC system control method based on dynamic address allocation according to claim 1, wherein In step S2, when the CPU module calls a true random number generator to generate a unique logical address for each physical ID, it further includes: The CPU module calls a true random number generator to generate a random number for each physical ID; The CPU module checks whether the newly generated random number has been assigned by traversing the mapping database. If it has not been assigned, it is assigned. If it has been assigned, it is processed through an exception handling mechanism; When the generated random number meets the uniqueness requirement, the physical ID is associated with the corresponding logical address, the mapping database is updated, and at the same time, the address status is recorded as assigned and the current last communication timestamp; 3. The control method of the PLC system based on dynamic address allocation according to claim 2, characterized in that, In step S4, when the CPU module monitors the online status of the IO module through a heartbeat detection mechanism, it includes: The CPU module periodically sends a heartbeat request to the IO module. If an IO module returns a response within the specified time, the CPU module resets the unresponsive count counter of the IO module to 0 and updates the last communication timestamp of the module in the database. If an IO module does not return a response within the specified time, the CPU module increments the unresponsive count counter of the module by 1; The CPU module checks the value of the continuous unresponsive count counter of the IO module. If the value of the unresponsive count counter exceeds the preset threshold, it is determined to be offline. When a new IO module accesses the system, the IO module sends a registration request for its physical ID to the CPU module through the communication bus. After the CPU module receives the registration request, the CPU determines it to be a new IO module after verifying the ID legality.

4. The PLC system control method based on dynamic address allocation according to claim 3, characterized in that, In step S4, releasing the dynamic address of the offline IO module and updating the database includes: The CPU module queries the mapping database according to the physical ID number of the offline IO module to find the corresponding logical address and related records; Update the address status flag of the record to the recyclable status, and after a preset delay period, if the IO module still fails to resume online, the CPU module deletes the entry from the mapping database and releases the corresponding logical address resources for subsequent reallocation to newly connected IO modules.

5. The control method of the PLC system based on dynamic address allocation according to claim 4, characterized in that, In step S4, when a new IO module goes online, the CPU module allocates an unoccupied logical address according to its physical ID number and updates the central database, the mapping database, and communication bindings, including: First, reuse an unoccupied random number from the released address pool, that is, if the address pool is not empty, select an unoccupied logical address from the released address pool, update the status of the logical address from the recyclable status to the allocated status, associate the physical ID of the new IO module with the logical address, record the current time as the last communication timestamp, and initialize the unresponse count counter to 0; If the address pool is empty, call the hardware true random number generator to generate a new 32-bit random number as a candidate logical address and perform uniqueness verification; The CPU module sends the allocated logical address to the corresponding IO module through the communication bus. After receiving the logical address, the IO module completes the communication binding with the CPU module based on the logical address, and the two parties can perform data interaction through this logical address subsequently.

6. The PLC system control method based on dynamic address allocation according to claim 5, characterized in that, The exception handling mechanism includes: Detect the status of the random number generator. If the random number generator fails or the output does not conform to the random characteristics, perform random number generator processing; During the process of generating a random number, if an address conflict is detected, perform address conflict handling; After the address is allocated, when the CPU module sends the logical address to the IO module, if the communication times out or the data verification fails, perform communication failure handling; Among them, the communication failure handling includes recording the communication failure event in the system log. The communication failure event information includes information such as the physical ID of the target IO module, the allocated logical address, the timestamp, and the failure reason, mark the logical address as a temporary conflict status, suspend using the address, and reallocate a new logical address for the IO module. If the communication fails multiple times, determine that the IO module is abnormal, trigger the disconnection handling process, and release the address resources.

7. The PLC system control method based on dynamic address allocation according to claim 6, wherein The random number generator processing includes: When the CPU module calls the hardware true random number generator, it monitors its working status in real time. If a hardware failure, an irrecoverable error, or the generated random number does not conform to the true random characteristics is detected, it is determined that the random number generator fails; The CPU module triggers the exception handling mechanism, extracts the physical ID of the IO module to be allocated, performs a hash operation on the physical ID using a preset hash function to generate a hash value of a fixed length as a candidate logical address, verifies the uniqueness of the hash value by traversing the database or Bloom filter. If an address conflict exists, perform the address conflict handling. If the logical address is unique, the CPU module binds it to the physical ID of the IO module and updates information such as the address status and the last communication timestamp in the mapping database.

8. The control method of the PLC system based on dynamic address allocation according to claim 7, characterized in that The address conflict handling includes: During the process of generating random numbers, if it is found that the newly generated random number already exists in the database, there is an address conflict. When an address conflict is detected, the conflict event is recorded in the system log, and the information including the conflict address, the physical ID of the involved IO module, and the timestamp is recorded. The CPU module will re - call the true random number generator to generate a new random number as the logical address, and traverse the mapping database again to perform uniqueness verification on the newly generated random number. This process of re - generation and verification will be repeated until the generated random number meets the uniqueness requirement or reaches the preset maximum number of retries. If the unique random number is still not found after reaching the maximum number of retries, the address allocation failure event is recorded in the system log, and abnormal handling measures including issuing an alarm and suspending address allocation are taken.

9. A computer device, characterized in that, It includes a memory and a processor. Computer - readable instructions are stored in the memory. When the computer - readable instructions are executed by the processor, the processor executes the module of the PLC system control method based on dynamic address allocation according to any one of claims 1 to 8.

10. A storage medium storing computer-readable instructions, characterized in that, When the computer - readable instructions are executed by one or more processors, the one or more processors execute the steps of the PLC system control method based on dynamic address allocation according to any one of claims 1 to 8.

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