Heat dissipation control system of server and server

Abstract

The invention discloses a heat dissipation control system of a server and the server, and relates to the technical field of server heat dissipation, and the heat dissipation control system comprises a main processing core, a co-processing core, a temperature sensor, a fan, a PWM controller and a target memory. When the main processing core is in a fault state, the co-processing core obtains a target duty ratio of a next period and writes the target duty ratio into the PWM controller based on a target operation mode of the current period of the server and temperature data of the current period read from the temperature sensor, and can also obtain a rotating speed of the current period based on a preset proportion and the PWM controller. According to the method, the problem that large noise and mechanical stress are generated due to the fact that a CPLD controls a fan at the maximum rotating speed under the condition that a main processing core breaks down in the prior art can be solved, on one hand, a multi-stage fault-tolerant mechanism can be achieved, and the heat dissipation reliability of a server is improved; and on the other hand, the rotating speed of the fan is intelligently and relatively smoothly adjusted, and relatively low noise and mechanical stress are generated.

Description

Technical Field

[0001] This application relates to the technical field of server heat dissipation, and particularly to a heat dissipation control system and a server for a server. Background Art

[0002] The heat dissipation problem of a server affects the performance of the server data center.

[0003] The heat dissipation of a server is usually executed by a Baseboard Management Controller (BMC) system. When the main processing core of the BMC system is alive, the main processing core adjusts the fan speed in real time according to the server temperature. However, when the main processing core malfunctions, a Complex Programmable Logic Device (CPLD) takes over the fan speed.

[0004] However, since the CPLD can only control the fan at a fixed set speed, which is usually the maximum speed, this causes the fan speed to change suddenly, generating relatively large noise and mechanical stress. Summary of the Invention

[0005] This application provides a heat dissipation control system and a server for a server, so as to at least solve the problem in the related art that when the main processing core fails, the CPLD controls the fan at the maximum speed, generating relatively large noise and mechanical stress.

[0006] This application provides a heat dissipation control system for a server, including:

[0007] A baseboard management controller, a temperature sensor, a fan, a Pulse Width Modulation (PWM) controller, and a target memory; the baseboard management controller includes a main processing core and a coprocessing core;

[0008] The main processing core and the coprocessing core share the target memory; target instructions are stored in the target memory;

[0009] The main processing core is used to periodically write heartbeat information into the target memory;

[0010] The coprocessing core is used to skip the execution of the target instructions when it is determined based on the heartbeat information in the target memory that the main processing core is in a non-fault state;

[0011] The coprocessing core is used to execute the target instructions through the following operations when it is determined based on the heartbeat information in the target memory that the main processing core is in a fault state:

[0012] Based on the target operating mode of the server in the current period and the temperature data read from the temperature sensor in the current period, obtain and write the target duty cycle for the next period to the PWM controller; or,

[0013] Based on the rotation speed of the current cycle obtained from a preset ratio and a PWM controller, obtain and write the target duty cycle of the next cycle to the PWM controller; the preset ratio is used to reduce the rotation speed of the next cycle.

[0014] The PWM controller is used to output a PWM signal based on the target duty cycle of the next cycle in the next cycle to adjust the rotation speed of the fan in the next cycle.

[0015] This application also provides a server, and the server includes the heat dissipation control system of the server provided in the first aspect.

[0016] Through this application, when the baseboard management controller includes a main processing core and a coprocessing core, and they share a target memory, it can achieve efficient, low-latency, and low-consumption data interaction.

[0017] The coprocessing core determines the fault status of the main processing core based on the heartbeat information, realizing millisecond-level fault monitoring of the main processing core. In the case where the main processing core is in a fault state, the coprocessing core executes the target command in the shared memory. The coprocessing core can obtain and write the target duty cycle of the next cycle to the PWM controller by based on the target operating mode of the current cycle of the server and the temperature data of the current cycle read from the temperature sensor, or based on the rotation speed of the current cycle obtained from the preset ratio and the PWM controller, so that the PWM adjusts the rotation speed of the fan based on the target duty cycle of the next cycle, which can solve the problem that in the case of a fault of the main processing core in the related technology, the CPLD controls the fan at the maximum rotation speed, resulting in relatively large noise and mechanical stress. On the one hand, it can implement a multi-level fault tolerance mechanism, improve the reliability of server heat dissipation, and reduce the risk of server failure caused by heat dissipation problems. On the other hand, it realizes intelligent and relatively smooth adjustment of the rotation speed of the fan, generating relatively low noise and mechanical stress. Description of the Drawings

[0018] In order to more clearly illustrate the embodiments of this application, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0019] Figure 1 It is a schematic diagram of the architecture of a heat dissipation control system of a server provided in an embodiment of this application;

[0020] Figure 2 It is a schematic diagram of the process for a heat dissipation control system to adjust the rotation speed of a fan provided in an embodiment of this application. Detailed Embodiments

[0021] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts belong to the protection scope of the present application.

[0022] It should be noted that in the description of the present application, the terms "including", "comprising" or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0023] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] In the related technology, when the main processing core of the BMC system is alive, the main processing core adjusts the fan speed in real time according to the server temperature. However, when the main processing core malfunctions, the Complex Programmable Logic Device (CPLD) takes over the fan speed. There are the following problems with the CPLD taking over:

[0025] 1. Since the CPLD can only control the fan at a fixed established speed, which is usually the maximum speed, this will cause a sudden change in the fan speed, generating relatively large noise and mechanical stress.

[0026] 2. The BMC has no fault tolerance mechanism, and the CPLD is responsible for solving abnormal scenarios. The intervention of the CPLD usually requires a certain detection and switching time, and it is impossible to achieve rapid response, which may cause the server to overheat in a short time.

[0027] 3. The CPLD usually adopts a preset fixed strategy (controlling the fan rotation at the maximum speed) and cannot be dynamically adjusted according to the actual situation, which may lead to insufficient heat dissipation or excessive heat dissipation.

[0028] 4. There is a lack of a real-time data verification mechanism between the BMC and the CPLD, and it is impossible to detect and correct control errors in time.

[0029] 5. The related technology usually only provides simple alarm information and lacks detailed fault diagnosis data, which is not conducive to problem analysis and solution.

[0030] To solve at least one of the above technical problems, embodiments of the present application provide a heat dissipation system and a server for a server.

[0031] Embodiments of the present application provide a heat dissipation control system for a server. The heat dissipation control system for the server will be described in detail in combination with the components of the heat dissipation control system for the server and the functions of each part.

[0032] See Figure 1 , embodiments of the present application provide a schematic architecture diagram of a heat dissipation control system for a server. The heat dissipation control system includes a baseboard management controller, a temperature sensor, a fan, a pulse width modulation (PWM) controller, and a target memory;

[0033] Among them, the baseboard management controller includes a main processing core and a co-processing core;

[0034] Both the main processing core and the co-processing core are connected to the temperature sensor, both the main processing core and the co-processing core are connected to the PWM controller, both the main processing core and the co-processing core are connected to the target memory, and the PWM controller is connected to the fan and can control the rotation speed of the fan.

[0035] The main processing core and the co-processing core share the target memory; target instructions are stored in the target memory;

[0036] The main processing core is used to periodically write heartbeat information to the target memory;

[0037] The co-processing core is used to skip executing the target instructions when it is determined based on the heartbeat information in the target memory that the main processing core is in a non-fault state;

[0038] The co-processing core is used to execute the target instructions through the following operations when it is determined based on the heartbeat information in the target memory that the main processing core is in a fault state:

[0039] Based on the target operating mode of the server in the current period and the temperature data of the current period read from the temperature sensor, obtain and write the target duty cycle of the next period to the PWM controller; or,

[0040] Based on a preset ratio and the rotation speed of the current period obtained by the PWM controller, obtain and write the target duty cycle of the next period to the PWM controller; the preset ratio is used to reduce the rotation speed of the next period;

[0041] The PWM controller is used to output a PWM signal based on the target duty cycle of the next period in the next period to adjust the rotation speed of the fan in the next period.

[0042] The Baseboard Management Controller (BMC) is an independent processor that runs on a dedicated chip on the server motherboard. The BMC is commonly used to manage and monitor the health of server hardware. The BMC is usually part of the server management system, providing low-level hardware control and monitoring functions and generally not relying on the operation of the operating system.

[0043] In the embodiment of this application, the BMS integrates dual processing cores, namely the main processing core and the coprocessing core (also referred to as the "slave processing core").

[0044] In some embodiments, the main processing core and the coprocessing core are heterogeneous processing cores;

[0045] The main processing core runs a heavyweight operating system; the coprocessing core runs a lightweight real-time operating system.

[0046] The main processing core refers to the core processing unit in the BMC responsible for executing control, monitoring, and management tasks, such as monitoring CPU temperature, fan speed, voltage, current, memory status, hard disk health, etc.

[0047] The coprocessing core refers to the secondary processing unit in the BMC that assists the main processing core in executing specific tasks. The coprocessing core is usually used to execute some specific functions, relieve the burden of the main processing core, or execute some specific hardware monitoring and control tasks.

[0048] The main processing core and the coprocessing core are usually heterogeneous processing cores. The main processing core usually adopts a processor core with high computing power and multitasking capabilities, such as the ARM Cortex-A7. The coprocessing core usually adopts a processor core with low power consumption and high real-time requirements, such as the ARM Cortex-M4.

[0049] The main processing core usually runs a heavyweight operating system, such as Linux, Unix, etc. operating systems, responsible for complex control algorithms and user interfaces. The coprocessing core usually runs a lightweight operating system, such as FreeRTOS, etc., responsible for real-time monitoring and quick response.

[0050] In the embodiment of this application, the BMC adopts heterogeneous dual processing cores. By allocating high-performance computing tasks to the main processing core and tasks with high low-power real-time requirements to the coprocessing core, the system can minimize energy consumption while maintaining high efficiency, improve the response speed, extend the battery life, and optimize multitasking, enhancing real-time performance and user experience.

[0051] In the embodiment of this application, the main processing core and the coprocessing core share the target memory, and the target memory is used for data exchange between the two cores, that is, both the main processing core and the coprocessing core have the read and write permissions to the target memory.

[0052] In practical applications, the target memory typically uses a dual-port RAM (Random Access Memory).

[0053] In addition, there is a communication interface between the main processing core and the coprocessing core. This communication interface typically uses SPI (Serial Peripheral Interface) or I2C interface to achieve instruction and data transmission between the two cores.

[0054] The main processing core in the embodiment of this application includes a non-faulted state and a faulted state.

[0055] Among them, the non-faulted state of the main processing core refers to the working state of the main processing core under normal operation, that is, the main processing core does not encounter hardware faults or abnormalities and can correctly execute tasks according to the predetermined design and functions.

[0056] The faulted state of the main processing core refers to the state of the processing core when a hardware or software exception occurs. In this faulted state, the processing core cannot work properly, may stop executing instructions, enter an error mode, or be unable to continue processing tasks. The faulted state may be caused by various reasons, including hardware faults, program errors, or resource conflicts, etc.

[0057] The main processing core monitors the temperature sensor and controls the fan speed in the non-faulted state, and the coprocessing core monitors the temperature sensor and controls the fan speed in the faulted state.

[0058] The main processing core in the embodiment of this application periodically writes heartbeat information to the target memory. This heartbeat information is used to indicate that the main processing core is in a live state in this cycle. The duration of this cycle can be 100ms, 500ms, etc., and there is no limit to the duration of the cycle.

[0059] In addition, the main processing core writes a target instruction to the target memory. This target instruction is used to indicate that the coprocessing core performs heat dissipation control. This target instruction can be pre-written or periodically written, and there is no limit to this.

[0060] In some embodiments, the target instruction includes at least one of a first instruction, a second instruction, and a third instruction;

[0061] The first instruction is used to instruct the coprocessing core to read temperature data from the temperature sensor;

[0062] The second instruction is used to instruct the coprocessing core to write a duty cycle to the PWM controller;

[0063] The third instruction is used to instruct the coprocessor core to report its own status to the main processor core.

[0064] The target command in the embodiment of the present application may specifically include at least one of the above commands. The first instruction is also called the "temperature sensor data reading instruction", the second instruction is also called the "duty cycle setting instruction", and the third instruction is also called the "status query instruction".

[0065] In the embodiment of the present application, the coprocessor core determines the status of the main processor core based on the heartbeat information of the main processor core. The main processor core writing heartbeat information to the target memory will trigger an interrupt. The coprocessor core reads the heartbeat information based on the interrupt. When it is determined based on the heartbeat information that the main processor core is in a non-fault state, the coprocessor core will skip executing (not execute) the target instruction, that is, continue to monitor the temperature data of the temperature sensor by the main processor core and control the fan speed.

[0066] However, when the coprocessor core determines that the main processor core is in a fault state based on the heartbeat information in the target memory, it will execute the target instruction to take over the monitoring of the temperature data of the temperature sensor and control the fan speed, which can realize the flexibility of the main processor core and the coprocessor core in controlling the fan speed and can take over the adjustment of the fan speed in time after the main processor core fails.

[0067] The coprocessor core in the embodiment of the present application has two ways to adjust the fan speed:

[0068] Method 1: The coprocessor core obtains and writes the target duty cycle of the next cycle to the PWM controller based on the target operating mode of the server in this cycle and the temperature data read from the temperature sensor in this cycle; or,

[0069] Method 2: The coprocessor core obtains and writes the target duty cycle of the next cycle to the PWM controller based on a preset ratio and the rotation speed obtained by the PWM controller in this cycle; the preset ratio is used to reduce the rotation speed of the next cycle.

[0070] The number of temperature sensors in the embodiment of the present application is one or more, and the temperature sensors are used to collect the temperature of the device cards of the server.

[0071] The server has multiple operating modes, and the multiple operating modes include but are not limited to the minimum energy consumption mode, the maximum heat dissipation mode, the balanced mode, the energy-saving mode, etc.

[0072] The server can switch different operating modes according to different application scenarios or service types.

[0073] For the adjustment method of Method 1, each operating mode of the server has corresponding PID (Proportional-Integral-Derivative Controller) parameters, and the PID parameters are used to adjust the duty cycle in the PWM (Pulse Width Modulation) controller.

[0074] The PID parameters include three gain parameters, namely the P (Proportional) gain, the I (Integral) gain, and the D (Derivative) gain. The P gain affects the rapid adjustment of the rotational speed; the I gain eliminates long-term errors and ensures the accuracy of the rotational speed in the steady state; the D gain helps reduce oscillations and overshoots and increases the stability of the rotational speed.

[0075] There is at least one different gain among the P gain, the I gain, and the D gain for every two operating modes.

[0076] The corresponding PID parameters for each operating mode can be preset based on experience or set in other ways, and there is no restriction on this.

[0077] The corresponding PID parameters for each operating mode can be stored in a table or a function library, which is convenient for expansion and maintenance. The coprocessor core can obtain the PID parameters of each operating mode in the form of looking up the table or the function library.

[0078] After obtaining the temperature data of this cycle from the temperature sensor, the coprocessor core can determine the temperature difference between the temperature data of this cycle and the set target temperature data, the integral of the temperature differences of each cycle, and the derivative of the temperature differences of each cycle.

[0079] The number of temperature sensors can be one or more. In the case where the number of temperature sensors is more than one, the temperature data of the temperature sensors at key positions can be read.

[0080] The coprocessor core can weight the temperature difference of this cycle with the P gain to obtain a first weighted value, weight the integral of the temperature differences of each cycle with the I gain to obtain a second weighted value, weight the derivative of the temperature differences of each cycle with the D gain to obtain a third weighted value, sum up the first weighted data, the second weighted value, and the third weighted value to obtain a target weighted sum, and determine the duty cycle corresponding to the target weighted sum according to the relationship between the pre-created weighted sum and the duty cycle. The duty cycle corresponding to the target weighted sum is the target duty cycle for the next cycle.

[0081] The adjustment method of Method 2 is called the progressive speed reduction adjustment method. The coprocessor core can obtain a preset ratio (the preset ratio can be preset based on the fan characteristics, such as 20%). This preset ratio refers to the speed reduction rate. The coprocessor core will reduce the speed of the current cycle obtained from the PWM controller based on the preset ratio to obtain the speed of the next cycle, and determine the target duty cycle of the next cycle required by the PWM controller in the next cycle according to the speed of the next cycle; the preset ratio is used to reduce the speed of the next cycle.

[0082] The duty cycle is the ratio of the time in the "on" state in a periodic signal to the entire cycle. Simply put, the duty cycle represents the ratio of the duration of the "high level" part of a signal in a cycle to the entire cycle.

[0083] The coprocessor core will write the target duty cycle obtained in the next cycle based on the above Method 1 or Method 2 into the PWM register.

[0084] The PWM controller is mainly used to adjust the width of the pulse according to the duty cycle, and then adjust the speed of the fan to achieve effective temperature control. In the next cycle, the PWM controller can output a PWM signal based on the target duty cycle of the next cycle to adjust the speed of the fan in the next cycle.

[0085] In the embodiment of the present application, the baseboard management controller includes a main processor core and a coprocessor core, and the two share the target memory, which can achieve efficient, low-latency, and low-consumption data interaction.

[0086] The coprocessor core determines the fault state of the main processor core based on the heartbeat information, realizing millisecond-level fault monitoring of the main processor core. In the case where the main processor core is in a fault state, the coprocessor core executes the target command in the shared memory. The coprocessor core can obtain and write the target duty cycle of the next cycle to the PWM controller by based on the target operation mode of the current cycle of the server and the temperature data of the current cycle read from the temperature sensor, or based on the preset ratio and the speed of the current cycle obtained by the PWM controller, so that the PWM adjusts the speed of the fan based on the target duty cycle of the next cycle, which can solve the problem in the related technology that the CPLD controls the fan at the maximum speed in the case of the main processor core failure, resulting in relatively large noise and mechanical stress. On the one hand, it can implement a multi-level fault tolerance mechanism, improve the reliability of server heat dissipation, and reduce the risk of server failure caused by heat dissipation problems. On the other hand, it realizes intelligent and relatively smooth adjustment of the fan speed, generating relatively low noise and mechanical stress.

[0087] In some embodiments, the heartbeat information includes the monitoring metrics of the current cycle and the first check value generated by the main processing core based on the monitoring metrics of the current cycle; the monitoring metrics include at least some of the sequence number, timestamp, and CPU load of the current cycle;

[0088] The coprocessing core is further configured to, when detecting that the main processing core writes the heartbeat information to the target memory, generate a second check value based on the monitoring metrics in the heartbeat information, and determine that the main processing core is in a non-fault state when the first check value and the second check value in the current cycle are consistent.

[0089] In the embodiments of the present application, the main processing core periodically writes its own heartbeat information to the target memory. The heartbeat information includes the monitoring metrics of the current cycle and the first check value generated by the main processing core based on the monitoring metrics of the current cycle. The monitoring metrics include at least some of the sequence number, timestamp, and CPU load of the current cycle.

[0090] Among them, the sequence number is used to uniquely indicate the heartbeat of the current cycle, and the sequence number can be used to detect the loss and out-of-order of the heartbeat packets.

[0091] The timestamp is used to calculate the delay of the heartbeat information.

[0092] The CPU load is used to determine whether the main core is overloaded.

[0093] To prevent the monitoring metrics from being tampered with, the main processing core generates a first check value based on the monitoring metrics of the current cycle.

[0094] The coprocessing core generates a second check value based on the monitoring metrics in the heartbeat information to determine whether the heartbeat packet is damaged, and determines whether the first check value and the second check value are consistent. If the two are consistent, it can be determined that the main processing core is in a non-fault state.

[0095] In practical applications, the coprocessing core can perform the above verification based on a hardware accelerator, thereby improving the verification speed.

[0096] The main processing core and the coprocessing core can generate check values based on the same verification algorithm. The verification algorithm can be a CRC (Cyclic Redundancy Check) algorithm, specifically 16CRC, CRC32, etc., or other algorithms, which are not limited thereto.

[0097] In some embodiments, the coprocessing core is further configured to send a first signal to the watchdog when the first check value and the second check value in the current cycle are consistent;

[0098] In the case that the watchdog does not receive the first signal for more than the target number of cycles, it sends a second signal to the coprocessor core; the second signal is used to indicate that the main processor core is in a fault state; the target number is determined based on the load of the CPU in this cycle and / or the network state in this cycle, or is a preset default value.

[0099] The coprocessor core is also used to determine that the main processor core is in a fault state based on the second signal.

[0100] In the case that the first check value and the second check value in this cycle are consistent in an embodiment of the present application, the coprocessor core sends a first signal to the watchdog. The watchdog belongs to a software watchdog, and the first signal is a signal that the software watchdog needs to monitor regularly. The first signal is used to indicate that the first check value and the second check value in this cycle are consistent.

[0101] A software watchdog is a monitoring mechanism implemented by software. It ensures the continuous operation of the system and can automatically perform recovery operations by regularly checking a preset signal.

[0102] In the case that the coprocessor core determines that the first check value and the second check value in this cycle are inconsistent, it does not send the first signal to the software watchdog. In addition, in the case that the heartbeat information in this cycle is not updated in the target memory, the coprocessor core cannot verify the heartbeat information in this cycle due to the loss of the heartbeat information, and naturally does not send the first signal to the watchdog in this cycle.

[0103] In the case that the software watchdog does not receive the first signal for more than the target number (for example, 3) of cycles, it sends a second signal to the coprocessor core; the second signal is used to indicate that the first signal has not been received for more than the target number of cycles.

[0104] The target number is determined based on the load of the CPU obtained last time and / or the network state in this cycle (for example, when the CPU load is high, the target number is large; when the network state is good, the target number is large), or is a preset default value (for example, 3).

[0105] The coprocessor core can determine that the main processor core is in a fault state based on the second signal.

[0106] In an embodiment of the present application, by monitoring the heartbeat information of the main processor core through the coprocessor core and the software watchdog, the fault of the main processor core can be detected in a timely manner (millisecond level), so that the coprocessor core can quickly and effectively adjust the fan speed in the case of determining the fault of the main processor core.

[0107] In some embodiments, the coprocessor core is also used to write a reset instruction to the target memory in the case of determining that the main processor core is in a fault state based on the heartbeat information in the target memory;

[0108] The main processing core is also used to start a preset hardware reset circuit based on a reset instruction of the target memory, so as to restart the main processing core through the hardware reset circuit.

[0109] In the embodiment of the present application, when the coprocessing core receives a second signal triggered by a software watchdog, it can determine that the main processing core is in a fault state, and in response to the second signal, write a reset instruction to the target memory, and the reset instruction is used to restart or wake up the main processing core.

[0110] The main processing core can start a preset hardware reset circuit based on the reset instruction of the target memory, so as to restart the main processing core through the hardware reset circuit.

[0111] In the embodiment of the present application, when the coprocessing core determines that the main processing core fails, it can start the hardware reset circuit in time through the reset instruction, which can realize restarting the main processing core in time, effectively solve the failure of the main processing core, and restore the service of the main processing core in time and effectively.

[0112] In some embodiments, the main processing core is specifically used to, when in a non-fault state, obtain the temperature data of the current cycle from a temperature sensor and the PID parameters of the current cycle obtained based on a preset algorithm, and obtain and write the target duty cycle of the next cycle to a PWM controller;

[0113] The preset algorithm includes at least one of fuzzy logic and a preset neural network algorithm.

[0114] In the embodiment of the present application, when the main processing core is in a non-fault state, it will perform temperature monitoring and speed setting. Specifically, the main processing core will periodically obtain temperature data from a temperature sensor and obtain the PID parameters of the current cycle based on a preset algorithm. As in the foregoing embodiment, the PID parameters include a P gain, an I gain, and a D gain. The preset algorithm can be fuzzy logic or a neural network algorithm to achieve adaptive control. The main processing core can obtain and write the target duty cycle of the next cycle to a PWM controller based on the temperature data of the current cycle and the PID parameters of the current cycle. The calculation methods of the temperature data and the PID parameters can refer to the foregoing embodiment, and are not limited thereto.

[0115] In the embodiment of the present application, when the main processing core is in a normal state, it determines the PID parameters of the current cycle through fuzzy logic or a neural network algorithm, realizes dynamic adjustment of the PID parameters, and then determines the target duty cycle of the next cycle according to the temperature data and the PID parameters, so as to achieve precise heat dissipation.

[0116] In addition, the main processing core also integrates a temperature sensor data fusion algorithm (weighted filtering), and adopts a Kalman filtering or extended Kalman filtering algorithm to improve the accuracy and stability of the obtained temperature data.

[0117] See Figure 2, an embodiment of the present application provides a schematic flowchart for a heat dissipation control system to adjust the fan speed. For the heat dissipation control system, refer to Figure 1 , and the schematic flowchart includes the following steps:

[0118] Step 201, when the main processing core is in a non-fault state, based on the temperature data of the current cycle obtained from the temperature sensor and the PID parameters of the current cycle obtained based on a preset algorithm, obtain and write the target duty cycle of the next cycle to the PWM controller; execute Step 206;

[0119] Step 202, the main processing core periodically writes heartbeat information to the target memory; execute Step 203;

[0120] Step 203, the co-processing core determines whether the main processing core is in a fault state based on the heartbeat information in the target memory. If so, execute Step 204 or Step 205, and execute Step 207; if not, execute Step 201;

[0121] Step 204, the co-processing core obtains and writes the target duty cycle of the next cycle to the PWM controller based on the target operating mode of the server in the current cycle and the temperature data of the current cycle read from the temperature sensor; execute Step 206;

[0122] Step 205, the co-processing core obtains and writes the target duty cycle of the next cycle to the PWM controller based on a preset ratio and the rotational speed of the current cycle obtained by the PWM controller; execute Step 206;

[0123] Step 206, the PWM controller outputs a PWM signal in the next cycle based on the target duty cycle of the next cycle to adjust the rotational speed of the fan in the next cycle;

[0124] Step 207, the co-processing core writes a reset instruction to the target memory; execute Step 207;

[0125] Step 208, the main processing core starts a preset hardware reset circuit based on the reset instruction in the target memory to restart the main processing core through the hardware reset circuit; execute Step 201.

[0126] For the detailed implementation process of each part of the above steps, refer to the foregoing embodiments and will not be elaborated here.

[0127] In some embodiments, the number of fans is multiple; each fan has a corresponding PWM controller;

[0128] The main processing core is specifically configured to, when in a non-fault state, obtain the first reference duty cycle of the next cycle based on the temperature data of the current cycle obtained from the temperature sensor and the PID parameters of the current cycle obtained based on a preset algorithm; the main processor can obtain and write the target duty cycle of the next cycle to the corresponding PWM controller of each fan based on the first reference duty cycle of the next cycle and the weights of each fan; the weights of each fan are obtained based on the fan information of each fan, and the fan information includes at least one of the fan model and the position;

[0129] The co-processing core is specifically configured to obtain the second reference duty cycle of the next cycle based on the target operating mode of the server in the current cycle and the temperature data of the current cycle read from the temperature sensor; obtain and write the target duty cycle of the next cycle to the corresponding PWM controller of each fan based on the second reference duty cycle of the next cycle and the weights of each fan; or,

[0130] Based on the rotation speed of the current cycle obtained based on a preset ratio and the PWM of each fan, obtain and write the target duty cycle of the next cycle to the corresponding PWM controller of each fan.

[0131] The embodiment of the present application also supports a multi-fan collaborative speed regulation strategy.

[0132] It can be understood that there are usually multiple fans in the server. In the same server, the models and positions of the fans may be different, and the positions of each temperature sensor may also be different. This means that the temperatures of each device card in the server are not necessarily the same, and the required heat dissipation levels are not necessarily the same. If each fan rotates at the same speed, it may cause relatively large power consumption.

[0133] To avoid the above situation, when the main processing core and the co-processing core of the embodiment of the present application regulate the rotation speeds of each fan, they will consider the fan information of each fan. The fan information, that is, the fan characteristics, includes at least one of the fan model and the position, and may also include other information, which is not limited herein.

[0134] Specifically, the main processing core is specifically configured to, when in a non-fault state, obtain the first reference duty cycle of the next cycle based on the temperature data of the current cycle obtained from the temperature sensor and the PID parameters of the current cycle obtained based on a preset algorithm. Specifically, the main processor can obtain a weighted sum based on the temperature data and the PID parameters of the current cycle, then obtain the first reference duty cycle based on the weighted sum, and then use the product of the first reference duty cycle of the next cycle and the weights of each fan as the target duty cycle of the corresponding PWM controller of each fan in the next cycle;

[0135] Similarly, the coprocessor core can be based on the target operating mode of the current cycle of the server and the temperature data of the current cycle read from the temperature sensor. Specifically, the coprocessor can obtain a weighted sum based on the temperature data of the current cycle and the PID parameters, and then obtain a second reference duty cycle based on the weighted sum; and then use the product of the second reference duty cycle of the next cycle and the weight of each fan as the target duty cycle of the next cycle of the fan's corresponding PWM controller.

[0136] Targeted heat dissipation can be achieved. Compared with all fans rotating at the same maximum speed, the speed of each fan is determined based on the fan signal and position of each fan, as well as the temperature information of the sensor. This can dissipate heat for each part of the server in a targeted manner, achieving effective heat dissipation while reducing the power consumption caused by heat dissipation.

[0137] In some embodiments, the target memory has an atomic operation lock;

[0138] The co-processing core or the main processing core is also used to write or write data to the target memory when the atomic operation lock is acquired, and release the atomic operation lock after the reading or writing of the data is completed.

[0139] It can be understood that the main processing core and the co-processing core share the target memory. The main processing core can write the above-mentioned first instruction, second instruction, third instruction and heartbeat information, etc. to the target memory, and read the data written by the co-processing core from the target memory. The co-processing core can write the execution result of at least one of the first instruction, the second instruction and the third instruction, as well as the reset instruction, etc. to the target memory, and will also read the data written by the main processing core from the target memory. It is inevitable that the two will read or write data to the shared memory at the same time. This situation will cause the two to occupy the target memory, which is prone to data inconsistency or splitting.

[0140] To avoid the above situation, the present application sets an atomic operation lock for the target memory, which allows only the main processing core or the co-processing core to have access rights (read or write) to the target memory at the same time, so that the main processing core or the co-processing core has exclusive use of the target memory.

[0141] The atomic operation lock ensures that the atomic operation (read or write) will not be interrupted by other operations during execution. In other words, when an atomic operation is performed, the state of the operation is unified throughout the process and will not change in the middle.

[0142] In practical applications, the atomic operation lock can be a mutex lock or a semaphore.

[0143] The embodiment of the present application adopts a bus mechanism of atomic operation lock, which can ensure that the integrity of data is not affected when the dual cores read and write the shared target memory, avoiding the risk of tearing.

[0144] In some embodiments, the co - processing core has a higher write priority to the PWM controller than the main processing core.

[0145] As can be seen from the foregoing embodiments, both the main processing core and the co - processing core have the write permission to the PWM. Logically, the main processing core writes the target duty cycle to the PWM controller in a non - fault state, and the co - processing core writes the target duty cycle to the PWM controller when the main processing core is in a fault state. However, to prevent the main processing core from still occupying the PWM controller in a fault state, the co - processing core is set to have a higher write priority to the PWM controller than the main processing core. Thus, the interference of the main processing core to the co - processing core writing to the PWM can be reduced, thereby improving the real - time performance and stability of the speed control.

[0146] In some embodiments, the co - processing core is further configured to output a first warning and write the first warning to the target memory when the first check value and the second check value are inconsistent; the first warning is used to indicate that the first check value and the second check value in this cycle are inconsistent.

[0147] The co - processing core in the embodiments of the present application can perform real - time hardware monitoring, and the real - time hardware monitoring includes heartbeat information monitoring (also called register mirror monitoring) and PWM duty cycle monitoring.

[0148] In fact, the target memory is composed of multiple registers, and each register has corresponding types of instructions or data.

[0149] After the main processing core updates the heartbeat information in the register each time, the co - processing core will regenerate a second check value, and judge whether the register writing the heartbeat information is tampered with based on the comparison result between the second check value and the first check value. When the first check value and the second check value are consistent, it indicates that the register writing the heartbeat information is not tampered with. When the first check value and the second check value are inconsistent, a first warning will be output, and the first warning is used to indicate that the first check value and the second check value in this cycle are inconsistent. Thus, the user can be informed in time that the heartbeat information is tampered with, which is convenient for manual intervention in time.

[0150] In addition, the first warning can also be written to the target memory, which is convenient for the main processing core to view and perform fault analysis after restart.

[0151] The ways of outputting the first warning information include but are not limited to at least one of voice playback, screen display, signal lamp flashing, etc., and there is no limitation on this.

[0152] In some embodiments, the main processing core is further configured to generate and display a monitoring interface when it is in a non - fault state;

[0153] The monitoring interface includes at least one of the fan speed in each cycle, the temperature heat map generated based on the temperature data in each cycle, and the inter-core communication status between the main processing core and the coprocessing core.

[0154] In the embodiment of the present application, the main processing core can generate a monitoring interface that provides visualization based on various monitoring data obtained through the BMC interface. This display interface can display the fan speed, temperature heat map, and inter-core communication status in real time in each cycle. The monitoring interface can be implemented using Web technology, facilitating remote access.

[0155] In the embodiment of the present application, the main processing core can generate a monitoring interface that includes the fan speed, temperature heat map, and inter-core communication status, which can facilitate users to view the monitoring status of the main processing core in real time.

[0156] In some embodiments, the coprocessing core is further configured to periodically scan the PWM controller to obtain the duty cycle of the PWM controller. When it is determined that the change rate of the duty cycle between two adjacent cycles exceeds the target change rate, a second alarm is output, and the second alarm is written to the target memory; the second alarm is used to indicate that the change rate of the duty cycle between two adjacent cycles exceeds the target change rate.

[0157] The foregoing embodiments have illustrated that real-time hardware monitoring also includes PWM duty cycle monitoring. Specifically:

[0158] The coprocessing core can also periodically scan the duty cycle in the PWM controller, determine the change rate of the duty cycle between two adjacent cycles based on the duty cycle of each cycle in the adjacent chain. If the change rate of the duty cycle between two adjacent cycles is greater than the target change rate (a preset threshold, such as 15%), a second alarm will be output. The second alarm is used to indicate that the change rate of the duty cycle between two adjacent cycles exceeds the target change rate. The target change rate can be adjusted according to the characteristics of the fan (model, location, etc.).

[0159] Thus, the user can be informed in a timely manner of the sudden change in the change rate of the duty cycle, facilitating timely manual intervention.

[0160] In addition, the second alarm can also be written to the target memory, facilitating the main processing core to view and perform fault analysis after restart.

[0161] Similarly, the manner of outputting the second alarm information includes but is not limited to at least one of voice playback, screen display, signal lamp flashing, etc., and is not limited thereto.

[0162] In some embodiments, the coprocessing core is further configured to, for any temperature sensor, when it is determined that the temperature difference between the temperature data of the temperature sensor in two adjacent cycles is greater than the target temperature difference, output a third alarm and write the third alarm to the target memory. The third alarm is used to indicate that the temperature sensor is in a failure state.

[0163] The co - processing core in the embodiments of the present application can also perform sensor failure detection and second - derivative threshold detection.

[0164] For sensor failure detection, the co - processing core is further configured to, for any temperature sensor, when determining that the temperature difference between the temperature data of two adjacent cycles of the temperature sensor is greater than a target temperature difference (a preset value, such as 10°), output a third warning, and write the third warning to a target memory. The third warning is used to indicate that the temperature sensor is in a failure state.

[0165] Thus, the user can be informed of the sensor failure in a timely manner, facilitating timely manual intervention.

[0166] In addition, the third warning can also be written to the target memory, facilitating the main processing core to view and perform fault analysis after restart.

[0167] Similarly, the manner of outputting the third warning message includes but is not limited to at least one of voice playback, screen display, signal lamp flashing, etc., and is not limited thereto.

[0168] In some embodiments, the co - processing core is further configured to, for any temperature sensor, generate a temperature change curve based on the temperature data of each cycle of the temperature sensor, obtain the rate of change of the temperature change based on the temperature change curve, and when determining that the rate of change of the temperature change is greater than a target rate of change, output a fourth warning message and write the fourth warning to the target memory. The fourth warning is used to indicate that there is hardware noise in the temperature sensor.

[0169] The co - processing core in the embodiments of the present application also needs to analyze the smoothness of the temperature change curve, that is, perform a second - order derivative on the temperature change curve. Thus, the rate of change of the temperature change can be obtained. When determining that the rate of change of the temperature change is greater than the target rate of change, a fourth warning message is output, thereby informing the user that there is hardware noise in the temperature sensor.

[0170] Thus, the user can be informed of the hardware noise in the temperature sensor in a timely manner, facilitating timely manual intervention.

[0171] In addition, the fourth warning can also be written to the target memory, facilitating the main processing core to view and perform fault analysis after restart.

[0172] Similarly, the manner of outputting the fourth warning message includes but is not limited to at least one of voice playback, screen display, signal lamp flashing, etc., and is not limited thereto.

[0173] In some embodiments, the co - processing core is further configured to generate a snapshot of the target memory after writing a reset instruction to the target memory and store the snapshot in the target storage.

[0174] The embodiments of the present application also support snapshot storage. After the co-processing core writes a reset instruction to the target memory, it can generate and store a snapshot of the target memory in the target memory, and the target memory can be a non-volatile memory. Thus, it is convenient for the main processing core to view and perform fault analysis after restarting.

[0175] In addition, the co-processing core of the embodiments of the present application can also transmit fault information and logs to a remote management platform through the IPMI channel, which is convenient for users to remotely monitor and maintain the server.

[0176] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0177] The embodiments of the present application also provide a computer-readable storage medium, in which a computer program is stored, and the computer program is configured to implement the heat dissipation control system of the server.

[0178] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drive, read-only memory (ROM for short), random access memory (RAM for short), mobile hard disk, magnetic disk, or optical disc and other various media that can store computer programs.

[0179] The embodiments of the present application also provide a computer program product, and the above computer program product includes a computer program, and the computer program can implement the heat dissipation control system of the aforementioned server.

[0180] The embodiments of the present application also provide another computer program product, including a non-volatile computer-readable storage medium, and the non-volatile computer-readable storage medium stores a computer program.

[0181] The embodiments of the present application also provide a server, and the server includes the heat dissipation control system of the aforementioned server.

[0182] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0183] The above has introduced in detail a heat dissipation control system for a server provided in this application. Specific examples are used herein to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of this application, several improvements and modifications can still be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A heat dissipation control system for a server, characterized in that, Including: A baseboard management controller, a temperature sensor, a fan, a pulse width modulation (PWM) controller, and a target memory; The baseboard management controller includes a main processing core and a coprocessing core; The main processing core and the coprocessing core share the target memory; Target instructions are stored in the target memory; The main processing core is used to periodically write heartbeat information to the target memory; The coprocessing core is used to skip executing the target instructions when it is determined based on the heartbeat information in the target memory that the main processing core is in a non-fault state; The coprocessing core is used to execute the target instructions through the following operations when it is determined based on the heartbeat information in the target memory that the main processing core is in a fault state: Based on the target operating mode of the server in the current cycle and the temperature data of the current cycle read from the temperature sensor, obtain and write the target duty cycle of the next cycle to the PWM controller; Or, Based on a preset ratio and the rotational speed obtained by the PWM controller in the current cycle, obtain and write the target duty cycle of the next cycle to the PWM controller; the preset ratio is used to reduce the rotational speed of the next cycle; The PWM controller is used to output a PWM signal based on the target duty cycle of the next cycle in the next cycle to adjust the rotational speed of the fan in the next cycle.

2. The heat dissipation control system of the server according to claim 1, wherein The coprocessing core is further used to write a reset instruction to the target memory when it is determined based on the heartbeat information in the target memory that the main processing core is in a fault state; The main processing core is further used to start a preset hardware reset circuit based on the reset instruction of the target memory to restart the main processing core through the hardware reset circuit.

3. The heat dissipation control system of the server according to claim 1, wherein The main processing core and the coprocessing core are heterogeneous processing cores; The main processing core runs a heavyweight operating system; the coprocessing core runs a lightweight real-time operating system.

4. The heat dissipation control system of the server according to claim 1, wherein The write priority of the coprocessing core to the PWM controller is higher than the write priority of the main processing core to the PWM controller.

5. The heat dissipation control system of the server according to claim 1, wherein The main processing core is specifically used to obtain and write the target duty cycle of the next cycle to the PWM controller based on the temperature data of the current cycle obtained from the temperature sensor and the PID parameters of the current cycle obtained based on a preset algorithm when in a non-fault state; The preset algorithm includes at least one of fuzzy logic and a preset neural network algorithm.

6. The heat dissipation control system of the server according to claim 1, characterized in that The heartbeat information includes the monitoring metrics of the current cycle and the first check value generated by the main processing core based on the monitoring metrics of the current cycle; the monitoring metrics include at least part of the serial number, timestamp, and CPU load of the current cycle; The co - processing core is further configured to, when detecting that the main processing core writes the heartbeat information to the target memory, generate a second verification value based on the monitoring metrics in the heartbeat information, and determine that the main processing core is in a non - fault state when the first verification value in the current cycle is consistent with the second verification value.

7. The heat dissipation control system of the server according to claim 6, wherein the co - processing core is further configured to send a first signal to the watchdog when the first verification value in the current cycle is consistent with the second verification value; the watchdog is configured to send a second signal to the co - processing core when it has not received the first signal for more than a target number of cycles; the target number is determined based on the load of the CPU obtained last time and / or the network status in the current cycle, or is a preset default value; the co - processing core is further configured to determine that the main processing core is in a fault state based on the second signal.

8. The heat dissipation control system of the server according to claim 6, characterized in that the co - processing core is further configured to output a first alarm and write the first alarm to the target memory when the first verification value is inconsistent with the second verification value; the first alarm is used to indicate that the first verification value in the current cycle is inconsistent with the second verification value.

9. The heat dissipation control system of the server according to claim 1, characterized in that, The target instruction includes at least one of a first instruction, a second instruction, and a third instruction; The first instruction is used to instruct the co - processing core to read temperature data from the temperature sensor; The second instruction is used to instruct the co - processing core to write a duty cycle to the PWM controller; The third instruction is used to instruct the co - processing core to report its own status to the main processing core.

10. The heat dissipation control system of the server according to claim 1, characterized in that, The target memory has an atomic operation lock; The co - processing core or the main processing core is further configured to write or write data to the target memory when obtaining the atomic operation lock, and release the atomic operation lock after reading or writing the data.

11. The heat dissipation control system of the server according to claim 1, wherein the main processing core is further configured to generate and display a monitoring interface when in a non - fault state; The monitoring interface includes at least one of the fan speed in each cycle, a temperature heat map generated based on the temperature data in each cycle, and the inter - core communication status between the main processing core and the co - processing core.

12. The heat dissipation control system of the server according to any one of claims 1 - 11, wherein the co - processing core is further configured to periodically scan the PWM controller to obtain the duty cycle of the PWM controller, output a second alarm and write the second alarm to the target memory when determining that the change rate of the duty cycle between two adjacent cycles exceeds a target change rate; the second alarm is used to indicate that the change rate of the duty cycle between two adjacent cycles exceeds the target change rate.

13. The heat dissipation control system of the server according to any one of claims 1 - 11, wherein The co - processing core is further configured to, for any temperature sensor, in the case where the temperature difference between the temperature data of two adjacent periods of the temperature sensor is determined to be greater than the target temperature difference, output a third warning and write the third warning to the target memory, where the third warning is used to indicate that the temperature sensor is in a failure state.

14. The heat dissipation control system of the server according to any one of claims 1 - 11, wherein The co - processing core is further configured to, for any temperature sensor, generate a temperature change curve based on the temperature data of each period of the temperature sensor, obtain a change rate of the temperature change based on the temperature change curve, in the case where the change rate of the temperature change is determined to be greater than the target change rate, output a fourth warning message and write the fourth warning to the target memory, where the fourth warning is used to indicate that there is hardware noise in the temperature sensor.

15. The heat dissipation control system of the server according to any one of claims 1-11, characterized in that, The co - processing core is further configured to, after writing a reset instruction to the target memory, generate a snapshot of the target memory and store the snapshot in a target storage.

16. A server, characterized in that, Comprising the heat dissipation control system of the server according to any one of claims 1 - 15.

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