Button detection jitter removal implementation method
A FPGA-based key detection system addresses the complexity of key bounce in multiple-key scenarios by using a counter and control module for XOR operations and threshold checks, achieving efficient and flexible key bounce elimination.
Patent Information
- Application Number
- CN202510385334.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2025-07-15
AI Technical Summary
The prior art requires multiple control registers in key detection, which leads to complex controllers and large amount of logical resources, making it difficult to effectively remove key jitter.
The simple key detection debounce method implemented by FPGA is adopted. By constructing a count controller, counter, judgment module and control module, and using XOR operation and count threshold judgment, stable detection of key input and output signals is achieved.
It realizes jitter removal when key presses and lifts, and has flexible configurations, reducing controller complexity and logical resource usage.
Smart Images
Figure CN120320747A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of computer board design, and particularly relates to a method for realizing key detection and debouncing. Background Art
[0002] The length of the jitter time is determined by the mechanical characteristics of the key, generally 5 ms to 10 ms. This is a very important time parameter and is used in many occasions. The length of the stable closing time of the key is determined by the operator's key-pressing action, generally from a few tenths of a second to several seconds. Key jitter can cause a single key press to be misread multiple times. To ensure that the CPU processes only one closure of the key, it is necessary to remove the key jitter. Read the state of the key when it is stably closed, and it must be determined that the key has been released stably before further processing.
[0003] Debouncing is to avoid the influence caused by the severe jitter of the level when the key is pressed or released. Debouncing of the key can be achieved by either hardware or software methods.
[0004] Hardware Debouncing:
[0005] When the number of keys is small, the hardware method can be used to eliminate key jitter. The RS flip-flop shown in the following figure is a commonly used hardware debouncer. In the figure, two NAND gates form an RS flip-flop. When the key is not pressed, the output is 0; when the key is pressed, the output is 1. At this time, even if the mechanical properties of the key cause the key to have an instantaneous disconnection (jitter jump to B) due to elastic jitter, as long as the key does not return to the original state A, the state of the bistable circuit does not change, and the output remains 0, and no jitter waveform will be generated. That is to say, even if the voltage waveform at point B is jittery, after passing through the bistable circuit, its output is a regular rectangular wave. This can be easily verified by analyzing the working process of the RS flip-flop.
[0006] Software Debouncing:
[0007] If there are many keys, the software method is commonly used for debouncing, that is, after detecting that the key is closed, a delay program is executed for a delay of 5 ms to 10 ms. After the front-edge jitter disappears, the state of the key is detected again. If the closed-state level is still maintained, it is confirmed that there is a real key press. When it is detected that the key is released, a delay of 5 ms to 10 ms is also given, and after the trailing-edge jitter disappears, the processing program of this key can be entered.
[0008] Generally speaking, the software debouncing method is to continuously detect the key value until the key value is stable. Implementation method: Assume that the input is 1 when the key is not pressed, the input is 0 after the key is pressed, and it is uncertain during jitter. The following detections can be made: After detecting that the key input is 0, delay for 5 ms to 10 ms, and then detect again. If the key is still 0, then it is considered that there is a key input. The delay of 5 ms to 10 ms just avoids the jitter period.
[0009] The prior art requires multiple control registers for multiple state machine jump controls such as input detection, counting control, input detection confirmation, re - counting control, input end detection, and input end delay control. The controller is complex and occupies a large amount of logic resources. Summary of the Invention
[0010] The purpose of the present invention is to overcome the deficiencies of the prior art and propose a method for realizing key detection and debouncing. A simple key detection and debouncing method implemented by FPGA can not only eliminate the jitter when the key is pressed but also eliminate the jitter when the key is released, with flexible configuration.
[0011] The present invention solves its technical problems by adopting the following technical solutions:
[0012] A method for realizing key detection and debouncing includes the following steps:
[0013] Step 1: Construct a key detection and debouncing system;
[0014] Step 2: According to the key detection and debouncing system constructed in Step 1, set signals and debouncing methods;
[0015] Step 3: Input the key input into the key detection and debouncing system for debouncing.
[0016] Moreover, the specific implementation method of Step 1 is as follows: The key detection and debouncing system uses a counting controller, a counter, a judgment module, and a control module in the FPGA. Among them, the counting controller, the counter, the judgment module, and the control module are connected in sequence. The counting controller is used to perform an exclusive - OR operation on the key input signal and the debounced output signal. The counter is used to output a count value. The judgment module is used to judge whether the count reaches a threshold. The control module is used to perform an operation of inverting the debounced output signal or maintaining the debounced output signal.
[0017] Moreover, the signals set in Step 2 are an input clock signal clk; a key input signal dsty_in; a debounced output signal: dsty_jitter; a counting register cnt for storing the preset detection jitter clock cycle; a counting control signal dsty_ctr for controlling the counter jitter detection time.
[0018] Moreover, Step 3 includes the following steps:
[0019] Step 1: Detect the low level of the key input dsty_in, set the reset initial value of the debounced output signal dsty_jitter to high; the initial value of the counter is 0;
[0020] Step 2: After a key input is detected and a low level is detected, if the XOR of the input signal and the debounced output signal is high, debounce counting is performed. If the key input becomes high before the count value is reached, it is determined as a jitter key. If the XOR of the input signal and the debounced output signal is low, the count value is cleared and the debounced output remains unchanged;
[0021] Step 3: After a key input is detected and a low level is detected, if the XOR of the input signal and the debounced output signal is high, debounce counting is performed. If the key is released after a key press time longer than the counting time, it is determined as a real key. After the counter accumulates to a predetermined threshold, the counting stops, the debounced output signal is inverted, and a low level is output. Further, the counter is cleared by XORing with the low level of the key input;
[0022] Step 4: After the key is released, the key input becomes high. After XORing with the debounced output (which is low), it becomes high, controlling the counter to work. After counting to a predetermined value, the debounced output signal becomes high, and further XORing with the input signal controls the counter to stop working.
[0023] The advantages and positive effects of the present invention are:
[0024] The present invention constructs a key detection and debounce system; according to the constructed key detection and debounce system, wherein a count controller, a counter, a judgment module, and a control module are connected in sequence. The count controller is used to perform an XOR operation on the key input signal and the debounced output signal. The counter is used to output a count value. The judgment module is used to judge whether the count reaches a threshold. The control module is used to perform an operation of inverting the debounced output signal or keeping the debounced output signal unchanged; setting signals and debounce methods; inputting the key input into the key detection and debounce system to achieve key detection and debounce. The simple key detection and debounce method implemented by the present invention using FPGA can not only eliminate the jitter when the key is pressed, but also eliminate the jitter when the key is lifted, and has flexible configuration. At the same time, the present invention can flexibly control the jitter detection time by configuring the counter value. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 is a flowchart of the present invention. DETAILED DESCRIPTION OF THE INVENTION
[0026] The following further describes the present invention in detail with reference to the drawings.
[0027] A method for realizing key detection and debounce includes the following steps:
[0028] Step 1: Construct a key detection and debounce system.
[0029] The key detection and debounce system uses a count controller, a counter, a judgment module, and a control module in an FPGA. Among them, the count controller, the counter, the judgment module, and the control module are connected in sequence. The count controller is used to perform an exclusive OR operation on the key input signal and the debounce output signal. The counter is used to output a count value. The judgment module is used to judge whether the count reaches a threshold value. The control module is used to perform an operation of inverting the debounce output signal or maintaining the debounce output signal.
[0030] Step 2: According to the key detection and debounce system constructed in Step 1, set the signals and the debounce method.
[0031] The set signals are the input clock signal clk; the key input signal dsty_in; the debounce output signal: dsty_jitter; the count register cnt, which is used to store the preset detection jitter clock cycle; the count control signal dsty_ctr, which is used to control the counter jitter detection time.
[0032] Step 3: Input the key to the key detection and debounce system for debouncing.
[0033] As Figure 1 shown, Step 3 includes the following steps:
[0034] Step 1: Assume that the low level of the key input (dsty_in) is detected, and set the reset initial value of the debounce output signal (dsty_jitter) to high; the initial value of the counter is 0;
[0035] Step 2: After there is a key input and a low level is detected, after the input signal is exclusive ORed with the debounce output signal and the result is high, perform debounce counting. Assume that before the count value is reached, the key input becomes high (jittery key), after the input signal is exclusive ORed with the debounce output signal and the result is low, the count value is cleared, and the debounce output remains unchanged (high);
[0036] Step 3: After there is a key input and a low level is detected, after the input signal is exclusive ORed with the debounce output signal and the result is high, perform debounce counting. Assume that the key is released after a long press (real key), after the counter accumulates to the predetermined threshold, the counting stops, the debounce output signal is inverted, and the output is low. Further, after being exclusive ORed with the low key input, it controls the counter to be cleared.
[0037] Step 4: After the key is released, the key input becomes high. After being exclusive ORed with the debounce output (low), the result becomes high, which controls the counter to work. After counting to the predetermined value, the debounce output signal becomes high. Further, after being exclusive ORed with the input signal, it controls the counter to stop working.
[0038] The advantages and positive effects of the present invention are:
[0039] The present invention realizes key detection and debouncing by constructing a key detection and debouncing system; according to the constructed key detection and debouncing system, wherein, a counting controller, a counter, a judgment module and a control module are connected in sequence. The counting controller is used for performing an exclusive OR operation on the key input signal and the debounced output signal. The counter is used for outputting a count value. The judgment module is used for judging whether the count reaches a threshold value. The control module is used for performing an operation of inverting the debounced output signal or maintaining the debounced output signal; setting signals and a debouncing method; inputting the key input into the key detection and debouncing system. The simple key detection and debouncing method implemented by the present invention using FPGA can not only eliminate the jitter when the key is pressed, but also eliminate the jitter when the key is lifted, and has flexible configuration. At the same time, the present invention can flexibly control the jitter detection time by configuring the counter value.
[0040] It should be emphasized that the embodiments described in the present invention are illustrative rather than restrictive. Therefore, the present invention includes but is not limited to the embodiments described in the specific embodiments. Any other embodiments obtained by those skilled in the art according to the technical solutions of the present invention also belong to the scope of protection of the present invention.
Claims
1. A method for implementing key detection and debouncing, characterized in that: Including the following steps: Step 1: Construct a key detection and debounce system; Step 2: Set signals and debounce methods according to the key detection and debounce system constructed in Step 1; Step 3: Input the key input into the key detection and debounce system for debouncing.
2. The key detection and debounce implementation method according to claim 1, wherein: The specific implementation method of Step 1 is as follows: The key detection and debounce system uses a counting controller, a counter, a judgment module, and a control module in the FPGA. Among them, the counting controller, the counter, the judgment module, and the control module are connected in sequence. The counting controller is used to perform an exclusive OR operation on the key input signal and the debounce output signal. The counter is used to output a count value. The judgment module is used to judge whether the count reaches the threshold. The control module is used to perform an operation of inverting the debounce output signal or maintaining the debounce output signal.
3. A method for implementing key detection and debouncing according to claim 1, characterized in that: The signals set in Step 2 are: input clock signal clk; key input signal dsty_in; debounce output signal: dsty_jitter; counting register cnt, which is used to store the preset detection jitter clock cycle; counting control signal dsty_ctr, which is used to control the counter jitter detection time.
4. A method for implementing key detection and debouncing according to claim 1, characterized in that: Step 3 includes the following steps: Step 1: Detect the low level of the key input dsty_in, and set the reset initial value of the debounce output signal dsty_jitter to high; the initial value of the counter is 0; Step 2: After a key input, when a low level is detected, if the exclusive OR of the input signal and the debounce output signal is high, perform debounce counting. If the key input becomes high before the count value is reached, it is recognized as a jitter key. If the exclusive OR of the input signal and the debounce output signal is low, the count value is cleared and the debounce output remains unchanged; Step 3: After a key input, when a low level is detected, if the exclusive OR of the input signal and the debounce output signal is high, perform debounce counting. If the key is released after a time longer than the counting time, it is recognized as a real key. After the counter accumulates to the predetermined threshold, the counting stops, the debounce output signal is inverted, and a low level is output. Further, the exclusive OR with the low key input controls the counter to be cleared; Step 4: After the key is released, the key input becomes high. The exclusive OR with the debounce output (which is low) becomes high, controlling the counter to work. After counting to the predetermined value, the debounce output signal becomes high, and further the exclusive OR with the input signal controls the counter to stop working.