Frequency offset estimation method and system for QPSK (Quadrature Phase Shift Keying) modulation format signal

Abstract

The invention provides a frequency offset estimation method and system for a QPSK modulation format signal. The method comprises the steps of 1, converting an input serial signal into a parallel signal; 2, coarse frequency offset estimation with the symbol delay length being 1 and the interval extraction length being n is carried out on the parallel signals; 3, converting a coarse frequency deviation phase component, and performing coarse compensation; 4, performing fine frequency offset estimation with the symbol delay length of L and the interval extraction length of n on the signal subjected to coarse compensation; and step 5, adding the fine frequency offset and the coarse frequency offset to obtain final frequency offset, and restoring the final frequency offset to the phase for final frequency offset compensation. According to the method, the design thought of interval extraction is applied to the two-stage frequency offset estimation method, so that the operation complexity is reduced, and the resource use of the field programmable gate array is reduced.

Description

Technical Field

[0001] The present application relates to the field of communication technologies, and particularly to a frequency offset estimation method and system for QPSK modulation format signals. Background Art

[0002] QPSK is a Quadrature Phase Shift Keying (QPSK) modulation format, which is commonly used in the field of coherent communication. In theory, coherent communication requires that the receiving end has a local oscillator electromagnetic wave with the same frequency and phase as the transmitting end for coherent demodulation. However, due to device processes and actual working environments, the center frequencies of the local oscillators at the transmitting and receiving ends cannot be guaranteed to be the same frequency, so frequency offset will occur. The frequency offset will accumulate over time as a phase offset, causing the symbol constellation diagram of the QPSK format to rotate, twisting the symbol from one decision region to another decision region, thereby generating bit errors. When the frequency offset is large, it will cause the receiving environment to deteriorate sharply, thus affecting the transmission quality.

[0003] In an actual hardware receiving system, algorithms are often deployed on a Field-Programmable Gate Array (FPGA) for frequency offset estimation. There is an existing two-stage frequency offset estimation algorithm, which is a high-precision frequency offset estimation algorithm and can achieve correct frequency offset estimation under harsh conditions. However, the calculations in the two stages involve a large number of complex multiplication steps, which will cause the number of mathematical operations to increase exponentially, resulting in a large consumption of internal resources of the FPGA, thereby increasing the system cost. Summary of the Invention

[0004] The purpose of the present application is to provide a frequency offset estimation method and system for QPSK modulation format signals, which is used to solve the problem of excessive computational complexity of the two-stage frequency offset estimation algorithm, and can reduce the number of operations and the use of hardware resources without sacrificing performance.

[0005] The technical solution for achieving the object of the present invention is as follows:

[0006] A frequency offset estimation method for QPSK modulation format signals includes the following steps:

[0007] Step 1: Convert the input serial signal into a parallel signal with a parallelism of N;

[0008] Step 2: Perform a coarse frequency offset estimation on the parallel signal with a symbol delay length of 1 and an interval extraction length of n;

[0009] Step 3: For the estimated coarse frequency offset, perform a conversion from the coarse frequency offset to the phase component and perform the first compensation;

[0010] Step 4: Perform fine frequency offset estimation on the signal after coarse compensation, with a symbol delay length of L and an interval extraction length of n.

[0011] Step 5: For the estimated coarse frequency offset and fine frequency offset, add the fine frequency offset and the coarse frequency offset to obtain the final frequency offset, and restore the phase for the final frequency offset compensation.

[0012] Further, in the said Step 1, each clock cycle of the serial signal contains only one sampled data S0, S1, S2, … S k ..., where k is the signal subscript and is a positive integer. For the serial signal, perform parallel deceleration processing with a parallelism of N, then the signals in each clock cycle are respectively S0 to S N-1 , S N to S 2N-1 ..., S k to S k+N-1 ..., etc.

[0013] Further, in the said Step 2, first, it is necessary to delay the signal by one sampling length. For the signal S k to S k+N-1 within a single clock cycle, after delaying by one symbol, it becomes 0, S k to S k+N-2 , and then take the conjugate to get 0, where * represents the conjugate operation. For the signals before and after delay, perform extraction with an interval length of n. For S k to S k+N-1 before delay, after extraction, the remaining signals are S k , S k+n , S k+2n , …, for the signal after delay and taking the conjugate, after extraction, the remaining are 0, Multiply them respectively, take the fourth power and sum them up, we have:

[0014]

[0015] Take the argument of p1 and divide it by the coefficient to obtain the estimator where m represents the upper and lower bounds of the summation, starting from 0, stepping by 1 until N / n ends, Δω is the estimated coarse angular frequency offset, T s is the signal sampling interval, and arg represents the angle calculation operation.

[0016] Further, in the said Step 3, convert the frequency offset amount into the phase ΔωT s . According to the signal sampling principle, t = kT s , so multiply ΔωT s by the sampling time base k to restore it to the phase: And construct the complex exponential Multiply the original signal by a complex exponential for coarse frequency offset compensation: where S' k is the signal after coarse compensation.

[0017] Further, in the step 4, for the signal S' after coarse compensation k ~S' k+N-1 delay by L symbol lengths, then each clock period of the signal becomes: 0, …0, S' k ~S' k+N-L-1 , there are the first L 0s, then take the conjugate to get Then perform decimation with an interval length of n. Since there are the first L 0s, participating in the decimation calculation will affect the subsequent accuracy. Therefore, this step starts decimating from the signal at index L. The signals before and after the delay are respectively decimated into: S' k+L , S' k+n+L , … and Multiply them respectively, take the fourth power and sum them up, we have:

[0018]

[0019] where m represents the upper and lower bounds of the summation, starting from 0, stepping by 1 until (N - L) / n ends. Take the argument of p2 and divide by the coefficient to obtain the fine estimator where Δω' is the estimated fine angular frequency offset.

[0020] Further, in the step 5, the final frequency offset is the sum of the coarse and fine frequency offsets: ωT s = ΔωT s + Δω'T s , multiply ωT s by the sampling time base k to restore it to a phase: and construct a complex exponential Multiply the original signal by the complex exponential for the final compensation: where S f is the signal with the final frequency offset removed.

[0021] A frequency offset estimation system for QPSK modulation format signals, comprising:

[0022] A signal conversion unit that converts an input serial signal into a parallel signal;

[0023] A coarse frequency offset estimation unit that performs coarse frequency offset estimation on the parallel signal with a symbol delay length of 1 and an interval decimation length of n;

[0024] A coarse compensation unit that converts the estimated coarse frequency offset into a phase component and performs the first compensation;

[0025] A fine frequency offset estimation unit performs fine frequency offset estimation on the signal after coarse compensation, with a symbol delay length of L and an interval extraction length of n.

[0026] A comprehensive compensation unit adds the estimated fine frequency offset and coarse frequency offset to obtain the final frequency offset, restores it to the phase, and performs final frequency offset compensation.

[0027] This application provides a field programmable gate array to implement the steps of the above frequency offset estimation method.

[0028] Compared with the prior art, the beneficial effects of the present invention are:

[0029] For the problem of excessive number of complex multiplications in the existing two-stage frequency offset estimation method, the frequency offset estimation method provided in this application adopts the method of interval extraction in the conjugate multiplication module to reduce the number of multiplication operations, thereby reducing the operation complexity, and further reducing the hardware resource consumption of this method on the field programmable gate array and controlling the cost. Experiments show that the method provided in this application can retain the bit error rate performance of the original method while reducing the resource usage by more than 50%. Brief Description of the Drawings

[0030] Figure 1 It is a flowchart of the frequency offset estimation method provided in an embodiment of this application.

[0031] Figure 2 It is a data parallelization structure diagram in the frequency offset estimation method provided in an embodiment of this application.

[0032] Figure 3 It is a field programmable gate array structure diagram of the first-stage coarse estimation in an embodiment of this application.

[0033] Figure 4 It is a field programmable gate array structure diagram of the first-stage coarse frequency offset compensation in an embodiment of this application.

[0034] Figure 5 It is a field programmable gate array structure diagram of the second-stage fine estimation in an embodiment of this application.

[0035] Figure 6 It is a field programmable gate array structure diagram of the final frequency offset compensation in an embodiment of this application.

[0036] Figure 7 It is a function image for determining the optimal parameter n in an embodiment of this application.

[0037] Figure 8 It is an experimental result diagram for determining the optimal parameter L in an embodiment of this application.

[0038] Figure 9The error rate simulation curve of a frequency offset estimation method provided by an embodiment of the present application. Detailed implementation manners

[0039] To make the technical solutions and advantages of the present application clearer, the embodiments of the present application will be introduced in detail below with reference to the accompanying drawings.

[0040] Please refer to Figure 1 , Figure 1 A flowchart of a frequency offset estimation method for signals with a QPSK modulation format provided by the present application, and its steps are as follows:

[0041] Step 1: Convert the input serial signal into a parallel signal;

[0042] Step 2: Perform a coarse frequency offset estimation on the parallel signal with a symbol delay length of 1 and an interval extraction length of n;

[0043] Step 3: For the estimated coarse frequency offset, perform a conversion from the coarse frequency offset to the phase component and perform the first compensation;

[0044] Step 4: Perform a fine frequency offset estimation on the signal after the coarse compensation with a symbol delay length of L and an interval extraction length of n;

[0045] Step 5: For the estimated coarse frequency offset and fine frequency offset, add the fine frequency offset and the coarse frequency offset to obtain the final frequency offset, restore it to the phase and perform the final frequency offset compensation.

[0046] Please refer to Figure 2 , Figure 2 The data parallelization structure required for an embodiment of the present application, corresponding to Step 1. Since the analog data enters the field programmable gate array for signal processing after being sampled by the analog-to-digital converter, the interval time between adjacent data is the sampling time. When the sampling rate is very high, the data rate will exceed the maximum frequency that the field programmable gate array can work at. To enable the embodiments of the present application to work properly, parallelization speed reduction processing is required. Figure 2 The structure shown processes N serial data in N clock cycles originally in one clock cycle. At this time, the clock cycle can be reduced to 1 / N of the original, and the frequency becomes 1 / N of the original, greatly reducing the requirement for the system working frequency.

[0047] In different rate scenarios, the value of the parallelism N needs to be determined according to specific circumstances, and the value of N does not affect the feasibility of this embodiment.

[0048] Please refer to Figure 3 , Figure 3In the embodiment of the present application, it is a field programmable gate array circuit structure for implementing step 2. In the figure, data blocks of 1 to T clock cycles are first marked, and their internal structures are the same. Taking the first data block as an example, its content is in step 2 For the specific implementation, if decimation with an interval length of n is not performed, the upper bound of m will be N. After decimation, the upper bound becomes N / n, and the amount involved in the operation becomes one nth of the original, thereby reducing the number of operations.

[0049] Furthermore, after all T data blocks are decimated and the fourth-power summation is completed, it is also necessary to accumulate and average all the results in the T data blocks to reduce the influence of noise. After the accumulation and averaging are completed, the arg angle calculation is performed. Then the coarse frequency offset can be estimated

[0050] It should be noted that in a field programmable gate array, the division operation will consume a large amount of logic resources. Therefore, dividing by 4 can be replaced with a shift operation to reduce the delay and resource usage.

[0051] Please refer to Figure 4 , Figure 4 In the embodiment of the present application, it is a field programmable gate array circuit structure for implementing step 3. For the estimated coarse frequency offset ΔωT s , the next step is to multiply by the time base k to convert it to ΔωkT s , and this parallel process is achieved through accumulation. It is preset that K = [1, 2,..., N]. All signals of each clock cycle are first multiplied by K and then added to the last signal of the previous clock cycle to achieve the infinite superposition of k. Its expression is Δω n KT s +Δω n-1 NT s =ΔωkT s , realizing the conversion of frequency offset to phase, where n only represents the sequence of time. Figure 4 Z in -1 represents the delay of one clock cycle, which is used to cache the last data.

[0052] Furthermore, the phase is converted to a complex exponential through the CORDIC integrated in the field programmable gate array The overall input data will be pre-cached to the FIFO, and then participate in the compensation step to achieve coarse frequency offset compensation.

[0053] Please refer to Figure 5 , Figure 5 In the embodiment of the present application, it is a field programmable gate array circuit structure for implementing step 4. Similarly, data blocks of T clock cycles are marked. Taking the first data block as an example, the data before and after the delay are decimated starting from the Lth data respectively, and then multiplied and taken to the fourth root. There is:

[0054]

[0055] This step differentiates the method of the present application from the original method. The present application has only (N - L) / n multiplications, while the original method has N - L multiplications. The operation count is reduced by decimation. Then, the data within T clock cycles are added and averaged to remove the influence of noise, and then the angle is calculated and divided by 4.

[0056] It should be noted that after obtaining the angle and dividing it by 4 in the fine frequency offset estimation, it is also necessary to divide by the symbol delay length L again to improve the resolution of the fine frequency offset estimation, and finally the fine frequency offset is obtained.

[0057] Please refer to Figure 6 , Figure 6 which is the field programmable gate array circuit structure used to implement step 5 in the embodiment of the present application. The final frequency offset ωT obtained by adding the coarse and fine frequency offsets s = ΔωT s + Δω'T s will be converted back to the phase component again. K = [1, 2,... N] is preset. For all signals in each clock cycle, they are first multiplied by K and then added to the last signal of the previous clock cycle to achieve the infinite superposition of k. Its expression is ω n KT s + ω n-1 NT s = ωkT s . After being converted to the phase, it is necessary to convert the phase to the complex exponential through CORDIC. The input range of CORDIC is limited to (-π, π]. Therefore, there is a quadrant correction look-up table (LUT) to limit the input range. The process of the look-up table is a linear process. By judging the range where the angle is located, it is rotated back to (-π, π] without affecting the result. The phase is converted to the complex exponential and then multiplied by the data to be compensated stored in the FIFO to achieve the final compensation.

[0058] The optimal parameters of the embodiment of the present application need to be determined through the following derivation. Since the algorithm includes two stages before and after, it is required that the total amount of information involved in the calculation of the two stages is similar to the amount of information in the first-stage coarse estimation. The parameter N is the parallelism, n is the interval decimation length, T is the averaging period, and L is the symbol delay length in the second stage. For the traditional method, the total number of symbols involved in the operation within each average length is NT, while for the method of the present application, to ensure the effectiveness of the algorithm, the averaging period is appropriately extended to 2T. Therefore, the number of symbols involved in the operation is (4N - 2L)T / n. It is required that the number of these two symbols is close, and the equation is constructed

[0059]

[0060] Cancel out T. According to different experimental environments, the parallelism N can be determined first. Under the experimental conditions of this application, N is 16. Construct the binary function f(n, L) as:

[0061]

[0062] Then discuss its domain of definition. n represents the interval step size selected at intervals, taking the k-th power of 2 and not exceeding 8. After exceeding this value, only at least one data participates in the calculation. L represents the delay length in the second stage, also taking the k-th power of 2 and having a minimum delay of 2 symbols. Otherwise, it cannot be distinguished from the first stage and the residual frequency offset cannot be distinguished. Under this constraint, it also cannot exceed 8. Therefore, the domain of definition of f(n, L) is {1 ≤ n ≤ 8, 2 ≤ L ≤ 8}.

[0063] Next, take the partial derivatives of f(n, L) with respect to L and n respectively to get:

[0064]

[0065] The partial derivative represents the change rate of the function with respect to the two independent variables. According to the domain of definition, the value range of is [-2, 1 / 4], while the value range of is not intuitive. According to the definition of the extreme value of the binary function, let there is 2L - 64 = 0, which is obviously unsolvable in the domain of definition. Therefore, consider the four boundary points of the domain of definition: (1, 2), (1, 8), (8, 2), (8, 8), and substitute them into to calculate the value range. Finally, there is:

[0066]

[0067] It can be seen that the change rate of the binary function f(n, L) in the L direction is obviously less than that of n, and n has the greatest influence on f(n, L). At the same time, the function is monotonic with respect to the two independent variables, and this property simplifies the analysis. Therefore, for the other independent variable L, the linear functions f(n, 2) and f(n, 8) can be constructed by taking its upper and lower bounds respectively.

[0068] Please refer to Figure 7 , Figure 7 which is the function image used to determine the optimal parameter n in the embodiment of this application. From Figure 7 it can be seen that when n takes 4, it is closest to the position where N = 16 is located, which can ensure the optimized performance of the algorithm and further reduce the calculation amount.

[0069] Please refer to Figure 8 , Figure 8In the embodiments of this application, it is the experimental result graph for determining the optimal parameter L. L is selected through experiments and is determined by Figure 8 As can be seen, when L takes 2, the performance of the algorithm is the worst. When L takes 4 and 8, the performance is similar, but when L takes 8, the number of multiplications can be reduced. Therefore, L finally takes 8.

[0070] The process of determining the parameters depends on different experimental situations, but Figure 7 the results have shown that a suitable parameter can always be found such that f(n, L) is close to N.

[0071] The optimal parameters selected for each group through the above process are: N = 16, n = 4, L = 8. For comparison with the original method, please refer to Figure 9 , Figure 9 This is the bit error rate simulation curve of a frequency offset estimation method provided by the embodiments of this application. It can be seen that the bit error rate performance of this application and the original method is the same. When the bit error rate reaches 10 -3 the required optical signal-to-noise ratios are both 7.2 dB. At the same time, the frequency offset estimation ranges of both methods are -300 MHz to 300 MHz, and the performance has not deteriorated. The two methods are synthesized and implemented using Vivado software, and the resource consumption is shown in the following table:

[0072]

[0073] During the implementation process of this application, compared with the original method, the LUT consumed by this application is reduced by 40.36%, the MemoryLUT is reduced by 77.58%, the Flip-Flop is reduced by 48.19%, and the DSP48 is reduced by 72.36%. The resource consumption is significantly reduced. This shows that this application optimizes a large amount of computational workload while retaining the performance.

[0074] This application provides a frequency offset estimation system for QPSK modulation format signals, including:

[0075] A signal conversion unit that converts the input serial signal into a parallel signal;

[0076] A coarse frequency offset estimation unit that performs a coarse frequency offset estimation on the parallel signal with a symbol delay length of 1 and an interval extraction length of n;

[0077] A coarse compensation unit that converts the estimated coarse frequency offset into a phase component and performs the first compensation;

[0078] A fine frequency offset estimation unit that performs a fine frequency offset estimation on the signal after coarse compensation with a symbol delay length of L and an interval extraction length of n;

[0079] The comprehensive compensation unit adds the fine frequency offset and the coarse frequency offset to obtain the final frequency offset for the estimated coarse and fine frequency offsets, restores it to the phase, and performs the final frequency offset compensation.

[0080] This application provides a field programmable gate array for implementing the steps of the above frequency offset estimation method.

[0081] In summary, a frequency offset estimation method provided by this application reduces the computational complexity of the original two-stage frequency offset estimation method through the interval extraction method, and can select the optimal parameters through experiments to ensure the processing performance, thereby reducing the resource consumption of the original method and the processing cost.

[0082] The embodiments of this application described above do not constitute a limitation on the protection scope of this application. Different forms of changes made to the above description still fall within the protection scope of the present invention.

Claims

1. A frequency offset estimation method for QPSK modulation format signals, characterized in that, Including: Step 1: Convert the input serial signal into a parallel signal with a parallelism of N. Step 2: Perform a coarse frequency offset estimation on the parallel signal with a symbol delay length of 1 and an interval extraction length of n. Step 3: For the estimated coarse frequency offset, perform a conversion from the coarse frequency offset to the phase component and perform the first compensation. Step 4: Perform a fine frequency offset estimation on the signal after the coarse compensation with a symbol delay length of L and an interval extraction length of n. Step 5: For the estimated coarse frequency offset and fine frequency offset, add the fine frequency offset and the coarse frequency offset to obtain the final frequency offset, and restore it to the phase for the final frequency offset compensation.

2. The frequency offset estimation method for QPSK modulation format signals according to claim 1, characterized in that In the said step 1, each clock cycle of the serial signal only contains one sampled data S0, S1, S2, …, S k , …, where S k represents the k-th signal, k is a positive integer. For the serial signal, a parallel deceleration process is performed with a parallelism of N. Then the signals in each clock cycle are respectively S0~S N-1 , S N ~S 2N-1 , …, S k ~S k+N-1 , ….

3. The frequency offset estimation method for QPSK modulation format signals according to claim 1, wherein The said Step 2 includes: Delay the signal by one sampling length for the signal S within a single clock cycle k ~S k+N-1 , after delaying by one symbol, it becomes 0, S k ~S k+N-2 , take the conjugate to get 0, where * represents the conjugate operation; Decimate the signals before and after the delay with an interval length of n. For the signals S k ~S k+N-1 before the delay, after decimation, the remaining signals are S k 、S k+n 、S k+2n 、… For the signals after taking the conjugate of the delay, after decimation, the remaining signals are 0, Multiply them respectively, take the fourth power and sum them up, we get: Taking the argument of p1 and dividing by the coefficient gives the coarse frequency offset estimator. where m represents the upper and lower bounds of the summation, starting from 0, stepping by 1, until N / n ends, Δω is the estimated coarse angular frequency offset, T s is the signal sampling interval, and arg represents the angle calculation operation.

4. The frequency offset estimation method for QPSK modulation format signals according to claim 1, wherein Step 3 includes: Based on the signal sampling principle, multiplying ΔωT s by the sampling time base k to restore it to a phase: and constructing a complex exponential multiplying the original signal by the complex exponential for coarse frequency offset compensation: where S' k is the signal after coarse compensation.

5. The frequency offset estimation method for QPSK modulation format signals according to claim 1, characterized in that, Step 4 specifically includes: For the signal S' after rough compensation k ~S' k+N-1 Delay by L symbol lengths, then each clock cycle of the signal becomes: 0, …, 0, S' k ~S' k+N-L-1 , there are the first L 0s, take the conjugate to obtain Decimation with an interval length of n starts from the signal with subscript L, and the signals before and after delay are decimated into: S' k+L 、S' k+n+L 、… and Multiply them respectively, take the fourth power and sum them up, we get: where m represents the upper and lower bounds of the summation, starting from 0, with a step of 1, until (N - L) / n ends. Take the argument of p2 and divide by the coefficient to obtain the fine frequency offset estimator where Δω' is the estimated fine angular frequency offset.

6. The frequency offset estimation method for the QPSK modulation format signal according to claim 1, characterized in that Step 5 specifically includes: Add the fine frequency offset and the coarse frequency offset to obtain the final frequency offset: ωT s = ΔωT s + Δω'T s ; Multiply ωT s by the upsampling time base k to restore it to a phase: Construct complex exponential Multiply the original signal by the complex exponential for final compensation: where S f is the signal with the frequency offset finally removed.

7. The frequency offset estimation method for QPSK modulation format signals according to any one of claims 1-6, characterized in that, The said N = 16, n = 4, L = 8.

8. A frequency offset estimation system for QPSK modulation format signals based on the method according to any one of claims 1-7, characterized in that, Including: A signal conversion unit that converts the input serial signal into a parallel signal. A coarse frequency offset estimation unit that performs a coarse frequency offset estimation on the parallel signal with a symbol delay length of 1 and an interval extraction length of n. A coarse compensation unit that, for the estimated coarse frequency offset, performs a conversion from the coarse frequency offset to the phase component and performs the first compensation. A fine frequency offset estimation unit that performs a fine frequency offset estimation on the signal after the coarse compensation with a symbol delay length of L and an interval extraction length of n. A comprehensive compensation unit that, for the estimated coarse frequency offset and fine frequency offset, adds the fine frequency offset and the coarse frequency offset to obtain the final frequency offset, and restore it to the phase for the final frequency offset compensation.

9. A field programmable gate array, characterized in that, A frequency offset estimation program for QPSK modulation format signals is stored on the said storage medium. When the program is executed by a processor, it implements the steps of the frequency offset estimation method for QPSK modulation format signals as described in any one of claims 1 to 7.

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