A vibration suppression circuit applied to a wheel speed sensor and a suppression method thereof

Abstract

The application discloses a vibration suppression circuit applied to a wheel speed sensor and a suppression method thereof, and comprises a Hall_R disc, a Hall_C disc, a Hall_L disc, a first signal link, a second signal link, a digital processor DSP and a current signal output module IOUT. Differential electric signals output by the Hall_R disc and the Hall_C disc are input into input ends of the first signal link, differential electric signals output by the Hall_L disc and the Hall_C disc are input into input ends of the second signal link, output ends of the first signal link and the second signal link are connected with first and second input ends of the digital processor DSP respectively, and a first output end of the digital processor DSP is connected with the current signal output module IOUT. The application improves the vibration suppression function of the wheel speed sensor and reduces the difficulty of vibration suppression of the digital signal processor DSP.

Description

Technical Field

[0001] The present invention relates to a vibration suppression circuit and a suppression method thereof, in particular to a vibration suppression circuit and a suppression method thereof applied to a wheel speed sensor, and belongs to the technical field of semiconductor integrated circuits. Background Art

[0002] Wheel speed sensor chips, core components for measuring vehicle speed and direction, as well as for anti-lock braking systems, play a crucial role in ensuring safe driving. However, in actual operation, signal jitter caused by mechanical vibration or electromagnetic interference can introduce noise into the signals collected by the analog front-end, leading to erroneous signal output from the chip. Therefore, vibration suppression is necessary to ensure that the wheel speed sensor chip can eliminate the effects of vibration and output accurate signals under varying external conditions, thereby ensuring optimal performance.

[0003] The traditional wheel speed sensor chip quantizes the analog sinusoidal signal into a digital sinusoidal signal through the analog-to-digital converter ADC, and inputs it into the digital signal processor DSP. The maximum value Dmax and minimum value Dmin of the digital sinusoidal signal are calculated through an algorithm. The average value Daverage of the two is (Dmax +Dmin) / 2. The difference between the average value Daverage and 0 is the back magnetic offset information. The corresponding digital code value DDAC for eliminating the back magnetic offset is calculated and fed back to the digital-to-analog converter DAC to eliminate the back magnetic offset information. The difference Dsubtraction between the two is Dmax -Dmin. The difference Dsubtraction is the amplitude information. The corresponding gain adjustment code value DGAIN is calculated and input into the programmable gain amplifier PGA. The gain is adjusted to amplify the signal to an appropriate size. After completing the back magnetic offset calibration and gain adjustment, the block diagram of the zero-crossing detection circuit of the traditional wheel speed sensor chip is as follows. Figure 3 As shown, a digital comparator is used in the digital signal processor DSP to compare the input digital sinusoidal signal with 0. When the input digital sinusoidal signal is greater than 0, the output of the digital comparator and the output of the current signal IOUT module are flipped. When the input digital sinusoidal signal is less than 0, the output of the digital comparator and the output of the current signal IOUT module are flipped again. The speed information is transmitted to the outside world in the form of current through encoding.

[0004] However, when the wheel speed sensor chip is actually working, signal jitter caused by mechanical vibration or electromagnetic interference will cause noise in the analog front-end collected sinusoidal signal, and there is quantization noise when the analog sinusoidal signal is quantized into a digital sinusoidal signal by an analog-to-digital converter ADC, which will cause the digital sinusoidal signal input into the digital signal processor DSP to have not small noise. When a digital comparator is used to compare the input digital sinusoidal signal with 0, false flipping is prone to occur due to the influence of noise, and the output of the wrong speed information affects the function of the wheel speed sensor chip. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a vibration suppression circuit applied to a wheel speed sensor and a suppression method thereof, and to improve the vibration suppression function of the wheel speed sensor.

[0006] To solve the above technical problems, the technical solution adopted by the present application is:

[0007] A vibration suppression circuit applied to a wheel speed sensor, comprising a Hall_R disc, a Hall_C disc, a Hall_L disc, a first signal link, a second signal link, a digital processor DSP and a current signal output module IOUT, the differential electrical signals output by the Hall_R disc and the Hall_C disc are input to the input end of the first signal link, the differential electrical signals output by the Hall_L disc and the Hall_C disc are input to the input end of the second signal link, the output end of the first signal link is connected with the first input end of the digital processor DSP, the output end of the second signal link is connected with the second input end of the digital processor DSP, and the first output end of the digital processor DSP is connected with the current signal output module IOUT.

[0008] Further, the differential electrical signals output by the Hall_R disc include a voltage signal VR+ and a voltage signal VR-, the differential electrical signals output by the Hall_C disc include a voltage signal VC+ and a voltage signal VC-, and the differential electrical signals output by the Hall_L disc include a voltage signal VL+ and a voltage signal VL-.

[0009] Furthermore, the first signal chain includes a differential amplifier DDA_R, a programmable gain amplifier PGA_R, a low-pass filter LPF_R, a successive approximation analog-to-digital converter SARADC_R and a calibration digital-to-analog converter DAC_R, the four input terminals of the differential amplifier DDA_R are sequentially input with a voltage signal VR+, a voltage signal VR-, a voltage signal VC+ and a voltage signal VC-, the two output terminals of the differential amplifier DDA_R are sequentially connected with the two input terminals of the programmable gain amplifier PGA_R, the two output terminals of the programmable gain amplifier PGA_R are sequentially connected with the two input terminals of the low-pass filter LPF_R, and the two input terminals of the low-pass filter LPF_R are sequentially connected. The output end of the successive approximation analog-to-digital converter SARADC_R is connected in sequence to the two input ends of the successive approximation analog-to-digital converter SARADC_R, the output end of the successive approximation analog-to-digital converter SARADC_R is connected to the first input end of the digital processor DSP and generates a digital code value DO_R, the second output end of the digital processor DSP is connected to the input end of the calibration digital-to-analog converter DAC_R and generates a digital code value DDAC_R, the output end of the calibration digital-to-analog converter DAC_R is connected to the second control end of the programmable gain amplifier PGA_R and generates a digital code value SDAC_R, and the third output end of the digital processor DSP is connected to the first control end of the programmable gain amplifier PGA_R and generates a digital code value DGAIN_R.

[0010] Furthermore, the second signal chain includes a differential amplifier DDA_L, a programmable gain amplifier PGA_L, a low-pass filter LPF_L, a successive approximation analog-to-digital converter SARADC_L and a calibration digital-to-analog converter DAC_L, the four input terminals of the differential amplifier DDA_L are sequentially input with a voltage signal VL-, a voltage signal VL+, a voltage signal VC- and a voltage signal VC+, the two output terminals of the differential amplifier DDA_L are sequentially connected with the two input terminals of the programmable gain amplifier PGA_L, the two output terminals of the programmable gain amplifier PGA_L are sequentially connected with the two input terminals of the low-pass filter LPF_L, and the two input terminals of the low-pass filter LPF_L are sequentially connected. The output end of the digital processor DSP is connected to the two input ends of the successive approximation analog-to-digital converter SARADC_L in sequence, the output end of the successive approximation analog-to-digital converter SARADC_L is connected to the second input end of the digital processor DSP and generates a digital code value DO_L, the fourth output end of the digital processor DSP is connected to the first control end of the programmable gain amplifier PGA_L and generates a digital code value DGAIN_L, the fifth output end of the digital processor DSP is connected to the input end of the calibration digital-to-analog converter DAC_L and generates a digital code value DDAC_L, and the output end of the calibration digital-to-analog converter DAC_L is connected to the second control end of the programmable gain amplifier PGA_L and generates a digital code value SDAC_L.

[0011] Furthermore, the digital processor DSP includes a digital integrator DIG Integrator1_R, a digital hysteresis comparator DIG HYS comparator1_R, a digital hysteresis comparator DIG HYS comparator2_R, a switch S1, a switch S2, a switch S3, a switch S4, a switch S5, an extremum calculator 1_R, a smoothing filter 1_R, a threshold calculator 1_R, and an offset calibration and gain adjustment module. An input end of the digital integrator DIG Integrator1_R is connected to the digital code value DO_R, one end of the switch S3, and one end of the switch S1. A first output end of the digital integrator DIG Integrator1_R is connected to a non-inverting input end of the digital hysteresis comparator DIG HYS comparator1_R. An inverting input end of the digital hysteresis comparator DIG HYS comparator1_R is connected to a preset threshold value VTH1 or a preset threshold value -VTH1. The digital hysteresis comparator DIG HYS comparator2_R is connected to a preset threshold value VTH1 or a preset threshold value -VTH1. An output terminal of comparator1_R generates an output signal OUT1. A second output terminal of the digital integrator DIG Integrator1_R is connected to one end of the switch S2. The other end of the switch S2 is connected to the non-inverting input terminal of the digital hysteresis comparator DIG HYS comparator2_R and the other end of the switch S3. An inverting input terminal of the digital hysteresis comparator DIG HYS comparator2_R is connected to one end of the switch S4 and one end of the switch S5. The other end of the switch S4 is connected to a preset threshold value VTH2 or a preset threshold value -VTH2. An output terminal of the digital hysteresis comparator DIG HYS comparator2_R generates an output signal OUT2. The other end of the switch S1 is connected to the input terminal of the extremum calculator1_R. A first output terminal of the extremum calculator1_R is connected to the input terminal of the smoothing filter1_R and generates the maximum value Dmax_R of the input signal or the minimum value Dmin_R of the input signal. The output terminal of the smoothing filter1_R is connected to the threshold calculator Threshold The input of calculator1_R is connected to generate the reference amplitude Amplitude. The output of threshold calculator1_R is connected to the other end of switch S5 to generate the hysteresis thresholds VTH3 and -VTH3.The second output terminal of the extreme value calculator Extremum calculator1_R is connected to the input terminal of the offset calibration and gain adjustment module to generate the maximum input signal Dmax_R or the minimum input signal Dmin_R. The first output terminal of the offset calibration and gain adjustment module generates the digital code value DDAC_R, and the second output terminal of the offset calibration and gain adjustment module generates the digital code value DGAIN_R.

[0012] A vibration suppression method for a wheel speed sensor includes the following steps:

[0013] The Hall plates Hall_R, Hall_C, and Hall_L convert external sinusoidal magnetic signals into sinusoidal electrical signals that are easily processed by the chip. The voltage signals VR+, VR-, VC+, and VC- sensed by the Hall plates Hall_R and Hall_C are input into the differential amplifier DDA_R in the first signal chain. The differential electrical signals sensed by the Hall plates Hall_R and Hall_C are subtracted to eliminate most of the back magnetism, and the signal and back magnetism offset are initially amplified. The signal amplified by the differential amplifier DDA_R is input into the programmable gain amplifier PGA_R for further amplification. At this time, the programmable gain amplifier PGA_R uses the minimum amplification factor, and the output signal of the programmable gain amplifier PGA_R is input into the low-pass filter LPF_R to filter out all high-frequency noise and high-frequency vibration signals.

[0014] The output signal of the low-pass filter LPF_R is input to a successive approximation analog-to-digital converter SARADC_R for quantization to obtain a digital code value DO_R that is easily processed by the digital processor DSP. A digital integrator DIGIntegrator1_R in the digital signal processor DSP first integrates the input digital code value DO_R and then compares the integrated value with a preset threshold value VTH1 or a preset threshold value -VTH1 via a digital hysteresis comparator DIGHYScomparator1_R.

[0015] According to the positive or negative of the signal slope, the signal is increased or decreased. When the signal is increased, the output of the digital integrator DIGIntegrator1_R is less than the preset threshold VTH1, it is considered that the input signal is an invalid magnetic field signal, and the wheel speed sensor is in a stationary state. When the output of the digital integrator DIGIntegrator1_R is greater than the preset threshold VTH1, the digital hysteresis comparator DIG HYS comparator1_R flips, and it is considered that the input signal is a valid magnetic field signal. When the signal is decreased, the output of the digital integrator DIGIntegrator1_R is greater than the preset threshold -VTH1, it is considered that the input signal is an invalid magnetic field signal, and the wheel speed sensor is in a stationary state. When the output of the digital integrator DIGIntegrator1_R is less than the preset threshold -VTH1, the digital hysteresis comparator DIG HYS comparator1_R flips, and it is considered that the input signal is a valid magnetic field signal.

[0016] When the signal is increased and the input signal is a valid magnetic field signal, at this time, the switches S2 and S4 are closed, and the switches S3 and S5 are disconnected. The digital hysteresis comparator DIG HYS comparator2_R compares the output of the digital integrator DIGIntegrator1_R with the preset threshold VTH2. When the output of the digital integrator DIGIntegrator1_R is greater than the preset threshold VTH2, the output of the digital hysteresis comparator DIG HYS comparator2_R and the output of the current signal IOUT module flip. When the signal is decreased and the input signal is a valid magnetic field signal, the digital hysteresis comparator DIG HYS comparator2_R compares the output of the digital integrator DIGIntegrator1_R with the preset threshold -VTH2. When the output of the digital integrator DIGIntegrator1_R is greater than the preset threshold VTH2, the output of the digital hysteresis comparator DIG HYS comparator2_R and the output of the current signal IOUT module flip. The speed information is transmitted to the outside in the form of current through coding.

[0017] At the same time, once the input signal is deemed to be a valid magnetic field signal, switch S1 closes, and the digital code value DO_R is input into the extreme value calculator Extremum calculator1_R to determine the maximum and minimum values. The maximum value Dmax_R and minimum value Dmin_R of the input signal are calculated in the digital signal processor DSP. The average value Daverage_R of the maximum value Dmax_R and the minimum value Dmin_R of the input signal is (Dmax_R + Dmin_R) / 2. The difference between the average value Daverage_R and 0 is the back magnetic offset information. The corresponding digital code value DDAC_R for eliminating the back magnetic offset is calculated and fed back to the digital-to-analog converter DAC_R to eliminate the back magnetic offset information. The difference Dsubtraction_R between the maximum value Dmax_R and the minimum value Dmin_R of the input signal is Dmax_R - Dmin_R. The difference Dsubtraction_R is the amplitude information, and the corresponding gain adjustment code value DGAIN_R is calculated and input into the programmable gain amplifier PGA_R to adjust the gain and amplify the signal to an appropriate level.

[0018] Similarly, in the second signal chain, the corresponding digital code value DDAC_L for eliminating back magnetic offset is calculated and fed back to the digital-to-analog converter DAC_L to eliminate back magnetic offset information. The corresponding gain adjustment code value DGAIN_L is calculated and input into the programmable gain amplifier PGA_L, which adjusts the gain to amplify the signal to an appropriate level. The digital code values ​​DO_R and DO_L are processed by an algorithm to obtain direction information, which is used to control the current signal IOUT module and transmit the direction information to the outside world in the form of current through encoding.

[0019] After completing the back magnetic offset calibration and gain adjustment, switches S2 and S4 are opened, and switches S3 and S5 are closed. The smoothing filter 1_R in the digital processor DSP smoothes the amplitude signal of several cycles to obtain a reference amplitude Amplitude. The hysteresis thresholds VTH3 and -VTH3 are set based on the reference amplitude Amplitude, replacing the preset thresholds VTH2 and -VTH2 before completing the back magnetic offset calibration. As long as the noise caused by vibration in the signal does not exceed the set hysteresis threshold, the chip will not output erroneous information due to vibration. By detecting the signal amplitude in real time and performing smoothing filtering, the new reference amplitude is compared with the previous reference amplitude, and the hysteresis threshold is adjusted in real time.

[0020] Compared with the prior art, the present invention has the following advantages and effects:

[0021] 1. The present invention discloses a vibration suppression circuit and suppression method for a wheel speed sensor. The output signal of a programmable gain amplifier (PGA_R) is input into a low-pass filter (LPF_R), which filters out high-frequency noise and high-frequency vibration signals, thereby improving the vibration suppression function of the wheel speed sensor and reducing the difficulty of vibration suppression in a digital signal processor (DSP).

[0022] 2. Before calibrating the back magnetic offset, the present invention uses a digital integrator to calculate the change in the sinusoidal magnetic field signal to eliminate the influence of the back magnetic offset on the signal size. The validity of the magnetic field signal is determined by the digital hysteresis comparator 1 to avoid the problem of misjudgment due to noise. The period of the magnetic field signal is determined by the digital hysteresis comparator 2 to avoid the problem of false flipping due to noise.

[0023] 3. After the back magnetic offset is calibrated, the present invention uses a smoothing filter to calculate the amplitude of the magnetic field signal in real time, and adjusts the hysteresis threshold of the digital hysteresis comparator 2 in real time; it avoids the problem of poor vibration suppression effect caused by a fixed hysteresis threshold, and avoids the problem of wave loss caused by a too large hysteresis threshold, thereby achieving a more ideal vibration suppression effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 The diagram is a schematic diagram of a vibration suppression circuit applied to a wheel speed sensor according to the present invention.

[0025] Figure 2 It is a schematic diagram of the digital processor DSP of the present invention.

[0026] Figure 3 Schematic diagram of a zero-crossing detection circuit of a wheel speed sensor in the prior art. DETAILED DESCRIPTION

[0027] In order to elaborate on the technical solutions adopted by the present invention to achieve the predetermined technical purpose, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0028] like Figure 1As shown, the application of a vibration suppression circuit applied to a wheel speed sensor comprises a Hall_R, a Hall_C, a Hall_L, a first signal link, a second signal link, a digital processor DSP and a current signal output module IOUT, the differential electrical signals output by the Hall_R and the Hall_C are input to the input end of the first signal link, the differential electrical signals output by the Hall_L and the Hall_C are input to the input end of the second signal link, the output end of the first signal link is connected with the first input end of the digital processor DSP, the output end of the second signal link is connected with the second input end of the digital processor DSP, the first output end of the digital processor DSP is connected with the current signal output module IOUT.

[0029] The differential electrical signals output by the Hall_R comprises a voltage signal VR+ and a voltage signal VR-, the differential electrical signals output by the Hall_C comprises a voltage signal VC+ and a voltage signal VC-, the differential electrical signals output by the Hall_L comprises a voltage signal VL+ and a voltage signal VL-.

[0030] The first signal link comprises a differential difference amplifier DDA_R, a programmable gain amplifier PGA_R, a low pass filter LPF_R, a successive approximation analog-to-digital converter SARADC_R and a calibration digital-to-analog converter DAC_R, the four input ends of the differential difference amplifier DDA_R are sequentially input with the voltage signal VR+, the voltage signal VR-, the voltage signal VC+ and the voltage signal VC-, the two-way output ends of the differential difference amplifier DDA_R are sequentially connected with the two-way input ends of the programmable gain amplifier PGA_R, the two-way output ends of the programmable gain amplifier PGA_R are sequentially connected with the two-way input ends of the low pass filter LPF_R, the two-way output ends of the low pass filter LPF_R are sequentially connected with the two-way input ends of the successive approximation analog-to-digital converter SARADC_R, the output end of the successive approximation analog-to-digital converter SARADC_R is connected with the first input end of the digital processor DSP and generates a digital code value DO_R, the second output end of the digital processor DSP is connected with the input end of the calibration digital-to-analog converter DAC_R and generates a digital code value DDAC_R, the output end of the calibration digital-to-analog converter DAC_R is connected with the second control end of the programmable gain amplifier PGA_R and generates a digital code value SDAC_R, the third output end of the digital processor DSP is connected with the first control end of the programmable gain amplifier PGA_R and generates a digital code value DGAIN_R.

[0031] The second signal link comprises a differential difference amplifier DDA_L, a programmable gain amplifier PGA_L, a low pass filter LPF_L, a successive approximation analog-to-digital converter SARADC_L and a calibration digital-to-analog converter DAC_L, four input terminals of the differential difference amplifier DDA_L are sequentially connected with a voltage signal VL-, a voltage signal VL+, a voltage signal VC- and a voltage signal VC+ respectively, two output terminals of the differential difference amplifier DDA_L are sequentially connected with two input terminals of the programmable gain amplifier PGA_L, two output terminals of the programmable gain amplifier PGA_L are sequentially connected with two input terminals of the low pass filter LPF_L, two output terminals of the low pass filter LPF_L are sequentially connected with two input terminals of the successive approximation analog-to-digital converter SARADC_L, an output terminal of the successive approximation analog-to-digital converter SARADC_L is connected with a second input terminal of the digital processor DSP and generates a digital code value DO_L, a fourth output terminal of the digital processor DSP is connected with a first control terminal of the programmable gain amplifier PGA_L and generates a digital code value DGAIN_L, a fifth output terminal of the digital processor DSP is connected with an input terminal of the calibration digital-to-analog converter DAC_L and generates a digital code value DDAC_L, an output terminal of the calibration digital-to-analog converter DAC_L is connected with a second control terminal of the programmable gain amplifier PGA_L and generates a digital code value SDAC_L.

[0032] As Figure 2As shown, the digital processor DSP includes a digital integrator DIG Integrator1_R, a digital hysteresis comparator DIG HYS comparator1_R, a digital hysteresis comparator DIG HYS comparator2_R, a switch S1, a switch S2, a switch S3, a switch S4, a switch S5, an extremum calculator 1_R, a smoothing filter 1_R, a threshold calculator 1_R, and an offset calibration and gain adjustment module. An input terminal of the digital integrator DIG Integrator1_R is connected to a digital code value DO_R, one end of the switch S3, and one end of the switch S1. A first output terminal of the digital integrator DIG Integrator1_R is connected to a non-inverting input terminal of the digital hysteresis comparator DIG HYS comparator1_R. An inverting input terminal of the digital hysteresis comparator DIG HYS comparator1_R is connected to a preset threshold value VTH1 or a preset threshold value -VTH1. The digital hysteresis comparator DIG HYS An output terminal of comparator1_R generates an output signal OUT1. A second output terminal of the digital integrator DIG Integrator1_R is connected to one end of the switch S2. The other end of the switch S2 is connected to the non-inverting input terminal of the digital hysteresis comparator DIG HYS comparator2_R and the other end of the switch S3. An inverting input terminal of the digital hysteresis comparator DIG HYS comparator2_R is connected to one end of the switch S4 and one end of the switch S5. The other end of the switch S4 is connected to a preset threshold value VTH2 or a preset threshold value -VTH2. An output terminal of the digital hysteresis comparator DIG HYS comparator2_R generates an output signal OUT2. The other end of the switch S1 is connected to the input terminal of the extremum calculator1_R. A first output terminal of the extremum calculator1_R is connected to the input terminal of the smoothing filter1_R and generates the maximum value Dmax_R of the input signal or the minimum value Dmin_R of the input signal. The output terminal of the smoothing filter1_R is connected to the threshold calculator Threshold The input of calculator1_R is connected to generate the reference amplitude Amplitude. The output of threshold calculator1_R is connected to the other end of switch S5 to generate the hysteresis thresholds VTH3 and -VTH3.The second output end of the extremum calculator 1_R is connected with the input end of the offset calibration and gain adjustment module Offset calibration Gain adjustment and generates the input signal maximum value Dmax_R or the input signal minimum value Dmin_R, the first output end of the offset calibration and gain adjustment module Offset calibration Gain adjustment generates the digital code value DDAC_R, and the second output end of the offset calibration and gain adjustment module Offset calibration Gain adjustment generates the digital code value DGAIN_R.

[0033] A suppression method of a vibration suppression circuit applied to a wheel speed sensor, comprising the following steps:

[0034] The Hall disk Hall_R, the Hall disk Hall_C and the Hall disk Hall_L convert the external sinusoidal magnetic signal into a sinusoidal electric signal which is easy to process by the chip. The voltage signals VR+, VR-, VC+ and VC- sensed by the Hall disk Hall_R and the Hall disk Hall_C are input into the differential difference amplifier DDA_R in the first signal link, the differential electric signals sensed by the Hall disk Hall_R and the Hall disk Hall_C are subtracted to eliminate most of the back magnetism, and the signals and the back magnetism are preliminarily amplified; the amplified signals of the differential difference amplifier DDA_R are input into the programmable gain amplifier PGA_R for re-amplification; at this time, the programmable gain amplifier PGA_R adopts the minimum amplification factor to avoid the output saturation caused by the large amplification factor. The output signals of the programmable gain amplifier PGA_R are input into the low-pass filter LPF_R to filter out all the high-frequency noise and high-frequency vibration signals, improve the vibration suppression function of the wheel speed sensor, and reduce the difficulty of vibration suppression of the digital signal processor DSP.

[0035] The output signals of the low-pass filter LPF_R are input into the successive approximation type analog-to-digital converter SARADC_R to obtain the digital code value DO_R which is easy to process by the digital processor DSP; the digital integrator DIGIntegrator1_R in the digital signal processor DSP first integrates the input digital code value DO_R, and then compares the integrated value with the preset threshold value VTH1 or the preset threshold value -VTH1 through the digital hysteresis comparator DIG HYS comparator1_R.

[0036] According to the positive or negative of the signal slope, the signal is increased or decreased. When the signal is increased, the output of the digital integrator DIGIntegrator1_R is less than the preset threshold VTH1, it is considered that the input signal is invalid magnetic field signal, and the wheel speed sensor is in a stationary state; the output of the digital integrator DIGIntegrator1_R is greater than the preset threshold VTH1, the digital hysteresis comparator DIG HYS comparator1_R is flipped, and it is considered that the input signal is valid magnetic field signal; when the signal is decreased, the output of the digital integrator DIGIntegrator1_R is greater than the preset threshold -VTH1, it is considered that the input signal is invalid magnetic field signal, and the wheel speed sensor is in a stationary state; the output of the digital integrator DIGIntegrator1_R is less than the preset threshold -VTH1, the digital hysteresis comparator DIG HYS comparator1_R is flipped, and it is considered that the input signal is valid magnetic field signal.

[0037] When the signal is increased and the input signal is valid magnetic field signal, at this time, the switches S2 and S4 are closed, and the switches S3 and S5 are disconnected, the digital hysteresis comparator DIG HYS comparator2_R compares the output of the digital integrator DIGIntegrator1_R with the preset threshold VTH2, and when the output of the digital integrator DIGIntegrator1_R is greater than the preset threshold VTH2, the output of the digital hysteresis comparator DIG HYS comparator2_R and the output of the current signal IOUT module are flipped; when the signal is decreased and the input signal is valid magnetic field signal, the digital hysteresis comparator DIG HYS comparator2_R compares the output of the digital integrator DIGIntegrator1_R with the preset threshold -VTH2, and when the output of the digital integrator DIGIntegrator1_R is greater than the preset threshold VTH2, the output of the digital hysteresis comparator DIG HYS comparator2_R and the output of the current signal IOUT module are flipped; the speed information is transmitted to the outside in the form of current through coding.

[0038] At the same time, once the input signal is deemed to be a valid magnetic field signal, switch S1 closes, and the digital code value DO_R is input to the extreme value calculator Extremum calculator1_R for maximum and minimum value calculation. The maximum value Dmax_R and minimum value Dmin_R of the input signal are calculated in the digital signal processor DSP. The average value Daverage_R of the maximum value Dmax_R and the minimum value Dmin_R of the input signal is (Dmax_R + Dmin_R) / 2. The difference between the average value Daverage_R and 0 is the back magnetic offset information. The corresponding digital code value DDAC_R for eliminating the back magnetic offset is calculated and fed back to the digital-to-analog converter DAC_R to eliminate the back magnetic offset information. The difference Dsubtraction_R between the maximum value Dmax_R and the minimum value Dmin_R of the input signal is Dmax_R -Dmin_R. The difference Dsubtraction_R is the amplitude information, and the corresponding gain adjustment code value DGAIN_R is calculated and input to the programmable gain amplifier PGA_R to adjust the gain and amplify the signal to an appropriate level.

[0039] Similarly, in the second signal chain, the corresponding digital code value DDAC_L for eliminating back magnetic offset is calculated and fed back to the digital-to-analog converter DAC_L to eliminate the back magnetic offset information; the corresponding gain adjustment code value DGAIN_L is calculated and input into the programmable gain amplifier PGA_L, which adjusts the gain to amplify the signal to an appropriate size; the digital code values ​​DO_R and DO_L are algorithmically processed to obtain direction information, which is used to control the current signal IOUT module and transmit the direction information to the outside world in the form of current through encoding.

[0040] After backfield offset calibration and gain adjustment, switches S2 and S4 are opened, and switches S3 and S5 are closed. The smoothing filter1_R in the digital processor (DSP) smoothes the amplitude signal over several cycles to obtain a reference amplitude, Amplitude. Hysteresis thresholds VTH3 and -VTH3 are set based on the reference amplitude, replacing the preset thresholds VTH2 and -VTH2 before backfield offset calibration. As long as the noise caused by vibration in the signal does not exceed the set hysteresis thresholds, the chip will not output erroneous information due to vibration. The smoothing filter in the digital processor (DSP) smoothes the amplitude signal over several cycles, preventing the reference amplitude obtained from only one cycle from being too large or too small, which could affect the hysteresis threshold setting. By detecting the signal amplitude in real time and performing smoothing, the new reference amplitude is compared with the previous reference amplitude, and the hysteresis threshold is adjusted in real time. This avoids the problem of poor vibration suppression caused by fixed hysteresis thresholds and the problem of signal loss caused by excessive hysteresis thresholds, achieving relatively ideal vibration suppression.

[0041] The present invention discloses a vibration suppression circuit and a suppression method for a wheel speed sensor. The output signal of a programmable gain amplifier (PGA_R) is input into a low-pass filter (LPF_R) to filter out all high-frequency noise and high-frequency vibration signals, thereby improving the vibration suppression function of the wheel speed sensor and reducing the difficulty of vibration suppression of a digital signal processor (DSP). Before the back magnetic offset is calibrated, the present invention uses a digital integrator to calculate the variation of a sinusoidal magnetic field signal to eliminate the influence of the back magnetic offset on the signal size. The validity of the magnetic field signal is judged by a digital hysteresis comparator 1 to avoid the problem of misjudgment due to noise. The period of the magnetic field signal is judged by a digital hysteresis comparator 2 to avoid the problem of erroneous flipping due to noise. After the back magnetic offset is calibrated, the present invention uses a smoothing filter to calculate the amplitude of the magnetic field signal in real time and adjust the hysteresis threshold of the digital hysteresis comparator 2 in real time. The problem of poor vibration suppression effect caused by a fixed hysteresis threshold and the problem of wave loss caused by a too large hysteresis threshold are avoided, thereby achieving a relatively ideal vibration suppression effect.

[0042] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement of the above embodiments made according to the technical essence of the present invention, within the spirit and principles of the present invention, without departing from the content of the technical solution of the present invention, shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A vibration suppression circuit for a wheel speed sensor, characterized in that: The system comprises a Hall plate Hall_R, a Hall plate Hall_C, a Hall plate Hall_L, a first signal chain, a second signal chain, a digital processor DSP, and a current signal output module IOUT. The differential electrical signal output by the Hall plates Hall_R and Hall_C is input to the input end of the first signal chain, and the differential electrical signal output by the Hall plates Hall_L and Hall_C is input to the input end of the second signal chain. The output end of the first signal chain is connected to the first input end of the digital processor DSP, the output end of the second signal chain is connected to the second input end of the digital processor DSP, and the first output end of the digital processor DSP is connected to the current signal output module IOUT. The differential electrical signal at the output end of the Hall disk Hall_R includes a voltage signal VR+ and a voltage signal VR-, the differential electrical signal at the output end of the Hall disk Hall_C includes a voltage signal VC+ and a voltage signal VC-, and the differential electrical signal at the output end of the Hall disk Hall_L includes a voltage signal VL+ and a voltage signal VL-; The first signal chain includes a differential amplifier DDA_R, a programmable gain amplifier PGA_R, a low-pass filter LPF_R, a successive approximation analog-to-digital converter SARADC_R, and a calibration digital-to-analog converter DAC_R. The four input terminals of the differential amplifier DDA_R are sequentially input with a voltage signal VR+, a voltage signal VR-, a voltage signal VC+, and a voltage signal VC-. The two output terminals of the differential amplifier DDA_R are sequentially connected with the two input terminals of the programmable gain amplifier PGA_R. The two output terminals of the programmable gain amplifier PGA_R are sequentially connected with the two input terminals of the low-pass filter LPF_R. The two input terminals of the low-pass filter LPF_R are sequentially connected. The output end is connected to two input ends of a successive approximation analog-to-digital converter SARADC_R in sequence, the output end of the successive approximation analog-to-digital converter SARADC_R is connected to a first input end of a digital processor DSP and generates a digital code value DO_R, the second output end of the digital processor DSP is connected to an input end of a calibration digital-to-analog converter DAC_R and generates a digital code value DDAC_R, the output end of the calibration digital-to-analog converter DAC_R is connected to a second control end of a programmable gain amplifier PGA_R and generates a digital code value SDAC_R, and the third output end of the digital processor DSP is connected to a first control end of the programmable gain amplifier PGA_R and generates a digital code value DGAIN_R; The second signal chain includes a differential amplifier DDA_L, a programmable gain amplifier PGA_L, a low-pass filter LPF_L, a successive approximation analog-to-digital converter SARADC_L and a calibration digital-to-analog converter DAC_L. The four input terminals of the differential amplifier DDA_L are sequentially input with a voltage signal VL-, a voltage signal VL+, a voltage signal VC- and a voltage signal VC+. The two output terminals of the differential amplifier DDA_L are sequentially connected with the two input terminals of the programmable gain amplifier PGA_L. The two output terminals of the programmable gain amplifier PGA_L are sequentially connected with the two input terminals of the low-pass filter LPF_L. The two input terminals of the low-pass filter LPF_L are sequentially connected. The output end is connected in sequence to two input ends of a successive approximation analog-to-digital converter SARADC_L, the output end of the successive approximation analog-to-digital converter SARADC_L is connected to the second input end of the digital processor DSP and generates a digital code value DO_L, the fourth output end of the digital processor DSP is connected to the first control end of a programmable gain amplifier PGA_L and generates a digital code value DGAIN_L, the fifth output end of the digital processor DSP is connected to the input end of a calibration digital-to-analog converter DAC_L and generates a digital code value DDAC_L, and the output end of the calibration digital-to-analog converter DAC_L is connected to the second control end of the programmable gain amplifier PGA_L and generates a digital code value SDAC_L; The digital processor DSP includes a digital integrator DIG Integrator1_R, a digital hysteresis comparator DIG HYS comparator1_R, a digital hysteresis comparator DIG HYS comparator2_R, a switch S1, a switch S2, a switch S3, a switch S4, a switch S5, an extremum calculator 1_R, a smoothing filter 1_R, a threshold calculator 1_R, and an offset calibration and gain adjustment module. An input end of the digital integrator DIG Integrator1_R is connected to a digital code value DO_R, one end of the switch S3, and one end of the switch S1. A first output end of the digital integrator DIG Integrator1_R is connected to a non-inverting input end of the digital hysteresis comparator DIG HYS comparator1_R. An inverting input end of the digital hysteresis comparator DIG HYS comparator1_R is connected to a preset threshold value VTH1 or a preset threshold value -VTH1. The digital hysteresis comparator DIG HYS An output terminal of comparator1_R generates an output signal OUT1. A second output terminal of the digital integrator DIG Integrator1_R is connected to one end of the switch S2. The other end of the switch S2 is connected to the non-inverting input terminal of the digital hysteresis comparator DIG HYS comparator2_R and the other end of the switch S3. An inverting input terminal of the digital hysteresis comparator DIG HYS comparator2_R is connected to one end of the switch S4 and one end of the switch S5. The other end of the switch S4 is connected to the preset threshold VTH2 or the preset threshold -VTH2. An output terminal of the digital hysteresis comparator DIG HYS comparator2_R generates an output signal OUT2. The other end of the switch S1 is connected to the input terminal of the extreme value calculator Extremum calculator1_R. A first output terminal of the extreme value calculator Extremum calculator1_R is connected to the input terminal of the smoothing filter1_R and generates the maximum value Dmax_R of the input signal or the minimum value Dmin_R of the input signal. The smoothing filter Smoothing filter The output end of filter1_R is connected to the input end of the threshold calculator Thresholdcalculator1_R and generates a reference amplitude Amplitude. The output end of the threshold calculator Thresholdcalculator1_R is connected to the other end of the switch S5 and generates hysteresis thresholds VTH3 and -VTH3.The second output terminal of the extreme value calculator Extremum calculator1_R is connected to the input terminal of the offset calibration and gain adjustment module Offset calibration Gain adjustment to generate the maximum input signal Dmax_R or the minimum input signal Dmin_R. The first output terminal of the offset calibration and gain adjustment module Offset calibration Gain adjustment generates a digital code value DDAC_R, and the second output terminal of the offset calibration and gain adjustment module Offset calibration Gain adjustment generates a digital code value DGAIN_R.

2. A vibration suppression method for a wheel speed sensor according to claim 1, characterized in that The following steps are involved: The Hall plates Hall_R, Hall_C, and Hall_L convert external sinusoidal magnetic signals into sinusoidal electrical signals that are easily processed by the chip. The voltage signals VR+, VR-, VC+, and VC- sensed by the Hall plates Hall_R and Hall_C are input into the differential amplifier DDA_R in the first signal chain. The differential electrical signals sensed by the Hall plates Hall_R and Hall_C are subtracted to eliminate most of the back magnetism, and the signal and back magnetism offset are initially amplified. The signal amplified by the differential amplifier DDA_R is input into the programmable gain amplifier PGA_R for further amplification. At this time, the programmable gain amplifier PGA_R uses the minimum amplification factor, and the output signal of the programmable gain amplifier PGA_R is input into the low-pass filter LPF_R to filter out all high-frequency noise and high-frequency vibration signals. The output signal of the low-pass filter LPF_R is input to a successive approximation analog-to-digital converter SARADC_R for quantization to obtain a digital code value DO_R that is easily processed by the digital processor DSP. A digital integrator DIGIntegrator1_R in the digital signal processor DSP first integrates the input digital code value DO_R and then compares the integrated value with a preset threshold value VTH1 or a preset threshold value -VTH1 via a digital hysteresis comparator DIGHYScomparator1_R. The signal increases or decreases according to the positive or negative sign of the signal slope. When the signal increases and the output of the digital integrator DIGIntegrator1_R is less than the preset threshold value VTH1, it is considered that the input signal is an invalid magnetic field signal and the wheel speed sensor is in a stationary state. When the output of the digital integrator DIG Integrator1_R is greater than the preset threshold value VTH1, the digital hysteresis comparator DIG HYS comparator1_R flips and the input signal is considered to be a valid magnetic field signal. When the signal decreases and the output of the digital integrator DIGIntegrator1_R is greater than the preset threshold value -VTH1, it is considered that the input signal is an invalid magnetic field signal and the wheel speed sensor is in a stationary state. When the output of the digital integrator DIG Integrator1_R is less than the preset threshold value -VTH1, the digital hysteresis comparator DIG HYS comparator1_R flips and the input signal is considered to be a valid magnetic field signal. When the signal increases and the input signal is a valid magnetic field signal, switches S2 and S4 are closed, and switches S3 and S5 are opened. The digital hysteresis comparator DIG HYS comparator2_R compares the output of the digital integrator DIG Integrator1_R with the preset threshold value VTH2. When the output of the digital integrator DIG Integrator1_R is greater than the preset threshold value VTH2, the output of the digital hysteresis comparator DIG HYS comparator2_R and the output of the current signal IOUT module are flipped. When the signal decreases and the input signal is a valid magnetic field signal, the digital hysteresis comparator DIG HYS comparator2_R is used to compare the output of the digital integrator DIG Integrator1_R with the preset threshold value -VTH2. When the output of the digital integrator DIG Integrator1_R is greater than the preset threshold value VTH2, the output of the digital hysteresis comparator DIG HYS comparator2_R and the output of the current signal IOUT module are flipped. The speed information is transmitted to the outside world in the form of current through encoding. At the same time, once the input signal is deemed to be a valid magnetic field signal, switch S1 closes, and the digital code value DO_R is input into the extreme value calculator Extremum calculator1_R to determine the maximum and minimum values. The maximum value Dmax_R and minimum value Dmin_R of the input signal are calculated in the digital signal processor DSP. The average value Daverage_R of the maximum value Dmax_R and the minimum value Dmin_R of the input signal is (Dmax_R + Dmin_R) / 2. The difference between the average value Daverage_R and 0 is the back magnetic offset information. The corresponding digital code value DDAC_R for eliminating the back magnetic offset is calculated and fed back to the digital-to-analog converter DAC_R to eliminate the back magnetic offset information. The difference Dsubtraction_R between the maximum value Dmax_R and the minimum value Dmin_R of the input signal is Dmax_R - Dmin_R. The difference Dsubtraction_R is the amplitude information, and the corresponding gain adjustment code value DGAIN_R is calculated and input into the programmable gain amplifier PGA_R to adjust the gain and amplify the signal. Similarly, in the second signal chain, the corresponding digital code value DDAC_L for eliminating back magnetic offset is calculated and fed back to the digital-to-analog converter DAC_L to eliminate back magnetic offset information; the corresponding gain adjustment code value DGAIN_L is calculated and input into the programmable gain amplifier PGA_L to adjust the gain and amplify the signal; the digital code values ​​DO_R and DO_L are algorithmically processed to obtain direction information, which is used to control the current signal IOUT module and transmit the direction information to the outside world in the form of current through encoding; After completing the back magnetic offset calibration and gain adjustment, switches S2 and S4 are opened, and switches S3 and S5 are closed. The smoothing filter 1_R in the digital processor DSP smoothes the amplitude signal of several cycles to obtain a reference amplitude Amplitude. The hysteresis thresholds VTH3 and -VTH3 are set based on the reference amplitude Amplitude, replacing the preset thresholds VTH2 and -VTH2 before completing the back magnetic offset calibration. As long as the noise caused by vibration in the signal does not exceed the set hysteresis threshold, the chip will not output erroneous information due to vibration. By detecting the signal amplitude in real time and performing smoothing filtering, the new reference amplitude is compared with the previous reference amplitude, and the hysteresis threshold is adjusted in real time.

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