PCBA electrical performance detection method, apparatus and device, and storage medium

Abstract

The invention provides a PCBA electrical performance detection method, device and equipment and a storage medium, and the method comprises the steps: collecting multi-channel time sequence electrical signals of a plurality of test nodes on a PCBA, and carrying out the synchronous processing of the signals, and generating a signal sequence tensor; performing multi-scale feature extraction on the tensor, and constructing a channel-level embedded vector group; mapping the embedded vectors to corresponding nodes of a PCBA circuit diagram structure to generate a circuit diagram node set; performing adjacent node feature deviation analysis based on node state representation extracted by a graph neural network in combination with an original signal to generate an abnormal score value vector; meanwhile, a label-free representation model is constructed; and finally, based on the score value and the representation model, performing electrical performance scoring and state judgment on the newly acquired signal. The method can be used for global electrical performance detection of a complex circuit board, solves the problem of missing detection caused by inconsideration of overall structure perception and local anomaly recognition, and improves the accuracy of electrical performance detection.

Description

Technical Field

[0001] This application relates to the technical field of printed circuit board detection, and particularly to a method, device, equipment and storage medium for detecting the electrical performance of PCBA. Background Art

[0002] With the continuous evolution of electronic devices towards high-density integration and high-performance output, as the core functional unit of electronic systems, the stability of the electrical performance of PCBA (Printed Circuit Board Assembly) is directly related to the functional integrity and operation reliability of the entire machine system. In fields such as intelligent terminals, industrial control, and medical equipment, a large number of complex PCBA boards are deployed in key control links, posing higher requirements for the timeliness and accuracy of the quality inspection of their electrical performance. Taking the in-vehicle control unit of new energy vehicles as an example, there are dozens to hundreds of key nodes distributed on such control boards, and their electrical characteristics may cause signal interference, system failure, or even safety hazards under minor fluctuations. There is an urgent need for efficient and traceable detection methods to accurately evaluate each board and each node level by level.

[0003] However, existing technologies generally rely on manual configuration of rules, static waveform comparison, or functional testing (FT) to judge electrical performance, and often can only detect relatively obvious fault modes. They lack the ability to deeply model complex problems such as weak anomalies in timing behavior, coupling effects between nodes, or structural deviations between multiple channels, and it is difficult to support the intelligent analysis of high-dimensional and large-scale PCBA samples. Especially when facing circuit boards with complex structures and numerous signal channels, traditional detection means are difficult to simultaneously consider overall structure perception and local anomaly recognition, and there are problems of misjudgment, missed detection, or inability to explain. Summary of the Invention

[0004] This application provides a method, device, equipment and storage medium for detecting the electrical performance of PCBA, which is used to solve the problems that related technologies are difficult to simultaneously consider overall structure perception and local anomaly recognition, resulting in misjudgment and missed detection.

[0005] In the first aspect of this application, a method for detecting the electrical performance of PCBA is provided. The method for detecting the electrical performance of PCBA includes: Generating a signal sequence tensor after time series synchronization according to the multi-channel time series electrical signal data collected from the test nodes on the PCBA; Obtaining the local change characteristics of the multi-channel time series electrical signal data by performing feature processing on the signal sequence tensor, and constructing a channel-level embedding vector group; Mapping the channel-level embedding vector group to the corresponding nodes of the circuit diagram structure corresponding to the PCBA to generate a circuit diagram node set; Determine the feature deviation between each target node and its corresponding adjacent node according to the node state representation tensor of the circuit diagram node set; Generate an abnormal score value vector corresponding to the target node according to the feature deviation; Construct a signal characterization model according to the set of simulated signal variants generated by performing perturbation transformation on the signal sequence tensor; Score the newly collected test signal data according to the abnormal score value vector and the signal characterization model, and output the PCBA electrical performance detection result.

[0006] Optionally, in the first implementation manner of the first aspect of the present application, the step of generating a signal sequence tensor after time synchronization according to the multi-channel time-series electrical signal data collected by the test nodes on the PCBA includes: Obtain the original sampling sequences of multiple channels according to multiple signal test nodes of a preset test station; wherein, the original sampling sequences include original time-series voltage, current, and frequency response sampling sequences; Perform time offset alignment processing on each channel of the original sampling sequence through a preset time base reference signal to generate a time synchronization index set; Perform interpolation resampling operation on the original sampling sequence according to the time synchronization index set to generate a standardized signal sequence with consistent time steps between channels; Generate a signal sequence tensor after time synchronization by performing amplitude normalization and data clipping processing on the standardized signal sequence.

[0007] Optionally, in the second implementation manner of the first aspect of the present application, the step of obtaining the local change characteristics of the multi-channel time-series electrical signal data by performing feature processing on the signal sequence tensor and constructing a channel-level embedding vector group includes: Perform sliding window segmentation processing on the time-series electrical signal data of each channel according to the signal sequence tensor to generate a local signal slice sequence containing time-series segments; Perform one-dimensional convolution operation on the local signal slice sequence to obtain local change feature maps of each signal channel at different time scales, and construct a feature hierarchy with time multi-resolution according to the multi-level setting of the receptive field of the convolution kernel; Generate an initial channel-level embedding vector sequence containing the difference representation between channels through concatenation operation and position encoding processing on the feature hierarchy; Obtain a channel-level embedding vector group expressing the global time-series relationship and channel feature distribution through attention encoding on the initial embedding vector sequence.

[0008] Optionally, in the third implementation manner of the first aspect of the present application, the step of mapping the channel-level embedding vector group to the corresponding nodes of the circuit diagram structure corresponding to the PCBA to generate a circuit diagram node set includes: Generate a circuit diagram structure including the topological indexes of each component node according to the component connection relationship in the PCBA schematic diagram structure and the predefined node address rule; Map the channel-level embedding vector group to the circuit diagram structure according to the mapping relationship between the channels and the nodes, and generate a set of node initialization feature tensors; After the step of generating the set of node initialization feature tensors, the following steps are further included: Jointly embed the node features of the set of node initialization feature tensors and the edge attributes in the circuit diagram structure through graph structure encoding to generate an original graph neural network input graph; Perform layer-by-layer graph convolution operations on the input graph in the predefined graph convolution layer stacking structure to obtain a circuit diagram node state representation tensor after structural context fusion.

[0009] Optionally, in the fourth implementation manner of the first aspect of the present application, the step of determining the feature deviation between each target node and its corresponding adjacent node according to the node state representation tensor of the circuit diagram node set includes: According to the circuit diagram node state representation tensor, perform feature decoding on the state representation of each target node and the synchronization signal of its corresponding channel to generate a node-level reconstruction signal sequence; Obtain a node-level error residual sequence by calculating the difference between the node-level reconstruction signal sequence and the original signal sequence at each time step, and obtain the reconstruction error index value of the corresponding target node through a residual weighted integration operation; Process the state representation tensor of any target node and the state representation of its adjacent nodes to generate a feature deviation matrix between multiple pairs of nodes.

[0010] Optionally, in the fifth implementation manner of the first aspect of the present application, the step of scoring the newly collected test signal data according to the anomaly score value vector and the signal characterization model and outputting the PCBA electrical performance detection result includes: Obtain the test signal data of the PCBA sample and generate a corresponding target signal sequence tensor; Perform feature projection and characterization decoding on the target signal sequence tensor according to the signal characterization model to generate a predicted reconstruction signal sequence; Determine a target reconstruction error vector according to the residual information between the predicted reconstruction signal sequence and the sampling sequence corresponding to the test signal data; Perform mapping scoring on the corresponding positions of each node channel in the PCBA sample according to the abnormal score value vector, and generate a comprehensive scoring tensor in combination with the target reconstruction error vector; Determine the electrical performance detection result of the PCBA sample by performing threshold analysis on the comprehensive scoring tensor.

[0011] Optionally, in the sixth implementation manner of the first aspect of the present application, the method further includes: Identify test samples corresponding to a preset abnormal threshold interval according to the electrical performance detection result, and generate an initial abnormal sample candidate set; Perform joint statistical processing on the node-level scoring information and prediction reconstruction error information of the abnormal sample candidate set, construct a sample label generation matrix, and generate a pseudo-label index set according to a preset clustering strategy; Combine the pseudo-label index set with the signal sequence tensor into a training sample, and input it into the signal representation model to perform parameter fine-tuning and update, and generate an iteratively optimized signal representation model version; Determine the model drift amount by performing difference analysis on the structural parameters of the signal representation model version and the historical model parameters; Generate a dynamic scoring adjustment factor based on the drift amount, and update the bias term parameters in the abnormal score value vector and the comprehensive scoring tensor.

[0012] The second aspect of the present application provides a PCBA electrical performance detection device, and the PCBA electrical performance detection device includes: A generation module, configured to generate a signal sequence tensor after time sequence synchronization according to multi-channel time sequence electrical signal data collected from test nodes on the PCBA; An acquisition module, configured to obtain local change characteristics of the multi-channel time sequence electrical signal data by performing feature processing on the signal sequence tensor, and construct a channel-level embedding vector group; A mapping module, configured to map the channel-level embedding vector group to corresponding nodes of the circuit diagram structure corresponding to the PCBA, and generate a circuit diagram node set; A determination module, configured to determine the feature deviation between each target node and the corresponding adjacent node according to the node state representation tensor of the circuit diagram node set; The generation module is further configured to generate an abnormal score value vector corresponding to the target node according to the feature deviation; A construction module, configured to construct a signal representation model according to a set of simulated signal variants generated by performing perturbation transformation on the signal sequence tensor; An output module, configured to score newly acquired test signal data according to the abnormal score value vector and the signal characterization model, and output the PCBA electrical performance detection result.

[0013] A third aspect of the embodiments of the present application provides an electronic device, including a memory and a processor. The processor is configured to execute a computer program stored on the memory. When the processor executes the computer program, the steps in the PCBA electrical performance detection method provided in the first aspect of the embodiments of the present application are implemented.

[0014] A fourth aspect of the embodiments of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps in the PCBA electrical performance detection method provided in the first aspect of the embodiments of the present application are implemented.

[0015] In summary, according to a PCBA electrical performance detection method, device, equipment and storage medium provided by the solution of the present application, multi-channel timing electrical signals of multiple test nodes on the PCBA are collected, and the signals are synchronously processed to generate a signal sequence tensor; multi-scale feature extraction is performed on the tensor to construct a channel-level embedding vector group; the embedding vectors are mapped to the corresponding nodes of the PCBA circuit diagram structure to generate a circuit diagram node set with signal attributes; based on the node state representation extracted by the graph neural network, combined with the original signal, reconstruction error calculation and adjacent node feature deviation analysis are performed to generate an abnormal score value vector; at the same time, the original signal is perturbed to generate a set of simulated signals, and an unlabeled characterization model is constructed; finally, based on the score value and the characterization model, the electrical performance of the newly acquired signal is scored and the state is judged. The present application combines the advantages of timing modeling and structure modeling, can be used for global electrical behavior detection of complex circuit boards, and solves the problem of missed detection caused by the inability to capture topological dependencies and time dynamic interactions in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic flow chart of the PCBA electrical performance detection method provided by the embodiments of the present application; Figure 2 It is a schematic diagram of the program module of the PCBA electrical performance detection device provided by the embodiments of the present application; Figure 3 It is a schematic diagram of the structure of the electronic device provided by the embodiments of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] To make the invention objectives, features, and advantages of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0018] To solve the problem that it is difficult to simultaneously consider the overall structure perception and local anomaly recognition in related technologies, and there are problems of misjudgment and missed detection, the embodiments of the present application provide a PCBA electrical performance detection method, as Figure 1 is a schematic flowchart of the PCBA electrical performance detection method provided in this embodiment. The PCBA electrical performance detection method includes the following steps: Step 110: Generate a signal sequence tensor after time synchronization according to the multi-channel time-series electrical signal data collected from the test nodes on the PCBA.

[0019] Specifically, the multi-channel time-series electrical signal data collected from the test nodes on the PCBA is used as the input. After sampling operations triggered by a unified clock reference, the time-series signals of each channel are aligned on the time axis. The trigger offset between channels is calibrated using a preset time-base reference signal, and the sampling data of each channel at the same time step is resynchronized through interpolation or imputation methods. Then, amplitude normalization and data clipping processing are performed on all signals. Finally, electrical characteristics such as voltage, current, and frequency response are organized into a time-series tensor in a unified format according to the time sequence, providing input data with strong time-domain consistency for subsequent deep learning models.

[0020] In an optional implementation manner of this embodiment, the step of generating a signal sequence tensor after time synchronization according to the multi-channel time-series electrical signal data collected from the test nodes on the PCBA includes: obtaining the original sampling sequences of multiple channels according to multiple signal test nodes of a preset test station; wherein, the original sampling sequences include the original time-series voltage, current, and frequency response sampling sequences; performing time offset alignment processing on each channel of the original sampling sequences through a preset time-base reference signal to generate a time synchronization index set; performing interpolation resampling operations on the original sampling sequences according to the time synchronization index set to generate a standardized signal sequence with consistent time steps between channels; and generating a signal sequence tensor after time synchronization by performing amplitude normalization and data clipping processing on the standardized signal sequence.

[0021] Specifically, according to the signal test nodes configured on the preset test station, the original sampling sequences of each channel are obtained through a high-speed sampling device. The original sampling sequences cover three dimensions: voltage, current, and frequency response. Among them, the voltage data reflects the instantaneous potential change of the circuit node, the current data shows the dynamic waveform of the current over time, and the frequency response data describes the amplitude and phase characteristics of the signal in different frequency bands. For example, when monitoring harmonic components, this data has important reference value. Next, according to the preset time-base reference signal, time-offset alignment operations are performed on the original sequences collected from each channel. By comparing the differences between the sampling start times of each channel and the standard clock, a unified time synchronization index set is generated. This index set provides a basis for correcting the data of each channel, thereby ensuring that all signals are expressed on a unified time scale. For example, when a sampling delay occurs in a certain channel, the time-domain offset can be compensated according to the generated index set, so that the time nodes of the data of each channel are consistent. Subsequently, interpolation resampling operations are performed on the original sampling sequences according to the obtained time synchronization index set. Through mathematical interpolation methods, the data of each channel is reconstructed, and the sequences with originally different sampling frequencies are "stretched" or "compressed" to the same time step, generating a standardized signal sequence with consistent time steps between channels. This process can solve problems such as inconsistent sampling frequencies caused by hardware differences in different test nodes. Then, amplitude normalization and data clipping operations are performed on the standardized signal sequence. By setting a predetermined amplitude range, the values of each channel are adjusted to the same scale, making the signal data comparable in amplitude. At the same time, abnormal signal data outside the reasonable range is clipped, thereby removing the abnormal points introduced by external interference. For example, when the instantaneous abnormal amplitude caused by electromagnetic interference is limited outside the preset threshold, it can be automatically filtered out during the data processing. After the above continuous data processing steps, the finally obtained signal sequence tensor after time series synchronization has consistency in both the time axis and the amplitude scale, providing accurate and standardized input data for the deep learning-based feature extraction in the subsequent steps.

[0022] Step 120: By performing feature processing on the signal sequence tensor, local change features of the multi-channel time series electrical signal data are obtained, and a channel-level embedding vector group is constructed.

[0023] Specifically, time series feature extraction is performed on the above-generated signal sequence tensor. The sliding window mechanism is used to segment the data of each channel, constructing a local signal slice sequence, and one-dimensional convolution operations are used to extract local feature maps at different time scales. Combining the hierarchical setting of the receptive field of the convolution kernel to achieve multi-scale information aggregation, and at the same time introducing a position encoding mechanism to clarify the time series structure. On this basis, the features between multiple channels are fused, and the attention mechanism is used to encode the dependencies between channels, forming a channel-level embedding vector group with rich semantic expression capabilities, thereby constructing an information representation space that contains both time dynamic changes and retains differences between channels.

[0024] In an alternative implementation of this embodiment, the steps of obtaining the local change features of the multi-channel time-series electrical signal data and constructing the channel-level embedding vector group by performing feature processing on the signal sequence tensor include: performing sliding window segmentation processing on the time-series electrical signal data of each channel according to the signal sequence tensor to generate a local signal slice sequence containing time-series segments; performing one-dimensional convolution operations on the local signal slice sequence to obtain local change feature maps of each signal channel at different time scales, and constructing a feature hierarchy with time multi-resolution according to the multi-level settings of the receptive field of the convolution kernel; generating an initial channel-level embedding vector sequence containing the difference representation between channels through concatenation operations and position encoding processing on the feature hierarchy; and obtaining the channel-level embedding vector group expressing the global time-series relationship and channel feature distribution by performing attention encoding on the initial embedding vector sequence.

[0025] Specifically, based on the time-series electrical signal data of each channel in the signal sequence tensor, through sliding window segmentation processing, the continuous time signal is divided into several local segments according to a fixed length and a certain overlap rate, forming a local signal slice sequence. This method ensures the capture accuracy of local signal changes and facilitates subsequent feature extraction. For example, when segmenting a voltage waveform, each slice can reflect the instantaneous voltage fluctuation characteristics, laying a foundation for local feature modeling. Next, a one-dimensional convolution operation is performed on the obtained local signal slice sequence. One-dimensional convolution is a convolution structure in a convolutional neural network suitable for processing time-series data. Its core lies in using a pre-set convolution kernel to slide and scan the slice data in the time dimension to extract local features. With the multi-level setting of the receptive field of the convolution kernel, different kernel sizes correspond to different scale feature capture capabilities, thus constructing a feature hierarchy with time multi-resolution. For example, a smaller convolution kernel can focus on capturing minute detail changes, while a larger convolution kernel can reflect trend changes over a longer time span, thereby forming a series of hierarchical feature maps. Subsequently, the feature maps at each level are concatenated in the order of time series through a concatenation operation. Then, combined with the position encoding technology, the concatenated sequence is encoded. Position encoding helps the model distinguish the data content at different time points by adding position information to the signal, thereby generating an initial channel-level embedding vector sequence containing the representation of differences between channels. This embedding vector sequence preserves local features while endowing global time-series information to better express the dynamic changes of the signal in the time dimension. For example, in the feature representation of a certain sampling channel, the position where the signal peak and valley appear can be clearly indicated through position encoding. Furthermore, an attention encoding mechanism is used to process the initial embedding vector sequence. The attention encoding mechanism re-weights the global time-series relationship and the features of each channel by calculating the similarity between the embedding vectors, thereby forming a channel-level embedding vector group expressing the global time-series relationship and the overall feature distribution between channels. This process enables the feature expression of each channel to take into account the semantic information of other channels, facilitating the capture of cross-channel correlation anomalies in detection.

[0026] Step 130: Map the channel-level embedding vector group to the corresponding nodes of the circuit diagram structure of the PCBA to generate a circuit diagram node set.

[0027] Specifically, map the constructed channel-level embedding vector group to the corresponding functional nodes in the PCBA circuit diagram structure. According to the connection relationship and node numbering rules described in the circuit schematic diagram, establish a mapping relationship between each signal channel and the circuit component nodes, and assign the channel representation to the corresponding graph nodes to form a set of node initialization features. Further introduce the connection information between nodes in the circuit diagram structure as the attributes of the edges in the graph, construct the input graph of the multi-attribute graph neural network, and then propagate and fuse the context structure information between nodes through graph convolution operations to generate a structure-aware circuit diagram node state representation tensor, thereby realizing the joint encoding of electrical features and topological structures.

[0028] In an alternative implementation manner of this embodiment, the step of mapping the channel-level embedding vector group to the corresponding nodes of the corresponding circuit diagram structure of the PCBA to generate a circuit diagram node set includes: generating a circuit diagram structure including the topological indexes of each component node according to the component connection relationship and the predefined node address rules in the PCBA schematic diagram structure; mapping the channel-level embedding vector group to the circuit diagram structure according to the mapping relationship between the channels and the nodes, and generating a set of node initialization feature tensors; after the step of generating the set of node initialization feature tensors, it further includes: jointly embedding the node features of the set of node initialization feature tensors and the edge attributes in the circuit diagram structure through graph structure encoding to generate the input graph of the original graph neural network; performing layer-by-layer graph convolution operations on the input graph in the predefined graph convolution layer stacking structure to obtain the circuit diagram node state representation tensor after structure context fusion.

[0029] Specifically, when constructing the circuit diagram structure based on the component connection relationships in the PCBA schematic diagram structure and the predefined node address rules, first, each component shown in the schematic diagram is abstracted as a node in the graph, and a unique topological index is assigned to each node according to the predefined address rules, thereby generating a circuit diagram structure that includes component nodes and their interconnection relationships. This graph structure clearly expresses the physical connection information between components such as microprocessors, capacitors, resistors, and sensors. For example, if there is a direct electrical connection between a capacitor and a control chip, then there is an edge between the corresponding nodes in the circuit diagram, and the edge attributes can include information such as the connection method and impedance. Next, according to the channel-level embedding vector group obtained during the electrical signal data acquisition process, through the pre-determined mapping relationship between channels and nodes, the embedding vector of each channel is mapped to the corresponding component node in the circuit diagram structure, thereby generating a set of node initialization feature tensors. This tensor set stores the initial feature expressions of each node in the form of a multi-dimensional array, where the feature expression not only reflects the temporal electrical dynamic changes of a single channel but also retains multi-scale information. For example, a channel embedding collected from a temperature sensor can include descriptions of short-term fluctuations and long-term trends. Subsequently, through graph structure encoding, the node features in the set of node initialization feature tensors and the edge attributes in the graph are jointly embedded. Graph structure encoding is to fuse information such as node features, edge weights, and edge types to generate an original graph neural network input graph that comprehensively represents the node states and the relationships between nodes. For example, information such as the connection strength and transmission delay between a certain control component and the connected sensor is encoded into the input graph to ensure that information exchange between nodes can be transmitted in subsequent operations. Finally, according to the predefined stacked structure of graph convolutional layers, layer-by-layer graph convolutional operations are performed on the obtained input graph. In graph convolution, through neighborhood sampling and feature aggregation, the node representation gradually incorporates the information of its adjacent nodes in each layer of convolution operation, thereby generating a circuit diagram node state representation tensor after structural context fusion. This tensor can comprehensively reflect the state of each node in the entire circuit network. For example, during the detection process, if the electrical response of a certain node is abnormal, after multiple layers of graph convolution, its state representation not only includes the signal characteristics of the node itself but also mixes the normal or abnormal behavior information of the neighboring nodes, facilitating subsequent anomaly detection and localization.

[0030] It should be noted that the final circuit diagram node state representation tensor can be obtained through the following formula, that is: , where, represents the final state representation of node i, represents the initial feature vector of node i, represents the initial feature vector of node j, represents the set of adjacent nodes of node i, Represents the edge attribute value between node i and node j, which can reflect the connection strength, impedance or other electrical parameters. represents the Euclidean norm, represents the square of the Euclidean distance between the feature vectors of node j and node i, To prevent division by zero for extremely small positive numbers, and Represent the natural logarithm and exponential function respectively, the outer This formula combines node self-information and neighborhood information and captures complex structural relationships through nonlinear transformation. First, by taking the logarithm The edge attributes are nonlinearly amplified. Connections with larger edge attributes (such as between two nodes with strong electrical coupling) receive higher weights during the aggregation process, thereby amplifying the impact of important neighborhood information on node status. At the same time, the difference term It reflects the relative difference between the characteristics of the neighborhood nodes and the central node, which is used to capture the deviation in the electrical signal performance between the two. The deviation is divided by After that, the contribution ratio between similar nodes and different nodes can be adaptively adjusted to avoid excessive impact of too large or too small values on the aggregation results; in this summation term, the contributions of all neighboring nodes are accumulated, reflecting the idea of information propagation and multi-level feature fusion in graph convolution operations. Then, the accumulated result is combined with the feature of node i itself The addition not only retains the node's own information, but also integrates the external information transmitted by the adjacent nodes. Then, the exponential function is used to map the linear superposition relationship into a richer nonlinear representation. Finally, the outer layer adds logarithmic operations to the overall result to complete the compression and normalization of the data dynamic range. This formula helps to closely link the state representation of each node in the circuit diagram with the characteristic information of its surrounding nodes, so that the output of the final circuit diagram node state representation tensor contains both the unique electrical signal properties of each node and the structural contextual relationship between adjacent nodes in the circuit, and nonlinearly characterizes the information differences between different nodes due to connection properties. For example, during the detection process, if the electrical signal of a capacitor node is slightly abnormal and other components connected to it in its neighborhood perform normally, the calculated component will reflect the abnormal deviation of the node, thereby providing an effective basis for subsequent abnormal scoring and detection judgment.

[0031] Step 140: Determine the feature deviation between each target node and the corresponding adjacent node according to the node state representation tensor of the circuit diagram node set.

[0032] Specifically, after obtaining the node state representation tensor, according to the mapping relationship between channels and nodes, each target node state is decoded to restore the electrical signal sequence. The restored reconstructed signal sequence is compared with the original input signal step by step in time, the difference is calculated, and the error residual sequence is generated. The reconstruction error is quantified through operations such as weighted integration. At the same time, the state representations of the target nodes and all their adjacent nodes are extracted from the graph structure, the vector distance or similarity deviation between each node is calculated, and a feature deviation matrix is formed as an anomaly criterion in the structural environment, so as to obtain the deviation degree of each node from its topological neighborhood in the feature space.

[0033] In an alternative implementation manner of this embodiment, the steps of determining the feature deviation between each target node and its corresponding adjacent node according to the node state representation tensor of the circuit diagram node set include: performing feature decoding on the state representation of each target node and the synchronization signal of its corresponding channel according to the circuit diagram node state representation tensor to generate a node-level reconstructed signal sequence; obtaining a node-level error residual sequence by calculating the difference step by step in time between the node-level reconstructed signal sequence and the original signal sequence, and obtaining the reconstruction error index value of the corresponding target node through a residual weighted integration operation; processing the state representation tensor of any target node and the state representation of its adjacent nodes to generate a feature deviation matrix between multiple pairs of nodes.

[0034] Specifically, according to the node state of the circuit diagram, the state representation of each target node in the tensor is used. This representation reflects the multi-dimensional information aggregated by the node in the overall circuit topology after graph convolution operations. The synchronization signal of the corresponding channel is used as an auxiliary input. Through the feature decoder, the node state representation is mapped back to the original time series signal space. The inverse convolution or transposed one-dimensional convolution network technology is used to transform the node state to generate a node-level reconstructed signal sequence. Its function is to reconstruct a reconstructed signal that reflects the temporal variation of the electrical signal from the high-dimensional graph features. For example, when a certain node shows an atypical pattern in temperature or voltage fluctuation detection, the decoder can output a reconstructed signal sequence that is similar to but deviated from the trend of the original signal, thus providing a basis for subsequent comparison. Then, the difference between the obtained node-level reconstructed signal sequence and the original signal sequence is calculated at each time point, and methods such as absolute value calculation or Euclidean distance are used to obtain an error residual sequence for each time step. This sequence accurately reflects the deviation between the original signal and the reconstructed signal in the local time domain, and through the residual weighted integration operation, a predetermined weight is applied to the error residual sequence for weighted summation. The setting of the weight is determined according to time correlation or signal feature importance. The result generates a reconstruction error index value corresponding to the target node. This index value expresses the cumulative deviation degree that occurs in the node signal during the reconstruction process, thus becoming an important quantitative identifier for determining whether the electrical performance of the node is abnormal. Subsequently, the state representation tensor of any target node is compared with the state representations of its adjacent nodes in the circuit diagram, and a feature deviation matrix between multiple pairs of nodes is generated by calculating the distance between vectors (for example, by solving the vector difference through the L2 norm). Each element in the matrix represents the deviation magnitude between the target node and its adjacent nodes in the feature space. This matrix helps to reveal the distribution of nodes with abnormal electrical signal performance in the local area during detection. For example, if there is a large difference between a certain node and its neighboring nodes in a certain circuit area, then this node may show a unique electrical response due to component abnormalities or connection problems. This method as a whole generates a quantitative index reflecting the feature deviation between the node individual and the local collective through joint decoding of the node state and the corresponding channel synchronization signal, error signal calculation, and neighborhood information comparison, providing a solid technical basis for subsequent determination based on the abnormal score value, and further meeting the in-depth detection requirements for abnormal electrical performance of complex PCBA.

[0035] Step 150: Generate an abnormal score value vector corresponding to the target node according to the feature deviation.

[0036] Specifically, based on the above-obtained reconstruction error and feature deviation information, an anomaly score value vector corresponding to each node is comprehensively calculated and generated. This score vector reflects the deviation intensity of each node in terms of the original signal reconstruction ability and structural consistency, and can be used to express the potential possibility of its abnormal behavior. The scoring mechanism can process multi-source metrics by combining a non-linear weighting function, and set different sensitivity weights according to node categories or functional regions for reference in subsequent judgment processes.

[0037] Step 160: Construct a signal characterization model based on the set of simulated signal variants generated by perturbing and transforming the signal sequence tensor.

[0038] Specifically, to enhance the model's expression ability for unseen samples, the original signal sequence tensor is used as the basis, and signal perturbation operations are performed on it to construct a set of simulated signal variants. The perturbation methods include random noise injection, amplitude compression, time segment shuffling, or other data augmentation strategies. Through these unlabeled data, self-supervised training of the model is carried out to construct a signal characterization model. This model learns the internal structure and variation laws of the signal by performing prediction tasks (such as sequence reconstruction, segment sorting, etc.), thereby obtaining an unsupervised signal embedding representation with strong generalization ability.

[0039] Step 170: Score the newly collected test signal data according to the anomaly score value vector and the signal characterization model, and output the PCBA electrical performance detection result.

[0040] Specifically, after collecting test signals from a new PCBA sample, the signal characterization model mentioned above is used to extract its feature vector, and the corresponding electrical signal sequence is reconstructed through a decoder. Calculate the error between the original sampling data and the reconstructed signal, and combine the above-mentioned anomaly score value vector to form a comprehensive score tensor under the channel-node mapping relationship. Perform threshold analysis and anomaly localization processing on this score tensor, and finally output the electrical performance detection result, including the node-level score value, the potential abnormal positions in the circuit structure, and the whole-board-level status classification result, thereby completing the in-depth evaluation and anomaly identification of the PCBA electrical function status.

[0041] In an alternative implementation of this embodiment, the steps of scoring the newly collected test signal data according to the anomaly score value vector and the signal characterization model and outputting the PCBA electrical performance detection result include: obtaining the test signal data of the PCBA sample and generating a corresponding target signal sequence tensor; performing feature projection and characterization decoding on the target signal sequence tensor according to the signal characterization model to generate a predicted reconstructed signal sequence; determining a target reconstruction error vector according to the residual information between the predicted reconstructed signal sequence and the sampling sequence corresponding to the test signal data; performing mapping scoring on the corresponding positions of each node channel in the PCBA sample according to the anomaly score value vector, and generating a comprehensive score tensor in combination with the target reconstruction error vector; and determining the electrical performance detection result of the PCBA sample by performing threshold parsing on the comprehensive score tensor.

[0042] Specifically, after obtaining the test signal data of the PCBA sample, a target signal sequence tensor is constructed based on the multi-channel time-series electrical signals output by the acquisition device. The signal data refers to numerical sequences such as voltage, current, and frequency response that change over time, and its construction process is converted into a standardized multi-dimensional data structure through preprocessing (such as normalization and clipping). This tensor serves as the basic data for subsequent model processing. Subsequently, a pre-trained signal characterization model, which includes a feature projection network and a characterization decoder, is used. The target signal sequence tensor is input into the network, and a predicted reconstructed signal sequence is obtained through non-linear mapping. This process uses a deep neural network to abstract and reconstruct the features of the time-series data, thereby generating a predicted signal that reflects the original time-series features. For example, when local waveform deviations are detected in the signal, the generated reconstructed sequence will show corresponding subtle differences. Next, by calculating the residual information between the predicted reconstructed signal sequence and the sampling sequence corresponding to the original test signal data, a target reconstruction error vector is obtained using a step-by-step time comparison method. The calculation method can obtain the residual information through the absolute difference or the square difference formula. This vector reflects the reconstruction error of the signal at each sampling moment, providing a basis for anomaly analysis. At the same time, by using the anomaly score value vector to perform mapping scoring on the corresponding positions of each node channel in the PCBA sample, an anomaly distribution based on the structural position is established. This score vector reflects the degree of deviation of the electrical behavior from the expected value at the node level. Then, the anomaly score value vector is combined with the target reconstruction error vector. The calculation of the comprehensive score tensor can be expressed by the following formula: , where, represents the comprehensive score value of node i, represents the anomaly score value of the corresponding node, represents the reconstruction error value of node i, represents the variance of the error vector, used to measure the overall fluctuation of the error, is a very small positive number to prevent division-by-zero errors, and the combination of logarithmic and exponential functions is used for dynamic interval compression and non-linear mapping of scores. The purpose of this formula is to fuse the abnormal score and the reconstruction error into a single quantitative index, so as to reveal whether there are abnormalities in the electrical performance of the node. For example, if and are both large, the comprehensive score will be higher than the preset threshold. Finally, threshold parsing is performed based on the comprehensive score tensor. By setting a decision threshold to compare the scores of each node in the tensor, it is determined whether the detection result of the node electrical performance exceeds the normal range, and the complete PCBA electrical performance detection result is output based on this. This detection result not only indicates the overall electrical state, but also locates the specific abnormal nodes, providing refined data support for subsequent maintenance and fault prevention.

[0043] In an optional implementation manner of this embodiment, test samples corresponding to a preset abnormal threshold interval are identified according to the electrical performance detection result, and an initial abnormal sample candidate set is generated; through joint statistical processing of the node-level score information and the predicted reconstruction error information of the abnormal sample candidate set, a sample label generation matrix is constructed, and a pseudo-label index set is generated according to a preset clustering strategy; by combining the pseudo-label index set with the signal sequence tensor into a training sample and inputting it into the signal representation model to perform parameter fine-tuning and update, an iteratively optimized signal representation model version is generated; by performing difference analysis on the structural parameters of the signal representation model version and the historical model parameters, the model drift amount is determined; based on the drift amount, a dynamic score adjustment factor is generated to update the bias term parameters in the abnormal score value vector and the comprehensive score tensor.

[0044] Specifically, based on the numerical data obtained from the electrical performance test results, first, the test samples falling within the preset abnormal threshold range are screened to generate an initial candidate set of abnormal samples. This set contains sample records that show significant differences in electrical response from the normal expectation. Its significance lies in providing preliminary candidate objects for subsequent abnormal sample identification. For example, during the detection process, if the voltage waveform of a certain control module deviates from the set range, the corresponding sample will be included in the candidate set. Next, the scoring information of each node in the candidate set and the predicted reconstruction error information generated by the signal characterization model are jointly statistically processed. By constructing a sample label generation matrix, feature fusion is performed on the candidate samples. The construction of this matrix is based on the statistical correlation between the scores of each node and the reconstruction error, and the fused data is classified according to the preset clustering strategy, thereby forming a pseudo-label index set. This index set identifies samples with similar characteristics in abnormal patterns. For example, if multiple nodes in a certain area all show high reconstruction errors, these nodes will show an aggregation effect in the matrix and will then be grouped into one category. Subsequently, by combining the pseudo-label index set with the original signal sequence tensor, a training sample with pseudo-labels is constructed. This training sample is then input into the signal characterization model for parameter fine-tuning and update, thereby generating an iteratively optimized version of the signal characterization model. This process enables the model to obtain a more refined expression of the inherent temporal characteristics and abnormal patterns of electrical signals. For example, the fine-tuned model can be more sensitive to slight abnormal changes. Then, a detailed difference analysis is performed on the differences in the structural parameters reflected in the newly generated version of the signal characterization model and the parameters in the historical version. The calculation formula for the corresponding model offset can be expressed as: ， where represents the model drift amount, and respectively represent the values of the iterated and historical signal characterization models at the i-th parameter. N is the total number of model parameters, and is a positive decimal number to prevent division by zero. This formula can accurately measure the drift level reflected by the parameter changes during the iteration of the model and provide a quantitative basis for generating a dynamic scoring adjustment factor; finally, based on the obtained drift amount, it is mapped to a dynamic scoring adjustment factor. This factor is used to update the bias term parameters in the abnormal score value vector and the comprehensive score tensor. Through this dynamic adjustment mechanism, the abnormal scoring system can adaptively adjust with model updates and data evolution, and then more accurately score and locate potential abnormalities in newly collected samples. For example, when the drift amount is large, the corresponding adjustment factor will amplify the score, making the abnormal samples more prominent in the comprehensive score tensor, thereby ensuring that the PCBA electrical performance test results output have high discriminant reliability and pertinence.

[0045] According to a PCBA electrical performance detection method provided by the solution of the present application, multi-channel time-series electrical signals of multiple test nodes on the PCBA are collected, and the signals are synchronously processed to generate a signal sequence tensor; multi-scale feature extraction is performed on the tensor to construct a channel-level embedding vector group; the embedding vectors are mapped to the corresponding nodes of the PCBA circuit diagram structure to generate a circuit diagram node set; based on the node state representation extracted by the graph neural network, combined with the original signals, the feature deviation analysis of adjacent nodes is performed to generate an abnormal score value vector; at the same time, an unlabeled characterization model is constructed; finally, based on the score value and the characterization model, the electrical performance of the newly collected signals is scored and the state is judged. The present application can be used for the global electrical performance detection of complex circuit boards, solve the problem of missed detection caused by the inability to consider the overall structure perception and local anomaly recognition, and improve the accuracy of electrical performance detection.

[0046] Figure 2 A PCBA electrical performance detection device provided by an embodiment of the present application can be used to implement the PCBA electrical performance detection method in the foregoing embodiment. As Figure 2 shown, the PCBA electrical performance detection device mainly includes: A generation module 10, configured to generate a signal sequence tensor after time series synchronization according to multi-channel time-series electrical signal data collected by test nodes on the PCBA; An acquisition module 20, configured to obtain local change features of multi-channel time-series electrical signal data by performing feature processing on the signal sequence tensor, and construct a channel-level embedding vector group; A mapping module 30, configured to map the channel-level embedding vector group to the corresponding nodes of the PCBA corresponding circuit diagram structure to generate a circuit diagram node set; A determination module 40, configured to determine the feature deviation between each target node and the corresponding adjacent node according to the node state representation tensor of the circuit diagram node set; The generation module 10 is further configured to generate an abnormal score value vector of the corresponding target node according to the feature deviation; A construction module 50, configured to construct a signal characterization model according to a set of analog signal variants generated by performing perturbation transformation on the signal sequence tensor; An output module 60, configured to score the newly collected test signal data according to the abnormal score value vector and the signal characterization model, and output the PCBA electrical performance detection result.

[0047] In an optional implementation of the present embodiment, the generation module is specifically used for: acquiring original sampling sequences of multiple channels according to multiple signal test nodes of a preset test station; wherein the original sampling sequence includes original timing voltage, current and frequency response sampling sequences; performing time offset alignment processing on each channel of the original sampling sequence through a preset time base reference signal to generate a time synchronization index set; performing interpolation resampling operations on the original sampling sequence according to the time synchronization index set to generate a standardized signal sequence with consistent time steps between channels; generating a signal sequence tensor after timing synchronization by performing amplitude normalization and data cropping processing on the standardized signal sequence.

[0048] In an optional implementation of the present embodiment, the acquisition module is specifically used for: performing sliding window segmentation processing on the time series electrical signal data of each channel according to the signal sequence tensor, and generating a local signal slice sequence containing time series segments; obtaining a local change feature map of each signal channel at different time scales by performing a one-dimensional convolution operation on the local signal slice sequence, and constructing a feature hierarchy with temporal multi-resolution according to the multi-level setting of the convolution kernel receptive field; generating an initial channel-level embedding vector sequence containing inter-channel difference representation by performing concatenation operation and position encoding processing on the feature hierarchy; obtaining a channel-level embedding vector group expressing the global time series relationship and channel feature distribution by performing attention encoding on the initial embedding vector sequence.

[0049] In an optional implementation of the present embodiment, the mapping module is specifically used to: generate a circuit diagram structure containing topological indexes of nodes of each component according to the component connection relationship and predefined node address rules in the PCBA schematic structure; map the channel-level embedding vector group to the circuit diagram structure according to the mapping relationship between the channel and the node, and generate a set of node initialization feature tensors; after the step of generating the set of node initialization feature tensors, it also includes: jointly embedding the node features of the node initialization feature tensor set with the edge attributes in the circuit diagram structure through graph structure encoding to generate the original graph neural network input graph; perform layer-by-layer graph convolution operations in a predefined graph convolution layer stacking structure according to the input graph to obtain the circuit diagram node state representation tensor after structural context fusion.

[0050] In an optional implementation of the present embodiment, the determination module is specifically used for: performing feature decoding on the state representation of each target node and the synchronization signal of its corresponding channel according to the circuit diagram node state representation tensor, and generating a node-level reconstructed signal sequence; obtaining a node-level error residual sequence by performing time-step difference calculation on the node-level reconstructed signal sequence and the original signal sequence, and obtaining the reconstruction error index value of the corresponding target node through a residual weighted integration operation; processing the state representation tensor of any target node and the state representation of its adjacent node, and generating a feature deviation matrix between multiple pairs of nodes.

[0051] In an alternative implementation of this embodiment, the output module is specifically configured to: acquire the test signal data of the PCBA sample and generate a corresponding target signal sequence tensor; perform feature projection and characterization decoding on the target signal sequence tensor according to the signal characterization model to generate a predicted reconstructed signal sequence; determine a target reconstruction error vector according to the residual information between the predicted reconstructed signal sequence and the sampling sequence corresponding to the test signal data; perform mapping scoring on the corresponding positions of each node channel in the PCBA sample according to the abnormal score value vector, and generate a comprehensive scoring tensor in combination with the target reconstruction error vector; determine the electrical performance detection result of the PCBA sample by performing threshold analysis on the comprehensive scoring tensor.

[0052] In an alternative implementation of this embodiment, the PCBA electrical performance detection device further includes an update module. The update module is configured to: identify test samples corresponding to a preset abnormal threshold interval according to the electrical performance detection result and generate an initial abnormal sample candidate set; perform joint statistical processing on the node-level scoring information and the predicted reconstruction error information of the abnormal sample candidate set to construct a sample label generation matrix, and generate a pseudo-label index set according to a preset clustering strategy; combine the pseudo-label index set with the signal sequence tensor to form a training sample, and input it into the signal characterization model to perform parameter fine-tuning and update, generating an iteratively optimized version of the signal characterization model; perform difference analysis on the structural parameters of the signal characterization model version and the historical model parameters to determine the model drift amount; generate a dynamic scoring adjustment factor based on the drift amount, and update the bias term parameters in the abnormal score value vector and the comprehensive scoring tensor.

[0053] A PCBA electrical performance detection device provided by the solution of the present application collects multi-channel time-series electrical signals of multiple test nodes on the PCBA, and synchronizes the signals to generate a signal sequence tensor; performs multi-scale feature extraction on the tensor to construct a channel-level embedding vector group; maps the embedding vectors to the corresponding nodes of the PCBA circuit diagram structure to generate a circuit diagram node set; performs adjacent node feature deviation analysis by combining the node state representation extracted by the graph neural network with the original signal to generate an abnormal score value vector; simultaneously constructs an unlabeled characterization model; finally, based on the score value and the characterization model, performs electrical performance scoring and state judgment on the newly collected signals. The present application can be used for the global electrical performance detection of complex circuit boards, solves the problem of missed detection caused by the inability to consider the overall structure perception and local anomaly recognition, and improves the accuracy of electrical performance detection.

[0054] According to the solution provided by the present application Figure 3 An electronic device provided by an embodiment of the present application. This electronic device can be used to implement the PCBA electrical performance detection method in the foregoing embodiments, and mainly includes: A memory 301, a processor 302, and a computer program 303 stored on the memory 301 and executable on the processor 302. The memory 301 and the processor 302 are communicatively connected. When the processor 302 executes the computer program 303, the PCBA electrical performance detection method in the foregoing embodiments is implemented. Among them, the number of processors can be one or more.

[0055] The memory 301 can be a high-speed random access memory (RAM), or a non-volatile memory, such as a disk memory. The memory 301 is used to store executable program codes, and the processor 302 is coupled to the memory 301.

[0056] Furthermore, an embodiment of the present application also provides a computer-readable storage medium, which can be disposed in the electronic device in the foregoing embodiments. The computer-readable storage medium can be the memory in the foregoing Figure 3 illustrated embodiments.

[0057] A computer program is stored on the computer-readable storage medium. When the program is executed by a processor, the PCBA electrical performance detection method in the foregoing embodiments is implemented. Furthermore, the computer-readable storage medium can also be various media such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a RAM, a magnetic disk, or an optical disc that can store program codes.

[0058] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein.

[0059] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The foregoing storage medium includes: various media such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disc that can store program codes.

[0060] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than limiting it; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for detecting the electrical performance of a PCBA, characterized in that, Including: Generating a signal sequence tensor after time synchronization according to multi-channel time-series electrical signal data collected from test nodes on the PCBA; Obtaining local change features of the multi-channel time-series electrical signal data by performing feature processing on the signal sequence tensor, and constructing a channel-level embedding vector group; Mapping the channel-level embedding vector group to corresponding nodes of the circuit diagram structure corresponding to the PCBA to generate a circuit diagram node set; Determining the feature deviation between each target node and its corresponding adjacent node according to the node state representation tensor of the circuit diagram node set; Generating an abnormal score value vector corresponding to the target node according to the feature deviation; Constructing a signal characterization model according to a set of simulated signal variants generated by performing perturbation transformation on the signal sequence tensor; Scoring newly collected test signal data according to the abnormal score value vector and the signal characterization model, and outputting the PCBA electrical performance detection result.

2. The PCBA electrical performance detection method according to claim 1, wherein The step of generating a signal sequence tensor after time synchronization according to multi-channel time-series electrical signal data collected from test nodes on the PCBA includes: Obtaining original sampling sequences of multiple channels according to multiple signal test nodes of a preset test station; wherein, the original sampling sequences include original time-series voltage, current, and frequency response sampling sequences; Performing time offset alignment processing on each channel of the original sampling sequence through a preset time base reference signal to generate a time synchronization index set; Performing interpolation resampling operation on the original sampling sequence according to the time synchronization index set to generate a standardized signal sequence with consistent time steps between channels; Generating a signal sequence tensor after time synchronization by performing amplitude normalization and data clipping processing on the standardized signal sequence.

3. The PCBA electrical performance detection method according to claim 1, characterized in that, The step of obtaining local change features of the multi-channel time-series electrical signal data by performing feature processing on the signal sequence tensor and constructing a channel-level embedding vector group includes: Performing sliding window segmentation processing on the time-series electrical signal data of each channel according to the signal sequence tensor to generate a local signal slice sequence containing time-series segments; Performing one-dimensional convolution operation on the local signal slice sequence to obtain local change feature maps of each signal channel at different time scales, and constructing a feature hierarchy with time multi-resolution according to the multi-level setting of the receptive field of the convolution kernel; Generating an initial channel-level embedding vector sequence containing the difference representation between channels through concatenation operation and position encoding processing on the feature hierarchy; Obtaining a channel-level embedding vector group expressing global time-series relationships and channel feature distributions by performing attention encoding on the initial embedding vector sequence.

4. The PCBA electrical performance detection method according to claim 3, wherein The step of mapping the channel-level embedding vector group to corresponding nodes of the circuit diagram structure corresponding to the PCBA to generate a circuit diagram node set includes: Generating a circuit diagram structure containing topological indexes of component nodes according to the component connection relationship in the PCBA schematic diagram structure and a predefined node address rule; Mapping the channel-level embedding vector group to the circuit diagram structure according to the mapping relationship between channels and nodes, and generating a set of node initialization feature tensors; After the step of initializing the set of feature tensors by the generation node, the following steps are further included: Through graph structure encoding, jointly embed the node features of the set of node-initialized feature tensors and the edge attributes in the circuit diagram structure to generate an original graph neural network input graph; Perform layer-by-layer graph convolution operations on the input graph in a predefined graph convolution layer stacking structure to obtain a circuit diagram node state representation tensor after structural context fusion.

5. The PCBA electrical performance detection method according to claim 1, characterized in that, The step of determining the feature deviation between each target node and its corresponding adjacent node according to the node state representation tensor of the circuit diagram node set includes: According to the circuit diagram node state representation tensor, perform feature decoding on the state representation of each target node and its corresponding channel synchronization signal to generate a node-level reconstruction signal sequence; By calculating the difference between the node-level reconstruction signal sequence and the original signal sequence at each time step, obtain a node-level error residual sequence, and obtain the reconstruction error index value of the corresponding target node through a residual weighted integration operation; Process the state representation tensor of any one of the target nodes and the state representations of its adjacent nodes to generate a feature deviation matrix between multiple pairs of nodes.

6. The PCBA electrical performance detection method according to claim 5, wherein The step of scoring the newly collected test signal data according to the abnormal score value vector and the signal characterization model and outputting the PCBA electrical performance detection result includes: Obtain the test signal data of the PCBA sample and generate a corresponding target signal sequence tensor; According to the signal characterization model, perform feature projection and characterization decoding on the target signal sequence tensor to generate a predicted reconstruction signal sequence; Determine a target reconstruction error vector according to the residual information between the predicted reconstruction signal sequence and the sampling sequence corresponding to the test signal data; Map and score the corresponding positions of each node channel in the PCBA sample according to the abnormal score value vector, and generate a comprehensive score tensor in combination with the target reconstruction error vector; Determine the electrical performance detection result of the PCBA sample by performing threshold analysis on the comprehensive score tensor.

7. The PCBA electrical performance detection method according to claim 6, wherein, The method further includes: Identify test samples corresponding to a preset abnormal threshold interval according to the electrical performance detection result, and generate an initial abnormal sample candidate set; Through joint statistical processing of the node-level scoring information and the predicted reconstruction error information of the abnormal sample candidate set, construct a sample label generation matrix, and generate a pseudo-label index set according to a preset clustering strategy; Combine the pseudo-label index set and the signal sequence tensor into a training sample, and input it into the signal characterization model to perform parameter fine-tuning and update to generate an iteratively optimized signal characterization model version; Determine the model drift amount by analyzing the difference between the structural parameters of the signal characterization model version and the historical model parameters; Generate a dynamic score adjustment factor based on the drift amount, and update the bias term parameters in the abnormal score value vector and the comprehensive score tensor.

8. A PCBA electrical performance detection device, characterized in that, The PCBA electrical performance detection device includes: A generation module for generating a signal sequence tensor after time sequence synchronization according to multi-channel time sequence electrical signal data collected by test nodes on the PCBA; An acquisition module, configured to acquire local change features of the multi-channel time-series electrical signal data by performing feature processing on the signal sequence tensor, and construct a channel-level embedding vector group; A mapping module, configured to map the channel-level embedding vector group to corresponding nodes of the circuit diagram structure corresponding to the PCBA to generate a circuit diagram node set; A determination module, configured to determine a feature deviation between each target node and a corresponding adjacent node according to a node state representation tensor of the circuit diagram node set; A generation module, further configured to generate an abnormal score value vector corresponding to the target node according to the feature deviation; A construction module, configured to construct a signal characterization model according to a set of analog signal variants generated by performing perturbation transformation on the signal sequence tensor; An output module, configured to score newly acquired test signal data according to the abnormal score value vector and the signal characterization model, and output a PCBA electrical performance detection result.

9. An electronic device, characterized in that, Comprising a memory and a processor, wherein: The processor is configured to execute a computer program stored on the memory; When the processor executes the computer program, the steps in the PCBA electrical performance detection method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, the steps in the PCBA electrical performance detection method according to any one of claims 1 to 7 are implemented.

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