Audio accelerator and audio processing method

Abstract

The invention relates to the field of audio processing, and discloses an audio accelerator and an audio processing method, and the audio accelerator comprises a data storage unit which is used for storing audio data and an intermediate calculation result; the address generation unit is used for generating and managing a storage address of the audio data; a data operation unit for performing calculation processing of the audio data; and the control unit is used for coordinating data streams and processing flows among the units. The processing efficiency and flexibility can be considered, and the audio data processing performance is improved.

Description

Technical Field

[0001] The present invention relates to the field of audio processing, and particularly to an audio accelerator and an audio processing method. Background Art

[0002] With the popularization of consumer electronic devices, audio processing technology plays an increasingly important role in daily life. Audio processing usually involves complex computational tasks such as audio equalization and dynamic range compression, which pose high requirements on the computing power of the processor.

[0003] Existing audio processing systems mainly adopt software implementation based on general-purpose processors or accelerator implementation based on dedicated hardware. Software implementation has high flexibility but insufficient efficiency, and it is difficult to meet the real-time processing requirements of resource-constrained devices; dedicated hardware accelerators have high processing efficiency but lack flexibility, and it is difficult to adapt to diverse audio processing requirements.

[0004] In terms of hardware structure, there are three main problems in existing audio accelerators: First, the storage structure is not optimized for the characteristics of sliding windows and strided access in audio processing, resulting in low storage access efficiency; second, the address generation mechanism only supports simple linear address generation and cannot effectively support complex addressing modes such as circular buffering and interleaved access common in audio processing; third, the design of the arithmetic unit is difficult to balance high-precision calculation and processing efficiency, and it is difficult to adapt to the precision requirements of different processing stages.

[0005] In terms of audio processing methods, existing technologies mostly focus on the implementation of single algorithms and lack a systematic design concept, resulting in inconsistent interfaces between different algorithms and making it difficult to flexibly combine them. Although common audio processing tasks such as equalization and compression have common basic operation modes, their implementations are often independent, with low code reuse rate, increasing the system complexity.

[0006] In addition, existing audio processing methods do not fully consider the hardware characteristics, resulting in a mismatch between algorithm implementation and hardware structure and unable to fully utilize the hardware acceleration advantage. For example, the implementation of basic algorithms such as finite impulse response filtering, infinite impulse response filtering, and fast Fourier transform fails to effectively utilize the functions of dedicated hardware, limiting the processing performance.

[0007] Therefore, there is an urgent need to propose an audio accelerator and an audio processing method to solve the above problems. Summary of the Invention

[0008] The object of the present invention is to propose an audio accelerator and an audio processing method, which can balance processing efficiency and flexibility and improve the audio data processing performance.

[0009] To solve the above technical problems, the present invention provides an audio accelerator, including: A data storage unit for storing audio data and intermediate calculation results; An address generation unit for generating and managing the storage addresses of audio data; A data operation unit for performing calculation processing on audio data; and A control unit for coordinating the data flow and processing flow among the units.

[0010] Furthermore, the data storage unit includes: An SRAM memory with a 64-bit data bit width and a 128-row storage capacity; And a data access controller for supporting 64-bit full data access and 32-bit partial data access.

[0011] Furthermore, the address generation unit includes: Multiple address registers for storing the data addresses being currently processed; An address update logic for supporting increment, decrement, offset, and loop operations of the values in the address registers; and An address mapping structure for mapping logical addresses to physical storage units.

[0012] Furthermore, the multiple address registers include 8 address registers with a 10-bit width, for supporting circular addressing and strided access modes in audio processing.

[0013] Furthermore, the data operation unit includes: A multiplier unit with 32-bit input channels and a 72-bit precision extension mechanism, performing multiple operation modes including independent multiplication operations, multiply-accumulate operations, and multiply-then-left-shift-accumulate operations; An accumulator unit for performing accumulation operations; An arithmetic logic unit including a high-precision operation part and a standard-precision operation part; and A bit width conversion unit for performing data bit width conversion.

[0014] Furthermore, the high-precision operation part includes a 72-bit data processing circuit for implementing at least one of right shift, saturation processing, rounding, and extreme value selection operations; the standard-precision operation part includes a 32-bit data processing circuit for implementing at least one of bidirectional shift, arithmetic operations, and comparison operations.

[0015] Furthermore, the control unit includes: An instruction decoder for parsing and executing audio processing instructions; A data flow controller for managing the data transfer paths among the units; and A parallel execution control circuit for enabling the simultaneous operation of the multiplier unit and the arithmetic logic unit.

[0016] In addition, the present invention also provides an audio processing method using the audio accelerator as described above, which specifically includes the following: Generate an address sequence through an address generation unit and load audio data into a data storage unit; Process and calculate the audio data using a data operation unit; and Output the processed audio data from the data storage unit.

[0017] Furthermore, the process of processing and calculating the audio data using the data operation unit specifically includes: Based on a multiplier unit and an accumulator unit, perform finite impulse response filtering or infinite impulse response filtering on the audio data; Based on the circular addressing and strided access functions of the address generation unit, perform a fast Fourier transform on the audio data; and Based on the high-precision operation part and the standard-precision operation part of the arithmetic logic unit, perform frequency response adjustment on the audio data.

[0018] Furthermore, during the processing of performing filtering, transformation, and adjustment, it specifically includes: Adopt the parallel execution control circuit of the control unit to simultaneously execute different instructions of the multiplier unit and the arithmetic logic unit; Generate the address of the next batch of processing data through the address update logic of the address generation unit; and Perform saturation and rounding operations through the high-precision operation part of the arithmetic logic unit.

[0019] Through the above technical solutions, the present invention has the following beneficial effects: Through the settings of the data storage unit, address generation unit, data operation unit, and control unit, a dedicated accelerator structure for audio processing is formed, which can effectively solve the problem that it is difficult to balance flexibility and efficiency in existing audio processing systems. This device can support multiple audio processing algorithms, maintain high efficiency in hardware acceleration, and significantly improve the real-time processing ability of audio data, especially suitable for resource-constrained embedded devices.

[0020] The 64-bit data bit width and flexible access mode of the data storage unit can meet the high data throughput requirements in audio processing; the multiple address registers and rich update mechanism of the address generation unit support complex circular addressing and strided access modes, which can accelerate data access in audio algorithms; the data operation unit can meet the high-precision calculation requirements in audio processing by integrating a 72-bit precision extension mechanism and multiple operation modes. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a block diagram of an audio accelerator in an embodiment of the present invention; Figure 2 It is a flowchart of an audio processing method in an embodiment of the present invention; Figure 3 It is an overall flowchart of an audio processing method in an embodiment of the present invention; Figure 4 It is a schematic diagram of the delay chain structure of the data operation unit in an audio processing method in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] Based on the inspiration of this specification and without generating technical contradictions, those skilled in the art can form new technical solutions through cross-combination of different embodiments, and such variations should be regarded as falling within the protection scope of this patent.

[0023] Hereinafter, an audio accelerator and an audio processing method of the present invention will be described in more detail with reference to the drawings, in which the preferred embodiments of the present invention are shown. It should be understood that those skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Therefore, the following description should be understood as broad guidance for those skilled in the art and not as a limitation to the present invention.

[0024] In the following paragraphs, the present invention will be described more specifically by way of example with reference to the drawings. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0025] As Figure 1 shown, an embodiment of the present invention provides an audio accelerator, including: a data storage unit for storing audio data and intermediate calculation results; an address generation unit for generating and managing the storage addresses of audio data; a data operation unit for performing calculation processing on audio data; and a control unit for coordinating the data flow and processing flow between the units.

[0026] Specifically, the data storage unit is the data storage area of the audio accelerator, responsible for storing the input audio data, intermediate results during the processing, and the final output data; the address generation unit manages the storage locations of these data, and supports special access patterns of various audio algorithms to the data by generating appropriate address sequences; the data operation unit performs actual calculation operations such as multiplication, accumulation, and displacement, and is the core calculation engine for audio processing; the control unit coordinates the work of the other three units to ensure the smooth execution of the entire processing flow.

[0027] In this embodiment, the data storage unit includes: an SRAM memory with a 64-bit data width and a storage capacity of 128 rows; and a data access controller for supporting 64-bit full data access and 32-bit partial data access.

[0028] Specifically, the SRAM memory adopts high-speed static random access storage technology, which has lower access latency and higher throughput compared to dynamic random access memory (DRAM), and is suitable for scenarios that require frequent access in audio processing; the 64-bit data width allows multiple audio sampling points or parameters to be processed simultaneously, enhancing the parallelism of data processing; the storage capacity of 128 rows not only meets the data caching needs of common audio algorithms but also controls the chip area cost. The data access controller enables the storage unit to have a flexible access mechanism. The 64-bit full access mode is suitable for batch data processing to improve throughput; the 32-bit partial access mode is suitable for occasions that require fine control, improving flexibility.

[0029] In a specific example, the SRAM memory can be organized into multiple independent storage blocks, and each block can perform different read and write operations simultaneously, further improving the parallelism of data access. For example, the 128-row storage capacity can be divided into 4 blocks of 32 rows. When performing the FFT algorithm, one block can read data while another block writes the results simultaneously, reducing data access conflicts and waiting times. Those skilled in the art know that the specific organization method of the memory can be adjusted according to actual application requirements and also includes other implementation manners besides this embodiment.

[0030] In this embodiment, the address generation unit includes: multiple address registers for storing the data addresses currently being processed; address update logic that supports increment, decrement, offset, and loop operations of the values in the address registers; and an address mapping structure for mapping logical addresses to physical storage units. This design can support common complex addressing modes in audio processing, thus significantly improving data access efficiency.

[0031] Specifically, multiple address registers can track the addresses of different data streams simultaneously, such as the positions of input data, coefficient data, intermediate results, and output data; the address update logic provides a rich variety of address update methods, enabling the address generation unit to automatically complete address calculations and reducing the burden on the control unit; the address mapping structure realizes the conversion from logical addresses to physical addresses, improving the flexibility and efficiency of memory usage.

[0032] In one embodiment, the multiple address registers include 8 address registers each with a width of 10 bits, which are used to support circular addressing and strided access modes in audio processing. The configuration of 8 address registers enables the audio accelerator to process multiple independent data streams simultaneously, improving the processing ability for complex algorithms. Those skilled in the art will know that the number of address registers can be set according to actual requirements.

[0033] In this embodiment, the data operation unit includes: a multiplier unit, having a 32-bit input channel and a 72-bit precision extension mechanism, which executes various operation modes including independent multiplication operations, multiply-accumulate operations, and multiply-left-shift-accumulate operations after multiplication; an accumulator unit for performing accumulation operations; an arithmetic logic unit, including a high-precision operation part and a standard-precision operation part; and a bit-width conversion unit for performing the conversion of data bit-widths.

[0034] Specifically, the multiplier unit is the core calculation component in audio processing. The 32-bit input channel supports high-precision audio data processing, and the 72-bit precision extension mechanism avoids precision loss during intermediate calculation processes; the support for multiple operation modes enables the multiplier to efficiently complete the core operations in various algorithms, such as the multiply-accumulate operation of filters and the complex multiplication of FFT; the accumulator unit works in cooperation with the multiplier to achieve signal accumulation and averaging; the arithmetic logic unit processes various non-multiplication operations, and its hierarchical precision design balances calculation precision and efficiency; the bit-width conversion unit builds a bridge between different precision data processing stages, ensuring a reasonable configuration of data precision and processing efficiency.

[0035] In one embodiment, the high-precision operation part includes a 72-bit data processing circuit that realizes at least one of right shift, saturation processing, rounding, and extreme value selection operations; the standard-precision operation part includes a 32-bit data processing circuit that realizes at least one of bidirectional shift, arithmetic operation, and comparison operation. This dual-precision design enables the arithmetic logic unit to select an appropriate processing circuit according to the precision requirements of different operations, improving the resource utilization efficiency.

[0036] Specifically, the 72-bit high-precision arithmetic part is mainly used to process the results after multiplication or intermediate calculation processes that require high-precision guarantee. The right shift operation is used to scale the data amplitude. The saturation processing prevents distortion caused by numerical overflow. The rounding operation controls the error during precision truncation. The extreme value selection operation is used to implement comparison and selection functions. The 32-bit standard-precision arithmetic part is used to process calculations with general precision requirements, such as logical operations and comparison operations. This hierarchical processing not only ensures the precision of key calculation links but also improves the efficiency of general operations.

[0037] In this embodiment, the control unit includes: an instruction decoder for parsing and executing audio processing instructions; a data flow controller for managing the data transfer path between each unit; and a parallel execution control circuit for enabling the simultaneous operation of the multiplier unit and the arithmetic logic unit.

[0038] Specifically, the instruction decoder is responsible for converting the instructions from the main controller into control signals inside the accelerator, supporting the execution of various audio processing algorithms. The data flow controller manages the flow of data between the storage unit, the address generation unit, and the data arithmetic unit, enabling the data to reach the required processing unit in a timely manner. The parallel execution control circuit is the core innovation of the control unit. By coordinating the working timings of the multiplier unit and the arithmetic logic unit, they can execute different instructions simultaneously, greatly improving the processing throughput.

[0039] In a specific example, the control unit can also implement an instruction-level pipeline, dividing the instruction execution into multiple stages such as instruction fetching, decoding, execution, and write-back, and enabling different stages of different instructions to be executed in parallel on different functional units, further improving the efficiency of instruction processing. In addition, the control unit can also support a conditional execution mechanism, dynamically adjusting the execution flow according to the operation results or external conditions, improving the flexibility of the program. Those skilled in the art know that the specific implementation of the control unit can be adjusted according to application requirements and hardware constraints, and also includes other implementation methods besides this embodiment.

[0040] In addition, as Figures 2 - 4 shown, this embodiment also proposes an audio processing method that uses the audio accelerator as described above, specifically including the following steps: S1. Generate an address sequence through the address generation unit and load the audio data into the data storage unit; S2. Process and calculate the audio data using the data arithmetic unit; and S3. Output the processed audio data from the data storage unit.

[0041] In step S2, the processing and operation of the audio data by the data operation unit specifically include: performing finite impulse response filtering or infinite impulse response filtering on the audio data based on a multiplier unit and an accumulator unit; performing fast Fourier transform on the audio data based on the circular addressing and strided access functions of the address generation unit; and performing frequency response adjustment on the audio data based on the high-precision operation part and the standard-precision operation part of the arithmetic logic unit. Specifically, finite impulse response (FIR) filtering and infinite impulse response (IIR) filtering are the most basic algorithms in audio processing. Through the collaborative work of the multiplier unit and the accumulator unit, these filtering operations can be efficiently implemented (as Figure 4 shown, Figure 4 shows a delay chain structure formed by a series of Z -1 units connected, where Z -1 represents a unit delay element, which is usually used to implement signal delay in digital signal processing. Figure 4 The arrows in

[0042] indicate the data flow direction and show how the signal is transmitted through the delay chain. This structure is commonly used in audio processing to implement finite impulse response filters or adaptive filters); fast Fourier transform (FFT) is the basis of frequency domain processing, and the special addressing function of the address generation unit greatly simplifies the complexity of FFT implementation; frequency response adjustment requires the precise calculation ability of the arithmetic logic unit, and through the cooperation of the high-precision and standard-precision operation parts, both the calculation accuracy and the processing efficiency are optimized. Preferably, during the processing of filtering, transformation, and adjustment, it specifically includes: using the parallel execution control circuit of the control unit to simultaneously execute different instructions of the multiplier unit and the arithmetic logic unit; generating the address of the next batch of processing data through the address update logic of the address generation unit; and performing saturation and rounding operations through the high-precision operation part of the arithmetic logic unit. Specifically, parallel execution control enables multiplication operations and non-multiplication operations to be performed simultaneously, significantly improving the processing throughput; the automatic operation of the address update logic reduces the overhead of address calculation, enabling the processor to continuously obtain the required data; the saturation and rounding operations in high-precision operations ensure the accuracy and range control of the processing results, avoiding problems such as numerical overflow and loss of precision.

[0043] In this embodiment, the working process of the audio accelerator mainly includes the following stages: First, the main controller sends the instructions and parameters of the audio processing task to the control unit of the audio accelerator; then, the control unit parses the instructions and coordinates each functional unit to start working; next, the address generation unit generates a data access sequence and loads the input audio data from the main memory into the data storage unit inside the accelerator; the data operation unit executes the corresponding processing algorithm on the data according to the instructions of the control unit; finally, the processed result data is written back to the main memory or directly output to the next-level processing unit.

[0044] During the processing, different types of audio processing algorithms will have different execution paths. For example, when performing FIR filtering, the address generation unit will generate a series of circular addressing sequences for obtaining input data and filter coefficients; the multiplier unit and the accumulator unit form a multiply-accumulate (MAC) structure to perform a dot product operation on the input data and coefficients; the high-precision part of the arithmetic logic unit performs scaling, saturation, and rounding processing on the accumulated result to make the output result within an appropriate range. When performing FFT, the address generation unit will use special bit-reversal and stride access patterns, combined with complex multiplication and butterfly operations, to efficiently complete the frequency-domain transformation.

[0045] This embodiment makes full use of the advantages of hardware acceleration. Through a dedicated storage structure, a flexible address generation mechanism, high-precision arithmetic units, and intelligent control logic, it realizes the efficient execution of various audio processing algorithms. Compared with the software implementation of general-purpose processors, this audio accelerator has significant advantages in terms of processing efficiency, real-time performance, and power consumption; compared with traditional hardware accelerators, this embodiment provides better flexibility and scalability through modular design and programmable control, and can adapt to various audio processing requirements.

[0046] In summary, an audio accelerator and an audio processing method proposed by the present invention have the following advantages: Through the settings of the data storage unit, the address generation unit, the data operation unit, and the control unit, a dedicated accelerator structure for audio processing is formed, which can effectively solve the problem that it is difficult to balance flexibility and efficiency in existing audio processing systems. This device can support a variety of audio processing algorithms, while maintaining the high efficiency of hardware acceleration and significantly improving the real-time processing ability of audio data, and is especially suitable for resource-constrained embedded devices.

[0047] The 64-bit data bit width and flexible access mode of the data storage unit can meet the high data throughput requirements in audio processing; the multiple address registers and rich update mechanism of the address generation unit support complex circular addressing and strided access modes, which can accelerate data access in audio algorithms; the data operation unit can meet the high-precision calculation requirements in audio processing by integrating a 72-bit precision extension mechanism and various operation modes.

[0048] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these changes and modifications.

Claims

1. An audio accelerator, characterized in that, Comprising: A data storage unit for storing audio data and intermediate calculation results; An address generation unit for generating and managing the storage addresses of audio data, the address generation unit including address update logic that supports circular addressing and strided access modes for data access in audio processing algorithms; A data operation unit for performing calculation processing on audio data, the data operation unit including a multiplier unit with 32-bit input channels and a precision extension mechanism and an arithmetic logic unit for performing saturation processing and rounding operations; And A control unit for coordinating the data flow and processing flow between the units.

2. The audio accelerator according to claim 1, wherein The data storage unit includes: An SRAM memory with a 64-bit data bit width and a 128-row storage capacity; And a data access controller for supporting 64-bit full data access and 32-bit partial data access.

3. The audio accelerator according to claim 1, characterized in that The address generation unit includes: Multiple address registers for storing the data addresses currently being processed; Address update logic that supports increment, decrement, offset, and circular operations of the address register values; and An address mapping structure for mapping logical addresses to physical storage units.

4. The audio accelerator according to claim 3, characterized in that, The multiple address registers include 8 of the 10-bit wide address registers for supporting circular addressing and strided access modes in audio processing.

5. The audio accelerator according to claim 1, characterized in that, The data operation unit includes: A multiplier unit with 32-bit input channels and a 72-bit precision extension mechanism, performing multiple operation modes including independent multiplication operations, multiply-accumulate operations, and multiply-left-shift-accumulate operations after multiplication; An accumulator unit for performing accumulation operations; An arithmetic logic unit including a high-precision operation part and a standard-precision operation part; and A bit width conversion unit for performing data bit width conversion.

6. The audio accelerator according to claim 5, wherein, The high-precision operation part includes a 72-bit data processing circuit for implementing at least one of right shift, saturation processing, rounding, and extreme value selection operations; the standard-precision operation part includes a 32-bit data processing circuit for implementing at least one of bidirectional shift, arithmetic operations, and comparison operations.

7. The audio accelerator according to claim 5, characterized in that, The control unit includes: An instruction decoder for parsing and executing audio processing instructions; A data flow controller for managing the data transfer paths between the units; and A parallel execution control circuit for enabling the simultaneous operation of the multiplier unit and the arithmetic logic unit.

8. An audio processing method, using the audio accelerator as described in any one of claims 1-7, characterized in that, Specifically including the following: Generating an address sequence through the address generation unit and loading the audio data into the data storage unit; Processing and operating on the audio data using the data operation unit; and Outputting the processed audio data from the data storage unit.

9. The audio processing method according to claim 8, wherein The processing and operating on the audio data using the data operation unit specifically includes: Performing finite impulse response filtering or infinite impulse response filtering on the audio data based on the multiplier unit and the accumulator unit; Performing a fast Fourier transform on the audio data based on the circular addressing and strided access functions of the address generation unit; and Performing frequency response adjustment on the audio data based on the high-precision operation part and the standard-precision operation part of the arithmetic logic unit.

10. The audio processing method according to claim 9, wherein During the processing of performing filtering, transformation, and adjustment, specifically including: A parallel execution control circuit of a control unit simultaneously executes different instructions of a multiplier unit and an arithmetic logic unit; An address update logic of the address generation unit generates an address of the next batch of processed data; and A high-precision operation part of the arithmetic logic unit performs saturation and rounding operations.

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