Binary translation method, translator, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides a binary translation method, a translator, electronic equipment and a readable storage medium, and the method comprises the steps: when a direct jump instruction in a first code block is translated, if it is determined that a jump target has a cross-page condition, recording jump target cross-page information, the jump target cross-page information being used for indicating a cross-page type; executing a target link strategy on the first translation code block and the second translation code block according to the jump target cross-page information; the target link strategy is used for judging whether the direct jump instruction meets an optimization condition or not according to a cross-page type indicated by the jump target cross-page information; and if the optimization condition is met, establishing a direct jump link for the first translation code block and the second translation code block. According to the embodiment of the invention, on the basis of ensuring the correct execution, the optimizable condition when the target page is skipped is identified, the link optimization operation is further executed, the code block search operation in the program running process is reduced, and the program running efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and particularly to a binary translation method, a translator, an electronic device, and a readable storage medium. Background Art

[0002] Binary translation can convert binary code of one ISA (Instruction Set Architecture) into binary code of another instruction set architecture. Through binary translation technology, an application program of one ISA (source architecture) can run on another ISA (target architecture).

[0003] Generally, the client is used to represent the platform to which the program to be emulated belongs, and the host is used to represent the platform on which the binary translation system runs, that is, the binary translation system can emulate and run the client program on the host. According to the level where the emulated program is located, it can be classified into user-level binary translation and system-level binary translation. User-level binary translation supports running client application programs, and system-level binary translation supports running a complete client operating system, so as to realize the running of any client application program.

[0004] For direct jump instructions, since the jump target is always determined, code block chaining technology can be used for translation optimization. By pre-generating the direct jump path between translation code blocks, it is possible to directly jump from one translation code block to another translation code block to continue execution, avoiding repeated search and translation overhead, and improving execution efficiency.

[0005] However, in system-level binary translation, it is necessary to simulate the dynamic address mapping of the client operating system (such as the real-time conversion from virtual address to physical address). When jumping across pages, the physical mapping of the target address may have changed, which will cause the originally linked translation block code to point to the wrong target, resulting in semantic errors or crashes. Therefore, code block chaining technology is usually not used for translation optimization when jumping across pages, sacrificing a certain amount of performance to ensure correctness. Summary of the Invention

[0006] In view of the above problems, embodiments of the present invention are proposed to provide a binary translation method that can overcome the above problems or at least partially solve the above problems. On the basis of ensuring correct execution, it can identify the optimizable situations when the jump target crosses pages, and then further perform optimization operations, further reducing the search operation of code blocks during the program running process, and improving the program running efficiency.

[0007] Correspondingly, embodiments of the present invention also provide a binary translator, an electronic device, and a computer program product to ensure the implementation and application of the above method.

[0008] In a first aspect, an embodiment of the present invention discloses a binary translation method, which is applied to a system-level binary translator. The method includes: When translating a direct jump instruction in a first code block, if it is determined that the jump target has a cross-page situation, record the cross-page information of the jump target; the cross-page information of the jump target is used to indicate the cross-page type; the direct jump instruction is to jump to a second code block; According to the recorded cross-page information of the jump target, execute a target linking strategy on the first translated code block and the second translated code block; the first translated code block is the code block after translating the first code block, and the second translated code block is the code block after translating the second code block; the target linking strategy is used to determine whether the direct jump instruction meets the optimization condition according to the cross-page type indicated by the cross-page information of the jump target; If it is determined that the direct jump instruction meets the optimization condition, establish a direct jump link between the first translated code block and the second translated code block.

[0009] In a second aspect, an embodiment of the present invention discloses a system-level binary translator. The system-level binary translator includes: An information recording module, configured to record the cross-page information of the jump target when translating a direct jump instruction in a first code block, if it is determined that the jump target has a cross-page situation; the cross-page information of the jump target is used to indicate the cross-page type; the direct jump instruction is to jump to a second code block; A link detection module, configured to execute a target linking strategy on the first translated code block and the second translated code block according to the recorded cross-page information of the jump target; the first translated code block is the code block after translating the first code block, and the second translated code block is the code block after translating the second code block; the target linking strategy is used to determine whether the direct jump instruction meets the optimization condition according to the cross-page type indicated by the cross-page information of the jump target; A link optimization module, configured to establish a direct jump link between the first translated code block and the second translated code block if it is determined that the direct jump instruction meets the optimization condition.

[0010] In a third aspect, an embodiment of the present invention discloses an electronic device, including: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete communication with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction causes the processor to execute the steps of the binary translation method as described in any one of the foregoing.

[0011] Fourthly, an embodiment of the present invention discloses a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the binary translation method described in any one of the foregoing can be implemented.

[0012] Fifthly, an embodiment of the present invention discloses a computer program product, including a computer program, and when the computer program is executed by a processor, the steps of the binary translation method described in any one of the foregoing are implemented.

[0013] The embodiments of the present invention have the following advantages: When the direct jump instruction in the first code block is translated in the embodiment of the present invention, it is judged whether there is a cross-page situation for the jump target. If it is determined that there is a cross-page situation for the jump target, the jump target cross-page information is recorded, and the jump target cross-page information is used to indicate the cross-page type. Thus, in the linking stage, according to the jump target cross-page information recorded in the translation stage, a target linking strategy is executed on the first translated code block and the second translated code block. The target linking strategy is used to judge whether the direct jump instruction meets the optimization condition according to the cross-page type indicated by the jump target cross-page information. When it is determined that the direct jump instruction meets the optimization condition, the code block linking technology can be used to execute the optimization operation to establish a direct jump link between the first translated code block and the second translated code block. Through the cooperation of the translation stage and the linking stage, the embodiments of the present invention identify different cross-page jump situations and perform targeted processing to efficiently implement jump linking, rather than completely abandoning the code block linking optimization operation when there is a cross-page situation for the jump target. On the basis of ensuring correct execution, the optimizable situations when the jump target is cross-page are identified, and then the optimization operation is further executed, further reducing the search operation of code blocks during the program running process and improving the program running efficiency. Description of the Drawings

[0014] Figure 1 is a flowchart of the steps of an embodiment of a binary translation method of the present invention; Figure 2 is a schematic flowchart of executing a target linking strategy according to jump target cross-page information of the present invention; Figure 3 is a schematic flowchart of executing a first detection operation of the present invention; Figure 4 is a schematic flowchart of executing a second detection operation of the present invention; Figure 5 is a schematic diagram of dynamic detection through a preset detection module of the present invention; Figure 6 is a structural block diagram of an embodiment of a system-level binary translator of the present invention; Figure 7It is a schematic structural diagram of an electronic device provided by an embodiment of the present invention. Detailed implementation manners

[0015] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation manners.

[0016] The terms "first", "second", etc. in the description and claims of the present invention are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are usually of the same category, and do not limit the number of objects. For example, the first object can be one or more. In addition, the term "and / or" in the description and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after. In the embodiments of the present invention, the term "plurality" refers to two or more, and other quantifiers are similar.

[0017] First, some concepts involved in the embodiments of the present invention will be explained.

[0018] A code block refers to a continuous sequence of instructions (composed of guest instructions) extracted from the executable binary code of a guest program. It is the basic processing unit of binary translation. A code block is also called a basic block, which has only one entry (the entry is the first instruction) and one exit (the exit is the last instruction), and there will be no jump instructions in the middle. Except for the last instruction (such as a jump instruction, a call instruction, a return instruction), other instructions are executed sequentially, without jumping out or being jumped in.

[0019] A translated code block refers to a code block after binary translation, that is, the guest instructions in the code block are translated into host instructions. The translated code blocks are usually cached in the code cache for subsequent direct execution to avoid repeated translation.

[0020] A guest virtual address (GVA) is the virtual memory address used by a guest program, that is, the logical address of program code and data.

[0021] The Guest Physical Address (GPA) is the address obtained by the guest operating system through its Memory Management Unit (MMU) after converting the GVA. It is the "physical address" recognized by the guest operating system or the runtime environment. The guest operating system maps the GVA to the GPA, but these addresses are not real physical addresses and are further mapped to the host's address space by the binary translator or the virtualization layer.

[0022] A page is the basic unit of the operating system's memory management and is usually a memory block of a fixed size (such as 4KB). In the memory management of the operating system, to effectively manage memory, the memory (virtual memory or physical memory) is divided into pages of a fixed size.

[0023] A virtual page is a division unit of the virtual memory space and is mapped to a physical page through a page table.

[0024] A physical page is a division unit of the physical memory space and is the memory block that actually stores data.

[0025] The guest virtual address GVA consists of a Virtual Page Number (VPN) and an offset within the page. The virtual page number VPN is used to locate the virtual page, and the offset within the page is used to locate the specific byte within the virtual page.

[0026] The guest physical address GPA consists of a Page Frame Number (PFN) and an offset within the page. The page frame number PFN is used to locate the physical page, and the offset within the page (Offset) is used to locate the specific byte within the physical page, which is exactly the same as the offset within the virtual page (because the virtual page and the physical page are of the same size).

[0027] The guest virtual address GVA can obtain the corresponding page frame number PFN through page table mapping, and then combine it with the offset within the page to generate the GPA, realizing the conversion from virtual memory to physical memory.

[0028] A code block spanning pages means that the code block covers at least two virtual pages. For example, if part of the instructions of code block A are in one virtual page and another part of the instructions are in the next virtual page, then code block A is said to span pages. Here, "covering" means that the instruction address range of the code block crosses the boundaries of two or more virtual pages.

[0029] It should be noted that a code block spanning pages means that and only that the instruction sequence of the code block is continuously distributed in the virtual address space, and there is at least one instruction in the code block whose starting address is located in virtual page P1, and there is another instruction in the code block whose starting address is located in virtual page P2; or, a part of an instruction is located in virtual page P1 and another part is located in virtual page P2 (P1 ≠ P2).

[0030] For a certain code block, if the code block does not span pages, that is, all the client instructions of the code block are within the same virtual page, so the code block will only correspond to one client physical page. After translation, the translated code block corresponding to the code block is called an in-page translated code block. If the code block spans pages, such as the client instructions of the code block span two adjacent virtual pages, then the code block will correspond to two client physical pages. After translation, the translated code block corresponding to the code block is called an inter-page translated code block.

[0031] A direct jump instruction spanning pages means that the jump target address of the direct jump instruction is different from the virtual page where the direct jump instruction is located, and it is also called a cross-page jump. For example, if code block A ends with a direct jump instruction that is used to jump to code block B, and the jump from code block A to code block B spans pages, then it is said that the direct jump instruction spans pages.

[0032] It should be noted that the page spanning in the embodiments of the present invention refers to spanning virtual pages, and the pages in the following descriptions all refer to virtual pages.

[0033] In binary translation, when translating the direct jump instruction in the above-mentioned code block A, if code block B spans pages, or the direct jump instruction spans pages, then the optimization operation of the translated code block of code block A and the translated code block of code block B through the code block linking technology is discarded to ensure correctness at the expense of the translator performance.

[0034] To further improve the translator performance and the program running efficiency on the basis of ensuring correctness, in the embodiments of the present invention, for the above two cases of page spanning, it is further determined whether the optimization conditions are met, and the code block linking technology can be continued to be used for optimization on the premise of ensuring the correctness of cross-page jumps to further improve the translator performance.

[0035] Refer to Figure 1 , which shows a step flowchart of an embodiment of a binary translation method of the present invention. The method is applied to a system-level binary translator, and the method may include the following steps: Step 101, when translating the direct jump instruction in the first code block, if it is determined that there is a cross-page situation for the jump target, record the cross-page information of the jump target; the cross-page information of the jump target is used to indicate the type of page spanning; the direct jump instruction is to jump to the second code block; Step 102: Execute a target linking policy on the first translated code block and the second translated code block according to the recorded cross-page information of the jump target; the first translated code block is the code block after translating the first code block, and the second translated code block is the code block after translating the second code block; the target linking policy is used to determine whether the direct jump instruction meets the optimization condition according to the cross-page type indicated by the cross-page information of the jump target. Step 103: If it is determined that the direct jump instruction meets the optimization condition, establish a direct jump link between the first translated code block and the second translated code block.

[0036] In system-level binary translation, it is necessary to use both the client virtual address GVA and the actual address (client physical address GPA) to uniquely identify a code block.

[0037] For ease of description, in the embodiments of the present invention, the system-level binary translator is simply referred to as the translator. Before executing the first translated code block in a page, the translator will check whether the virtual-to-real address mapping relationship of this page is correct. The virtual-to-real address mapping relationship refers to the mapping relationship between the client virtual address GVA and the actual address. This is because the operating system may perform various operations on the memory, such as page replacement, memory allocation adjustment, etc., which may cause the virtual-to-real address mapping relationship to change. If the virtual-to-real address mapping relationship is correct (such as no change), it means that all address accesses within this page are predictable and secure. When executing the subsequent translated code blocks in this page, there is no need to repeatedly check the virtual-to-real address mapping relationship of this page.

[0038] In the embodiments of the present invention, the first code block refers to the code block ending with a direct jump instruction. The second code block refers to the target code block to which the direct jump instruction in the first code block jumps.

[0039] In the embodiments of the present invention, when translating to the direct jump instruction in the first code block, it is judged whether there are the following two cross-page situations for the jump target: one is whether the second code block crosses pages; the second is whether the direct jump instruction crosses pages. When it is determined that any of the above cross-page situations exists, record the corresponding cross-page information of the jump target, and the cross-page information of the jump target is used to indicate the cross-page type, such as the first cross-page situation and / or the second cross-page situation.

[0040] Exemplarily, assume that the end of code block A (the first code block) is a direct jump instruction that jumps to code block B (the second code block). When translating the direct jump instruction in the first code block, whether code block A crosses a page is known information, for the following reasons: Memory pages usually have a fixed size (such as 4KB), and the starting address is always aligned with the page size. When the translator parses code block A, it can record the starting address start_A of code block A and the size size_A of code block A, so it can calculate: the end address end_A of code block A = start_A + size_A. By comparing whether start_A and end_A are within the same page, it can be determined whether code block A crosses a page.

[0041] When translating the direct jump instruction in the first code block (such as code block A), the second code block (such as code block B) has not been translated yet. In the embodiments of the present invention, at this time, it is determined in advance whether the jump target crosses a page, and when it is determined that the jump target crosses a page, the cross-page information of the jump target is recorded. Thus, after code block A is translated, in addition to recording the known information of whether code block A crosses a page, the translator can also record the cross-page information of the jump target additionally, providing a basis for judgment for subsequent optimization operations during linking.

[0042] Further, the cross-page types may include at least one of the following: the second code block that the direct jump instruction jumps to crosses a page; the direct jump instruction crosses a page. Exemplarily, the cross-page information of the jump target can be recorded as follows: Information 1: The second code block crosses a page.

[0043] Information 2: The direct jump instruction crosses a page.

[0044] The embodiments of the present invention do not limit the way and position of recording the cross-page information of the jump target. For example, it can be recorded in the first translated code block or in the code cache, etc.

[0045] The embodiments of the present invention determine in advance whether the jump target crosses a page during the code block translation stage, and when it is determined that the jump target crosses a page, record the cross-page information of the jump target, providing a reference basis for subsequent optimization processing, so that the code block linking technology can be used for optimization processing in different cases during the linking stage.

[0046] According to the recorded cross-page information of the jump target, a target linking strategy can be executed on the first translated code block and the second translated code block; the first translated code block is the code block after the first code block is translated, and the second translated code block is the code block after the second code block is translated.

[0047] The target link strategy is used to determine whether the direct jump instruction meets the optimization condition according to the cross-page type indicated by the jump target cross-page information, and then determine whether the first translation code block and the second translation code block can be optimized using the code block linking technology, that is, whether it is possible to directly jump from the first translation code block to the second translation code block through the link instruction sequence. The link instruction sequence is used to jump to the starting address of the second translation code block in the code cache, without having to perform the operation of searching for the second translation code block in the code cache, which can reduce the code block search operation during program execution and improve program operation efficiency.

[0048] For example, the target link strategy can perform corresponding detection operations for two different types of cross-page jump targets to detect whether the virtual-to-real address mapping relationship of the page where the second code block is located is correct; if it is correct, the optimization operation can be performed; otherwise, the optimization operation is not performed. Thus, under the premise of ensuring correct execution, the situation that can be optimized when the jump target crosses pages can be further identified, so as to perform the optimization operation.

[0049] If it is determined that the direct jump instruction meets the optimization condition, the optimization operation can be performed. Specifically, a direct jump link can be established for the first translation code block and the second translation code block. The establishment of a direct jump link refers to directly jumping through the link instruction sequence without searching for the second translation code block in the code cache. If it is determined that the direct jump instruction does not meet the optimization condition, the optimization operation is not performed. Specifically, the execution state can be exited and the second translation code block to be executed can be searched for, and then the jump can be performed. The search for the second translation code block to be executed can include: searching for the second translation code block corresponding to the second code block in the code cache, if found, obtaining the starting address of the second translation code block in the code cache, and jumping to the starting address for execution; if not found, entering the translation state, translating the second code block, and saving the second translation code block corresponding to the second code block to the code cache after the translation is completed, and jumping to the starting address of the second translation code block in the code cache for execution.

[0050] The embodiment of the present invention identifies different situations of cross-page jumps through the cooperation of the translation stage and the linking stage, and performs targeted processing to efficiently implement jump links, instead of completely abandoning the code block link optimization operation when the jump target crosses pages. On the basis of ensuring correct execution, the situation that can be optimized when the jump target crosses pages is identified, so as to further perform optimization operations, further reduce the code block search operations during the program running process, and improve the program running efficiency.

[0051] In an optional embodiment of the present invention, the method may further include: Step S11: Determine the maximum instruction length of the client architecture; Step S12: If the distance between the jump target address of the direct jump instruction and the current page boundary is less than the maximum instruction length, determine that the second code block spans pages; Step S13: Record the jump target page-crossing information including: the second code block spans pages.

[0052] In the embodiment of the present invention, according to the maximum instruction length of the client architecture and the distance between the jump target address of the direct jump instruction and the current page boundary, it is determined whether the second code block spans pages.

[0053] In specific implementation, the maximum instruction lengths of different client architectures may be different. For example, the instructions of the x86 architecture are variable-length (1 to 15 bytes), that is, the maximum instruction length is 15 bytes, which means the maximum length of an instruction is 15 bytes. If the distance between the jump target address of the direct jump instruction and the current page boundary is less than the maximum instruction length, such as less than 15 bytes, its opcode or operand may extend to the next page. As a result, the second code block is split into two parts by the page boundary: the first part is at the end of the current page, and the second part is at the beginning of the next page. Therefore, it can be determined that the second code block spans pages, and the jump target page-crossing information can be recorded including: the second code block spans pages.

[0054] In an alternative embodiment of the present invention, the method may further include: Step S21: Obtain the address of the direct jump instruction according to the current program counter value; Step S22: If the address of the direct jump instruction and the client virtual address of the second code block are not in the same page, determine that the direct jump instruction spans pages; Step S23: Record the jump target page-crossing information including: the direct jump instruction spans pages.

[0055] The direct jump instruction spanning pages means that the jump target address of the direct jump instruction is different from the page where the direct jump instruction is located. For example, when jumping from code block A to code block B across pages, code block B and code block A are not in the same page.

[0056] In the embodiment of the present invention, by determining whether the address of the direct jump instruction (this address is the client virtual address) and the client virtual address of the second code block are in the same page (that is, whether they are in the same virtual page), it can be determined whether the direct jump instruction spans pages.

[0057] Specifically, according to the current program counter value, the address of the direct jump instruction can be obtained. The PC (Program Counter) is a register used to store the address of the instruction to be executed currently. In binary translation, the PC value usually refers to the guest virtual address (GVA). The current PC value represents the address of the instruction to be executed currently (such as the address of the direct jump instruction in code block A).

[0058] The jump target address represents the address to which the direct jump instruction jumps, that is, the GVA address of the second code block (such as code block B) (denoted as GVA_B for example).

[0059] Determining whether the direct jump instruction crosses pages is actually to compare whether the current PC (the address of the current instruction) and GVA_B (the jump target address) are in the same page. That is, to compare whether the address of the direct jump instruction and the guest virtual address of the second code block are in the same page. If the two are in the same page, the direct jump instruction does not cross pages; if the two are not in the same page, the direct jump instruction crosses pages.

[0060] Furthermore, since the first code block (such as code block A) itself may also have the situation of crossing pages, therefore, when determining whether the direct jump instruction crosses pages, all the pages covered by the first code block need to be compared with the jump target address (the guest virtual address of the second code block).

[0061] In the translation stage, the current PC value (that is, the GVA address of the direct jump instruction, denoted as GVA_A_end for example) and the GVA address of the second code block (such as code block B) (denoted as GVA_B for example) are known information that can be obtained. By comparing whether the pages where GVA_A_end and GVA_B are located are the same, it can be determined whether the direct jump instruction crosses pages.

[0062] Assume that the page where the GVA address (GVA_A_end) of the direct jump instruction is located is denoted as Page_PC, and the page where the GVA address (GVA_B) of the second code block is located is denoted as Page_B. By determining whether Page_PC and Page_B are the same page, it can be determined whether the direct jump instruction crosses pages. Specifically, if Page_PC and Page_B are the same page, it is determined that the direct jump instruction does not cross pages; otherwise, it is determined that the direct jump instruction crosses pages.

[0063] The first code block (such as code block A) crossing pages means that the first code block (such as code block A) covers at least two pages. In the embodiments of the present invention, the cases of crossing pages are all illustrated by taking covering two pages as an example. For the cases of covering more than three pages, the processing procedures are similar and can be referred to each other.

[0064] Assume that the first code block (such as code block A) covers two pages, that is, the instruction sequence included in the first code block (such as code block A) spans two adjacent pages, such as Page_A1 and Page_A2. If the direct jump instruction may be in Page_A1 or Page_A2, it is necessary to determine whether Page_A1 and Page_B are the same page, and determine whether Page_A2 and Page_B are the same page. If Page_B is the same page as Page_A1 or Page_A2, it is determined that the direct jump instruction does not cross pages; otherwise, it is determined that the direct jump instruction crosses pages.

[0065] It can be understood that if the first code block (such as code block A) crosses multiple pages, all involved pages need to be checked.

[0066] In the case where the jump target of the direct jump instruction in the first code block (such as code block A) crosses pages, this solution further determines whether the optimization condition is met in the case of cross-page. During the judgment process, in addition to judging the cross-page situation of the second code block (such as code block B) and the cross-page situation of the direct jump instruction, the cross-page situation of the first code block (such as code block A) is also combined for judgment, and it is subdivided for different situations, and then different detection operations are performed to minimize the cost of performing the detection operation as much as possible, improve the execution efficiency of detecting whether the optimization condition is met in the case of cross-page, and then improve the program running efficiency and improve the performance of the translator.

[0067] It should be noted that the embodiments of the present invention do not limit the method for judging whether the second code block crosses pages and whether the direct jump instruction crosses pages, and there can be different judgment methods according to different client architectures and translator implementations.

[0068] In an alternative embodiment of the present invention, the cross-page types include at least one of the following: the second code block to which the direct jump instruction jumps crosses pages; the direct jump instruction crosses pages; according to the recorded cross-page information of the jump target, the target linking strategy for the first translated code block and the second translated code block may include: Step S31: If the second code block crosses pages, perform a first detection operation, and determine whether the direct jump instruction meets the optimization condition according to the result of the first detection operation; Step S32: If the second code block does not cross pages and the direct jump instruction crosses pages, perform a second detection operation, and determine whether the direct jump instruction meets the optimization condition according to the result of the second detection operation; Step S33: If the second code block does not cross pages and the direct jump instruction does not cross pages, it is determined that the direct jump instruction meets the optimization condition.

[0069] Refer to Figure 2, which shows a schematic flow chart of the present invention for executing a target link policy according to jump target cross-page information. Figure 2 The shown process is executed in the stage of linking the first translation code block after the first code block is translated to obtain the first translation code block.

[0070] As Figure 2 shown, it is determined whether the second code block is cross-page according to the recorded jump target cross-page information. If the second code block is cross-page, a first detection operation is executed. If the second code block is not cross-page, but the direct jump instruction is cross-page, a second detection operation is executed. If the second code block is not cross-page and the direct jump instruction is also not cross-page, it can be directly determined that the direct jump instruction meets the optimization condition, so that a direct jump link (direct link) can be established for direct jump.

[0071] Among them, in the case where the second code block is cross-page, it means that the second code block covers at least two pages. The first detection operation is used to detect whether the virtual-to-physical address mapping relationships of the multiple pages covered by the second code block are correct. According to the result of the first detection operation, it can be determined whether the direct jump instruction meets the optimization condition.

[0072] It can be understood that the single page, two pages, and multiple pages mentioned in the embodiments of the present invention refer to single virtual page, two virtual pages, and multiple virtual pages.

[0073] In the case where the second code block is not cross-page, but the direct jump instruction is cross-page, the second code block only covers a single page. The second detection operation is used to detect whether the virtual-to-physical address mapping relationship of the single page covered by the second code block is correct. According to the result of the second detection operation, it can be determined whether the direct jump instruction meets the optimization condition.

[0074] If the jump target cross-page information recorded in the translation stage is empty, it means that there is no cross-page situation for the jump target, that is, the second code block is not cross-page and the direct jump instruction is also not cross-page. At this time, it can be directly determined that the direct jump instruction meets the optimization condition without any detection operation, which can greatly improve the execution efficiency.

[0075] In an optional embodiment of the present invention, the execution of the first detection operation and determining whether the direct jump instruction meets the optimization condition according to the result of the first detection operation may include: Step S41: Determine whether all the pages covered by the second code block are the same as all the pages covered by the first code block; Step S42: If all the pages covered by the second code block are the same as all the pages covered by the first code block, determine that the direct jump instruction meets the optimization condition; Step S43: If there are different pages among all the pages covered by the second code block and all the pages covered by the first code block, perform dynamic detection on the different pages among all the pages covered by the second code block. When the different pages pass the dynamic detection, it is determined that the direct jump instruction meets the optimization condition; otherwise, it is determined that the direct jump instruction does not meet the optimization condition.

[0076] Refer to Figure 3 , which shows a schematic flowchart of the first detection operation executed in an embodiment of the present invention. Figure 3 The shown process is executed when it is determined that the second code block spans pages during the stage of linking the first translation code block. In this case, since the second code block covers at least two pages, it is possible to determine that the direct jump instruction meets the optimization condition only when the virtual-to-physical address mapping relationships of all the pages covered by the second code block are correct.

[0077] As Figure 3 shown, taking the second code block covering two pages as an example, determine whether the two pages covered by the second code block are the same as all the pages covered by the first code block.

[0078] Further, according to whether the first code block spans pages, there are the following two cases for step S41: The first case is that the first code block spans pages (taking two pages as an example), then determine whether the two pages covered by the second code block are the same as the two pages covered by the first code block. The second case is that the first code block does not span pages, then determine whether each of the two pages covered by the second code block is the same as one page covered by the first code block.

[0079] Assume that the two pages covered by the first code block are P1 and P2, and the two pages covered by the second code block are also P1 and P2. That is, all the pages covered by the second code block are the same as all the pages covered by the first code block, then it is determined that the direct jump instruction meets the optimization condition and can be directly linked.

[0080] Assume that the two pages covered by the first code block are P1 and P2, and the two pages covered by the second code block are P2 and P3. That is, there are different pages (such as P3) among all the pages covered by the second code block and all the pages covered by the first code block, then it is necessary to perform dynamic detection on this different page (P3). When the different page (P3) passes the dynamic detection, it is determined that the direct jump instruction meets the optimization condition; otherwise, it is determined that the direct jump instruction does not meet the optimization condition. Among them, the dynamic detection is used to check whether the virtual-to-physical address mapping relationship of this page is correct. If it is correct, it passes the dynamic detection; otherwise, it fails the dynamic detection.

[0081] Similarly, assume that the two pages covered by the first code block are P1 and P2, and the two pages covered by the second code block are P0 and P1. That is, if there are different pages (such as P0) among all the pages covered by the second code block and all the pages covered by the first code block, then dynamic detection needs to be performed on this different page (P0). When this different page (P0) passes the dynamic detection, it is determined that the direct jump instruction meets the optimization condition; otherwise, it is determined that the direct jump instruction does not meet the optimization condition.

[0082] Assume that the two pages covered by the first code block are P1 and P2, and the two pages covered by the second code block are P3 and P4. That is, if there are different pages (such as P3 and P4) among all the pages covered by the second code block and all the pages covered by the first code block, then dynamic detection needs to be performed on this different page (P3) and this different page (P4) respectively. When this different page (P3) and this different page (P4) both pass the dynamic detection, it is determined that the direct jump instruction meets the optimization condition; otherwise, it is determined that the direct jump instruction does not meet the optimization condition.

[0083] It should be noted that in binary translation, when executing the direct jump instruction in the first code block, since the first code block has been executed, it means that the page where the first code block is located has passed the dynamic detection. At this time, it is necessary to jump to the second code block. If there are different pages between the pages covered by the second code block and the pages covered by the first code block, then these different pages have not been dynamically detected yet. Therefore, only dynamic detection needs to be performed on each different page respectively. When all different pages pass the dynamic detection, it is determined that the direct jump instruction meets the optimization condition. If there is one different page that does not pass the dynamic detection, it is determined that the direct jump instruction does not meet the optimization condition.

[0084] It should be noted that in the above example, P0, P1, P2, P3, and P4 are 5 consecutive pages in terms of address, and P0 < P1, and so on.

[0085] In an alternative embodiment of the present invention, the performing the second detection operation and determining whether the direct jump instruction meets the optimization condition according to the result of the second detection operation may include: Step S51: Determine whether there is a same page between a single page covered by the second code block and all the pages covered by the first code block; Step S52: If there is a same page between a single page covered by the second code block and all the pages covered by the first code block, it is determined that the direct jump instruction meets the optimization condition; Step S53: If there is no same page between the single page covered by the second code block and all the pages covered by the first code block, perform dynamic detection on the single page covered by the second translation code block. When the single page passes the dynamic detection, it is determined that the direct jump instruction meets the optimization condition; otherwise, it is determined that the direct jump instruction does not meet the optimization condition.

[0086] Refer to Figure 4 , which shows a schematic flowchart of the second detection operation executed in an embodiment of the present invention. Figure 4 The shown process is executed when, in the stage of linking the first translation code block, it is determined that the second code block does not span pages, but the direct jump instruction spans pages. In this case, the second code block covers a single page. Therefore, when ensuring the correct virtual-to-physical address mapping relationship of the single page covered by the second code block, it can be determined that the direct jump instruction meets the optimization condition.

[0087] As Figure 4 shown, it is judged whether there is a same page between the single page covered by the second code block and all the pages covered by the first code block. It can be understood that for the first code block, there may be a case of spanning pages or not spanning pages, and the first code block may cover a single page or multiple pages (taking two pages as an example). If there is a same page between the single page covered by the second code block and all the pages covered by the first code block, it can be directly determined that the direct jump instruction meets the optimization condition without performing the detection operation. Since the page where the first code block is located has passed the dynamic detection at this time, and the second code block only covers a single page, if there is a same page between the single page covered by the second code block and all the pages covered by the first code block, it means that the single page covered by the second code block has also passed the dynamic detection and there is no need for further dynamic detection.

[0088] If there is no same page between the single page covered by the second code block and all the pages covered by the first code block, it is necessary to perform dynamic detection on the single page covered by the second translation code block. When the single page passes the dynamic detection, it is determined that the direct jump instruction meets the optimization condition; otherwise, it is determined that the direct jump instruction does not meet the optimization condition.

[0089] In an alternative embodiment of the present invention, the method may further include: Insert a first instruction sequence and a second instruction sequence at the end of the first translation code block; the first instruction sequence is used to execute the target link policy, and when it is determined that the direct jump instruction meets the optimization condition, jump to the second instruction sequence, and when it is determined that the direct jump instruction does not meet the optimization condition, exit the execution state and search for a second translation code block to be executed; the second instruction sequence is used to establish a direct jump link between the first translation code block and the second translation code block.

[0090] Exemplarily, when a system-level binary translator translates a direct jump instruction in a first code block, it translates the direct jump instruction into a target host instruction sequence, and the target host instruction sequence is used to find a second translation code block (to be executed) to which to jump according to the target jump address of the direct jump instruction, and perform the jump.

[0091] In an embodiment of the present invention, a first instruction sequence and a second instruction sequence are inserted before the target host instruction sequence, and the first instruction sequence is used to execute the target link policy for the first translation code block and the second translation code block according to the recorded cross-page information of the jump target, and when it is determined that the direct jump instruction meets the optimization condition, jump to the second instruction sequence, and when it is determined that the direct jump instruction does not meet the optimization condition, jump to the above target host instruction sequence, exit the execution state and enter the code block search phase, and search for a second translation code block to be executed.

[0092] Both the first instruction sequence and the second instruction sequence are instruction sequences of the host architecture.

[0093] The second instruction sequence can initially be a NOP (No Operation) instruction sequence of the host architecture. When the CPU executes the NOP instruction sequence, it will not have any substantial impact on registers, memory, or program status, but simply consume one or more clock cycles and then continue to execute the next instruction.

[0094] During the execution of the target link policy, if it is determined that the direct jump instruction meets the optimization condition, the NOP instruction sequence is replaced with a link instruction sequence, and thus it is possible to directly jump to the starting address of the second translation code block in the code cache through the link instruction sequence. If it is determined that the direct jump instruction does not meet the optimization condition, the NOP instruction sequence is not replaced, and the original target host instruction sequence is continued to be executed, thereby exiting the execution state and searching for a second translation code block to be executed, and then performing the jump.

[0095] In the embodiment of the present invention, the cross-page situation of the jump target of the direct jump instruction is judged in advance during the translation stage, the cross-page information of the jump target is recorded, and preprocessing is performed during the translation stage, such as inserting the first instruction sequence and the second instruction sequence, to prepare for the optimization processing in the linking stage. In the linking stage, the target linking policy is executed. According to the cross-page information of the jump target recorded in the translation stage, different detection operations are performed for different cross-page situations to judge whether the direct jump instruction meets the optimization conditions when the jump target has cross-page. In the case of meeting the optimization conditions, the optimization operation can still be executed.

[0096] It should be noted that the embodiment of the present invention does not limit the method of dynamic detection. Exemplarily, when each code block is translated, the GVA address of the code block can be converted to obtain the corresponding guest physical address (denoted as GPA1 for example), and the guest physical address GPA1 of the code block during translation is recorded. When dynamic detection is performed in the linking stage, the GVA address of the second code block can be input into the preset detection module. The detection module converts the GVA address of the second code block to obtain the corresponding guest physical address (denoted as GPA2 for example), and compares the guest physical address GPA2 obtained by real-time conversion with the guest physical address GPA1 of the second code block recorded during translation. If the two are the same, it indicates that the virtual-to-real address mapping relationship of the page where the second code block is located is correct, and the dynamic detection passes; otherwise, it indicates that the virtual-to-real address mapping relationship of the page where the second code block is located is incorrect, and the dynamic detection fails.

[0097] Refer to Figure 5 , which shows a schematic diagram of dynamic detection by the preset detection module in the embodiment of the present invention. The input of the detection module can be the guest virtual address (GVA) of the page to be detected of the second code block. The guest virtual address of the page to be detected may include the start address (denoted as GVA_start for example) and the end address (denoted as GVA_end for example) of the page to be detected. For example, when dynamic detection needs to be performed on two pages P3 and P4 covered by the second code block, P3 and P4 are the pages to be detected.

[0098] During the translation stage of the code block, the guest virtual address (GVA) of the code block can be converted to obtain the corresponding guest physical address (GPA1), and the guest physical address (GPA1) corresponding to the guest virtual address (GVA) is recorded. Specifically, the start address (GVA_start) and the end address (GVA_end) of the guest virtual address of the page covered by the code block are respectively converted to obtain the start address (GPA_start1) and the end address (GPA_end1) of the corresponding guest physical address.

[0099] During the link phase of the code block, the starting address GVA_start and the ending address GVA_end of the page to be detected are input into the preset module. The detection module converts the received starting address GVA_start and ending address GVA_end of the page to be detected, and can obtain the starting address (denoted as GPA_start2 for example) and the ending address (denoted as GPA_end2 for example) of the corresponding client physical address. Compare the GPA_start2 calculated in real time with the GPA_start1 recorded during translation, and compare the GPA_end2 calculated in real time with the GPA_end1 recorded during translation. If the comparisons are all the same, it indicates that the virtual-to-physical address mapping relationship of the page to be detected is correct, and the page to be detected passes the dynamic detection; otherwise, it indicates that the virtual-to-physical address mapping relationship of the page to be detected is incorrect, and the page to be detected fails the dynamic detection.

[0100] Furthermore, the detection module may include a multi-page detection module and a single-page detection module. The multi-page detection module is used to perform dynamic detection on multiple pages covered by the second code block. The single-page detection module is used to perform dynamic detection on a single page covered by the second code block.

[0101] For example, the pages covered by the second code block include P3 and P4. If dynamic detection needs to be performed on both P3 and P4, after inputting the GVA address range of the second code block into the multi-page detection module in the detection module, the multi-page detection module determines the corresponding starting address ranges of P3 and P4 according to the GVA address range of the second code block, converts the corresponding GVA starting address ranges of P3 and P4 to obtain the corresponding GPA starting address ranges of P3 and P4, and compares them with the GPA starting address ranges recorded during translation. If they are all consistent, the dynamic detection passes, ensuring that the mappings of both P3 and P4 are correct; otherwise, the dynamic detection fails.

[0102] In summary, when the embodiment of the present invention translates the direct jump instruction in the first code block, it determines whether there is a cross-page situation for the jump target. If it is determined that there is a cross-page situation for the jump target, the cross-page information of the jump target is recorded, and the cross-page information of the jump target is used to indicate the cross-page type. Thus, in the linking phase, according to the cross-page information of the jump target recorded in the translation phase, the target linking strategy can be executed on the first translation code block and the second translation code block. The target linking strategy is used to determine whether the direct jump instruction meets the optimization condition according to the cross-page type indicated by the cross-page information of the jump target. When it is determined that the direct jump instruction meets the optimization condition, the code block linking technology can be used to execute the optimization operation to establish a direct jump link between the first translation code block and the second translation code block. By the cooperation of the translation phase and the linking phase, the embodiment of the present invention identifies different cross-page jump situations and processes them specifically to efficiently implement the jump link, rather than completely abandoning the code block linking optimization operation when there is a cross-page situation for the jump target. On the basis of ensuring correct execution, the optimizable situation when the jump target is cross-page is identified, and then the optimization operation is further executed to further reduce the search operation of the code block during the program running process and improve the program running efficiency.

[0103] In addition, in the translation phase of the first code block, the embodiment of the present invention determines in advance whether there is a cross-page situation for the jump target and records the cross-page information of the jump target, providing a judgment basis for the subsequent linking phase to execute the optimization operation. In the linking phase of the first code block, different detection operations are executed according to different cross-page situations of the jump target to determine whether the direct jump instruction meets the optimization condition with the minimum dynamic detection cost, which helps to improve the system performance.

[0104] It should be noted that for the method embodiments, for simplicity of description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the embodiments of the present invention are not limited by the described action sequence, because according to the embodiments of the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0105] Referring to Figure 6 , a structural block diagram of an embodiment of a system-level binary translator of the present invention is shown. The system-level binary translator may include: An information recording module 601, configured to record the cross-page information of the jump target when translating the direct jump instruction in the first code block. If it is determined that there is a cross-page situation for the jump target, the cross-page information of the jump target is used to indicate the cross-page type. The direct jump instruction is to jump to the second code block; The link detection module 602 is configured to execute a target link policy on the first translated code block and the second translated code block according to the recorded cross-page information of the jump target; the first translated code block is the code block after translating the first code block, and the second translated code block is the code block after translating the second code block; the target link policy is used to determine whether the direct jump instruction meets the optimization condition according to the cross-page type indicated by the cross-page information of the jump target. The link optimization module 603 is configured to establish a direct jump link between the first translated code block and the second translated code block if it is determined that the direct jump instruction meets the optimization condition.

[0106] Optionally, the cross-page type includes at least one of the following: the second code block cross-page to which the direct jump instruction is to jump; the direct jump instruction cross-page; the link detection module includes: The first detection sub-module is configured to perform a first detection operation if the second code block is cross-page, and determine whether the direct jump instruction meets the optimization condition according to the result of the first detection operation. The second detection sub-module is configured to perform a second detection operation if the second code block is not cross-page and the direct jump instruction is cross-page, and determine whether the direct jump instruction meets the optimization condition according to the result of the second detection operation. The third detection sub-module is configured to determine that the direct jump instruction meets the optimization condition if the second code block is not cross-page and the direct jump instruction is not cross-page.

[0107] Optionally, the first detection sub-module includes: The first judgment unit is configured to judge whether all the pages covered by the second code block are the same as all the pages covered by the first code block. The first determination unit is configured to determine that the direct jump instruction meets the optimization condition if all the pages covered by the second code block are the same as all the pages covered by the first code block. The first detection unit is configured to perform dynamic detection on the different pages among all the pages covered by the second code block if there are different pages among all the pages covered by the second code block and all the pages covered by the first code block, and determine that the direct jump instruction meets the optimization condition if the different pages pass the dynamic detection, otherwise determine that the direct jump instruction does not meet the optimization condition.

[0108] Optionally, the second detection sub-module includes: The second judgment unit is configured to judge whether there are the same pages among the single page covered by the second code block and all the pages covered by the first code block. A second determination unit, configured to determine that the direct jump instruction meets the optimization condition if there is a same page among the single page covered by the second code block and all the pages covered by the first code block; A second detection unit, configured to, if there is no same page among the single page covered by the second code block and all the pages covered by the first code block, perform dynamic detection on the single page covered by the second translated code block, and determine that the direct jump instruction meets the optimization condition when the single page passes the dynamic detection, otherwise determine that the direct jump instruction does not meet the optimization condition.

[0109] Optionally, the system-level binary translator further includes: A length determination module, configured to determine the maximum instruction length of the client architecture; A first information determination module, configured to determine that the second code block spans pages if the distance between the jump target address of the direct jump instruction and the current page boundary is less than the maximum instruction length; A first information recording module, configured to record the jump target cross-page information including: the second code block spans pages.

[0110] Optionally, the system-level binary translator further includes: An address acquisition module, configured to acquire the address of the direct jump instruction according to the current program counter value; A second information determination module, configured to determine that the direct jump instruction spans pages if the address of the direct jump instruction and the client virtual address of the second code block are not in the same page; A second information recording module, configured to record the jump target cross-page information including: the direct jump instruction spans pages.

[0111] Optionally, the system-level binary translator further includes: An instruction insertion module, configured to insert a first instruction sequence and a second instruction sequence at the end of the first translated code block; the first instruction sequence is used to execute the target link policy, and jump to the second instruction sequence when it is determined that the direct jump instruction meets the optimization condition, and exit the execution state and search for the second translated code block to be executed when it is determined that the direct jump instruction does not meet the optimization condition; the second instruction sequence is used to establish a direct jump link between the first translated code block and the second translated code block.

[0112] Optionally, the system-level binary translator further includes: An exit search module, configured to exit the execution state and search for the second translated code block to be executed if it is determined that the direct jump instruction does not meet the optimization condition.

[0113] The system-level binary translator provided by the embodiments of the present invention determines whether there is a cross-page situation for the jump target when translating a direct jump instruction in the first code block. If it is determined that there is a cross-page situation for the jump target, the cross-page information of the jump target is recorded, and the cross-page information of the jump target is used to indicate the type of cross-page. Thus, in the linking phase, according to the cross-page information of the jump target recorded in the translation phase, a target linking strategy can be executed on the first translated code block and the second translated code block. The target linking strategy is used to determine whether the direct jump instruction meets the optimization condition according to the type of cross-page indicated by the cross-page information of the jump target. When it is determined that the direct jump instruction meets the optimization condition, the code block linking technology can be used to execute the optimization operation to establish a direct jump link between the first translated code block and the second translated code block. By the cooperation of the translation phase and the linking phase, the embodiments of the present invention identify different situations of cross-page jumps and perform targeted processing to efficiently implement jump linking, rather than completely abandoning the code block linking optimization operation when there is a cross-page situation for the jump target. On the basis of ensuring correct execution, the optimizable situations when the jump target is cross-page are identified, and further optimization operations are performed to further reduce the search operation of code blocks during the program running process and improve the program running efficiency.

[0114] In addition, the system-level binary translator provided by the embodiments of the present invention determines in advance whether there is a cross-page situation for the jump target during the translation phase of the first code block, and records the cross-page information of the jump target, providing a judgment basis for the subsequent linking phase to execute the optimization operation. In the linking phase of the first code block, different detection operations are performed according to different cross-page situations of the jump target to determine whether the direct jump instruction meets the optimization condition at the minimum dynamic detection cost, which helps to improve the system performance.

[0115] For the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple. For related parts, refer to the partial description of the method embodiments.

[0116] Refer to Figure 7 , which is a schematic structural diagram of an electronic device provided by the embodiments of the present invention. As Figure 7 shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete mutual communication through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction causes the processor to execute the steps of the binary translation method in the foregoing embodiments.

[0117] The embodiments of the present invention provide a non-transitory computer-readable storage medium. When the instructions in the storage medium are executed by a program or a processor of a terminal, the terminal can execute the steps of the binary translation method in the foregoing embodiments. Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the embodiments, they can be referred to each other.

[0118] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a binary translator, or a computer program product. Therefore, the embodiments of the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0119] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal devices generate a device for realizing the functions specified in one Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0120] These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing terminal devices to work in a predictive manner, so that the instructions stored in the computer-readable memory generate a manufactured product including an instruction device, and the instruction device realizes the functions specified in one Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0121] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal devices, so that a series of operation steps are executed on the computer or other programmable terminal devices to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable terminal devices provide steps for realizing the functions specified in one Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0122] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or terminal device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or terminal device comprising said element.

[0123] Specific examples are used in this article to illustrate the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A binary translation method, characterized in that, Applied to a system-level binary translator, the method includes: When translating a direct jump instruction in a first code block, if it is determined that the jump target has a cross-page situation, record the cross-page information of the jump target; the cross-page information of the jump target is used to indicate the cross-page type; the direct jump instruction is to jump to a second code block; According to the recorded cross-page information of the jump target, execute a target linking strategy on the first translated code block and the second translated code block; the first translated code block is the code block after translating the first code block, and the second translated code block is the code block after translating the second code block; the target linking strategy is used to determine whether the direct jump instruction meets the optimization condition according to the cross-page type indicated by the cross-page information of the jump target; If it is determined that the direct jump instruction meets the optimization condition, establish a direct jump link between the first translated code block and the second translated code block.

2. The method according to claim 1, wherein The cross-page type includes at least one of the following: the second code block that the direct jump instruction is to jump to is cross-page; the direct jump instruction is cross-page; The executing the target linking strategy on the first translated code block and the second translated code block according to the recorded cross-page information of the jump target includes: If the second code block is cross-page, perform a first detection operation, and determine whether the direct jump instruction meets the optimization condition according to the result of the first detection operation; If the second code block is not cross-page and the direct jump instruction is cross-page, perform a second detection operation, and determine whether the direct jump instruction meets the optimization condition according to the result of the second detection operation; If the second code block is not cross-page and the direct jump instruction is not cross-page, determine that the direct jump instruction meets the optimization condition.

3. The method according to claim 2, wherein The performing the first detection operation and determining whether the direct jump instruction meets the optimization condition according to the result of the first detection operation includes: Judge whether all pages covered by the second code block are the same as all pages covered by the first code block; If all pages covered by the second code block are the same as all pages covered by the first code block, determine that the direct jump instruction meets the optimization condition; If there are different pages among all pages covered by the second code block and all pages covered by the first code block, perform dynamic detection on the different pages among all pages covered by the second code block. If the different pages pass the dynamic detection, determine that the direct jump instruction meets the optimization condition, otherwise determine that the direct jump instruction does not meet the optimization condition.

4. The method according to claim 2, wherein The performing the second detection operation and determining whether the direct jump instruction meets the optimization condition according to the result of the second detection operation includes: Judge whether there is a same page between a single page covered by the second code block and all pages covered by the first code block; If there is a same page between a single page covered by the second code block and all pages covered by the first code block, determine that the direct jump instruction meets the optimization condition; If there is no same page between the single page covered by the second code block and all the pages covered by the first code block, perform dynamic detection on the single page covered by the second translated code block. If the single page passes the dynamic detection, determine that the direct jump instruction meets the optimization condition; otherwise, determine that the direct jump instruction does not meet the optimization condition.

5. The method according to any one of claims 1 to 4, characterized in that, The method further includes: Determine the maximum instruction length of the client architecture; If the distance between the jump target address of the direct jump instruction and the current page boundary is less than the maximum instruction length, determine that the second code block crosses pages; Record the jump target cross-page information including: the second code block crosses pages.

6. The method according to any one of claims 1 to 4, characterized in that, The method further includes: Obtain the address of the direct jump instruction according to the current program counter value; If the address of the direct jump instruction and the client virtual address of the second code block are not on the same page, determine that the direct jump instruction crosses pages; Record the jump target cross-page information including: the direct jump instruction crosses pages.

7. The method according to any one of claims 1 to 4, characterized in that The method further includes: Insert a first instruction sequence and a second instruction sequence at the end of the first translated code block; the first instruction sequence is used to execute the target link policy, and when it is determined that the direct jump instruction meets the optimization condition, jump to the second instruction sequence, and when it is determined that the direct jump instruction does not meet the optimization condition, exit the execution state and search for the second translated code block to be executed; the second instruction sequence is used to establish a direct jump link between the first translated code block and the second translated code block.

8. The method according to any one of claims 1 to 4, characterized in that, The method further includes: If it is determined that the direct jump instruction does not meet the optimization condition, exit the execution state and search for the second translated code block to be executed.

9. A system-level binary translator, characterized in that, The system-level binary translator includes: An information recording module, configured to record jump target cross-page information when translating to a direct jump instruction in the first code block. If it is determined that there is a cross-page situation for the jump target, the jump target cross-page information is used to indicate the cross-page type; the direct jump instruction is to jump to the second code block; A link detection module, configured to perform a target link policy on the first translated code block and the second translated code block according to the recorded jump target cross-page information; the first translated code block is the code block after translating the first code block, and the second translated code block is the code block after translating the second code block; the target link policy is used to determine whether the direct jump instruction meets the optimization condition according to the cross-page type indicated by the jump target cross-page information; A link optimization module, configured to establish a direct jump link between the first translated code block and the second translated code block if it is determined that the direct jump instruction meets the optimization condition.

10. The system-level binary translator according to claim 9, wherein The cross-page type includes at least one of the following: the second code block that the direct jump instruction is to jump to crosses pages; the direct jump instruction crosses pages; The link detection module includes: A first detection sub-module, configured to perform a first detection operation if the second code block crosses pages, and determine whether the direct jump instruction meets the optimization condition according to the result of the first detection operation; The second detection sub-module is used to perform a second detection operation if the second code block does not span pages and the direct jump instruction spans pages, and determine whether the direct jump instruction meets the optimization condition according to the result of the second detection operation; The third detection sub-module is used to determine that the direct jump instruction meets the optimization condition if the second code block does not span pages and the direct jump instruction does not span pages.

11. The system-level binary translator according to claim 10, characterized in that, The first detection sub-module includes: The first judgment unit is used to judge whether all the pages covered by the second code block are the same as all the pages covered by the first code block; The first determination unit is used to determine that the direct jump instruction meets the optimization condition if all the pages covered by the second code block are the same as all the pages covered by the first code block; The first detection unit is used to perform dynamic detection on the different pages among all the pages covered by the second code block if there are different pages among all the pages covered by the second code block and all the pages covered by the first code block. If the different pages pass the dynamic detection, it is determined that the direct jump instruction meets the optimization condition, otherwise it is determined that the direct jump instruction does not meet the optimization condition.

12. The system-level binary translator according to claim 10, wherein The second detection sub-module includes: The second judgment unit is used to judge whether there is a same page among the single page covered by the second code block and all the pages covered by the first code block; The second determination unit is used to determine that the direct jump instruction meets the optimization condition if there is a same page among the single page covered by the second code block and all the pages covered by the first code block; The second detection unit is used to perform dynamic detection on the single page covered by the second translated code block if there is no same page among the single page covered by the second code block and all the pages covered by the first code block. If the single page passes the dynamic detection, it is determined that the direct jump instruction meets the optimization condition, otherwise it is determined that the direct jump instruction does not meet the optimization condition.

13. The system-level binary translator according to any one of claims 9 to 12, characterized in that, The system-level binary translator further includes: The length determination module is used to determine the maximum instruction length of the client architecture; The first information determination module is used to determine that the second code block spans pages if the distance between the jump target address of the direct jump instruction and the current page boundary is less than the maximum instruction length; The first information recording module is used to record the jump target page-crossing information including: the second code block spans pages.

14. The system-level binary translator according to any one of claims 9 to 12, characterized in that The system-level binary translator further includes: The address acquisition module is used to acquire the address of the direct jump instruction according to the current program counter value; The second information determination module is used to determine that the direct jump instruction spans pages if the address of the direct jump instruction and the client virtual address of the second code block are not on the same page; The second information recording module is used to record the jump target page-crossing information including: the direct jump instruction spans pages.

15. The system-level binary translator according to any one of claims 9 to 12, characterized in that The system-level binary translator further includes: An instruction insertion module, configured to insert a first instruction sequence and a second instruction sequence at the end of the first translation code block; the first instruction sequence is used to execute the target link policy, and when it is determined that the direct jump instruction meets the optimization condition, jump to the second instruction sequence, and when it is determined that the direct jump instruction does not meet the optimization condition, exit the execution state and search for a second translation code block to be executed; the second instruction sequence is used to establish a direct jump link between the first translation code block and the second translation code block.

16. The system-level binary translator according to any one of claims 9 to 12, characterized in that The system-level binary translator further includes: An exit search module, configured to, if it is determined that the direct jump instruction does not meet the optimization condition, exit the execution state and search for a second translation code block to be executed.

17. An electronic device, characterized in that, Comprising: A processor, a memory, a communication interface, and a communication bus, and the processor, the memory, and the communication interface complete communication with each other through the communication bus; The memory is used to store at least one executable instruction, and the executable instruction causes the processor to execute the steps of the binary translation method according to any one of claims 1 to 8.

18. A readable storage medium, characterized in that, A program or instruction is stored on the readable storage medium, and when the program or instruction is executed by the processor, the steps of the binary translation method according to any one of claims 1 to 8 are implemented.

19. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, the steps of the binary translation method according to any one of claims 1 to 8 are implemented.

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