Software definition timeout detection method and system for processing PCIe packet blocking
Through the software-defined timeout detection method, the cred_avail signal in the PCIe switching structure is monitored, and Credit Timeout is triggered, which solves the problem of header packet blocking, improves system stability and bandwidth utilization, prevents blocking and diffusion, and avoids system crashes.
Patent Information
- Application Number
- CN202510399715.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-01
- Publication Date
- 2025-07-25
AI Technical Summary
The problem of head packet blocking in the PCIe switching structure causes the system throughput to decrease, the packet delay increases, and may spread to other ports, resulting in system crashes and jams. The existing credit backpressure mechanism can only alleviate local congestion and cannot be fundamentally solved.
Through the software-defined timeout detection method, the Egress Credit Timeout Detection Interval and Egress Credit Timeout Refresh Cycle generate detection time periods and cycles, monitor the cred_avail signal, trigger Credit Timeout to perform DPC functions, and quickly deal with downstream port blockage.
Effectively alleviate the impact of headpack blocking, prevent blocking from spreading, improve system stability and bandwidth resource utilization, reduce human intervention, and avoid the risk of system performance degradation and collapse.
Smart Images
Figure CN120378326A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of communications, and specifically to a software-defined timeout detection method and system for processing PCIe packet blocking. Background Art
[0002] To achieve a more complex topology and higher bandwidth utilization, PCIe switching technology allows devices to communicate with different devices simultaneously through multiple PCIe ports to achieve efficient communication between PCIe devices. Specifically, as Figure 1 shown, in the design of a PCIe switching structure, a one-master-multi-slave switching topology is usually constructed, which supports one upstream port (UP) for connecting to the root complex and multiple downstream ports (DP) for connecting to terminal devices to mount more PCIe devices for data transmission. During the switching and forwarding process between the upstream port and the downstream port, it supports the fan-out forwarding of packets from one source port to multiple destination ports.
[0003] In PCIe protocol communication, the protocol requires the implementation of different types of message packets such as P (Posted), NP (Non-Posted), and CPL (Completion). At the same time, transaction layer packets need to support strong ordering rules, which require that TLPs on the same channel be strictly scheduled and forwarded in the order they enter the switching structure. If a packet is blocked during transmission, even if the destinations are different, the subsequent packet must wait. However, in the upstream port's send queue, due to the blocking of the downstream destination port, the packet at the head of the queue cannot be sent for a long time, and at the same time, the strong ordering rule needs to be satisfied, resulting in the subsequent packets in the queue not being able to be sent to the downstream destination port in time, thus generating the head-of-line blocking problem in the switching structure.
[0004] The head-of-line blocking problem has an extremely serious impact on the switching structure. First, head-of-line blocking will lead to a decrease in the system's throughput and an increase in packet latency, thereby affecting the transmission efficiency of PCIe packets. Second, due to the dependency relationship between NP packets and CPL packets on different ports, the head-of-line blocking of one port will spread to the remaining ports, resulting in blocking diffusion. If it is not effectively processed for a long time, under high-load data transmission, in severe cases, the system will stall or freeze.
[0005] For each packet transmission, PCIe devices cannot tolerate packet loss or overflow. To alleviate the impact of head-of-line blocking, traditional technologies adopt a credit mechanism with specific flow control, and its principle is as Figure 2As shown in the figure, before a PCIe device sends out a packet, it needs to first check whether there is enough receiving buffer space at the receiving port. If there is, it extracts the packet from the sending buffer queue and sends it. After the receiving port receives the packet, it needs to timely transfer the buffer capacity information of the receiving party to the sending party through DLLP flow control credit. In addition, when the receiving end buffer is blocked and backlogged, a buffer backpressure mechanism based on the amount of credit is adopted. In this mechanism, the credit counter records the number of free buffers at the receiving end, and sends the amount of credit to the sending end when a buffer becomes available. After receiving the amount of credit, the sending end increments the credit count, thereby implementing backpressure on the number of data that the sending end can send. When the downstream port is blocked, the upstream port packets sent to this port are paused from being sent to avoid data overflow or loss. Until the downstream port blockage is released and the credit is updated, the upstream port that has a head packet blockage resumes and continues to send packets to this destination port.
[0006] In the traditional technology, although the downstream port can notify the upstream port device to slow down the sending rate or stop sending data packets through the credit backpressure mechanism, this mechanism can only alleviate the problem of local congestion. Although it ensures that there is no data loss and overflow, it cannot fundamentally solve the blockage problem of the downstream port. The head packet blockage problem can only be alleviated by relying on the completion of the downstream port packet forwarding process and automatically updating the credit count after the blockage is released to resume the communication of the upstream port. This will lead to the following problems that need to be urgently solved: the upstream port continuously tries to send data packets and gets stuck in a waiting state for a long time, consuming CPU time; the resources (bandwidth, buffer) of the upstream port will be continuously and invalidly occupied and cannot be used to process other normal traffic; the long-term head packet blockage will cause the performance of the entire system to decline, and due to the dependency relationship between packets of different ports, the blockage phenomenon will spread to the remaining ports. In high-load, low-latency, and high-performance application scenarios, there is still a risk of the switching fabric system crashing and freezing. Summary of the Invention
[0007] In view of the above problems, in the first aspect of the present invention, a software-defined timeout detection method for processing PCIe packet blockage is provided. The method includes:
[0008] Generate a detection time period A according to the Egress Credit Timeout Detection Interval register, and generate a detection cycle B according to the Egress Credit Timeout Refresh Cycle register. At the beginning of each detection cycle B, the credit exhaustion counter is reset to zero and re-counted.
[0009] Monitor whether the cred_avail signal is continuously pulled low within the detection time period A. If cred_avail[i] = 0 throughout the detection time period A, the value of the credit blockage counter is incremented by 1, otherwise it is not counted.
[0010] Every time the time of a detection time period A elapses, the value of the detection cycle counter is incremented by 1. Whenever the end of a detection cycle B is reached, if the credit blocking counter is greater than or equal to the trigger threshold register Egress Credit Timeout Threshold, then Credit Timeout is triggered and the DPC functional logic is executed.
[0011] Preferably, before the start of the method, it further includes setting a plurality of registers;
[0012] The plurality of registers include Egress Credit Timeout Enable, Egress Credit TimeoutValue, Egress Credit Timeout Status, Egress Credit Timeout Detection Interval, Egress Credit Timeout Refresh Cycle, Egress Credit Timeout Threshold, EgressCredit Timeout trigger behavior, and Egress Credit Timeout Type registers.
[0013] The two registers, Egress Credit Timeout Status and Egress Credit Timeout Type, are controlled by hardware, and the remaining registers are accessed by the system software through memory-mapped I / O.
[0014] Preferably, the execution of the DPC functional logic is specifically as follows:
[0015] Select the trigger mode according to the register Egress Credit Timeout For DPC Reason, and the trigger mode includes triggering a complete DPC process or executing the functional process of DPC but not reporting it as DPC.
[0016] Preferably, the Egress Credit Timeout Enable register is used for port credit blocking timeout enabling and is only configured at the downstream port.
[0017] The Egress Credit Timeout Value register is used to store the value size of the port credit blocking timeout.
[0018] The Egress Credit Timeout Status register is used to store the Egress Credit Timeout Status.
[0019] The Egress Credit Timeout Detection Interval register is used to store the detection interval for credit exhaustion backpressure, with the unit of clk cycle.
[0020] The Egress Credit Timeout Refresh Cycle register is used to store the refresh cycle for credit exhaustion backpressure detection, with the detection interval configured in the Egress Credit Timeout Detection Interval as the unit.
[0021] The Egress Credit Timeout Threshold register is used to store the trigger quantity threshold for credit exhaustion backpressure detection. When the number of detection intervals in full backpressure during the refresh cycle is greater than or equal to the value set in this register, Credit Timeout is triggered when Egress Credit timeout Enable = 1 is valid.
[0022] The Egress Credit Timeout trigger behavior register is used to control the behavior when Egress Credit Timeout is triggered, and is only valid when Egress Credit timeout Enable is enabled.
[0023] The Egress Credit Timeout Type register is used to store the type of trigger timeout, and is only valid when Egress Credit Timeout Status is 1.
[0024] In the second aspect of the present invention, a software-defined timeout detection system for processing PCIe packet blocking is provided. The system includes:
[0025] A time period and cycle generation module, configured to generate a detection time period A according to the Egress Credit Timeout Detection Interval register, and generate a detection cycle B according to the Egress Credit Timeout Refresh Cycle register. At the start of each detection cycle B, the credit exhaustion counter is reset to zero and re-counted.
[0026] The blocking detection and counting module is used to monitor whether the cred_avail signal is continuously pulled low within the detection time period A. If cred_avail[i] = 0 throughout the detection time period A, the value of the credit blocking counter is incremented by 1; otherwise, no counting is performed.
[0027] The timeout determination and triggering module is used to increment the detection cycle counter value every time the time of one detection time period A elapses. Whenever the end of a detection cycle B is reached, if the credit blocking counter is greater than or equal to the trigger threshold register EgressCredit Timeout Threshold, Credit Timeout is triggered to execute the DPC functional logic.
[0028] Preferably, before the start of the method, it further includes setting a plurality of registers.
[0029] The plurality of registers include the Egress Credit Timeout Enable, Egress Credit TimeoutValue, Egress Credit Timeout Status, Egress Credit Timeout Detection Interval, Egress Credit Timeout Refresh Cycle, Egress Credit Timeout Threshold, EgressCredit Timeout trigger behavior, and Egress Credit Timeout Type registers.
[0030] The two registers, Egress Credit Timeout Status and Egress Credit Timeout Type, are controlled by hardware, and the remaining registers are accessed by the system software through memory-mapped I / O.
[0031] Preferably, the execution of the DPC functional logic is specifically as follows:
[0032] Select the triggering method according to the register Egress Credit Timeout For DPC Reason. The triggering methods include triggering the complete DPC process or executing the functional process of DPC but not reporting it as DPC.
[0033] Preferably, the Egress Credit Timeout Enable register is used for port credit blocking timeout enabling and is only configured at the downstream port.
[0034] The Egress Credit Timeout Value register is used to store the size of the port credit block timeout value.
[0035] The Egress Credit Timeout Status register is used to store the Egress Credit Timeout Status;
[0036] The Egress Credit Timeout Detection Interval register is used to store the detection interval for the credit exhaustion backpressure, with the unit of clk cycle.
[0037] The Egress Credit Timeout Refresh Cycle register is used to store the refresh cycle for the credit exhaustion backpressure detection, with the detection interval configured in the Egress Credit Timeout Detection Interval as the unit.
[0038] The Egress Credit Timeout Threshold register is used to store the trigger quantity threshold for the credit exhaustion backpressure detection. During the refresh cycle, when the number of detection intervals in full backpressure is greater than or equal to the value set in this register, Credit Timeout is triggered when Egress Credit timeout Enable = 1 is valid.
[0039] The Egress Credit Timeout trigger behavior register is used to control the behavior when Egress Credit Timeout is triggered, and is only valid when Egress Credit timeout Enable is enabled.
[0040] The Egress Credit Timeout Type register is used to store the type of trigger timeout, and is only valid when Egress Credit Timeout Status is 1.
[0041] The software-defined timeout detection mechanism proposed by the present invention for processing PCIe switch fabric header packet blocking can effectively alleviate the impact brought by header packet blocking by monitoring and predicting the possible blocking of downstream ports in advance and quickly executing the DPC mechanism at the initial stage of header packet blocking.
[0042] First, different application scenarios may have different tolerances and handling methods for credit volume blocking. By designing the software-defined configuration register, users can flexibly choose how long the credit volume blocking lasts before triggering the DPC according to actual needs, so as to handle the head-of-packet blocking requirements under different load and latency scenarios.
[0043] Second, by designing the timeout detection mechanism, the DPC mechanism provided by the PCIe protocol is effectively utilized, which can quickly relieve the blocking phenomenon of downstream ports. There is no need to make major modifications to the existing switching structure. The hardware layer automatically identifies and processes the blocking situation, reducing the need for manual intervention. In addition, the timeout detection mechanism enables the system to identify and handle the problem of long-term insufficient credit at the early stage of head-of-packet blocking, avoiding the risk of system performance degradation caused by a single port blockage.
[0044] Finally, the present invention can effectively block the spread of blocking between ports. By triggering the DPC mechanism to quickly handle port blocking, according to the actual application situation, the time of head-of-packet blocking can be compressed within a very small range to prevent the spread of blocking. While improving the stability and security of the system, it enhances the utilization of upstream port bandwidth and buffer resources. Description of the Drawings
[0045] Figure 1 It is a schematic diagram of the switching topology structure;
[0046] Figure 2 It is a schematic diagram of the working principle of the credit volume mechanism;
[0047] Figure 3 It is a flowchart of the first embodiment;
[0048] Figure 4 It is a schematic diagram of the timeout detection mechanism;
[0049] Figure 5 It is a schematic diagram of the working process of the software-defined timeout detection mechanism;
[0050] Figure 6 It is a schematic diagram of the cred_avail signal level crossing. Detailed Embodiments
[0051] In the embodiments of the present invention, words such as "exemplary" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Exactly speaking, using words such as "exemplary" or "for example" aims to present relevant concepts in a specific way for easy understanding.
[0052] It is understood that the "embodiments" mentioned throughout the specification mean that specific features, structures, or characteristics related to the embodiments are included in at least one embodiment of the present application. Therefore, the embodiments throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics can be combined in one or more embodiments in any suitable manner. It is understood that in various embodiments of the present application, the magnitude of the sequence number of each process does not mean the order of execution, and the order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
[0053] In the present invention, unless otherwise specified, the same or similar parts between various embodiments can be referred to each other. In various embodiments of the present invention, as well as in each implementation manner / implementation method / realization method in each embodiment, if there is no special specification and logical conflict, the terms and / or descriptions between different embodiments, as well as between each implementation manner / implementation method / realization method in each embodiment, are consistent and can be cited mutually. The technical features in different embodiments, as well as in each implementation manner / implementation method / realization method in each embodiment, can be combined to form new embodiments, implementation manners, implementation methods, or realization methods according to their internal logical relationships. The implementation manners of the present application described below do not constitute a limitation to the protection scope of the present application.
[0054] Specific Embodiment 1, as Figure 3 A software-defined timeout detection method for processing PCIe packet blocking, the method comprising:
[0055] S101, generating a detection time period A according to the Egress Credit Timeout Detection Interval register, generating a detection cycle B according to the Egress Credit Timeout Refresh Cycle register, and at the start of each detection cycle B, the credit exhaustion counter is reset to zero and starts counting again.
[0056] S102, monitoring whether the cred_avail signal is continuously pulled low within the detection time period A. If cred_avail[i] = 0 throughout the detection time period A, the value of the credit blocking counter is incremented by 1; otherwise, no counting is performed.
[0057] S103, every time the time of a detection time period A has passed, the value of the detection cycle counter is incremented by 1. Whenever the end of a detection cycle B is reached, if the credit blocking counter is greater than or equal to the trigger threshold register Egress Credit Timeout Threshold, Credit Timeout is triggered and the DPC function logic is executed.
[0058] The core idea of the timeout detection mechanism is to identify and handle potential header packet blocking problems in the PCIe switching fabric at an early stage. By monitoring the peer credit volume, when a long-term credit shortage is detected and a blocking timeout is determined, a specific behavior is immediately triggered.
[0059] The cred_avail[2:0] signal is an indication signal that the current peer credit volume calculated in PCIe_txfc is not enough to send a Max_payload packet. [0] represents P, [1] represents NP, and [2] represents CPL. When this signal is low, no packet will be sent to the peer. A long-term low level is an abnormal manifestation, indicating that the sender has exhausted the credit volume, but the peer has not updated the credit volume through DLLP. Therefore, the duration of this signal being continuously low is used as the source for calculating the transmission credit volume blocking timeout at the sender. In the PCIe (Peripheral Component Interconnect Express) protocol, Posted (P), Non-Posted (NP), and Completion (CPL) packets are the basic classifications used by the Transaction Layer for different types of communication and data transfer. Posted packets are a type of request packet that does not require the receiving end to return an acknowledgment message. Such requests are mainly used for write operations because the sender does not expect any response from the target device. In contrast to Posted packets, Non-Posted packets require the receiving end to return a Completion Packet (CPL) as a response to the request. Such requests are usually used for read operations or those that require confirmation. The Completion Packet is a type of response for Non-Posted requests. When a device receives a Non-Posted request, it processes the request and returns the result to the request initiator by sending a Completion packet. It is only used in response to Non-Posted requests to carry the result data or status information of the request.
[0060] Figure 4 The timeout detection mechanism of the present invention is shown. During the B time period, it is checked whether the cred_avail signal is continuously pulled low within each A time period. If the cred_avail is continuously pulled low within an A time period, it is regarded as credit blocking within this time period, and the value of the credit blocking counter is increased. If the cred_avail is pulled high once within this time period, it is not counted as credit blocking. At the end of each B time period, it is compared whether the credit blocking counter reaches the set threshold. If it exceeds the threshold, it is regarded as a blocking timeout.
[0061] Specific process of timeout detection:
[0062] Detection interval A: A time period generated according to the register Egress Credit Timeout Detection Interval. During this time period, it is monitored whether the cred_avail signal is continuously pulled low.
[0063] Detection interval counter: If cred_avail[i] = 0 throughout the detection interval A, the value of the credit block counter is incremented by 1; otherwise, no counting is performed. Secondly, at the boundary of the detection period B, the credit exhaustion counter is reset to zero and starts counting again.
[0064] Detection period B: A time period set by the register Egress Credit Timeout Refresh Cycle. At the start of each detection period, the credit exhaustion counter is reset to zero and starts counting again.
[0065] Detection period counter: Used to generate the time of the detection period B. Every time the time of a detection interval A passes, the value of the detection period counter is incremented by 1. When the detection period counter reaches the value configured in Egress Credit timeout Refresh Cycle, one time period B is counted, and it returns to 0 and starts counting again.
[0066] Trigger logic: Whenever the end of a detection period B is reached, if it is determined that the credit block counter is greater than or equal to the trigger threshold register Egress Credit Timeout Threshold, Credit Timeout is triggered and the DPC functional logic is executed.
[0067] By designing to use a two-level counting method to reduce the bit width of a single counter, the trigger threshold configuration becomes more flexible. If a large-range counter is directly used to record the credit exhaustion situation during the entire detection period, a relatively large bit width may be required to store the count value. For example, assuming that the detection period is very long and it is necessary to be accurate to each clock cycle, the bit width of the counter will be very large.
[0068] By dividing the detection process into two levels (detection interval and detection period), the bit width requirement of a single counter can be significantly reduced. Specifically:
[0069] First-level counter (detection interval counter): Only needs to record the credit exhaustion situation within a relatively short time period, so its bit width is small.
[0070] Second-level counter (detection period counter): Only needs to record how many of the multiple detection intervals meet the conditions, so its bit width is also relatively small.
[0071] In addition, if only a large-range counter is used, the configuration of the trigger threshold may be restricted by hardware, making it difficult to achieve fine-grained adjustment. For example, if the bit width of the counter is limited, it may not be possible to precisely set a small threshold. Advantages of the two-level counter: Through the design of the two-level counter, the trigger threshold can be flexibly configured at different levels:
[0072] Detection interval threshold: The Egress Credit Timeout DetectionInterval can be adjusted according to actual requirements to control the length of each detection.
[0073] Detection period threshold: The Egress Credit Timeout Threshold can be adjusted according to actual requirements to control how many of the multiple detection intervals need to meet the conditions to trigger Credit Timeout.
[0074] The hierarchical design allows users to flexibly adjust the parameters of the detection interval and detection period according to the requirements of specific application scenarios under the premise of supporting software definition, thereby achieving more refined control.
[0075] In addition, the DPC mechanism is a mechanism in the PCIe switching fabric used to handle and isolate downstream port errors, aiming to improve the reliability and stability of the system. It quickly isolates blocked downstream ports to prevent error propagation, while sending error notifications to the software and attempting to quickly restore the function of the error port, reducing the risk of system crashes. By flexibly triggering the DPC through the timeout detection mechanism, the recording method of whether the credit timeout triggers the DPC and the triggering reason is designed to be configurable through registers. According to the configuration of the register Egress Credit Timeout For DPC Reason, the triggering method can be selected. It is possible to trigger the complete DPC process or execute the functional process of the DPC but not report it as a DPC (applicable to cases where the operating system software does not support it). Utilizing the DPC mechanism provided by the PCIe protocol, the recovery of the downstream blocked port can be quickly achieved, thereby alleviating the impact of head-of-packet blocking. The complete workflow of the software-defined timeout detection mechanism is as Figure 5 shown.
[0076] As Figure 5 shown, check whether Egress Credit Timeout Enable is enabled. If Enable = 0 (enable disabled), the counter logic does not work, supporting power consumption reduction.
[0077] If Enable = 1 (enable is on), the hardware behavior is to start the counting logic and begin detecting CreditTimeout, and the software behavior is to wait for the enable to be on. Once the Credit Timeout trigger condition is met, the method of triggering DPC (Downstream Port Containment) is selected according to the configuration of the EgressCredit Timeout For DPC Reason register. There are the following possibilities: Egress Credit Timeout For DPC Reason = 10: In the Extended Reason, if the reserved value is detected, DPC is triggered. Egress Credit Timeout For DPC Reason = 11: When an Uncorrectable Error is detected, DPC is triggered. Egress Credit Timeout For DPC Reason = 0x, an interrupt is reported, and the Item is driven to the Disabled state, but DPC is not triggered.
[0078] If DPC is triggered (Reason = 10 or 11), an interrupt and an ERR_COR message (Correctable Error Message is mislabeled as Uncorrectable) are reported according to the DPC register configuration, and the Item of the Downstream port enters the disabled state. The RC underlying driver (modified kernel) senses the DPC trigger. If it determines that the trigger reason is CreditTimeout, the software decides the error status recovery process. If DPC is not triggered (Reason = 0x), an interrupt is reported, the Item is driven to Disabled, and DPC is not triggered. When the RC senses the Credit Timeout trigger, the software decides the error status recovery process.
[0079] After DPC is triggered or Credit Timeout is sensed, the software needs to intervene to handle the error recovery. The Uncorrectable Error register in AER (Advanced Error Reporting) clears the relevant error status, the DPC trigger status register clears the DPC trigger status, and the status related to Credit Timeout is cleared. The specific error recovery steps are determined by the software according to the system design and the error type.
[0080] In addition, the Egress Credit Timeout Status register can record the status of credit volume blocking timeout, and the Egress Credit Timeout Type register can record the specific packet type at the moment when the timeout is triggered. Recording the specific reasons for triggering DPC through registers helps to better understand the system status and troubleshoot problems. In addition, recording the triggering reasons not only helps to handle problems immediately, but also provides a basis for subsequent system analysis and optimization. The reasons for frequent credit volume blocking can be found through log analysis, and corresponding improvement measures can be taken.
[0081] In one embodiment, the present invention further provides a credit_timeout_ctrl module, which is instantiated once for each port in the switching fabric to implement the timeout detection logic. As Figure 6 shown, the signals related to credit flow control are located in the pcie5_txfc module, which is responsible for calculating and generating the flow control signal cred_avail on the PCIe link and dynamically adjusting the sending behavior according to the status of the link. To implement this function, the cred_avail signal calculated in the pcie5_txfc module needs to be input across levels into the error management module pcie5_errmgt. The DPC-related logic and registers are located in the pcie5_errmgt module, which is used to determine whether there is a credit blocking timeout and trigger the corresponding blocking handling process. Specifically, the cred_avail[2:0] signal, a total of 3 bits, is led out from the port controller and needs to cross levels within the system, representing the credit volumes of P, NP, and CPL respectively, so as to monitor the credit blocking situation. The modules participating in the interaction are all driven by the same-source clock, so the design of this signal crossing levels reduces the problem of cross-clock domains and at the same time maintains a clear interface between the modules.
[0082] In an alternative embodiment, before the start of the method, it further includes setting a plurality of registers.
[0083] The multiple registers include the Egress Credit Timeout Enable, Egress Credit Timeout Value, Egress Credit Timeout Status, Egress Credit Timeout Detection Interval, Egress Credit Timeout Refresh Cycle, Egress Credit Timeout Threshold, Egress Credit Timeout trigger behavior, and Egress Credit Timeout Type registers.
[0084] The Egress Credit Timeout Status and Egress Credit Timeout Type registers are controlled by hardware, and the remaining registers are accessed by the system software through memory-mapped I / O.
[0085] The Egress Credit Timeout Enable register is used for port credit blocking timeout enabling and is only configured for downstream ports.
[0086] The Egress Credit Timeout Value register is used to store the port credit blocking timeout value.
[0087] The Egress Credit Timeout Status register is used to store the Egress Credit Timeout Status.
[0088] The Egress Credit Timeout Detection Interval register is used to store the detection interval for the credit exhaustion backpressure, with the unit of clk cycle.
[0089] The Egress Credit Timeout Refresh Cycle register is used to store the refresh cycle for the credit exhaustion backpressure detection, with the unit of the detection interval configured in the Egress Credit Timeout Detection Interval.
[0090] The Egress Credit Timeout Threshold register is used to store the trigger quantity threshold for the detection of credit exhaustion backpressure. During the refresh cycle, when the number of detection intervals with backpressure throughout is greater than or equal to the value set in this register, Credit Timeout is triggered, and it is valid when Egress Credit timeout Enable = 1.
[0091] The Egress Credit Timeout trigger behavior register is used to control the behavior when Egress Credit Timeout is triggered, and it is only valid when Egress Credit timeout Enable is enabled.
[0092] The Egress Credit Timeout Type register is used to store the type of trigger timeout, and it is only valid when Egress Credit Timeout Status is 1.
[0093] Define and design the registers as shown in Table 1. Among them, the two registers of Egress Credit Timeout Status and Egress Credit Timeout Type are controlled by hardware and are used to execute the trigger process and record the trigger reason. The remaining registers are all accessed by the system software (device driver) through memory-mapped I / O. The system software can configure key parameters such as the enable switch, trigger threshold, and detection interval size of the registers with different granularities by reading and writing the memory addresses of these registers, so as to flexibly control the behavior of the credit block timeout detection mechanism and improve the scenario adaptability of the present invention.
[0094] Table 1 Design Register Description
[0095]
[0096]
[0097] Specific Embodiment 2 provides a software-defined timeout detection system for processing PCIe packet blocking, and the system includes:
[0098] A time period and cycle generation module, which is used to generate a detection time period A according to the Egress Credit Timeout Detection Interval register and generate a detection cycle B according to the Egress Credit Timeout Refresh Cycle register. At the start of each detection cycle B, the credit exhaustion counter is reset to zero and starts counting again.
[0099] The Blocking Detection and Counting Module is used to monitor whether the cred_avail signal is continuously pulled low within the detection time period A. If cred_avail[i]=0 throughout the detection time period A, the value of the credit blocking counter is incremented by 1; otherwise, no counting is performed.
[0100] The Timeout Judgment and Trigger Module is used to increment the detection cycle counter value every time the time of one detection time period A elapses. Whenever the end of a detection cycle B is reached, if the credit blocking counter is greater than or equal to the trigger threshold register Egress Credit Timeout Threshold, Credit Timeout is triggered to execute the DPC functional logic.
[0101] Preferably, before the start of the method, setting a plurality of registers is further included.
[0102] The plurality of registers include the Egress Credit Timeout Enable, Egress Credit Timeout Value, Egress Credit Timeout Status, Egress Credit Timeout Detection Interval, Egress Credit Timeout Refresh Cycle, Egress Credit Timeout Threshold, Egress Credit Timeout trigger behavior, and Egress Credit Timeout Type registers.
[0103] The two registers, Egress Credit Timeout Status and Egress Credit Timeout Type, are controlled by hardware, and the remaining registers are accessed by the system software through memory-mapped I / O.
[0104] Preferably, the execution of the DPC functional logic is specifically as follows:
[0105] The trigger mode is configured according to the register Egress Credit Timeout For DPC Reason. The trigger mode includes triggering a complete DPC process or executing the functional process of DPC but not reporting it as DPC.
[0106] Preferably, the Egress Credit Timeout Enable register is used for enabling port credit blocking timeout and is only configured for the downstream port.
[0107] The Egress Credit Timeout Value register is used to store the size of the port credit blocking timeout value.
[0108] The Egress Credit Timeout Status register is used to store the Egress Credit Timeout Status.
[0109] The Egress Credit Timeout Detection Interval register is used to store the detection interval for the credit exhaustion backpressure, in clk cycles.
[0110] The Egress Credit Timeout Refresh Cycle register is used to store the refresh cycle for the credit exhaustion backpressure detection, in units of the detection interval configured in the Egress Credit Timeout Detection Interval.
[0111] The Egress Credit Timeout Threshold register is used to store the trigger quantity threshold for the credit exhaustion backpressure detection. When the number of detection intervals in the refresh cycle that are under backpressure throughout is greater than or equal to the value set in this register, Credit Timeout is triggered when Egress Credit timeout Enable = 1 is valid.
[0112] The Egress Credit Timeout trigger behavior register is used to control the behavior when Egress Credit Timeout is triggered, and is only valid when Egress Credit timeout Enable is enabled.
[0113] The Egress Credit Timeout Type register is used to store the type of trigger timeout, and is only valid when and only when Egress Credit Timeout Status is 1.
[0114] The above embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (such as coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium accessible by a computer or a data storage device such as a server or data center integrating one or more available media. The available medium may be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)).
[0115] The steps of the methods or algorithms described in the embodiments of the present application may be directly embedded in hardware, a software unit executed by a processor, or a combination of the two. The software unit may be stored in a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium in the art. Exemplarily, the storage medium may be connected to the processor so that the processor can read information from the storage medium and write information to the storage medium. Optionally, the storage medium may also be integrated into the processor. The processor and the storage medium may be provided in an ASIC.
[0116] These computer program instructions may also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are performed on the computer or other programmable device to generate a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in a process Figure 1 a process or multiple processes and / or blocks Figure 1 steps for implementing the functions specified in a block or multiple blocks.
[0117] Although the present application has been described in connection with specific features and their embodiments, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the present application. Accordingly, the present specification and drawings are merely exemplary illustrations of the present application as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the present application. Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these changes and modifications.
Claims
1. A software-defined timeout detection method for handling PCIe packet blocking, characterized in that, The method includes: Generating a detection time period A according to the Egress Credit Timeout Detection Interval register, and generating a detection cycle B according to the Egress Credit Timeout Refresh Cycle register. At the start of each detection cycle B, the credit exhaustion counter is reset to zero and starts counting again; Monitoring whether the cred_avail signal is continuously pulled low within the detection time period A. If cred_avail[i] = 0 throughout the detection time period A, the value of the credit block counter is incremented by 1; otherwise, no counting is performed; Every time the time of a detection time period A elapses, the value of the detection cycle counter is incremented by 1. Whenever the end of a detection cycle B is reached, if the credit block counter is greater than or equal to the trigger threshold register Egress Credit Timeout Threshold, Credit Timeout is triggered and the DPC functional logic is executed.
2. The method according to claim 1, wherein Before the start of the method, it also includes setting multiple registers; The multiple registers include the Egress Credit Timeout Enable, Egress Credit Timeout Value, Egress Credit Timeout Status, Egress Credit Timeout Detection Interval, Egress Credit Timeout Refresh Cycle, Egress Credit Timeout Threshold, Egress Credit Timeout trigger behavior, and Egress Credit Timeout Type registers; The Egress Credit Timeout Status and Egress Credit Timeout Type registers are controlled by hardware, and the remaining registers are accessed by the system software through memory-mapped I / O.
3. The method according to claim 1, wherein The execution of the DPC functional logic specifically is: Selecting the trigger mode according to the register Egress Credit Timeout For DPC Reason. The trigger modes include triggering a complete DPC process or executing the DPC functional process but not reporting it as a DPC.
4. The method according to claim 1, wherein The Egress Credit Timeout Enable register is used for enabling port credit block timeout and is only configured for downstream ports; The Egress Credit Timeout Value register is used to store the magnitude of the port credit block timeout value; The Egress Credit Timeout Status register is used to store the Egress Credit Timeout Status; The Egress Credit Timeout Detection Interval register is used to store the detection interval for the backpressure caused by the exhaustion of the credit amount, with the unit of clk cycle; The Egress Credit Timeout Refresh Cycle register is used to store the refresh cycle for the detection of the backpressure caused by the exhaustion of the credit amount, with the detection interval configured in the Egress Credit Timeout Detection Interval as the unit; The Egress Credit Timeout Threshold register is used to store the trigger quantity threshold for the detection of the backpressure caused by the exhaustion of the credit amount. When the number of detection intervals that are in backpressure throughout the refresh cycle is greater than or equal to the value set in this register, Credit Timeout is triggered when Egress Credit timeout Enable = 1 is valid; The Egress Credit Timeout trigger behavior register is used to control the behavior when Egress Credit Timeout is triggered, and is only valid when Egress Credit timeout Enable is enabled; The Egress Credit Timeout Type register is used to store the type of the triggered timeout, and is only valid when EgressCredit Timeout Status is 1.
5. A software-defined timeout detection system for handling PCIe packet blocking, characterized in that, The system includes: A time period and cycle generation module, which is used to generate a detection time period A according to the Egress Credit Timeout Detection Interval register and generate a detection cycle B according to the Egress Credit Timeout Refresh Cycle register. At the start of each detection cycle B, the credit exhaustion counter is reset to zero and starts counting again; A blocking detection and counting module, which is used to monitor whether the cred_avail signal is continuously pulled low within the detection time period A. If cred_avail[i] = 0 throughout the detection time period A, the value of the credit blocking counter is incremented by 1, otherwise no counting is performed; A timeout determination and trigger module, which is used to increment the value of the detection cycle counter by 1 every time the time of a detection time period A has passed. Whenever the end of a detection cycle B is reached, if the credit blocking counter is greater than or equal to the trigger threshold register Egress CreditTimeout Threshold, Credit Timeout is triggered and the DPC functional logic is executed.
6. The system according to claim 5, wherein Before the start of the method, it also includes setting multiple registers; The multiple registers include Egress Credit Timeout Enable, Egress Credit Timeout Value, Egress Credit Timeout Status, Egress Credit Timeout Detection Interval, Egress Credit Timeout Refresh Cycle, Egress Credit Timeout Threshold, Egress Credit Timeout trigger behavior, and Egress Credit Timeout Type registers; The two registers, Egress Credit Timeout Status and Egress Credit Timeout Type, are controlled by hardware, and the remaining registers are accessed by the system software through memory-mapped I / O.
7. The system according to claim 5, characterized in that The execution of the DPC function logic is specifically as follows: Select the trigger mode according to the configuration of the register Egress Credit Timeout For DPC Reason. The trigger modes include triggering the complete DPC process or executing the DPC function process but not reporting it as DPC.
8. The system according to claim 5, wherein The Egress Credit Timeout Enable register is used for enabling port credit blocking timeout and is only configured for the downstream port; The Egress Credit Timeout Value register is used to store the size of the port credit blocking timeout value; The Egress Credit Timeout Status register is used to store the Egress Credit Timeout Status; The Egress Credit Timeout Detection Interval register is used to store the detection interval for the backpressure caused by the exhaustion of the credit amount, with the unit of clk cycle; The Egress Credit Timeout Refresh Cycle register is used to store the refresh cycle for the detection of the backpressure caused by the exhaustion of the credit amount, with the detection interval configured in the Egress Credit Timeout Detection Interval as the unit; The Egress Credit Timeout Threshold register is used to store the trigger quantity threshold for the detection of the backpressure caused by the exhaustion of the credit amount. When the number of detection intervals in the full cycle of backpressure within the refresh cycle is greater than or equal to the value set in this register, Credit Timeout is triggered when Egress Credit timeout Enable = 1 is valid; The Egress Credit Timeout trigger behavior register is used to control the behavior when an Egress Credit Timeout is triggered, and it is only valid when Egress Credit timeout Enable is enabled; The Egress Credit Timeout Type register is used to store the type of triggered timeout, and it is only valid when the Egress Credit Timeout Status is 1.